19-3026; Rev 1; 11/04
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
Features
♦ Pin Compatible with the Mindspeed
MC2045-2/MC2045-2Y
♦ 500µV Input Sensitivity (BER = 10-12)
♦ Compatible with 4B/5B Data Coding
♦ Programmable LOS Threshold
♦ Stable LOS Threshold Over Supply Range
♦ Output Disable Function and Automatic Squelch
♦ Single +3.3V or +5.0V Power Supply
♦ 18mA Supply Current
The MAX3645 limiting amplifier functions as a data
quantizer and is pin compatible with the Mindspeed
MC2045-2 and MC2045-2Y postamplifiers. The amplifier accepts a wide range of input voltages and provides
constant-level positive emitter-coupled logic (PECL)
output voltages with controlled edge speeds.
The MAX3645 features an integrated power detector
with complementary PECL loss-of-signal (LOS) outputs
that indicate when the input power level drops below a
programmable threshold. An optional squelch function
holds the data outputs at static levels during a
LOS condition.
Ordering Information
The MAX3645 operates from a single +3.3V or +5.0V
power supply over a -40°C to +85°C temperature
range. It is available in 16-pin SO and 16-pin QSOP
packages.
PART
Applications
TEMP RANGE
PIN-PACKAGE
MAX3645ESE
-40°C to +85°C
16 SO
MAX3645EEE
-40°C to +85°C
16 QSOP
MAX3645EEE+
-40°C to +85°C
16 QSOP
+Denotes lead-free package.
Pin Configuration
SONET 155Mbps Transceivers
Fast Ethernet Receivers
TOP VIEW
FDDI 125Mbps Receivers
CAZ2 1
16 TH
FTTx Receivers
CAZ1 2
15 N.C.
ESCON Receivers
GNDA 3
DIN+ 4
14 VCCE
MAX3645
13 DOUT+
DIN- 5
12 DOUT-
VCCA 6
11 GNDE
CSD 7
10 LOS
9
DIS 8
LOS
SO/QSOP
Typical Application Circuit
VCC
VCC
VCC
CAZ
0.1µF
CSD
1nF
VCC
CSD VCCA CAZ1
CAZ2 VCCE
N.C.
0.1µF
PIN K
MAX3644*
IN
OUT+
DIN+
OUT-
DIN-
DOUT+
MAX3645
0.1µF
GNDA
DOUTLOS
TH
DIS
LOS
GNDE
50Ω
GND
RTH
100Ω
50Ω
50Ω
50Ω
*FUTURE PRODUCT
VCC - 2V
VCC - 2V
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3645
General Description
MAX3645
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCCA, VCCE) ....................-0.5V to +7.0V
Voltage at CAZ1, CAZ2, DIN+,
DIN-, CSD, DIS, TH ................................-0.5V to (VCC + 0.5V)
PECL Output Current (DOUT+, DOUT-, LOS, LOS) ...........50mA
Differential Voltage between CAZ1 and CAZ2......-1.5V to +1.5V
Differential Voltage between DIN+ and DIN- ........-1.5V to +1.5V
Continuous Power Dissipation (TA = +85°C)
16-Pin SO (derate 8.7mW/°C above +85°C)................565mW
16-Pin QSOP (derate 8.3mW/°C above +85°C)...........540mW
Storage Ambient Temperature Range (TS)…….-65°C to +160°C
Lead Temperature (soldering, 10s)...........……………….+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, PECL outputs are terminated with 50Ω to VCC - 2V, RTH = 100Ω, CAZ = 0.1µF, CSD = 1nF, TA = -40°C to
+85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
18
27
mA
4.8
6.4
kΩ
POWER SUPPLY
Supply Current
ICC
Excludes PECL termination currents
RIN
Single ended; VIN = ±200mV
INPUT SPECIFICATIONS
Input Resistance
Input Sensitivity (Note 1)
VIN-MIN
Input Overload (Note 1)
VIN-MAX
Input-Referred RMS Noise
0.5
Differential
1.0
Single ended
750
Differential
1500
Unterminated input, output offset divided by
DC gain (Note 2)
Input-Referred Offset Voltage
Input Common-Mode Voltage
3.3
Single ended
VIN-NOISE
mVP-P
2
40
VCC 0.87
VCMM
(Notes 2, 3)
mVP-P
36
µV
V
50
µVRMS
DIS Input High
VIH
PECL or CMOS logic
VCC 1160
VCC
mV
DIS Input Low
VIL
PECL or CMOS logic
0
VCC 1480
mV
-10
+10
µA
DIS Input Current
IIL, IIH
0V ≤ VDIS ≤ VCC
OUTPUT SPECIFICATIONS
PECL Output-Voltage High
(Notes 1, 2)
VCC 1085
VCC 880
mV
PECL Output-Voltage Low
(Notes 1, 2)
VCC 1830
VCC 1555
mV
Data Output Transition Time
tR, tF
20% to 80% (Notes 1, 2, 4)
0.7
1.4
ns
Pulse-Width Distortion
PWD
(Notes 1, 2, 4, 5)
30
200
ps
2
_______________________________________________________________________________________
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
(VCC = +2.97V to +5.5V, PECL outputs are terminated with 50Ω to VCC - 2V, RTH = 100Ω, CAZ = 0.1µF, CSD = 1nF, TA = -40°C to
+85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
150
250
MAX
UNITS
TRANSFER CHARACTERISTICS
Bandwidth
Gain = 60dB
Low-Frequency Cutoff
CAZ = open
500
CAZ = 0.1µF
0.5
MHz
kHz
LOSS-OF-SIGNAL SPECIFICATIONS (Notes 2, 4, 6)
LOS Sensitivity Range
0Ω ≤ RTH ≤ 2kΩ
LOS Hysteresis
10log (VDEASSERT/VASSERT)
1.4
LOS Assert/Deassert Time
(Note 7)
2.3
RTH = 0Ω, low setting
0.5
0.9
1.3
LOS Assert Level
LOS Deassert Level
Signal-Dectect Filter Resistance
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
RSD
2
20
2
mVP-P
dB
80.0
RTH = 1kΩ, medium setting
4.8
6.6
8.3
RTH = 2kΩ, high setting
12
17
22
RTH = 0Ω, low setting
1.1
1.5
1.9
RTH = 1kΩ, medium setting
8.0
10.8
13.5
RTH = 2kΩ, high setting
20
28
36
Pin 7
14
20
26
µs
mVP-P
mVP-P
kΩ
Between sensitivity and overload, the output amplitude is >95% of the fully limited amplitude and all AC specifications are met.
Guaranteed by design and characterization.
Noise is derived from BER measurement.
The data input transition time is controlled by a 4th-order Bessel filter with f-3dB = 0.75 × data rate.
PWD = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 155Mbps 0011 pattern.
All LOS specifications are measured using a 155Mbps 223 - 1 PRBS pattern.
The signal at the input is switched between two amplitudes, SIGNAL_ON and SIGNAL_OFF, as shown in Figure 1.
VIN
SIGNAL ON
1dB
6dB
MAXIMUM DEASSERT LEVEL
MAXIMUM POWER-DETECT WINDOW
MINIMUM ASSERT LEVEL
0V
SIGNAL OFF
TIME
Figure 1. Signal Levels for LOS Assert/Deassert Time
Measurement
_______________________________________________________________________________________
3
MAX3645
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VCC = 3.3V, PECL outputs terminated with 50Ω to VCC - 2V, RTH = 100Ω, CAZ = 0.1µF, CSD = 1nF, TA = +25°C, unless otherwise noted.)
OUTPUT EYE DIAGRAM
(VIN = 1mVP-P, 155Mbps, 223 - 1PRBS)
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDES PECL OUTPUT CURRENTS)
MAX3645 toc03
MAX3645 toc01
45
40
SUPPLY CURRENT (mA)
OUTPUT EYE DIAGRAM
(VIN = 1500mVP-P, 155Mbps, 223 - 1PRBS)
MAX3654 toc02
50
35
30
200mV/
div
VCC = 5.0V
25
200mV/
div
20
15
VCC = 3.3V
10
5
-15
-40
10
35
60
1ns/div
1ns/div
BIT-ERROR RATIO vs.
DIFFERENTIAL INPUT VOLTAGE
INPUT-REFERRED RMS NOISE
vs. TEMPERATURE
85
RTH = 100Ω
1400
1200
RTH = 1kΩ
1000
800
RTH = 2kΩ
10-6
10-7
10-8
10-9
10-10
600
10-11
10-12
400
0.01
0.1
1
100
10
0.2
0.3
0.4
0.5
0.6
0.7
-40
0.8
-15
10
35
60
LOSS-OF-SIGNAL THRESHOLD
vs. RTH (VCC = +3.3V AND +5.0V)
LOSS-OF-SIGNAL HYSTERESIS
vs. TEMPERATURE
60
50
40
30
20
VIN = 0.1mVP-P
0
0.2
0.5
0.7
1.0
RTH (kΩ)
1.2
1.5
1.7
2.0
155Mbps, 223 - 1 PRBS
LOS DEASSERT
LOS ASSERT
3.2
85
155Mbps, 223 - 1 PRBS
3.0
10log (DEASSERT/ASSERT) (dB)
MAX3645 toc07
70
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
MAX3645 toc08
SMALL-SIGNAL GAIN vs. RTH
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
TEMPERATURE (°C)
80
0
0.1
VCC = +3.3V
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
90
10
0
VCC = +5.0V
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
100
4
10-5
MAX3645 toc06
1600
10
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
2.8
2.6
MAX3645 toc09
RTH = 0Ω
155Mbps, 223 - 1 PRBS
-4
BIT-ERROR RATIO
1800
10-3
MAX3654 toc04
DIFFERENTIAL OUTPUT VOLTAGE (mVP-P)
2000
INPUT-REFERRED NOISE (µVRMS)
TRANSFER FUNCTION
MAX3645 toc05
TEMPERATURE (°C)
20log (VOUT/VIN) (dB)
MAX3645
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
RTH = 2kΩ
2.4
2.2
2.0
1.8
RTH = 1kΩ
RTH = 100Ω
1.6
1.4
1.2
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
RTH (kΩ)
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
MAX3654 toc10
100
155Mbps 0011 PATTERN
90
PULSE-WIDTH DISTORTION (ps)
VIN
VOUT
80
MAX3645 toc11
PULSE-WIDTH DISTORTION
vs. DIFFERENTIAL INPUT VOLTAGE
LOSS-OF-SIGNAL WITH SQUELCH
(155Mbps, 223 - 1PRBS)
70
60
50
40
30
20
10
LOS
0
0.1
10µs/div
1
10
100
1000
10,000
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
DATA OUTPUT TRANSITION TIME
vs. DIFFERENTIAL INPUT VOLTAGE
MAX3645 toc12
3.0
TRANSITION TIME (ns)
2.5
2.0
1.5
1.0
0.5
0
0.1
1
10
100
1000
10,000
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
_______________________________________________________________________________________
5
MAX3645
Typical Operating Characteristics (continued)
(VCC = 3.3V, PECL outputs terminated with 50Ω to VCC - 2V, RTH = 100Ω, CAZ = 0.1µF, CSD = 1nF, TA = +25°C, unless otherwise noted.)
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
MAX3645
Pin Description
PIN
MINDSPEED
MC2045-2
MC2045-2Y
PIN NAME
MAXIM
MAX3645
PIN NAME
1
CAZ-
CAZ2
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and
CAZ1 sets the time constant of the offset correction loop. The offset correction is disabled
when the CAZ1 and CAZ2 pins are shorted together.
2
CAZ+
CAZ1
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and
CAZ2 sets the time constant of the offset correction loop. The offset correction is disabled
when the CAZ2 and CAZ1 pins are shorted together.
3
GNDA
GNDA
Analog Supply Ground. Must be at the same potential as the GNDE pin.
4
DIN
DIN+
Positive Data Input
FUNCTION
5
DIN
DIN-
Negative Data Input
6
VCCA
VCCA
+2.97V to +5.5V Analog Supply Voltage. Must be at same potential as the VCCE pin.
7
CF
CSD
Signal-Detect-Filter Capacitor Connection. Connect the CSD capacitor between CSD and VCCA.
8
JAM
DIS
Disable Input, PECL or CMOS Compatible. Data outputs are held to a static logic 0 when DIS is
asserted high. The LOS function remains active when the outputs are disabled. When
connected to the LOS pin, an automatic squelch function is enabled.
9
ST
LOS
Positive Loss-of-Signal Output, PECL. LOS is high when the level of the input signal drops
below the threshold set by the TH input. LOS is low when the signal level is above the
threshold. LOS can be connected directly to DIS for automatic squelch.
10
ST
LOS
Negative Loss-of-Signal Output, PECL. LOS is low when the level of the input signal drops
below the threshold set by the TH input. LOS is high when the signal level is above the
threshold.
11
GNDE
GNDE
12
DOUT
DOUT-
Negative Data Output, PECL. A high at DIS forces DOUT- high.
13
DOUT
DOUT+
Positive Data Output, PECL. A high at DIS forces DOUT+ low.
14
VCCE
VCCE
15
NC
N.C.
16
VSET
TH
Digital Supply Ground. Must be at the same potential as the GNDA pin.
+2.97V to +5.5V Digital Supply Voltage. Must be at the same potential as the VCCA pin.
No Connection
Loss-of-Signal Threshold Pin. Resistor (RTH) to ground sets the LOS threshold. This pin cannot
be left open.
Detailed Description
The MAX3645 consists of gain stages, offset correction,
power detector, LOS indicators, and PECL output buffers.
See Figure 2 for the functional diagram.
Data Input
The data inputs have a single-ended input resistance of
4.8kΩ and are internally DC-biased to VCC - 0.87V (see
Figure 3). External capacitors are required to AC-couple the data signals. Pattern-dependent jitter is minimized by using coupling capacitor values large enough
to pass the lowest frequencies of interest (consecutive
ones and zeros) with the given input resistance.
Typically, 0.1µF coupling capacitors yield a -3dB frequency of 354Hz. Capacitor tolerance and input resis6
tance variation (3.3kΩ to 6.4kΩ) must be considered to
accurately calculate the -3dB frequency. Capacitor values should be chosen that set the -3dB frequency at
least a factor of 10 below the lowest frequency of interest. A capacitor value of 0.1µF is recommended.
Gain Stage and Offset Correction
The limiting amplifier provides approximately 74dB
(RTH = 100Ω) of gain. This large gain makes the amplifier susceptible to small DC offsets in the signal path.
To correct DC offsets, the amplifier has an internal feedback loop that acts as a DC autozero circuit. By correcting the DC offsets, the limiting amplifier improves
receiver sensitivity and power-detector accuracy.
_______________________________________________________________________________________
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
MAX3645
TH
VCC
CSD
VCC
VCC - 0.87V
LOS
LOS
4.8kΩ
POWER
DETECTOR
4.8kΩ
MAX3645
DIN+
DOUT+
DIN-
DOUT-
DIN+
DIS
OFFSET
CORRECTION
DINESD
STRUCTURES
CINT
CAZ1
CAZ2
Figure 2. Functional Diagram
Figure 3. Equivalent Data Input Circuit
The external autozero capacitor (CAZ), in parallel with
internal capacitance (CINT), determines the time constant of the DC offset correction loop. With CAZ = 0.1µF
(recommended), the -3dB frequency cutoff of the signal
path is typically 0.5kHz.
detector time constant, which determines the LOS
assert/deassert time. With C SD = 1nF the assert/
deassert time is in the range of 2.3µs to 80µs. This provides a long enough time constant to avoid false triggering due to variations in mark density.
Power Detector and LOS Indicators
Disable Function
The external resistor RTH sets the gain of the first limiting stage. This gain setting controls the threshold at
which the power detector indicates an LOS condition.
Power detection is accomplished by rectifying and lowpass filtering the data signal, then comparing it to the
programmed threshold voltage. A hysteresis of 2dB
prevents the LOS output from chattering when the input
signal is near the threshold.
When the DIS input is forced high, the disable function
is enabled, which holds DOUT+ low and DOUT- high.
The disable function is used to prevent the data outputs
from toggling due to noise when no signal is present.
The LOS output can be connected to the DIS input for
automatic squelch.
PECL Output Buffer
The data outputs (DOUT+, DOUT-) and the loss-of-signal outputs (LOS+, LOS-) are PECL outputs. The equivalent PECL output circuit is shown in Figure 4.
Applications Information
Programming LOS Assert/Deassert Levels
The appropriate value of RTH is determined by using
the Loss-Of-Signal Threshold vs. R TH graph in the
Typical Operating Characteristics.
LOS Time Constant
The lowpass filter of the power detector comprises a
20kΩ on-chip resistor (RSD) and an external capacitor
(CSD). The CSD capacitor value determines the power-
PECL Output Terminations
The proper termination for a PECL output is 50Ω to
(VCC - 2V), but other standard termination techniques
can be used. For more information on PECL terminations and how to interface with other logic families, refer
to Maxim Application Note HFAN-01.0: Introduction to
LVDS, PECL, and CML.
Layout Considerations
For best performance, use good high-frequency layout
techniques. Filter power supplies, keep ground connections short, and use multiple vias where possible.
Power-supply decoupling should be placed close to
the VCC pins. Minimize the distance from the preamplifier and use controlled-impedance transmission lines to
interface with the outputs when possible.
_______________________________________________________________________________________
7
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
MAX3645
Chip Information
TRANSISTOR COUNT: 1026
VCC
PROCESS: Silicon bipolar
DOUT+/LOS
DOUT+/LOS
ESD
STRUCTURES
Figure 4. Equivalent PECL Output Circuit
8
_______________________________________________________________________________________
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
N
E
H
INCHES
MILLIMETERS
MAX
MIN
0.069
0.053
0.010
0.004
0.014
0.019
0.007
0.010
0.050 BSC
0.150
0.157
0.228
0.244
0.016
0.050
MAX
MIN
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
1.27 BSC
3.80
4.00
5.80
6.20
0.40
SOICN .EPS
DIM
A
A1
B
C
e
E
H
L
1.27
VARIATIONS:
1
INCHES
TOP VIEW
DIM
D
D
D
MIN
0.189
0.337
0.386
MAX
0.197
0.344
0.394
MILLIMETERS
MIN
4.80
8.55
9.80
MAX
5.00
8.75
10.00
N MS012
8
AA
14
AB
16
AC
D
A
B
e
C
0∞-8∞
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
21-0041
REV.
B
1
1
_______________________________________________________________________________________
9
MAX3645
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX3645
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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