MAX3676EHJ+TG05

19-1537; Rev 4; 3/09 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier The MAX3676 is a complete clock-recovery and dataretiming IC incorporating a limiting amplifier. It is intended for 622Mbps SDH/SONET applications and operates from a single +3.3V supply. The MAX3676 is designed for both section-regenerator and terminal-receiver applications in OC12/STM-4 transmission systems. Its jitter performance exceeds all SONET/SDH specifications. The MAX3676 has two differential input amplifiers: one accepts positive-referenced emitter-coupled logic (PECL) levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-ofpower (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated phase-locked loop (PLL). Applications SDH/SONET Receivers and Regenerators SDH/SONET Access Nodes Add/Drop Multiplexers ATM Switches Digital Cross-Connects Features ♦ Single +3.3V or +5.0V Power Supply ♦ Exceeds ITU/Bellcore SDH/SONET Regenerator Specifications ♦ Low Power: 237mW at +3.3V ♦ Selectable Data Inputs, Differential PECL or Analog ♦ Received-Signal-Strength Indicator ♦ Loss-of-Power and Loss-of-Lock Monitors ♦ Differential PECL Clock and Data Outputs ♦ No External Reference Clock Required Ordering Information PART TEMP RANGE PIN-PACKAGE MAX3676EHJ -40°C to +85°C 32 TQFP MAX3676EHJ+ -40°C to +85°C 32 TQFP +Denotes a lead(Pb)-free/RoHS-compliant package. Pin Configuration appears at end of data sheet. Typical Operating Circuit +3.3V +3.3V CLOL 0.01μF CF 2.2μF +3.3V 130Ω INSEL FILT PHADJ+ FIL+ PHADJ- FIL- DDI+ VCC LOL SDO+ PHOTODIODE CIN 0.01μF MAX3664 INREF ZO = 50Ω ZO = 50Ω DDISDO- 100pF 130Ω 0.1μF 0.01μF OUT+ ZO = 50Ω ADI+ 82Ω MAX3676 82Ω +3.3V 100Ω IN OUTGND ZO = 50Ω SCLKO+ ADI- 130Ω C +3.3V IN 0.01μF COMP 130Ω SCLKOZO = 50Ω VCC 220pF CFILT OLC+ OLC- GND RSSI INV VTH LOP CFILT 47nF COLC 33nF ZO = 50Ω 82Ω 82Ω R2 R1 20k ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3676 General Description MAX3676 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +6.5V Input Voltage Levels, DDI+, DDI-, ADI+, ADI- ...........................-0.5V to (VCC + 0.5V) Input Differential Voltage (ADI+) - (ADI-)...............................±3V PECL Output Currents, SDO+, SDO-, SCLKO+, SCLKO-...100mA LOL, LOP, INSEL, PHADJ+, PHADJ- .........-0.5V to (VCC + 0.5V) FIL-, OLC+, OLC-, RSSI, VTH ....................-0.5V to (VCC + 0.5V) (OLC+) - (OLC-).....................................................................±3V FIL+..................................................Internally connected to VCC CFILT ...............................................(VCC - 2.5V) to (VCC + 0.5V) INV.........................................................................-0.5V to +2.0V Continuous Power Dissipation (TA = +85°C) TQFP (derate 18.7mW/°C above +85°C) ................1214.8mW Operating Junction Temperature Range ...........-40°C to +150°C Storage Temperature Range .............................-65°C to +150°C Processing Temperature (die) .........................................+400°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Supply Current SYMBOL ICC CONDITIONS MAX3676EHJ, PECL outputs unterminated MIN TYP MAX INSEL = VCC 72 111 INSEL = GND 51 81 UNITS mA PECL Input-Voltage High VIH VCC - 1.16 VCC - 0.88 PECL Input-Voltage Low VIL VCC - 1.81 VCC - 1.48 V PECL Input-Current High IIH -10 10 μA PECL Input-Current Low IIL μA PECL Output-Voltage High VOH PECL Output-Voltage Low VOL LOP, LOL Voltage High VOH LOP, LOL Voltage Low VOL INV Input Bias Voltage -10 10 TA = 0°C to +85°C VCC - 1.025 VCC - 0.88 TA = -40°C VCC - 1.085 VCC - 0.88 TA = 0°C to +85°C VCC - 1.81 VCC - 1.620 TA = -40°C VCC - 1.83 VCC - 1.555 2.4 4kΩ between INV and VTH 1.10 V V V 1.23 Note 1: At TA = -40°C, DC characteristics are guaranteed by design and characterization. 2 V _______________________________________________________________________________________ 0.4 V 1.30 V 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier (VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN Differential Input Voltage Range VID BER < 10-10, ADI inputs (Note 4) Input-Referred Noise VN ADI inputs Power-Detect Hysteresis Limiting Amplifier SmallSignal Bandwidth RSSI Output Voltage Threshold Voltage VTH 0.003 MAX UNITS 1.2000 VP-P 80 3 (Notes 5, 6) BW TYP μVRMS 6 (Note 7) 650 (ADI+) - (ADI-) = 2mVP-P 1.40 (ADI+) - (ADI-) = 20mVP-P 1.93 MHz V 1.41 (Note 6) -2 dB V +2 LOP Threshold Accuracy (Note 6) RSSI Linearity (ADI+) - (ADI-) = 2mVP-P to 50mVP-P ±0.7 % RSSI Slope (ADI+) - (ADI-) = 2mVP-P to 50mVP-P (Note 8) 26 mV/dB Loop Bandwidth CF = 2.2μF 250 500 kHz Jitter Generation (Note 9) CF = 2.2μF 2.0 2.6 mUI Jitter-Transfer Peaking CF = 2.2μF 0.03 0.08 dB 8.9 f = 10kHz Jitter Tolerance (Note 10) CF = 2.2μF dB f = 25kHz (Note 11) 3.64 f = 250kHz 0.55 0.77 f = 1MHz 0.45 0.69 Maximum Consecutive Input Run Length (1 or 0) UI 1200 Bits Clock Transition Time tr, tf 20% to 80% 205 245 ps Data Transition Time tr, tf 20% to 80% 180 230 ps 275 400 ps Serial Clock-to-Q Delay Serial Clock Frequency tCLK-Q fSCLK 140 622.08 MHz Note 2: AC parameters are guaranteed by design and characterization. Note 3: The MAX3676 is characterized with a PRBS of 223 - 1 maintaining a BER of ≤ 10-10 having a confidence level of 99.9%. Note 4: A lower minimum input voltage of 2mVP-P is achievable; however, the LOP hysteresis is not guaranteed below 3.6mVP-P. Note 5: Hysteresis = 20log(VRELEASE/VASSERT). Note 6: R1 = 20kΩ, R2 = 3.0kΩ, resulting in VRELEASE ≈ 3.6mVP-P. Note 7: Small-signal bandwidth cannot be measured directly. Note 8: RSSI slope = [VRSSI2 - VRSSI1]/[20log (VID2/VID1)]. Note 9: 1UI = 1 unit interval = (622.08MHz)-1 = 1.608ns. Note 10: At jitter frequencies