19-1210; Rev 3; 3/07
KIT
ATION
EVALU
E
L
B
AVAILA
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
______________________________Features
The MAX3680/MAX3680A deserializer is ideal for converting 622Mbps serial data to 8-bit-wide, 77Mbps parallel data in ATM and SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts PECL serial clock and data inputs, and delivers TTL clock and data outputs. The MAX3680 also provides a TTL synchronization input that enables data
realignment and reframing.
The MAX3680/MAX3680A is available in the extendedindustrial temperature range (-40°C to +85°C), in a 28pin SSOP package.
♦ Single +3.3V Supply
__________________________Applications
________________Ordering Information
♦ 622Mbps Serial to 77Mbps Parallel Conversion
♦ 165mW Power
♦ Synchronization Input for Data Realignment and
Reframing (MAX3680)
♦ Differential 3.3V PECL Clock and Data Inputs
♦ TTL Data Outputs
622Mbps SDH/SONET Transmission Systems
PART
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
28 SSOP
MAX3680EAI+
-40°C to +85°C
28 SSOP
MAX3680AEAI
-40°C to +85°C
28 SSOP
622Mbps ATM/SONET Access Nodes
MAX3680EAI
Add/Drop Multiplexers
Digital Cross-Connects
+Denotes lead-free package.
Pin Configuration appears at end of data sheet.
___________________________________________________________________Typical Operating Circuit
VCC = +3.3V
VCC
PD7
VCC = +3.3V
VCC = +3.3V
130Ω
MAX3680/
MAX3680A
130Ω
PD5
SD+
PHOTODIODE
MAX3675
PD6
SDPD4
82Ω
PREAMP
100Ω
LIMITING
AMP
DATA
AND
CLOCK
RECOVERY
OVERHEAD
TERMINATION
82Ω
PD3
VCC = +3.3V
MAX3664
PD2
130Ω
130Ω
PD1
SCLK+
SCLK-
PD0
82Ω
82Ω
PCLK
SYNC
GND
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3680/MAX3680A
_________________General Description
MAX3680/MAX3680A
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
VCC ........................................................................-0.5V to +5V
PECL Inputs (SD+/-, SCLK+/-) ................-0.5V to (VCC + 0.5V)
TTL Input (SYNC) ....................................-0.5V to (VCC + 0.5V)
TTL Outputs (PCLK, PD_)........................-0.5V to (VCC + 0.5V)
Continuous Power Dissipation (TA = +85°C)
SSOP (derate 9.52mW/°C above +85°C) .....................619mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.)
PARAMETER
Supply Current
SYMBOL
ICC
CONDITIONS
TTL outputs = high
MIN
TYP
MAX
UNITS
25
50
90
mA
V
PECL INPUTS (SD+/-, SCLK+/-)
Input High Voltage
VIH
VCC - 1.16
VCC - 0.88
Input Low Voltage
VIL
VCC - 1.81
VCC - 1.48
V
Input High Current
IIH
VIN = VIH(MAX)
-10
10
µA
Input Low Current
IIL
VIN = VIL(MAX)
-10
10
µA
TTL INPUT AND OUTPUTS (SYNC, PCLK, PD_) (Note 1)
Input High Voltage
VIH
Input Low Voltage
VIL
2.0
Input High Current
IIH
VIN = VIH(MAX)
Input Low Current
IIL
V
0.8
V
-10
10
µA
VIN = VIL(MAX)
-10
10
µA
2.4
VCC
V
0
0.44
V
MAX
UNITS
Output High Voltage
VOH
Output sourcing = 400µA
Output Low Voltage
VOL
Output sinking = 400µA
Note 1: The SYNC input is available only on the MAX3680.
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
Maximum Serial Clock Frequency
SYMBOL
CONDITIONS
MIN
TYP
fSCLK
622
MHz
Serial Data Setup Time
tSU
800
ps
Serial Data Hold Time
tH
50
Parallel Clock to Data Output Delay
tCLK-Q
VCC = +3.3V, CL = 18pF
-200
ps
500
Note 2: AC characteristics guaranteed by design and characterization.
2
_______________________________________________________________________________________
2000
ps
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
SERIAL DATA SETUP TIME
vs. TEMPERATURE
MAXIMUM SERIAL-CLOCK FREQUENCY
vs. TEMPERATURE
1.2
1.1
1.0
0.9
MAX3680-02
MAX3680-01
400
SERIAL DATA-SETUP TIME (ps)
360
320
280
240
200
0.8
-50
-25
0
25
50
75
100
-50
-25
25
50
75
100
SUPPLY CURRENT
vs. TEMPERATURE
SERIAL DATA HOLD TIME
vs. TEMPERATURE
70
MAX3680-03
-100
VCC = +3.6V
60
-160
SUPPLY CURRENT (mA)
SERIAL DATA-HOLD TIME (ps)
0
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX3680-04
SERIAL CLOCK FREQUENCY (GHz)
1.3
-220
-280
50
VCC = +3.3V
40
VCC = +3.0V
30
20
-340
10
0
-400
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
3
MAX3680/MAX3680A
__________________________________________Typical Operating Characteristics
(VCC = +3.0V to +3.6V, unless otherwise noted.)
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
MAX3680/MAX3680A
Pin Description
PIN
NAME
FUNCTION
MAX3680
MAX3680A
1, 2, 5, 8,
14, 18, 25
1, 2, 5, 8,
14, 18, 25
VCC
+3.3V Supply Voltage
3
3
SD+
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive
transition.
4
4
SD-
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6
6
SCLK+
Noninverting PECL Serial Clock Input
7
7
SCLK-
Inverting PECL Serial Clock Input
9, 11, 12,
16, 20, 23,
27
11, 12, 16,
20, 23, 27
GND
Ground
10
—
SYNC
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data
alignment by dropping one bit in the serial input data stream.
—
9, 10
N.C.
No Connection
13
13
PCLK
TTL Parallel Clock Output
15, 17, 19,
21, 22, 24,
26, 28
15, 17, 19,
21, 22, 24,
26, 28
PD0–PD7
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the
relationship between serial-data-bit position and output-data-bit assignment.
Detailed Description
The MAX3680/MAX3680A deserializer uses an 8-bit
shift register, 8-bit parallel output register, 3-bit counter,
PECL input buffers, and TTL input/output buffers to
convert 622Mbps serial data to 8-bit-wide, 77Mbps parallel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel output
clock (PCLK) by dividing down the serial clock frequency. The PCLK signal is used to clock the parallel output
register. During normal operation, the counter divides the
SCLK frequency by eight, causing the output register to
latch every eight bits of incoming serial data.
The MAX3680 synchronization input (SYNC) is used for
data realignment and reframing. When the SYNC signal
is pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
4
TTL
SD+
SD-
8-BIT
SHIFT
REGISTER
SCLK+
SCLK-
TTL
PECL
TTL
PECL
TTL
8-BIT
PARALLEL
OUTPUT
REGISTER
TTL
TTL
MAX3680/
MAX3680A
TTL
TTL
SYNC
TTL
3-BIT
COUNTER
Figure 1. Functional Diagram
_______________________________________________________________________________________
TTL
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLK
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
MAX3680/MAX3680A
SCLK*
SD*
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
PCLK
PD7
D8-
D0
D8
PD6
D7-
D1
D9
PD5
D6-
D2
D10
PD4
D5-
D3
D11
PD3
D4-
D4
D12
PD2
D3-
D5
D13
PD1
D2-
D6
D14
PD0
D1-
D7
D15
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2a. Functional Timing Diagram—Normal Operation
_______________________________________________________________________________________
5
MAX3680/MAX3680A
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
SCLK*
SD*
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
SYNC
PCLK
PD7
D8-
D1
D9
PD6
D7-
D2
D10
PD5
D6-
D3
D11
PD4
D5-
D4
D12
PD3
D4-
D5
D13
PD2
D3-
D6
D14
PD1
D2-
D7
D15
PD0
D1-
D8
D16
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2b. Functional Timing Diagram—SYNC Operation (MAX3680)
tSCLK = 1 / fSCLK
SCLK*
tSU
tH
SD*
PCLK
tCLK-Q
PD0–PD7
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 3. Timing Parameters
6
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
Applications Information
THEVENIN-EQUIVALENT TERMINATION
+3.3V
130Ω
130Ω
MAX3680/
MAX3680A
ZO = 50Ω
Alternative PECL Input Termination
Figure 4 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
(VCC - 2V) termination voltage is not available. If AC
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termination.
MAX3680/MAX3680A
PECL Inputs
The serial data and clock PECL inputs (SD+, SD-,
SCLK+, SCLK-) require 50Ω termination to (VCC - 2V)
when interfacing with a PECL source (see Alternative
PECL Input Termination).
PECL
INPUTS
ZO = 50Ω
82Ω
82Ω
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3680 data inputs.
ECL AC-COUPLING TERMINATION
+3.3V
1.6k
1.6k
ZO = 50Ω
MAX3680/
MAX3680A
50Ω
Pin Configuration
ZO = 50Ω
PECL
INPUTS
-2V
TOP VIEW
50Ω
VCC 1
28 PD7
VCC 2
27 GND
SD+ 3
26 PD6
SD- 4
25 VCC
VCC 5
SCLK+ 6
MAX3680/
MAX3680A
2.7k
2.7k
-2V
Figure 4. Alternative PECL Input Termination
24 PD5
23 GND
SCLK- 7
22 PD4
VCC 8
21 PD3
GND
(N.C.) 9
SYNC
(N.C.) 10
19 PD2
GND 11
18 VCC
GND 12
17 PD1
PCLK 13
16 GND
VCC 14
15 PD0
20 GND
Chip Information
TRANSISTOR COUNT: 1346
SSOP
() MAX3680A ONLY.
_______________________________________________________________________________________
7
________________________________________________________Package Information
2
SSOP.EPS
MAX3680/MAX3680A
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
1
INCHES
E
H
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
0.068
0.078
1.73
1.99
A1
0.002
0.008
0.05
0.21
B
0.010
0.015
0.25
0.38
C
0.09
0.20
0.004 0.008
SEE VARIATIONS
D
E
e
0.205
0.212
0.0256 BSC
5.20
MILLIMETERS
INCHES
D
D
D
D
D
5.38
MIN
MAX
MIN
MAX
0.239
0.239
0.278
0.249
0.249
0.289
6.07
6.07
7.07
6.33
6.33
7.33
0.317
0.397
0.328
0.407
8.07
10.07
8.33
10.33
N
14L
16L
20L
24L
28L
0.65 BSC
H
0.301
0.311
7.65
7.90
L
0.025
0∞
0.037
8∞
0.63
0∞
0.95
8∞
N
A
C
B
e
A1
L
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
21-0056
REV.
C
1
1
Revision History
Rev 0;
3/97:
Rev 1; 11/00:
Rev 2; 7/04:
Initial MAX3680 release.
Changed tCLK-Q max from 1300ps to 2000ps (page 2); replaced TOC3 (page 3).
Added lead-free package to Ordering Information table (page 1).
Rev 3;
Added MAX3680A (pages 1, 2, 4, 6, 7).
3/07:
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
