MAX3815CCM+TD

19-3466; Rev 2; 2/08 KIT ATION EVALU E L B AVAILA TMDS Digital Video Equalizer for DVI/HDMI Cables The MAX3815 cable equalizer automatically provides compensation for DVI™, HDMI™, DFP, PanelLink®, and ADC cables. It extends the usable cable distance up to 36 meters. The MAX3815 is designed to equalize signals encoded in the transition-minimized differential signaling (TMDS®) format. The MAX3815 features four CML-differential inputs and outputs (three data and one clock). It provides a lossof-signal (LOS) output that indicates loss-of-clock signal. The outputs include a disable function or the equalizer can be powered down to conserve power. For direct chip-to-chip communication, the output drivers can be switched to one-half the DVI output specification to conserve power and reduce EMI. Equalization can be automatic or set to manual control for specific in-cable applications. The MAX3815 is available in a 7mm x 7mm, 48-pin TQFP-EP package and operates over a 0°C to +70°C temperature range. Features ♦ Extends TMDS Cable Reach to Projectors or Monitors Using DVI, DFP, PanelLink, ADC, or HDMI Interfaces ♦ Extends TMDS Interface Length as Follows: 0 to 50 Meters Over DVI-Cable, 24 AWG STP (Shielded-Twisted Pair) 0 to 36 Meters Over DVI-Cable, 28 AWG STP 0 to 30 Meters Over DVI-Cable, 30 AWG STP ♦ Compatible with DTV Resolutions 480i, 480p, 720p, 1080i, and 1080p ♦ Compatible with Computer Resolutions VGA, SVGA, XGA, SXGA, UXGA ♦ Fully Automatic Equalization Up to 40dB at 825MHz (1.65Gbps), No System Control Required ♦ 3.3V Power Supply ♦ Power Dissipation of 0.6W (typ) ♦ 7mm x 7mm 48-Pin TQFP Lead-Free Package Applications Front-Projector DVI/HDMI Inputs Ordering Information TEMP RANGE PART High-Definition Televisions and Displays DVI-D/HDMI Cable-Extender Modules and Active Cable Assemblies PINPACKAGE PKG CODE MAX3815CCM 0°C to +70°C 48 TQFP-EP* C48E-8 MAX3815CCM+ 0°C to +70°C 48 TQFP-EP* C48E-8 +Denotes lead-free package. *EP = Exposed pad. LCD Computer Monitors Pin Configuration appears at end of data sheet. Typical Application Circuits LAPTOP RGB/HV ADC/SYNC VGA INPUT DVI-D INPUT MAX3815 EQUALIZER TMDS DESERIALIZER SELECT VIDEO PROJECTOR IMAGE SCALER AND PROCESSOR PANEL INTERFACE TIMING AND DRIVERS LCD, DLP, OR LCOS DVI-D CABLE UP TO 36m OR 120ft (28AWG STP) Typical Application Circuits continued at end of data sheet. DVI is a trademark of Digital Display Working Group. HDMI is a trademark of HDMI Licensing, LLC. PanelLink and TMDS are registered trademarks of Silicon Image, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3815 General Description MAX3815 TMDS Digital Video Equalizer for DVI/HDMI Cables ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC ..............................................-0.5V to +4.0V Voltage at All I/O Pins.................................-0.5V to (VCC + 0.7V) Voltage between any CML I/O Complementary Pair ..........±3.3V Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP-EP (derate 36.2mW/°C above +70°C) ..2896mW Operating Junction Temperature Range ...........-55°C to +150°C Storage Temperature Range .............................-55°C to +150°C Die Attach Temperature...................................................+400°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +70°C. Typical Values are at VCC = +3.3V, external terminations = 50Ω ±1%, TMDS rate = 250Mbps to 1.65Gbps, TA = +25°C, unless otherwise noted.) PARAMETER Power-Supply Current SYMBOL ICC Supply-Noise Tolerance CONDITIONS MIN TYP MAX PWRDWN = HIGH 165 230 PWRDWN = LOW 10 DC to 500kHz 200 UNITS mA mVP-P EQUALIZER PERFORMANCE 1dB skin-effect loss at 825MHz Residual Output Jitter (Cables Only) 0.25Gbps to 1.65Gbps (Notes 1, 2, and 3) 0.2 24dB skin-effect loss at 825MHz 0.2 40dB skin-effect loss at 825MHz 0.2 CID Tolerance 20 UI Bits CONTROL AND STATUS Differential peak-to-peak at EQ input with 165MHz clock CLKLOS Assert Level 50 mVP-P CML INPUTS (CABLE SIDE) Differential Input Voltage Swing VID At cable input Common-Mode Input Voltage VCM Input Resistance RIN Single-ended VOD 50Ω load, each side to VCC 800 1000 VCC 0.4 1400 mVP-P VCC + 0.1 V Ω 45 50 55 OUTLEVEL = HIGH 800 1000 1200 OUTLEVEL = LOW 350 500 650 CML OUTPUTS (ASIC SIDE) Differential Output-Voltage Swing Output-Voltage High Single-ended, OUTLEVEL = HIGH Output-Voltage Low Single-ended, OUTLEVEL = HIGH VCC 600 VCC 400 mV Output Voltage During Power-Down Single-ended, PWRDWN = LOW VCC 10 VCC +10 mV 2 VCC mVP-P _______________________________________________________________________________________ mV TMDS Digital Video Equalizer for DVI/HDMI Cables (VCC = +3.0V to +3.6V, TA = 0°C to +70°C. Typical Values are at VCC = +3.3V, external terminations = 50Ω ±1%, TMDS rate = 250Mbps to 1.65Gbps, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Common-Mode Output Voltage 50Ω load, each side to VCC, OUTLEVEL = HIGH Rise/Fall Time (Note 1) 20% to 80% MIN TYP MAX VCC 0.25 80 UNITS V 130 200 ps LVTTL CONTROL AND STATUS INTERFACE LVTTL Input High Voltage VIH LVTTL Input Low Voltage VIL 2.0 LVTTL Input High Current V 0.8 V -50 µA -100 µA VIH(MIN) < VIN < VCC LVTTL Input Low Current GND < VIN < VIL(MAX) Open-Collector Output High RLOAD ≥ 10kΩ to VCC Open-Collector Output Low RLOAD ≥ 2kΩ to VCC 2.4 V Open-Collector Output Sink 0.4 V 5 mA Note 1: AC specifications are guaranteed by design and characterization. Note 2: Cable input swing is 800mV to 1400mV differential peak-to-peak. Residual output jitter is defined as peak-to-peak deterministic jitter + 14.2 times random jitter. Note 3: Test pattern is a 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros. Typical Operating Characteristics (Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE OUTLEVEL = HIGH -15 160 -20 GAIN (dB) SUPPLY CURRENT (mA) -5 -10 170 150 140 130 -25 -30 -45 100 -50 20 30 40 50 TEMPERATURE (°C) 350mV/div -40 110 10 60 70 DATA RATE = 1.65Gbps 40dB CABLE SKIN-EFFECT LOSS AT 825MHz 128mV/div -35 OUTLEVEL = LOW 120 0 MAX3815 toc02 190 MAX3815 toc03 0 MAX3815 toc01 200 180 EQUALIZER INPUT AFTER 205ft OF GORE 89 CABLE (TOP) EQUALIZER OUTPUT (BOTTOM) DIFFERENTIAL INPUT RETURN LOSS vs. FREQUENCY 0 500 1000 1500 2000 2500 3000 5ns/div FREQUENCY (MHz) _______________________________________________________________________________________ 3 MAX3815 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, unless otherwise noted.) EQUALIZER INPUT EYE AFTER 205ft OF GORE 89 CABLE (TOP) EQUALIZER OUTPUT (BOTTOM) EQUALIZER INPUT EYE AFTER 205ft OF GORE 89 CABLE (TOP) EQUALIZER OUTPUT (BOTTOM) MAX3815 toc04 EQUALIZER EYES AFTER 100ft MADISON DIGITAL FLAT-PANEL CABLE, 28 AWG (DATA RATE = 1.65Gbps) MAX3815 toc06 MAX3815 toc05 DATA RATE = 250Mbps 40dB CABLE SKIN-EFFECT LOSS AT 825MHz DATA RATE = 1.65Gbps 40dB CABLE SKIN-EFFECT LOSS AT 825MHz 350mV/div 350mV/div 300mV/div 152ps/div 1ns/div 200ps/div EQUALIZER EYES AFTER 100ft MADISON DIGITAL FLAT-PANEL CABLE, 28 AWG (DATA RATE = 350Mbps) EQUALIZER EYES AFTER 3ft CABLE (DATA RATE = 1.65Gbps) JITTER vs. DATA RATE AFTER 205ft CABLE WITH 40dB SKIN-EFFECT LOSS AT 825MHz MAX3815 toc08 120 MAX3815 toc09 MAX3815 toc07 GORE 89 CABLE 350mV/div JITTER (psP-P) 100 350mV/div RESIDUAL JITTER = DJ + 14.2 x RJ 80 60 40 20 DETERMINISTIC JITTER 0 1ns/div 250 200ps/div 450 650 850 1050 1250 1450 1650 DATA RATE (Mbps) DETERMINISTIC JITTER vs. CABLE LENGTH (TENSOLITE TWIN-AX 28 AWG) 160 150 140 130 120 0.5 800Mbps 0.4 250Mbps NO EQ 0.3 WITH MAX3815 EQ 0.2 0.1 110 1 10 100 1000 FREQUENCY (kHz) 10,000 100,000 120 110 205ft OF GORE 89 CABLE WITH 40dB SKINEFFECT LOSS AT 825MHz RESIDUAL JITTER = DJ + 14.2 X RJ 100 90 80 70 0 100 4 1.65Gbps RESIDUAL JITTER (psP-P) TOTAL JITTER (psP-P) 170 0.6 RESIDUAL JITTER vs. SIGNAL AMPLITUDE INPUT TO CABLE (DATA RATE = 1.65Gbps) MAX3815 toc11 NOISE AMPLITUDE: 200mVP-P DATA THROUGH 100ft MADISON DIGITAL FLAT-PANEL CABLE, 28AWG DETERMINISTIC JITTER (UIP-P) 180 MAX3815 toc10 TOTAL JITTER vs. POWER-SUPPLY NOISE FREQUENCY (DATA RATE = 1.65Gbps) MAX3815 toc12 MAX3815 TMDS Digital Video Equalizer for DVI/HDMI Cables 60 0 50 100 CABLE LENGTH (ft) 150 200 0.6 0.8 1.0 1.2 DIFFERENTIAL AMPLITUDE (mVP-P) _______________________________________________________________________________________ 1.4 TMDS Digital Video Equalizer for DVI/HDMI Cables -0.2 -0.3 -0.4 180 160 140 120 EQCONTROL VOLTAGE -0.5 100 -0.6 80 60 -0.7 RESIDUAL JITTER AT 1.65Gbps -0.8 -0.9 -1.0 0 20 40 60 80 CABLE IS TENSOLITE TWIN-AX 28 AWG 100 RESIDUAL JITTER (psP-P) EQCONTROL VOLTAGE (V) -0.1 200 200mV/div 40 20 0 120 350 MAX3815 toc15 CABLE IS TENSOLITE TWIN-AX 28 AWG WITH APPROXIMATELY 0.34dB OF LOSS PER FOOT AT 825MHz MAX3815 toc14 DIFFERENTIAL CLOCK AMPLITUDE (mVP-P) MAX3815 toc13 0 LOSS-OF-CLOCK ASSERT THRESHOLD vs. CABLE LENGTH EQUALIZER OUTPUT EYE AFTER 120ft OF CABLE (DATA RATE = 1.65Gbps) EQCONTROL VOLTAGE (RELATIVE TO VCC) vs. CABLE LENGTH (MANUAL EQ CONTROL) CABLE IS TENSOLITE TWIN-AX 28 AWG 300 250 200 165MHz CLOCK FREQUENCY 150 100 50 25MHz CLOCK FREQUENCY 0 100ps/div 0 20 40 60 80 100 120 CABLE LENGTH (ft) CABLE LENGTH (ft) Pin Description PIN NAME 1, 4, 5, 8, 9, 12, 13, 16, 38, 41, 43, 44 VCC FUNCTION Supply Voltage. All pins must be connected to VCC. 2 RX0_IN- 3 RX0_IN+ Negative Data Input, CML Positive Data Input, CML 6 RX1_IN- Negative Data Input, CML 7 RX1_IN+ Positive Data Input, CML 10 RX2_IN- Negative Data Input, CML 11 RX2_IN+ Positive Data Input, CML 14 RXC_IN+ Positive Clock Input, CML 15 RXC_IN- Negative Clock Input, CML 17 Equalizer Control. This pin allows the user to control the equalization level of the MAX3815. Connect the pin to GND for automatic operation. Set the voltage to VCC / 2 for minimum equalization, or set EQCONTROL the voltage between VCC - 1V to VCC for manual equalization. See the Typical Operating Characteristics for more information. 18 CLKLOS Loss-of-Clock Signal Output, LVTTL Open Collector. This pin asserts low upon loss of the input TMDS clock from the cable. 19 PWRDWN Power-Down Input, LVTTL. This input allows the IC to be powered down to conserve power. Connect high for normal operation. Pull low for power-down mode. _______________________________________________________________________________________ 5 MAX3815 Typical Operating Characteristics (continued) (Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, unless otherwise noted.) TMDS Digital Video Equalizer for DVI/HDMI Cables MAX3815 Pin Description (continued) PIN NAME 20, 23, 24, 25, 28, 29, 32, 33, 36, 37, 42 GND FUNCTION Ground 21 RXC_OUT- 22 RXC_OUT+ Negative Clock Output, CML Positive Clock Output, CML 26 RX2_OUT+ Positive Data Output, CML 27 RX2_OUT- Negative Data Output, CML 30 RX1_OUT+ Positive Data Output, CML 31 RX1_OUT- Negative Data Output, CML 34 RX0_OUT+ Positive Data Output, CML 35 RX0_OUT- Negative Data Output, CML 39 OUTLEVEL Output-Level Control Input, LVTTL. This input sets the output amplitude to the standard DVI level (1000mVP-P) when high, and sets the output amplitude to 1/2 the DVI level (500mVP-P) when low. 40 OUTON 45–48 N.C. EP Exposed Pad Output-Enable Control Input, LVTTL. This input enables the CML outputs when forced low and sets a differential logic zero when forced high. No Connection Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal and electrical operation. Detailed Description The MAX3815 TMDS equalizer accepts differential CML input data at rates of 250Mbps up to 1.65Gbps (individual channel data rate). It automatically adjusts to attenuation levels of up to 40dB at 825MHz due to skin-effect losses in copper cable. It consists of four CML input buffers, a loss-of-clock signal detector, three independent adaptive equalizers, four limiting amplifiers, and four output buffers (Figure 1). CML Input Buffers and Output Drivers The input buffers and the output drivers are implemented using current-mode logic (CML) (see Figures 3 and 4). The output drivers are open-collector and can be turned off with the OUTON pin, or can be set to output a one-half amplitude signal (500mV P-P differential) using the OUTLEVEL pin. For details on interfacing with CML, refer to Maxim Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML. Loss-of-Clock Signal Detector The loss-of-clock signal detector indicates a loss-ofclock signal at the CLKLOS pin. 6 Adaptive Equalizer The three data channels each contain an independent adaptive equalizer. Each channel analyzes the incoming signal and determines the amount of equalization to apply. Limiting Amplifier The limiting amplifier amplifies the signal from the adaptive equalizer and truncates the top and bottom of the waveform to provide a clean high- and low-level signal to the output drivers. Applications Information Typical shielded twisted pair (STP) and unshielded twisted pair (UTP) cables exhibit skin-effect losses, which attenuate the high-frequency spectrum of a TMDS signal, eventually causing data errors or even closing the signal eye altogether given a long enough cable. The MAX3815 recovers the data and opens the signal eye through compensating equalization. The basic TMDS interface is composed of four differential serial links: three links carry serial data up to 1.65Gbps each, and the fourth is a one-tenth-rate (0.1x) clock that operates up to 165MHz. TMDS, as with _______________________________________________________________________________________ TMDS Digital Video Equalizer for DVI/HDMI Cables RX1_IN+/- RX0_IN+/- TERMINATED 3.3V CML TERMINATED 3.3V CML TERMINATED 3.3V CML INPUT BUFFER ADAPTIVE EQ LIMITING AMPLIFIER DRIVER RX2_OUT+/- INPUT BUFFER ADAPTIVE EQ LIMITING AMPLIFIER DRIVER RX1_OUT+/- INPUT BUFFER ADAPTIVE EQ LIMITING AMPLIFIER DRIVER RX0_OUT+/- MAX3815 RX2_IN+/- EQCONTROL RXC_IN+/- TERMINATED 3.3V CML CLKLOS CLOCK LOS DETECTOR LIMITING AMPLIFIER INPUT BUFFER DRIVER RXC_OUT+/- OUTON MAX3815 OUTLEVEL Figure 1. Functional Diagram analog nVGA links, must handle a variety of resolutions and screen update rates. The actual range of digital serial rates is roughly 250Mbps to 1.65Gbps. For applications requiring ultra-high resolutions (e.g., QXGA), a “double-link” TMDS interface is used and is composed of six data links plus the clock, requiring two MAX3815 ICs with the clock going to both ICs. See Figure 2. The MAX3815 can be used to extend any TMDS interface as used under the following trademarked names: DVI (digital visual interface), DFP™ (digital flat-panel), PanelLink, ADC™ (Apple display connector), and HDMI (high-definition multimedia interface). D0 D0 D1 D1 D2 D2 MAX3815 CLK D3 CLK MAX3815 D3 D4 D4 D5 D5 Loss-of-Clock Signal (CLKLOS) Output Loss-of-clock signal is indicated by the CLKLOS output. A low level on CLKLOS indicates that the signal power on the RXC_IN pins has dropped below a threshold. When there is sufficient input voltage to the channel (typically greater than 100mVP-P differential), CLKLOS is high. The CLKLOS output is suitable for indicating problems with the transmission link caused by, for example, a broken cable, a defective driver, or a lost connection to the equalizer. Figure 2. Connection Scheme for MAX3815 in Dual Link Application ADC is a trademark of Apple Computer, Inc. DFP is a trademark of Video Electronics Standards Association (VESA). _______________________________________________________________________________________ 7 MAX3815 TMDS Digital Video Equalizer for DVI/HDMI Cables A squelching function can be created by sending the CLKLOS output through an inverter to the OUTON pin. This will squelch the CML outputs whenever the clock signal is removed. A loss-of-signal LED indicator can be incorporated into the circuit as well (see Figure 3). VCC 10kΩ Output Level Control (OUTLEVEL) Input The OUTLEVEL pin is an LVTTL input that allows the user to select between standard output amplitude (1000mVP-P differential) or one-half output amplitude (500mVP-P differential). Forcing this pin high results in the standard output signal level, and forcing this pin low results in the reduced output signal level. Equalizer Control (EQCONTROL) Input The EQCONTROL pin allows the user to control the equalization in one of three ways: forcing the pin to ground sets the equalizer in automatic equalization mode, forcing the pin to VCC / 2 sets the equalizer to minimum equalization, and forcing a voltage between VCC - 1V to VCC allows manual control of the equalization level applied to the input signals. See the Typical Operating Characteristics for more information. Power-Down (PWRDWN) Input The PWRDWN pin allows the part to be powered down to reduce system power consumption. Force the pin high for normal operation. Force the pin low to powerdown the IC. When powered down, the part consumes approximately 10mA. 4.7kΩ CLKLOS OUTON 200Ω LOSS-OF-CLOCK LED Figure 3. Squelch Circuit Output On (OUTON) Input The OUTON pin is an LVTTL input. Force the pin low to enable the outputs. Force the pin high to set a differential zero on the outputs. When disabled, the outputs will go to a differential zero, irrespective of the signal at the inputs. Cable Selection TMDS performance is heavily dependent on cable quality. Deterministic jitter (DJ) can be caused by differential-to-common-mode conversion (or vice-versa) Interface Models VCC MAX3815 MAX3815 VCC RX_OUT+ RX_OUT- 50Ω RX_IN+/- Figure 4. Simplified Input Circuit Schematic 8 Figure 5. Simplified Output Circuit Schematic _______________________________________________________________________________________ TMDS Digital Video Equalizer for DVI/HDMI Cables TYPICAL MAX3815 CABLE REACH 60 CABLE LENGTH (meters) 50 15 X38 NGE MA H RA Gbps = EA GT .65 AR EN O 1 ED BLE L UP T D A SH LE CA ATES IR AB US LL DV A T A 40 30 20 10 AT NGTH WITHOUT EQ LIMIT OF CABLE LE 1.65Gbps • An uninterrupted ground plane should be positioned beneath the high-speed I/Os. • Ground-path vias should be placed close to the IC and the input/output interfaces to allow a return current path to the IC and the DVI cable. • Maintain 100Ω differential transmission line impedance into and out of the MAX3815. • Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. TYPICAL DVI WIRE GAUGE RANGE 5 32 AWG 30 AWG 28 26 AWG AWG DVI WIRE GAUGE 24 AWG 22 AWG Figure 6. Cable Reach within a twisted pair (STP or UTP), usually a result of cable twist or dielectric imbalance. Refer to Application Note HFAN-04.5.4: ‘Jitter Happens’ when a Twisted Pair is Unbalanced for more information. Layout Considerations The data and clock inputs are the most critical paths for the MAX3815 and great care should be taken to minimize discontinuities on these transmission lines between the connector and the IC. Here are some suggestions for maximizing the performance of the MAX3815: • The data and clock inputs should be wired directly between the cable connector and IC without stubs. Exposed-Pad Package The exposed pad on the 48-pin TQFP-EP provides a very low thermal resistance path for heat removal from the IC. The pad is also electrical ground on the MAX3815 and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Maxim Application Note HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for additional information. Chip Information PROCESS: SiGe BiPOLAR Package Information (For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE TYPE DOCUMENT NO. 48 TQFP 21-0065 _______________________________________________________________________________________ 9 MAX3815 • Input and output data channel designations are only a guide. Polarity assignments can be swapped and channel paths can be interchanged. TMDS Digital Video Equalizer for DVI/HDMI Cables MAX3815 Typical Application Circuits (continued) DVI-D OR HDMI EXTENDER BOX UP TO 36m OF DVI-D OR HDMI CABLE (28 AWG) STANDARD LENGTH DVI-D OR HDMI CABLE MAX3816 DDC EXTENDER HDTV MAX3815 EQUALIZER VIDEO SOURCE DIGITAL BROADCAST DIGITAL CABLE DIGITAL SATELLITE DVD Blu-ray Disc™ Blu-ray Disc IS A TRADEMARK OF Blu-ray DISC ASSOCIATION. GND VCC OUTLEVEL VCC GND VCC VCC N.C. N.C. N.C. N.C. TOP VIEW OUTON Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 GND VCC 1 RX0_IN- 2 35 RX0_OUT- RX0_IN+ 3 34 RX0_OUT+ VCC 4 33 GND VCC 5 32 GND RX1_IN- 6 31 RX1_OUT- MAX3815 RX1_IN+ 7 30 RX1_OUT+ VCC 8 29 GND VCC 9 28 GND RX2_IN- 10 27 RX2_OUT- RX2_IN+ 11 26 RX2_OUT+ VCC 12 25 GND GND GND RXC_OUT+ RXC_OUT- GND PWRDWN CLKLOS EQCONTROL VCC RXC_IN- RXC_IN+ VCC 13 14 15 16 17 18 19 20 21 22 23 24 48 TQFP-EP 10 ______________________________________________________________________________________ TMDS Digital Video Equalizer for DVI/HDMI Cables REVISION NUMBER REVISION DATE 0 10/04 1 2 DESCRIPTION PAGES CHANGED Initial release. — 8/05 Removed future status from the lead-free package in the Ordering Information table. 1 2/08 Removed reference to the schematic and board layers in the Layout Considerations section. 9 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX3815 Revision History