MAX3981UTH+T

19-2178; Rev 2; 12/08 3.125Gbps XAUI Quad Cable Equalizer Features The MAX3981 quad equalizer provides compensation for transmission medium losses for four “lanes” of digital NRZ data at a data rate of 3.125Gbps in one package. It is tailor-made for 10Gigabit Ethernet applications that require attenuation of noise and jitter that occur in communicating with chassis-to-chassis interconnect. In support of IEEE-802.3ae for the XAUI interface, the MAX3981 adaptively allows XAUI lanes to reach 10m (33ft) with inexpensive twin-axial cable for extended backplane applications. The equalizer has 100Ω differential CML data inputs and outputs. The MAX3981 is available in a 44-pin exposed-pad QFN package. The MAX3981 consumes only 700mW at 3.3V or 175mW per channel. ♦ Four Differential Digital Data “Lanes” at 3.125Gbps ♦ Span 10m (33ft) of Twin-Axial Cable ♦ Receiver Equalization Reduces Intersymbol Interference (ISI) ♦ Low Power, 175mW per Channel ♦ Standby Mode—Power-Down State ♦ Single 3.3V Supply ♦ Signal Detect Ordering Information Applications IEEE–802.3ae XAUI Interface (3.125Gbps) PART TEMP RANGE PIN-PACKAGE MAX3981UGH 0°C to +85°C 44 QFN-EP* *EP = Exposed pad. InfiniBandSM (2.5Gbps) Pin Configuration appears at end of data sheet. Typical Operating Circuit SWITCH CARD LINE CARD PMD Rx MAC Tx 4 Rx SWITCH 4 Tx IN 4 x 3.125Gbps 3.3V SUPPLY 10GbE Tx Rx 4 Tx Rx 4 OUT MAX3981 OUT MAX3981 4 Rx 3.3V SUPPLY 4 IN Tx 10m (33ft)100Ω TWIN-AX CABLE InfiniBand is a trademark and service mark of the InfiniBand Trade Association. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3981 General Description MAX3981 3.125Gbps XAUI Quad Cable Equalizer ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +85°C) 44-Pin QFN-EP (derate 26.3mW/°C above +85°C)....2105mW Operating Ambient Temperature Range ................0°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Supply Voltage, VCC..............................................-0.5V to +4.0V Voltage at SDET .........................................-0.5V to (VCC + 0.5V) Voltage at IN_±...........................................-0.5V to (VCC + 0.5V) Current Out of OUT_±.......................................-25mA to +25mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, input data rate = 3.125Gbps, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP EN = TTL low Supply Power MAX 0.25 EN = TTL high 0.7 0.9 UNITS W 10Hz < f < 100Hz 100 Supply Noise Tolerance 100Hz < f < 1MHz 40 Signal Detect Assert Input signal level to assert SDET (Note 1) Signal Detect Deassert Input signal level to deassert SDET (Note 1) 30 mVp-p Signal Detect Delay Delay time in detecting a change in presence of a signal (Note 4) 10 µs Latency From input to output 1MHz < f < 2.5GHz mVp-p 10 100 mVp-p 0.32 ns CML RECEIVER INPUT XAUI transmitter output measured differentially at point A, Figure 1, using K28.5 pattern (Note 4) Input Voltage Swing Return Loss 100MHz to 2.5GHz Input Resistance Differential 200 800 12 80 100 mVp-p dB 120 Ω EQUALIZATION Residual Jitter Random Jitter Total jitter (Notes 2, 4) 0.3 Deterministic jitter (Note 4) 0.2 (Note 2) 1.5 UIp-p psRMS CML TRANSMITTER OUTPUT (into 100Ω ±1Ω) Output Voltage Swing Differential swing 550 VCC 0.3 Common-Mode Voltage Transition Time tf, tr 20% to 80% (Notes 3, 4) Differential Skew Difference in 50% crossing between OUT_+ and OUT_- (Note 4) Output Resistance Single ended 2 850 60 40 50 _______________________________________________________________________________________ mVp-p V 130 ps 12 ps 60 Ω 3.125Gbps XAUI Quad Cable Equalizer (VCC = +3.0V to +3.6V, input data rate = 3.125Gbps, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Voltage 0.8 V Input High Current 250 µA 500 µA TTL CONTROL PINS Input High Voltage 2.0 V Input Low Current Output High Voltage Internal 10kΩ pullup Output Low Voltage Internal 10kΩ pullup 2.4 V 0.4 V Note 1: K28.7 pattern is applied differentially at point A as shown in Figure 1. Note 2: Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 ✕ RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for the random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from mediainduced loss and not from clock source modulation. Jitter is measured at 0V at point C of Figure 1. Note 3: Using K28.7 (0011111000) pattern. Note 4: AC specifications are guaranteed by design and characterization. A SIGNAL SOURCE FR4 CABLE FR4 2" ≤ 10 FEET 2" C B MAX3981 SMA CONNECTOR MADISON #14487, 100Ω SHIELDED TWISTED PAIR SMA CONNECTOR IN OUT Figure 1. Test Conditions Referenced in the Electrical Characteristics Table _______________________________________________________________________________________ 3 MAX3981 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +3.3V, 3.125Gbps, 500mVp-p cable input with 27 - 1 PRBS, TA = +25°C, unless otherwise noted. Note: Twin-axial cable used was Tensolite, Z-Skew, 100Ω, 28AWG. Shielded twisted pair used was Madison 100Ω, 30AWG, spec #14887.) EQUALIZER OUTPUT EYE DIAGRAM AFTER 10m (33ft) OF TWIN-AXIAL CABLE MAX3981 toc03 210 NORMAL OPERATION (EN = TTL HIGH) 190 CURRENT (mA) 100mV/ div 100mV/ div EQUALIZER OPERATING CURRENT vs. TEMPERATURE MAX3981 toc02 MAX3981 toc01 EQUALIZER INPUT EYE DIAGRAM AFTER 10m (33ft) OF TWIN-AXIAL CABLE 170 150 130 110 90 STANDBY POWER (EN = TTL LOW) 70 50 50ps/div 0 50ps/div 10 20 30 40 50 60 70 80 TEMPERATURE (°C) INPUT RETURN GAIN (S11, DIFFERENTIAL, INPUT SIGNAL = -60dBm, DEVICE POWERED OFF) EQUALIZER OUTPUT EYE DIAGRAM AFTER 5m (16ft) OF SHIELDED TWISTED PAIR MAX3981 toc06 10 MAX3981 toc05 MAX3981 toc04 EQUALIZER INPUT EYE DIAGRAM AFTER 5m (16ft) OF SHIELDED TWISTED PAIR 0 GAIN (dB) -10 100mV/ div 60mV/ div -20 -30 -40 -50 50ps/div 1050 50 50ps/div 2050 3050 4050 5050 FREQUENCY (MHz) JITTER (ps) 30 20 10 30 TWIN-AXIAL (TENSOLITE) 250 200 0 0 1 2 3 4 5 6 LENGTH (m) 7 8 9 10 350 300 10 0 450 400 40 20 TWIN-AXIAL (TENSOLITE) 500 DELAY (ps) SHIELDED TWISTED PAIR (MADISON) 40 SHIELDED TWISTED PAIR (MADISON) 50 EQUALIZER LATENCY vs. TEMPERATURE MAX3981 toc08 50 4 60 MAX3981 toc07 60 EQUALIZER DETERMINISTIC JITTER vs. CABLE LENGTH (K28.5 PATTERN, 2.5Gbps) MAX3981 toc09 EQUALIZER DETERMINISTIC JITTER vs. CABLE LENGTH (K28.5 PATTERN, 3.125Gbps) JITTER (ps) MAX3981 3.125Gbps XAUI Quad Cable Equalizer 0 1 2 3 4 5 6 LENGTH (m) 7 8 9 10 0 10 20 30 40 50 60 TEMPERATURE (°C) _______________________________________________________________________________________ 70 80 90 3.125Gbps XAUI Quad Cable Equalizer PIN NAME 1, 5, 9, 13, 23, 27, 31, 35 VCC +3.3V Supply Voltage 4, 8, 12, 16, 26, 30, 34, 38 GND Supply Ground 2 IN1+ Positive Equalizer Input Channel 1, CML 3 IN1- Negative Equalizer Input Channel 1, CML 6 IN2+ Positive Equalizer Input Channel 2, CML 7 IN2- Negative Equalizer Input Channel 2, CML 10 IN3+ Positive Equalizer Input Channel 3, CML 11 IN3- Negative Equalizer Input Channel 3, CML 14 IN4+ Positive Equalizer Input Channel 4, CML 15 IN4- Negative Equalizer Input Channel 4, CML 17–22, 39–42 N.C. No Connection. Leave unconnected. 24 OUT4- 25 OUT4+ Positive Equalizer Output Channel 4, CML 28 OUT3- Negative Equalizer Output Channel 3, CML 29 OUT3+ Positive Equalizer Output Channel 3, CML 32 OUT2- Negative Equalizer Output Channel 2, CML 33 OUT2+ Positive Equalizer Output Channel 2, CML 36 OUT1- Negative Equalizer Output Channel 1, CML 37 OUT1+ 43 EN 44 SDET — EP FUNCTION Negative Equalizer Output Channel 4, CML Positive Equalizer Output Channel 1, CML Enable Equalizer Input. A TTL high selects normal operation. A TTL low selects low-power standby mode. Signal Detect Output for Channel 1. Produces a TTL high output when a signal is detected. Exposed Pad. The exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance. _______________________________________________________________________________________ 5 MAX3981 Pin Description MAX3981 3.125Gbps XAUI Quad Cable Equalizer Detailed Description Receiver and Transmitter The adaptive equalizer accepts four lanes of 3.125Gbps CML digital data signals and compensates each received signal for dielectric and skin losses. A limiting amp shapes the output of the equalizer and the output driver transmits the regenerated XAUI lanes as CML signals. The source impedance and termination impedance are 100Ω differential. General Theory of Operation Internally, the MAX3981 is comprised of signal-detect circuitry, four matched equalizers, and one equalizer control loop. The four equalizers are made up of a master equalizer and three slave equalizers. The adaptive control is generated from only channel 1. It is assumed that all channels have the same characterization in frequency content, coding, and transmission length. The master equalizer consists of the following functions: signal detect, adaptive equalizer, equalizer control, limiting and output drivers. The signal detect indicates input signal power. When the input signal level is sufficiently high, the SDET output is asserted. This does not directly control the operation of the part. The equalizer core reduces intersymbol interference (ISI), compensating for frequency-dependent, mediainduced loss. The equalization control detects the spectral contents of the input signal and provides a control voltage to the equalizer core, adapting it to dif- ferent media. The equalizer operation is optimized for short-run DC-balanced transmission codes such as 8b/10b codes. CML Input and Output Buffers The input and output buffers are implemented using current-mode logic (CML). Equivalent circuits are shown in Figures 2 and 3. For details on interfacing with CML, see Maxim application note HFAN-1.0, Interfacing Between CML, PECL, and LVDS. The common-mode voltages of the input and output are above 2.5V. ACcoupling capacitors are required when interfacing this part. Values of 0.10µF or greater are recommended. Media Equalization Equalization at the input port compensates for the highfrequency loss encountered with twin-axial cable or shielded twisted pair. This part is optimized for 10ft (3m) and 3.125Gbps; however, the part will reduce ISI for signals spanning longer distances and functions for data rates from 2Gbps to 4Gbps providing that shortlength balanced codes, such as 8b/10b, are used. Applications Information Standby Mode The standby state allows reduced-power operation. The TTL input, EN, must be set to TTL high for normal operation. A TTL low at EN forces the equalizer into the standby state. The signal EN does not affect the opera- Functional Diagram IP1, IN1 ONLY IN1+ IN1- 2 2 SIGNAL DETECT SDET OUT1+ 3 3 CML 4 3 3 EN SDET FUNCTION IS INDEPENDENT OF EN 2 3 4 4 POWER MANAGEMENT OUT1- 2 2 2 4 2 LIMITING AMP EQUALIZER 4 6 TTL 3 4 MAX3981 _______________________________________________________________________________________ 2 3 3 4 4 3.125Gbps XAUI Quad Cable Equalizer MAX3981 VCC VCC 50Ω 50Ω 1.2kΩ OUT+ 50Ω 50Ω OUT- IN+ Q1 Q2 INDATA 200μA ESD STRUCTURES ESD STRUCTURES Figure 2. CML Input Buffer tion of the signal detect (SDET) function. For constant operation, connect the EN signal directly to VCC. Signal Detect with Standby Mode Signal activity is detected on channel 1 only (IN1±). When the peak-to-peak differential voltage at IN1± is less than 30mVp-p, the TTL output SDET goes low. When the peak-to-peak differential voltage becomes greater than 100mVp-p, SDET is asserted high. SDET can be used to automatically force the equalizer into standby mode by connecting SDET directly to the EN input. When not used, SDET should not be connected. Figure 3. CML Output Buffer Layout Considerations Circuit board layout and design can significantly affect the MAX3981 performance. Use good high-frequency design techniques, including minimizing ground inductances and vias and using controlled-impedance transmission lines for the high-frequency data signals. Signals should be routed differentially to reduce EMI susceptibility and crosstalk. Power-supply decoupling capacitors should be placed as close as possible to the VCC pins. The signal-detect function continues to operate while the part is in standby mode. While connected to the EN pin, the signal detect can “wake up” the part and resume normal operation. _______________________________________________________________________________________ 7 3.125Gbps XAUI Quad Cable Equalizer Package Information MAX3981 Pin Configuration For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. VCC GND VCC IN1+ 1 33 2 32 IN1GND 3 31 4 30 VCC IN2+ 5 29 6 28 IN2GND VCC 7 27 8 26 9 25 IN3+ IN3- 10 24 MAX3981 *EP DOCUMENT NO. 44 QFN-EP G4477-1 21-0092 OUT2+ OUT2VCC GND OUT3+ OUT3VCC GND OUT4+ OUT4VCC 22 21 20 19 PACKAGE CODE N.C. N.C. N.C. N.C. 18 17 16 15 13 14 12 VCC IN4+ IN4GND N.C. N.C. 23 GND 11 PACKAGE TYPE 34 35 36 37 38 39 SDET N.C. N.C. N.C. GND OUT1+ OUT140 41 42 43 44 EN N.C. TOP VIEW QFN-EP *NOTE: EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND. 8 _______________________________________________________________________________________ 3.125Gbps XAUI Quad Cable Equalizer REVISION NUMBER REVISION DATE 0 12/01 1 5/03 DESCRIPTION Initial release. — Added the package code to the Ordering Information table. 1 Updated the 21-0092 package drawing in the Package Information section. 2 12/08 PAGES CHANGED Changed the Absolute Maximum Ratings of SDET, IN_± from +5.0V to (VCC to 0.5V) to –5.0V to (VCC to 0.5V). 8, 9 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX3981 Revision History