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MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
General Description
Benefits and Features
The MAX40025 and MAX40026 are single-supply, highspeed comparators with a typical propagation delay of
280ps. The overdrive dispersion is extremely low (typical
25ps), making these comparators ideal for time-of-flight
distance measurement applications.
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The input common mode range of 1.5V to VDD + 0.1V
is compatible with the output swings of several widely
used high-speed trans-impedance amplifiers, such as the
MAX40658.
The output stage is LVDS (Low-Voltage Differential Signaling), which helps to minimize power dissipation and interfaces directly with many FPGAs and CPUs. Complementary outputs help in suppression of common-mode
noise on each output line.
The MAX40025 is offered in a space-saving, tiny,
1.218mm x 0.818mm, 6-bump wafer-level package
(WLP), while the MAX40026 is available in a 2mm x 2mm
8-pin TDFN side-wettable package and meets AEC-Q100
automotive qualification requirements. The MAX40025/
MAX40026 operate over -40°C to +125°C temperature
range and run from a single supply voltage of 2.7V to 3.6V.
Applications
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Distance Sensing in LIDAR, RADAR, and SONAR
Time-of-Flight Sensors
High-Speed Differential Line Receivers
High-Speed Triggering in Oscilloscopes
Communications
Oscillators
Threshold Detectors
High-Speed Level-Shifting
Test and Measurement
Automotive Applications
19-100439; Rev 5; 9/19
Fast Propagation Delay: 280ps, Typ
Low Overdrive Dispersion: 25ps (VOD = 10mV to 1V)
Supply Voltage 2.7V to 3.6V
39.4mW at 2.7V Supply
Power-Efficient LVDS Outputs
-40°C to +125°C Temperature Range
Automotive AEC-Q100 Qualified (TDFN-8 Version)
Internal 1.5mV Hysteresis: MAX40026
Internal 2.5mV Hysteresis: MAX40025A
Ordering Information appears at end of data sheet.
Functional Diagram
VCC
IN+
IN-
+
MAX40025
MAX40026
GND
OUT+
LVDS
OUT-
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Absolute Maximum Ratings
VCC to GND........................................................... -0.3V to +3.6V
Either IN+ or IN- to GND .............................. -0.3V to VCC + 0.3V
Either OUT+ or OUT- to GND ...................... -0.3V to VDD + 0.3V
OUT+ to OUT- ....................................................... -0.5V to +0.5V
Current Into Any Pin (Continuous) ...................................... 10mA
Continuous Power Dissipation (Multilayer Board) (WLP) (TA =
+70°C, derate 10.51mW/°C above +70°C)....................... 816mW
Continuous Power Dissipation (Multilayer Board) (TDFN) (TA =
+70°C, derate 9.8mW/°C above +70°C.) ..........................784mW
Operating Temperature Range ...........................-40°C to +125°C
Junction Temperature ....................................................... +150°C
Storage Temperature Range ..............................-40°C to +150°C
Soldering Temperature (reflow) ........................................ +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
WLP
Package Code
W60D1+1
Outline Number
21-100296
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction-to-Ambient (θJA)
95.15°C/W
Junction-to-Case Thermal Resistance (θJC)
N/A
8-TDFN
Package Code
T822Y+3
Outline Number
21-100185
Land Pattern Number
90-100070
Thermal Resistance, Single-Layer Board:
Junction-to-Ambient (θJA)
130°C/W
Junction-to-Case Thermal Resistance (θJC)
8°C/W
Thermal Resistance, Four-Layer Board:
Junction-to-Ambient (θJA)
102°C/W
Junction-to-Case Thermal Resistance (θJC)
8°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
Electrical Characteristics
(VCC = 3.3V, VCM = 2.5V, RLOAD = 100Ω, connected from OUT+ to OUT-, TA = -40ºC to +125ºC (Note 1))
PARAMETER
SYMBOL
Supply Voltage (Note 2)
VCC
Supply Current
ICC
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CONDITIONS
Guaranteed by PSRR specification
MIN
TYP
2.7
17
MAX
UNITS
3.6
V
23
mA
Maxim Integrated | 2
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Electrical Characteristics (continued)
(VCC = 3.3V, VCM = 2.5V, RLOAD = 100Ω, connected from OUT+ to OUT-, TA = -40ºC to +125ºC (Note 1))
PARAMETER
Power-Up Time
Power Supply Rejection
Ratio (Note 2)
SYMBOL
tON
PSRR
CONDITIONS
Measured using supply current >75% of
final value
2.7V ≤ VCC ≤ 3.6V
50
1.5
Input Common Mode
Range (Note 2)
VCM
Guaranteed by CMRR specification
Input Offset Voltage
(Note 2)
VOS
Over the Input common mode range
Common Mode
Rejection Ratio (Note 2)
CMRR
Over the Input common mode range
Input Hysteresis
VHYS
Input Bias Current
IB
dB
µA
|VOUT+ - VOUT-|
247
|VOUT+ - VOUT-|
-50
Either output polarity
-50
Output Common-Mode
Transient
Either output transition polarity
350
1.23
pF
454
mV
+50
mV
1.375
V
+50
mV
18
Either output shorted to ground, either
polarity
Outputs shorted together, either polarity
mV
2
Output Common-Mode
Voltage Match
tOD-disp
80
4
1.125
Overdrive Dispersion
mV
0.1
Either output polarity
tJITTER
5
µA
VOUTDIFF
Jitter
V
10
Output Differential
Voltage
tPD
VCC +
0.1
1.3
Either input, over entire Input common
mode range
Propagation Delay
dB
Over the Input common mode range.
Inputs shorted together.
CIN
ISC
80
1.5
Input Capacitance
Output Short-Circuit
Current
µs
MAX40026
VIN+ = VIN-
VCMOUT
UNITS
20
0.5
52
MAX
2.5
IOS
Output Common-Mode
Voltage
TYP
MAX40025A
Input Offset Current
Output Differential
Voltage Match
MIN
mVp-p
24
-12
mA
+12
20mV overdrive
270
100mV overdrive
280
200mV overdrive
280
Measured using square wave with Rise
and Fall Time = 150ps, 100mV overdrive
2
10mV to 1V
25
20mV to 100mV
10
ps
ps
ps
Rise Time
tR
From 25% to 75% output swing
150
ps
Fall Time
tF
From 75% to 25% output swing
165
ps
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Maxim Integrated | 3
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Electrical Characteristics (continued)
(VCC = 3.3V, VCM = 2.5V, RLOAD = 100Ω, connected from OUT+ to OUT-, TA = -40ºC to +125ºC (Note 1))
PARAMETER
SYMBOL
Measured using
square wave with
Rise and Fall Time
= 150ps, 100mV
overdrive
Output Skew
Maximum Toggle Rate
Minimum Pulse Width
CONDITIONS
TR
VOUT = 550mV,
VOD = 100mV
MIN
TYP
Propagation Delay
difference between
OUT+ and OUT-
10
MAX40025
4
MAX40026
3
both MAX40025/ MAX40026
330
MAX
UNITS
ps
Gbps
ps
Note 1: Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization.
Note 2: Specifications are guaranteed by design and characterization and not production tested.
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Maxim Integrated | 4
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Typical Operating Characteristics
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Maxim Integrated | 5
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Typical Operating Characteristics (continued)
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Maxim Integrated | 6
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Typical Operating Characteristics (continued)
Pin Configurations
8 TDFN
TOP VIEW
6
VCC
5
IN+
3
7
GND
VCC
2
8
GND
OUT+
1
+
OUT-
MAX40026
EP
4
IN-
2mm x 2mm
WLP
TOP VIEW
MAX40025A/
MAX40025A/MAX
MAX40025C
40025C
2
3
A
IN+
VCC
OUT+
B
IN-
GND
OUT-
+
1
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Maxim Integrated | 7
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Pin Description
PIN
MAX40026
MAX40025A/
MAX40025C
NAME
FUNCTION
1
B3
OUT-
Inverting LVDS Output. Connect a 100Ω termination resistor between OUTand OUT+. OUT- is at logic-low if VIN+ is at higher voltage compared to VIN-.
2, 3
B2
GND
Ground. Signal and power return (for TDFN-8: connect pins 2 and 3 together
externally).
4
B1
IN-
Inverting Input
5
A1
IN+
Non-Inverting Input
6,7
A2
VCC
Positive Supply. For TDFN-8, connect pins 6 and 7 together externally.
8
A3
OUT+
EP
—
Exposed
Paddle
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Non-Inverting LVDS Output. Connect a 100Ω termination resistor between
OUT+ and
OUT-. OUT+ is at logic-high if VIN+ is at higher voltage compared to VIN-.
Exposed Pad (TDFN-8 Only). This pad must be connected to ground.
Maxim Integrated | 8
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Detailed Description
The MAX40025 and MAX40026 are single-supply, high-speed comparators with a typical propagation delay of 280ps.
The overdrive dispersion is extremely low (25ps, typ.), making these comparators ideal for time-of-flight distance
measurement applications.
The input common-mode range of 1.5V to VDD + 0.1V is compatible with the outputs of several widely used high-speed
transimpedance amplifiers, such as the MAX40658. The output stage is LVDS (Low-Voltage Differential Signaling), which
helps to minimize power dissipation and interfaces directly with many modern FPGAs and CPUs.
The MAX40025 and MAX40026 operate from a +2.7V to +3.6V power supply voltage while typically consuming only
17mA quiescent current at 3.3V. The MAX40025 and MAX40026 are available in space-saving 6-WLP and 8-TDFN
packages, respectively.
LVDS Outputs
Each LVDS output has a switched 3.25 mA current source. The outputs are differentially terminated with an external
100Ω resistor, which produces a ±350 mV differential output. The power delivered to the 100Ω load resistor is only 1.1mW
while enabling transmission data rates up to a few hundreds of Megabits per second. The output common-mode voltage
is maintained at 1.23 V on both outputs, and is independent of power supply voltage. The fully differential LVDS outputs
provide high-speed digital signalling with reduced EMI compared to single-ended outputs.
System Timing Definitions
Table 1. Timing Definitions
SYMBOL
SPECIFICATION
DESCRIPTION
VOD
Overdrive
Voltage
Differential voltage applied across inputs during test
tPDH
Propagation
Delay High on
OUT+
Propagation delay measured from the time the differential input signal changes polarity (± input
VOS) to the 50% point in the output low-to-high transition on OUT+
tPDL
Propagation
Delay Low on
OUT-
Propagation delay measured from the time the differential input signal changes polarity (± input
VOS) to the 50% point in the output high-to-low transition on OUT-
ΔtPDHO
Propagation
Delay Skew on
High
Difference in propagation delay on output transition from low to high on OUT+ to propagation delay
from high to low on OUT-
ΔtPDLO
Propagation
Delay Skew on
Low
Difference in propagation delay on output transition from high to low on OUT+ to propagation delay
from low to high on OUT-
tR
Output Rise
Time
Time taken by either OUT+ or OUT- to rise from 25% of final output voltage to 75% of final output
voltage
tF
Output Fall Time
Time taken by either OUT+ or OUT- to fall from 75% of final output voltage to 25% of final output
voltage
tPDL
Propagation
Delay Low on
OUT-
Propagation delay measured from the time the differential input signal changes polarity (± input
VOS) to the 50% point in the output high-to-low transition on OUT-
tPDH
Propagation
Delay High on
OUT-
Propagation delay measured from the time the differential input signal changes polarity (± input
VOS) to the 50% point in the output low-to-high transition on OUT-
Differential
Propagation
Delay High
Propagation delay measured from the time the differential input signal changes polarity (± input
VOS) to the 50% point in the output differential signal across OUT+ to OUT- while switching low to
high
tPDHD
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Maxim Integrated | 9
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Table 1. Timing Definitions (continued)
Differential
Propagation
Delay Low
Propagation delay measured from the time the differential input signal changes polarity (± input
VOS) to the 50% point in the output differential signal across OUT+ to OUT- while switching high to
low
VOH
Output Voltage
High
Comparator output high state voltage level
VOL
Output Voltage
Low
Comparator output low state voltage level
tPDLD
VOD
DIFFERENTIAL
INPUT SIGNAL
0V±VOS
ΔtPDHO
tR
ΔtPDLO
tPDH
VOUT+
75%
tPDL
VOUTtPDL?
25%
tF
1.25V
tPDH?
1.25V
tPDLD
0V
tPDHD
DIFFERENTIAL
OUTPUT
SIGNAL
Figure 1. System Timing Diagram
Propagation Delay
The propagation delay is defined as the delay between the differential comparator input voltage changing polarity and the
output(s) reaching the mid-point of the high-to-low or low-to-high transition. The low-to-high propagation delay is tPDH
on OUT+ and tPDH on OUT-, whereas the high-to-low propagation delay is tPDL on OUT+ and tPDL on OUT-. These
high-to-low and low-to-high timing parameters will differ slightly due to mismatches between the two complementary
outputs. As a result, this difference in propagation delay is considered to be a skew for a given combination of low-to-high
transitions on OUT+ and high-to-low transitions on OUT-.
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Maxim Integrated | 10
NON-INVERTING INPUT (mV)
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
VIN+
VIN- = VREF
tPDH
VOUT+
ΔtPDHO
VOUTtPDL?
Figure 2. Propagation Delay
Propagation Delay Dispersion
Dispersion, or variation of the propagation delay under different conditions, is affected by the amount of overdrive voltage
applied to the comparator inputs. As can be seen in the Typical Operating Characteristics, the dispersion is typically
under 25ps for 10mV to 1V, a wide range of input overdrive values.
VOD = 100mV
VOD = 10mV
0V ± VOS
DISPERSION
0V
Figure 3. Amplitude Overdrive Dispersion
Dispersion is also affected by the input slew rate. As the slew rate of the input signal changes, the propagation delay also
changes. The dispersion is typically under 15ps from 0.4V/μs to 1V/μs input slew rates.
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Maxim Integrated | 11
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
0V ± VOS
DISPERSION
0V
Figure 4. Slew Rate Dispersion
Hysteresis
NON-INVERTING INPUT (mV)
Adding a small amount hysteresis to a comparator in a noisy environment is useful when input signals are slow-moving
and have small noise levels superimposed on them. However, hysteresis must be used carefully when signals are small
because it can cause valid signals to be ignored. Figure 5 shows the input signal and output response for a comparator
with hysteresis applied.
VIN+
VTRIP+
VIN- = VREF
VTRIP-
OUT
VOH
VOL
VTRIP-
0V
VTRIP+
INPUT
Figure 5. Hysteresis Transfer Function
The MAX40025C is optimized for detecting very small, fast-changing signals and therefore has no internal hysteresis.
The MAX40025A has fixed internal 2.5mV hysteresis and the MAX40026 has fixed internal 1.5mV hysteresis, which
improves their usefulness for detecting larger differential input signals in the presence of noise. This helps to avoid the
external components and potential stability degradation associated with external positive feedback paths.
Input Stage Circuitry
The MAX40025/MAX40026 include internal protection circuitry that prevents damage to the precision input stage from
large differential input voltages. This protection circuitry consists of two groups of two front-to-back diodes between IN+
and IN-, as well as two 50Ω resistors (Figure 6). The diodes limit the differential voltage applied to the comparator’s
internal circuitry to no more than 2VF, where VF is the diode’s forward-voltage drop (about 0.7V at +25°C).
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Maxim Integrated | 12
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
For a large differential input voltage (exceeding 2VF), this protection circuitry increases the input bias current at IN+
(source) and IN- (sink).
INPUT CURRENT =
(VIN + − VIN − ) − 2 × VF
2 × 50
Input currents with large differential input voltages should not be confused with input bias currents (IB). As long as the
differential input voltage is less than 2VF , this input current is less than 2IB.
The input circuitry allows the MAX40025/MAX40026’s input common-mode range to extend 100mV beyond the positive
power-supply rail. The output remains in the correct logic state if one or both inputs are within the common-mode range.
Taking either input outside the common-mode range causes the input to saturate and the propagation delay to increase.
IN+
50Ω
TO INTERNAL
CIRCUITRY
IN50Ω
Figure 6. Input Stage Circuitry
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Maxim Integrated | 13
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Applications Information
Critical Layout Guidelines
Some critical Layout guidelines are listed below.
● Use a PC board with a low-impedance ground plane.
● Mount one or more 10nF ceramic capacitors between GND and VCC, as close to the pins as possible. Multiple bypass
capacitors help to reduce the effect of trace impedance and capacitor ESR.
● Choose bypass capacitors for minimum inductance and ESR.
● Use a 100Ω termination resistor for the LVDS output, connected directly between OUT+ and OUT-, if practical. If the
destination LVDS inputs can't be located adjacent to the outputs, use a 100Ω microstrip between the output pins and
the termination resistor, which should be close to the LVDS inputs of the FPGA or other destination component. This
will avoid the creation of stub beyond the termination resistor, which will cause reflections. The added length of the
differential trace has less degrading affects than added stub length.
● Ensure that there is no parasitic coupling between the inputs and the outputs. Such coupling serves as feedback, and
can result in oscillation.
● Minimize any parasitic layout inductance.
● It is recommended to use higher performance substrate materials (for example, Rogers).
● A differential micro-strip is the recommended layout for MAX40025/MAX40026 with terminations done close to the
inputs and outputs of the MAX40025 or MAX40026. Care must be taken to avoid unwanted stubs by removing ground
below the traces that are not part of the 50Ω termination line leading into input pins. The parasitic capacitance created
between traces and ground slow down and even distort the signals by creating reflections on the path.
● Below is an example from the MAX40025EVKIT#, where ground has been etched/removed underneath a stub as
shown in the layer below top layer.
MAX40025 EVKIT PCB
TOP LAYER
GND KEEP OUT POLYGON ON GND2, GND3
AND BOTTOM LAYER
Figure 7. Layout Guidelines—Ground Keep-Out to Avoid Stubs.
Input Slew Rate
With slower slew rates, when the input voltage is near the threshold any parasitic feedback paths can cause oscillation.
In addition, the comparator’s input noise will cause the output to undergo transitions. Eliminating feedback paths will stop
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Maxim Integrated | 14
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
oscillation. To avoid noise-induced chattering, the input slew rate should be greater than 1V/μs.
Typical Application Circuits
Receiver Section of Differential Time-of-Flight Measurement Circuit:
In Figure 8, the photodiode, shown at the far right, converts light incident upon it into current that drives the input of the
MAX40658 Transimpedance Amplifier (TIA). The MAX40658 then converts photodiode current to voltage, amplifies it,
and passes a replica of the incident light to input of the MAX40025 high-speed comparator. By default, the MAX40658
has -27mV differential output offset voltage when there is no input current. This offset can be adjusted using the
MAX40658's offset pin. The MAX40025 produces differential output pulses whenever an incident light pulse has intensity
sufficient to change the polarity of the comparator input signal.
3.3V
VCC
LVDS
OUTPUT
FPGA
100Ω
VCC
OUT+
MAX40025/
MAX40026
OUT-
OUT+
150Ω
OUTLVDS
INPUT
MAX40658
TIA
PHOTO DIODE
GND
OFFSET
GND
OUTPUT
OFFSET
CONTROL
VBIAS
Figure 8. Differential-Ended Output Receiver
Receiver Section of Single-Ended Time-of-Flight Measurement Circuit:
Figure 9 has a single-ended output configuration on the transimpedance amplifier, which drives one input of the
comparator. This functionality is the same as that of the differential configuration discussed above, except that the
threshold voltage can be adjusted by selecting the values of R1 and R2.
3.3V
VCC
LVDS
OUTPUT
FPGA
100Ω
OUT+
VCC
OUT+
MAX40025/
MAX40026
OUTGND
150Ω
OUT3.3V
R1
R2
MAX40658
TIA
IN
PHOTO DIODE
GND
OFFSET
OUTPUT
OFFSET
CONTROL
VBIAS
Figure 9. Single-Ended Output Receiver
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Maxim Integrated | 15
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Ordering Information
PART NUMBER
TEMPERATURE RANGE
PIN-PACKAGE
TOP MARK
HYSTERESIS
MAX40025AAWT+
-40°C to +125°C
6-WLP
+AAC
2.5mv
MAX40025CAWT+
-40°C to +125°C
6-WLP
+AAB
No Hysterisis
MAX40026ATA/VY+
-40°C to +125°C
8-TDFN
+BSS
1.5mV
MAX40026ATA+
-40°C to +125°C
8-TDFN
+BTF
1.5mV
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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Maxim Integrated | 16
MAX40025A/MAX40025C/
MAX40026
280ps High-Speed Comparator, Ultra-Low
Dispersion with LVDS Outputs
Revision History
REVISION
NUMBER
REVISION
DATE
0
11/18
Initial release
1
12/18
Updated part numbers in title and equation in Detailed Description
2
1/19
Updated Pin Configuration Diagram and Pin Description
3
2/19
Updated data sheet for release of MAX40026
1–18
4
3/19
Updated data sheet for release of MAX40025A
1–18
5
9/19
Updated Ordering Information table
DESCRIPTION
PAGES
CHANGED
—
1–17
7
18
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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2019 Maxim Integrated Products, Inc.