MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
General Description
The MAX40075/MAX40088 are wideband, low-noise,
low-input bias current operational amplifiers offering railto-rail outputs and single-supply operation down to 2.7V.
They draw 2.2mA of quiescent supply current per amplifier
when enabled. Ultra-low distortion (0.0002% THD+N), as
well as low input voltage-noise density (4.2nV/√Hz) and
low input current-noise density (0.5fA/√Hz). The low input
bias current and low noise together with the wide bandwidth
will suit transimpedance amplifiers and imaging applications.
For power conservation, the MAX40075/MAX40088 offer
a low-power shutdown mode that reduces supply current
to 0.1μA and places the amplifiers outputs into a high
impedance state. These amplifiers have outputs which
swing rail-to-rail and their input common-mode voltage
range includes ground. The MAX40075 is unity-gain
stable with a gain-bandwidth product of 10MHz. The
MAX40088 is gain-of-5 stable with a gain-bandwidth
product of 42MHz.
Applications
●● ADC Buffers
●● DAC Output Amplifiers
Benefits and Features
●● Low Input Voltage-Noise Density: 4.2nV/√Hz at 30kHz
●● Low Input Current-Noise Density: 0.5fA/√Hz
●● Low Input Bias Current: 2.5V ±1%
13
Shutdown Supply Current
Overtemperature, to 125°C
0.4
1.7
At 25°C
30
150
Input Offset Voltage
Input Offset Drift
2.7
MAX
Supply Voltage Range
Over the full temperature range
µs
450
Over temperature, to 125°C
mA
µA
µV
0.3
3
µV/°C
1
2300
pA
Input offset Current (Note 2)
0.2
500
Differential Input Resistance
1000
Input Bias Current (Note 2)
Input Capacitance
Input Common Mode
Range
Common Mode Rejection
Ratio
Either input, over entire CMIR
pF
-0.2
VDD - 1.5
Guaranteed by CMRR test, full
temperature range
-0.1
VDD - 1.5
90
DC, -0.1V < CMIR < VDD - 1.5V, full
temperature range
89
Common Mode Rejection
Ratio, AC
100 mVP-P 1MHz, with DC in 0V to
VDD - 2V range
Power Supply Rejection
Ratio, DC
DC, 2.7V < VDD < 5.5V
Power Supply Rejection
Ratio, AC
AC, 100mVPP 1MHz, superimposed on
VDD
Open-Loop Gain
10
Guaranteed by CMRR test, at 25°C
DC, -0.2V < CMIR < VDD - 1.5V, at 25°C
90
dB
60
dB
107
dB
40
dB
RL = 10kΩ to VDD/2, VOUT = 200mV to
VDD-250mV
93
114
RL = 1kΩ to VDD/2, VOUT = 200mV to
VDD-250mV
87
109
RL = 500Ω to VDD/2, VOUT = 200mV to
VDD-250mV
85
107
dB
RL = 10kΩ to VDD/2, VDD - VOH
3
10
30
60
RL = 500Ω to VDD/2, VDD - VOH
60
120
RL = 10kΩ to VDD/2, VDD - VSS
3
10
RL = 1kΩ to VDD/2, VOL - VSS
30
60
RL = 500Ω to VDD/2, VOL - VSS
60
120
Short-Circuit Current
Shorted to either power supply
48
Output Leakage Current
When Shut Down
VSS < VOUT < VDD
Output Voltage Swing Low
Shut-Down Input Low level
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V
109
RL = 1kΩ to VDD/2, VDD - VOH
Output Voltage Swing High
pA
GΩ
0.01
mV
mV
mA
1
µA
0.3 x VDD
V
Maxim Integrated │ 3
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
Electrical Characteristics (continued)
(VDD=+5V, VSS=0V, VCM=2.5V, SHDN =VDD, VOUT=VDD/2, RL=tied to VDD/2, TA=-40°C to +125°C, unless otherwise noted. Typical
values are at TA = +25°C. (Note 1) )
PARAMETER
SYMBOL
CONDITIONS
Shut-Down Input High level
Shut-Down Input Bias
-3dB Bandwidth
Phase Margin
MIN
TYP
MAX
0.7 x VDD
V
0.01
Unity-gain version, Av = +1
10
Gain of 5 stable, Av = +5
42
Unity-gain version, Av = +1
70
Gain of 5 stable, Av = +5
80
Gain Margin
UNITS
12
1
µA
MHz
°
dB
Unity-gain version, Av = +1
3
Gain of 5 stable, Av = +5
10
Unity-gain version, Av = +1, to 0.01%,
VOUT = 2V step
2
Gain of 5 Stable, Av = +5, to 0.01%,
VOUT = 2V step
2
Stable Capacitive Load
Guaranteed stability over all conditions
50
pF
Integrated 1/f Input Voltage
Noise
0.1Hz to 10Hz
1.7
µVPP
f = 10Hz
260
f = 1kHz
5.5
f = 30kHz
4.2
f = 1kHz
0.5
Slew Rate
Settling Time
Input Voltage Noise Density
Input Current Noise Density
Total Harmonic Distortion +
Noise
Electromagnetic
Interference Rejection Ratio
V/µs
µs
Unity-gain version, Av = +1, VOUT = 4VPP,
10kΩ to GND, 1kHz
-114.0
Unity-gain version, Av = +1, VOUT = 4VPP,
10kΩ to GND, 20kHz
-103.1
Unity-gain version, Av = +1, VOUT = 4VPP,
1kΩ to GND, 1kHz
-114.0
Unity-gain version, Av = +1, VOUT = 4VPP,
1kΩ to GND, 20kHz
-100.0
Gain of 5 version, Av = +5, VOUT = 4VPP,
10kΩ to GND, 1kHz
-108.0
Gain of 5 version, Av = +5, VOUT = 4VPP,
10kΩ to GND, 20kHz
-110
Gain of 5 version, Av = +5, VOUT = 4VPP,
1kΩ to GND, 1kHz
-106.0
Gain of 5 version, Av = +5, VOUT = 4VPP,
1kΩ to GND, 20kHz
-110
VRF_PP = 100mV, F = 900MHz to 2400MHz
55
nV/√Hz
fA/√Hz
dBc
dB
Note 1: Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization.
2: Guaranteed by design and bench characterization.
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Maxim Integrated │ 4
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
Typical Operating Characteristics
VDD = +5V, VSS = 0V, VCM = VDD/2, RL = 10kΩ to VDD/2, CL=10pF to GND, TA = +25°C, unless otherwise noted.
4
2
0
10
20
30
40
50
60
70
80
90
2
1.5
1
TA = 25°C
TA = -40°C
0.5
2.6
TB
6
TA = 85°C
2.5
toc02
TA = 125°C
QUIESCENT SUPPLY CURRENT (mA)
TB
QUIESCENT SUPPLY CURRENT (mA)
8
FREQUENCY (NO. OF UNITS)
3
toc01
10
0
D
2.5
2.45
2.4
2.35
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-40 -25 -10 5
5.5
30
20
10
0
-10
-20
-10
-20
TA = 85°C
-30
0
IB+
140
D
0.5
1
1.5
2
2.5
3
3.5
INPUT COMMON MODE VOLTAGE (V)
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4
IB-
-600
-800
-1000
IB+
-1400
-40 -25 -10 5
120
100
80
60
40
20
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
toc08
0
-50
-400
D
OUTPUT VOLTAGE HIGH
vs. OUTPUT SOURCE CURRENT
VDD = 5V
140
TB
TB
IB-
50
0
160
toc06
-200
OUTPUT VOTLAGE HIGH (VDD - VOUT) (mV)
toc07
100
-0.5
0.5
1.1
1.7
2.3
2.9
3.5
INPUT COMMON MODE VOLTAGE (V)
OUTPUT VOLTAGE LOW
vs. OUTPUT SINK CURRENT
VDD = 5V, VSS = 0V
VDD = 5.0V
D
-1200
TA = 125°C
-0.1
OUTPUT VOTLAGE LOW (VOUT - VSS) (mV)
TB
INPUT BIAS CURRENT (pA)
150
TA = 25°C
0
INPUT BIAS CURRENT vs.
INPUT COMMON MODE VOLTAGE
200
0
10
-40
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
D
20
VDD = 5V
TB
30
200
TA = -40°C
TB
40
D
INPUT BIAS CURRENT
vs. TEMPERATURE
INPUT OFFSET VOLTAGE vs. INPUT
COMMON MODE VOTLAGE toc05
INPUT BIAS CURRENT (pA)
D
INPUT OFFSET VOTLAGE (μV)
INPUT OFFSET VOLTAGE (µV)
TB
50
20 35 50 65 80 95 110 125
TEMPERATURE(°C)
SUPPLY VOLTAGE (V)
INPUT OFFSET VOLTAGE
vs. TEMPERATURE toc04
toc03
VDD = 3.3V
2.55
0
100
OFFSET VOLTAGE (µV)
D
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
OFFSET VOLTAGE HISTOGRAM
120
toc09
100
80
60
40
20
0
0
2
4
ISINK (mA)
6
8
10
0
2
4
6
8
10
ISOURCE (mA)
Maxim Integrated │ 5
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
Typical Operating Characteristics (continued)
VDD = +5V, VSS = 0V, VCM = VDD/2, RL = 10kΩ to VDD/2, CL=10pF to GND, TA = +25°C, unless otherwise noted.
TB
RLOAD = 500Ω
RLOAD = 1kΩ
10
RLOAD = 10kΩ
VSUPPLY = 5V
0
50
100
RLOAD = 1kΩ
RLOAD = 10kΩ
VSUPPLY = 5V
1
-50
0
50
D
toc13
D
2.E-6
2.E-6
80
IN VOLTS
60
50
40
95
150
-50
30
toc14
eN = 2.12µVP-P
5.E-7
0.E+0
-20
10000
100000
10
20
FREQUENCY(Hz)
-60
-80
-100
50
0.01
60
0.1
1
140
D
toc17
VDD = 2.7V
120
DC CMRR (dB)
-40
-50
-60
100
90
70
VDD = 5.5V
60
D
AV = 1000V/V
80
100
80
100
1000 10000 100000
GAIN AND PHASE
vs. FREQUENCY
(RL = 10kΩ, CL = 10pF)
COMMON MODE REJECTION RATIO vs. TEMPERATURE
toc16
10
FREQUENCY(kHz)
GAIN (dB)
-30
40
TB
D
30
10s/div
TB
TB
-20
toc15
-120
0
COMMON MODE REJECTION RATIO vs.
FREQUENCY
150
-40
-2.E-6
1000
100
D
0
-2.E-6
10
100
50
POWER-SUPPLY REJECTION RATIO vs.
FREQUENCY
-1.E-6
20
10
0
TEMPERATURE (°C)
-5.E-7
0
COMMON MODE REJECTION RATIO(dB)
100
1.E-6
70
1
VDD = 2.7V
INPUT VOLTAGE NOISE 0.1Hz TO 10Hz NOISE
TB
TB
VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz)
90
VDD = 5.5V
105
TEMPERATURE (°C)
TEMPERATURE (°C)
100
110
100
150
VOLTAGE NOISE DENSITY
vs. FREQUENCY
toc12
VDD = 5V
115
TB
-50
125
120
RLOAD = 500Ω
10
D
OPEN-LOOP GAIN
vs. TEMPERATURE
toc11
POWER-SUPPLY REJECTION RATIO (dB)
1
D
100
TB
toc10
OUTPUT VOTLAGE HIGH (VDD - VOUT) (mV)
OUTPUT VOTLAGE LOW (VOUT-VSS) (mV)
TB
100
OUTPUT VOLTAGE HIGH
vs. TEMPERATURE
OPEN-LOOP GAIN (dB)
D
OUTPUT VOLTAGE LOW
vs. TEMPERATURE
GAIN
toc18
toc13
200
PHASE CURVE IS
REFERRED TO DEGREE
UNITS ON AXIS FAR RIGHT
150
100
60
50
50
PHASE
40
0
30
-70
40
-80
20
-90
0.1
1
10
100
FREQUENCY(kHz)
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1000 10000 100000
-50
20
-100
10
-150
0
-10
0
0.01
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
250
-200
0.01
0.1
1
10
100
FREQUENCY (kHz)
1000 10000 100000
Thousands
Maxim Integrated │ 6
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
Typical Operating Characteristics (continued)
VDD = +5V, VSS = 0V, VCM = VDD/2, RL = 10kΩ to VDD/2, CL=10pF to GND, TA = +25°C, unless otherwise noted.
40
150
100
50
PHASE
30
20
0
-50
GAIN
10
-80
VOUT = 4 VP-P
D
toc21
fIN = 20kHz
-90
-90
-100
RL = 1KΩ
-100
RL = 1kΩ
-100
-10
-200
-20
-250
1000 10000 100000
0.01
0.1
1
10
100
FREQUENCY (kHz)
D
RL = 10kΩ
-120
TB
-120
20
200
30
20
UNSTABLE
0.5
1.5
2
2.5
3
3.5
4
4.5
5
D
SMALL-SIGNAL PULSE RESPONSE
(CLOAD= 10pF)
toc23
10
1
OUTPUT VOLTAGE SWING (VP-P)
100
RESISTIVE LOAD (kΩ)
STABLE
20000
STABILITY vs. CAPACITIVE AND RESISTIVE LOAD IN
PARALLEL WITH CL
toc22
40
2000
FREQUENCY(Hz)
UNDER THE CURVE AS
SHOWN IS UNSTABLE REGION
50
-110
RL = 10KΩ
Thousands
ISOLATION RESISTANCE vs.
CAPACITIVE STABILITY
60
-110
-150
AV = 5V/V or 14dB
TB
0
ISOLATION RESISTANCE (Ω)
-80
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT VOLTAGE SWING
toc20
TB
50
GAIN (dB)
200
PHASE CURVE IS
REFERRED TO DEGREE
UNITS ON AXIS FAR RIGHT
60
D
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
250
THD + N (dB)
70
toc19
toc13
TB
TB
80
THD + N (dB)
D
GAIN AND PHASE
vs. FREQUENCY
(RL = 10kΩ, CL = 10pF)
toc24
AAVV=1V/V
=1V/V
AV = 5V/V
IN+
10mV/div
UNSTABLE
STABLE
1
10
OUTPUT
50mV/div
0
10
100
1000
10000
0.1
100
1000
1µs/div
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
D
TB
LARGE-SIGNAL PULSE RESPONSE
(CL = 10pF)
toc25
AVV=1V/V
=1V/V
= 5V/V
AVAA=1V/V
V=1V/V
IN+
100mV/div
OUTPUT
500mV/div
100µs/div
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Maxim Integrated │ 7
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
Pin Configurations
+
OUT
6 VDD
1
VSS
2
IN+
3
MAX40075
MAX40088
5 SHDN
4 IN-
SOT23-6
TOP VIEW
Pin Description
PIN
NAME
FUNCTION
SOT23
6-WLP
1
A3
OUT
Amplifier Output
2
A2
VSS
Negative Supply. Connect to ground for single-supply operation.
3
A1
IN+
Non-Inverting Amplifier Input
4
B1
IN-
Inverting Amplifier Input
5
B2
SHDN
6
B3
VDD
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Shutdown, Active Low. Connect to VDD for normal operation (amplifier enabled)
Positive Supply. Connect 0.1μF and 4.7μF from VDD to VSS.
Maxim Integrated │ 8
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
Functional Diagrams
Internal ESD protection
VDD
IN-
60Ω
MAX40075
MAX40088
OUT
IN+
60Ω
VSS
SHDN
Figure 1. Internal ESD protection
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Maxim Integrated │ 9
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
Detailed Description
The MAX40075/MAX40088 single-supply operational
amplifiers feature ultra-low noise and distortion. Their
low distortion and low noise make them ideal for use
as pre-amplifiers in wide dynamic range applications,
such as 16-bit analog-to-digital converters. Their high
input impedance and low noise are also useful for signal
conditioning of high-impedance sources, such as piezoelectric transducers.
These devices have true rail-to-rail output operation, drive
output resistive loads as low as 1kΩ while maintaining
DC accuracy and can drive capacitive loads up to 200pF
without any oscillation. The input common-mode voltage
range extends from 0.2V below VSS to (VDD - 1.5V). The
push-pull output stage maintains excellent DC characteristics,
while delivering up to ±20 mA of source/sink output current.
The MAX40075 is unity-gain stable, while the
MAX40088 is a decompensated version that has higher
slew rate and is stable for Gain ≥ 5V/V. Both devices
feature a low-power shutdown mode, which reduces the
supply current to 0.1μA and places amplifiers outputs into
a high-impedance state.
Low Noise
The amplifiers input-referred voltage noise density is
dominated by flicker noise (also known as 1/f noise)
at lower frequencies and by thermal noise at higher
frequencies. Overall thermal noise contribution is affected
by the parallel combination of resistive feedback network
(RF||RG) depicted in Figure 2. These resistors should be
reduced in cases where system bandwidth is large and
thermal noise is dominant. Noise contribution factor can
be reduced with increased gain settings.
For example, the input noise voltage density(eN) of the
circuit with RF = 100kΩ, RG = 10kΩ (in Figure 2) with
Gain = 10V/V non-inverting configuration is eN = 12nV/√Hz.
eN can be reduced to 6nV/√Hz by choosing RF = 10kΩ,
RG = 1kΩ (in Figure 2) with Gain = 10V/V, as before, but
at the expense of higher current consumption and higher
distortion. Having a gain of 100V/V with RF = 100kΩ, RG = 1kΩ
(in Figure 2), input referred voltage noise density is still a
low 6nV/√Hz.
Low Distortion
Many factors can affect the noise and distortion
performance of the amplifier based on the design choices
made. The following guidelines offer valuable information on
the impact of design choices on Total Harmonic Distortion
(THD). Choosing correct feedback and gain resistor values
for a particular application can be a very important factor
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in reducing THD. In general, the smaller the closed-loop
gain, the smaller the THD generated, especially when
driving heavy resistive loads (e.g., smaller resistive load
with higher output current). Operating the device near or
above the full-power bandwidth significantly degrades
distortion.
Referencing the load to either supply also improves the
amplifier distortion performance, because only one of the
MOSFETs of the push-pull output stage drives the output.
Referencing the load to mid-supply increases the amplifier
distortion for a given load and feedback setting (see the
Total Harmonic Distortion vs. Frequency graph in Typical
Operating Characteristics).
For gains ≥ 5V/V, the decompensated MAX40088 deliver
the best distortion performance as they have a higher
slew rate and provide a higher amount of loop gain
for a given closed-loop gain setting. Capacitive loads
below 100pF do not significantly affect distortion results.
Distortion performance is relatively constant over supply
voltages.
Using a Feed-Forward Compensation
Capacitor, Cz
The amplifier’s input capacitance is 10pF and if the
resistance seen by the inverting input is large (in Figure 2)
as a result of feedback network, this resistance and
capacitance combination can introduce a pole within the
amplifier’s bandwidth resulting in reduced phase margin.
Compensate the reduced phase margin by introducing a
feed-forward capacitor (CZ) between the inverting input
and the output (shown in Figure 2). This effectively cancels
the pole from the inverting input of the amplifier. Choose
the value of CZ as follows:
CZ = 10 x (RF/RG) [pF]
In the unity-gain stable MAX40075, the use of right CZ is
most important for closed loop non-inverting gain AV = +2V/V,
and inverting gain AV = -1V/V.
In the decompensated MAX40088, CZ is most important
for closed loop gain AV = +10V/V.
Using a slightly smaller CZ than suggested by the
formula above achieves a higher bandwidth at the
expense of reduced phase and gain margin. As a general
guideline, consider using CZ for cases where RG||RF is
greater than 20kΩ (for MAX40075) and greater than 5kΩ
(for MAX40088).
Maxim Integrated │ 10
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
VDD=5V
IN+
MAX40075
VOUT
VIN
IN-
RG
SHDN =5V
VSS=0V RF
CZ
Figure 2. Adding Feed-Forward Compensation
Applications Information
Applications Information
The MAX40075/MAX40088 combine good driving capability
with ground-sensing input and rail-to-rail output operation.
With their low distortion and low noise, these devices are
ideal for use in ADC buffers, DAC output buffers, medical
instrumentation systems and other noise-sensitive applications.
Ground-Sensing and Rail-to-Rail Outputs
The common-mode input range of these devices extends
below ground over temperature that offers excellent common
mode rejection and can be used in low side current sensing applications. These devices are guaranteed not to
undergo phase-reversal when the input is overdriven over
input common mode voltage range as shown in Figure 3.
Figure 4 showcases the true rail-to-rail output operation of
the amplifier, configured with AV = 5V/V. The output swings
to within 8mV of the supplies with a 10kΩ load, making the
devices ideal in low-supply voltage applications.
Good layout improves performance by decreasing the
amount of stray capacitance and noise at the op amp inputs
and output. To decrease stray capacitance, minimize PC
board trace lengths and resistor leads, and place external
components close to the op amp’s pins.
Typical Application Circuit
The Typical Application Circuits shows the single
MAX40075 configured as an output buffer for the
MAX5541 16-bit DAC. Because the MAX5541 has an
unbuffered voltage output, the input bias current of the op
amp used must be less than 6nA to maintain 16-bit accuracy.
This family of amplifiers have an input bias current of only
2.3nA (max) over temperature, virtually eliminating this as
a source of error. In addition, the MAX40075 has excellent
open-loop gain and common-mode rejection, making this
an excellent output buffer amplifier.
Power Supplies and Layout
The MAX40075/MAX40088 operate from a single +2.7V
to +5.5V power supply or from dual supplies of ±1.35V
to ±2.75V. For single-supply operation, bypass the VDD
power supply pin with a 0.1μF ceramic capacitor placed
close to the VDD pin. If operating from dual supplies,
bypass both VDD and VSS supply pins with 0.1μF ceramic
capacitor to ground. If additional decoupling is needed
add another 4.7μF or 10μF where supply voltage is
applied on PCB.
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Maxim Integrated │ 11
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
NO PHASE REVERSAL
= 5V/V
AVVA=1V/V
V=1V/V
AVAA=1V/V
V=1V/V
IN+
2.5V/div
OUTPUT
2.5V/div
4µs/div
Figure 3. Scope Plot Showing Overdriven Input with No Phase Reversal
RAIL-TO-RAIL OUTPUT OPERATION (CL = 10pF)
A
= 5V/V
V
AVV=1V/V
=1V/V
AVAA=1V/V
V=1V/V
IN+
0.5V/div
OUTPUT
2.5V/div
4µs/div
Figure 4. Rail-to-Rail Output Operation with 10KΩ and AV = 5V/Vl
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Maxim Integrated │ 12
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
Typical Application Circuit
VDD=5V
VREF=2.5V
VDD=5V
CS
SERIAL
INTERFACE
VDD
REF
MAX5541
SCLK
DIN DGND
OUT
IN+
MAX40075
AGND
0V TO +2.5V
OUTPUT
INVSS=0V
SHDN =5V
Ordering Information
PART NUMBER
TEMP RANGE
MAX40075ANT+T*
MAX40075AUT+T
MAX40088ANT+T*
MAX40088AUT+T
TOP
MARK
PIN-PACKAGE
STABLE GAIN (V/V)
BW
-40°C to +125°C
6-WLP
1
10MHz
—
-40°C to +125°C
6-SOT23
1
10MHz
ACVD
-40°C to +125°C
6-WLP
5
42MHz
—
-40°C to +125°C
6-SOT23
5
42MHz
ACVE
* Future Product—Contact Maxim for availability.
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T Denotes tape-and-reel.
Chip Information
PROCESS: BiCMOS
www.maximintegrated.com
Maxim Integrated │ 13
MAX40075/MAX40088
10MHz/42MHz Low Noise, Low Bias Op-Amps
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0
6/17
Initial release
1
7/17
Updated Typical Operating Characteristics section
5, 6
—
2
12/17
Updated Ordering Information table
13
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 14
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