19-4439; Rev 0; 5/09
KIT
ATION
EVALU
E
L
B
AVAILA
Quad PCI Express Equalizer/Redriver
Features
(PCIe®)
♦ Single +3.3V Supply Operation
The MAX4950 PCI Express
quad equalizer/
redriver operates from a single +3.3V supply. This
device improves signal integrity at the receiver through
programmable input equalization and programmable
redrive circuitry. The output circuitry reestablishes deemphasis lost on the board, compensating for circuit
board loss. This device permits optimal placement of
key PCIe components and longer runs of stripline,
microstrip, or cable.
The MAX4950 contains four identical buffers capable of
equalizing differential signals at data rates up to 5GT/s,
and features electrical idle and receiver detection on
each channel. The MAX4950 is ideal for use with PCIe
Gen I (2.5GT/s) and Gen II (5.0GT/s) data rates and
features a power-saving mode.
♦ Generation I (2.5GT/s) and Generation II (5.0GT/s)
Capable
♦ Return Loss:
≥ 10dB (f ≤ 1.25GHz)
≥ 8dB (f ≤ 2.5GHz)
♦ Very Low Latency
280ps Propagation Delay
♦ Individual Lane Detection
♦ Low Lane-to-Lane Skew: ±50ps
♦ Total Jitter ≤ 35psP-P at BER = 10-12
♦ Three-Level-Programmable Input Equalization
The MAX4950 is available in a small, lead-free, 42-pin
(3.5mm x 9.0mm) TQFN package for optimal layout and
minimal space requirements. The board traces are flowthrough for ease of layout. The MAX4950 is specified
over the 0°C to +70°C operating temperature range.
♦ Three-Level-Programmable Output Deemphasis
♦ On-Chip 50Ω Input/Output Terminations
♦ ±2kV Human Body Model (HBM) Protection on All
Pins
Applications
♦ Space-Saving, 3.5mm x 9.0mm, TQFN Packaging
Servers
Industrial PCs
Ordering Information
Test Equipment
Desktop Computers
Laptop Computers (for External Video Cards)
PART
TEMP RANGE
PIN-PACKAGE
MAX4950CTO+
0°C to +70°C
42 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Communications Switchers
Storage Area Networks
PCIe is a registered trademark of PCI-SIG Corp.
Pin Configuration
VCC
GND
OUT3N
OUT3P
GND
OUT2N
OUT2P
GND
VCC
GND
OUT1N
OUT1P
GND
OUT0N
OUT0P
GND
VCC
TOP VIEW
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
EN 39
21 OEQ0
*EP
20 OEQ1
RX_DET 40
MAX4950
O_AMP 41
P_SAV 42
19 INEQ0
18 INEQ1
8
9
10 11 12 13 14 15 16 17
VCC
IN0P
IN0N
GND
IN1P
IN1N
GND
VCC
GND
VCC
7
GND
6
IN3N
5
IN3P
4
GND
3
IN2N
2
IN2P
1
GND
+
TQFN
*CONNECT EXPOSED PAD (EP) TO GND.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1
MAX4950
General Description
MAX4950
Quad PCI Express Equalizer/Redriver
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
VCC ........................................................................-0.3V to +4.0V
All Other Pins (Note 1)................................-0.3V to (VCC + 0.3V)
Continuous Current IN_P and IN_N..................................±30mA
Peak Current IN_P and IN_N (pulsed for 1µs,
1% duty cycle)............................................................±100mA
Continuous Power Dissipation (TA = +70°C)
42-Pin TQFN (derate 34.5mW/°C above +70°C) .......2759mW
Junction-to-Case Thermal Resistance (θJC) (Note 2)
42-Pin TQFN................................................................2.0°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 2)
42-Pin TQFN..............................................................29.0°C/W
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: All I/O pins are clamped by internal diodes.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, CCL = 75nF coupling capacitor on each output, RL = 50Ω resistor on each output, TA = 0°C to +70°C, unless
otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.6
V
262
328
100
125
DC PERFORMANCE
Power-Supply Range
Supply Current
VCC
ICC
3.0
EN = VCC
O_AMP = GND,
P_SAV = GND (Note 4) EN = GND
mA
Differential Input Impedance
ZRX-DIFF-DC
DC
80
100
120
Ω
Differential Output
Impedance
ZTX-DIFF-DC
DC
80
100
120
Ω
Common-Mode Resistance
to GND
ZRX-HIGH-IMP- VIN_P = VIN_N = 0 to +200mV, input
terminations not powered
DC-POS
50
kΩ
Common-Mode Resistance
to GND
ZRX-HIGH-IMP- VIN_P = VIN_N = -150mV to 0, input terminations
not powered
DC-NEG
1
kΩ
Common-Mode Resistance
to GND, Input Terminations
Powered
ZRX-DC
Output Short-Circuit Current
ITX-SHORT
Common-Mode Delta
Between Active and Idle
States
DC
40
50
60
Ω
Single-ended
90
mA
O_AMP = GND
100
mV
|(VOUT_P + VOUT_N)|
25
mV
|(VOUT_P + VOUT_N)|
10
mV
VTX-CM-DCACTIVE-IDLEDELTA
DC Output Offset During
Active State
VTX-CM-DC-
DC Output Offset During
Electrical Idle
VTX-IDLE-DIFF-
LINE-DELTA
DC
AC PERFORMANCE (Note 5)
Differential Input Return Loss
RLRX-DIFF
Common-Mode Input Return
Loss
RLRX-CM
2
f = 0.05GHz to 1.25GHz
10
f = 1.25GHz to 2.5GHz
8
f = 0.05GHz to 2.5GHz
6
_______________________________________________________________________________________
dB
dB
Quad PCI Express Equalizer/Redriver
(VCC = +3.0V to +3.6V, CCL = 75nF coupling capacitor on each output, RL = 50Ω resistor on each output, TA = 0°C to +70°C, unless
otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
f = 0.05GHz to 1.25GHz
10
f = 1.25GHz to 2.5GHz
8
RLTX-CM
f = 0.05GHz to 2.5GHz
6
Redriver Operation
Differential Input Signal
Range
VRX-DIFF-PP
f = 0.05GHz to 2.5GHz
120
Full-Swing Differential Output
Voltage (No Deemphasis)
VTX-DIFF-PP
2 x |(VOUT_P + VOUT_N)|, O_AMP = GND;
f = 500MHz
800
2 x |(VOUT_P + VOUT_N)|, O_AMP = VCC;
f = 500MHz
600
Differential Output Return
Loss
RLTX-DIFF
Common-Mode Output
Return Loss
Differential Output Voltage
(Low Swing, No Deemphasis)
VTX-DIFF-PPLOW
TYP
MAX
UNITS
dB
dB
1200
mVP-P
1000
1200
mVP-P
750
900
mVP-P
Output Deemphasis Ratio,
0dB
VTX-DE-RATIO- f = 2.5GHz, OEQ1 = GND, OEQ0 = GND;
see Table 3
0dB
0
dB
Output Deemphasis Ratio,
3.5dB
VTX-DE-RATIO- f = 2.5GHz, OEQ1 = GND, OEQ0 = VCC;
see Table 3
3.5dB
3.5
dB
Output Deemphasis Ratio,
6dB
VTX-DE-RATIO- f = 2.5GHz, OEQ1 = VCC, OEQ0 = VCC or GND;
see Table 3
6dB
6
dB
Input Equalization, 0dB
Input Equalization, 3.5dB
Input Equalization, 6dB
Output Common-Mode
Voltage Swing Peak-to-Peak
Propagation Delay
VRX-EQ-0dB
f = 2.5GHz, INEQ1 = GND, INEQ0 = GND;
see Table 2 (Note 6)
0
dB
VRX-EQ-3.5dB
f = 2.5GHz, INEQ1 = GND, INEQ0 = VCC;
see Table 2 (Note 6)
3.5
dB
6
dB
VRX-EQ-6dB
VTX-CM-AC-PP
TPD
f = 2.5GHz, INEQ1 = VCC, INEQ0 = VCC or GND;
see Table 2 (Note 6)
Max(VOUT_P + VOUT_N)/2 – Min(VOUT_P +
VOUT_N)/2
f = 2.5GHz, K28.7 pattern
160
TTX-RISE-FALL
(Note 7)
30
Rise/Fall Time Mismatch
TTX-RFMISMATCH
(Note 7)
Output Skew Same Pair
TSK
f = 2.5GHz
Output Skew Lane to Lane
TSKL
f = 2.5GHz
Rise/Fall Time
Deterministic Jitter
TTX-DJ-DD
K28.5 pattern, 5.0GT/s, AC-coupled, RL = 50Ω,
effects of deemphasis deembedded
Random Jitter
TTX-RJ-DD
K28.7 pattern, f > 1.5MHz, BER = 10-12
Electrical Idle Entry Delay
Electrical Idle Exit Delay
TTX-IDLE-SETTO-IDLE
TTX-IDLE-TODIFF-DATA
280
100
mVP-P
400
ps
ps
10
-50
20
ps
15
ps
50
ps
15
psP-P
1.4
psRMS
From input to output
15
ns
From input to output
8
ns
_______________________________________________________________________________________
3
MAX4950
ELECTRICAL CHARACTERISTICS (continued)
MAX4950
Quad PCI Express Equalizer/Redriver
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, CCL = 75nF coupling capacitor on each output, RL = 50Ω resistor on each output, TA = 0°C to +70°C, unless
otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
Electrical Idle Detect
Threshold
VTX-IDLETHRESH
Output Voltage During
Electrical Idle (AC)
VTX-IDLE-DIFF-
Receiver Detect Pulse
Amplitude
VTX-RCV-
AC-P
DETECT
CONDITIONS
MIN
TYP
MAX
UNITS
65
85
120
mVP-P
|(VOUT_P - VOUT_N)|, f = 2.5GHz
20
mVP-P
Voltage change in positive direction
600
mV
Squarewave input at 500MHz
Receiver Detect Pulse Width
100
ns
Receiver Detect Retry Period
200
ns
CONTROL LOGIC (INEQ1, INEQ0, OEQ1, OEQ0, EN, RX_DET, O_AMP, P_SAV)
Input Logic-Level Low
VIL
Input Logic-Level High
VIH
Input Logic Hysteresis
VHYST
Input Leakage Current
IIN
0.6
1.4
V
130
VCONTROL_LOGIC = +0.5V or +1.5V
V
-50
mV
+50
µA
ESD PROTECTION
All Pins
Human Body Model (HBM)
±2
kV
Note 3: All devices are 100% production tested at TA = +70°C. Specifications for all temperature limits are guaranteed by design.
Note 4: Currents are applicable for both PCIe Generation I and Generation II speeds. Power-saving mode (P_SAV), where electrical
idle and receiver detection are only performed on channel 0 and reduced output swing (O_AMP) reduces this current. Table
5 summarizes the predicted power consumption.
Note 5: Guaranteed by design, unless otherwise noted.
Note 6: Equivalent to same amount of deemphasis driving the input.
Note 7: Rise and fall times are measured using 20% and 80% levels.
Timing Diagram
VLOW_P-P VHIGH_P-P
⎡ ⎛ VHIGH _ P − P ⎞ ⎤
DE(dB) = 20 ⎢log ⎜
⎟⎥
⎢⎣ ⎝ VLOW _ P − P ⎠ ⎦⎥
Figure 1. Illustration of Output Deemphasis
4
_______________________________________________________________________________________
Quad PCI Express Equalizer/Redriver
200
0
-200
-400
200
0
-200
EYE DIAGRAM VOLTAGE (mV)
400
EYE DIAGRAM VOLTAGE (mV)
400
INEQ0 = INEQ1 = 0, O_AMP = 0,
VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 1
MAX4950 toc02
600
MAX4950 toc01
600
EYE DIAGRAM VOLTAGE (mV)
INEQ0 = INEQ1 = 0, O_AMP = 0,
VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 0
-400
-600
MAX4950 toc03
INEQ0 = INEQ1 = 0, O_AMP = 0,
VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 0
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-150ps-100ps -50ps 0ps
0
-100
-200
-300
-400
-500
300
400
200
100
0
-100
-200
-300
-400
-150ps-100ps -50ps 0ps
50ps 100ps 150ps
50ps 100ps 150ps
INEQ0 = INEQ1 = 0, O_AMP = 1,
VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 1
EYE DIAGRAM VOLTAGE (mV)
100
400
EYE DIAGRAM VOLTAGE (mV)
EYE DIAGRAM VOLTAGE (mV)
500
400
300
200
-150ps-100ps -50ps 0ps
INEQ0 = INEQ1 = 0, O_AMP = 1,
VIN = 200mVP-P, OEQ0 = 1, OEQ1 = 0
MAX4950 toc04
INEQ0 = INEQ1 = 0, O_AMP = 1,
VIN = 200mVP-P, OEQ0 = 0, OEQ1 = 0
50ps 100ps 150ps
MAX4950 toc06
50ps 100ps 150ps
MAX4950 toc05
-150ps-100ps -50ps 0ps
300
200
100
0
-100
-200
-300
-400
-150ps-100ps -50ps 0ps
50ps 100ps 150ps
-150ps-100ps -50ps 0ps
50ps 100ps 150ps
200
0
-200
-400
-600
200
0
-200
-400
50ps 100ps 150ps
400
200
0
-200
-400
-600
-600
-150ps-100ps -50ps 0ps
MAX4950 toc09
400
600
EYE DIAGRAM VOLTAGE (mV)
400
600
EYE DIAGRAM VOLTAGE (mV)
EYE DIAGRAM VOLTAGE (mV)
600
MAX4950 toc08
MAX4950 toc07
INEQ0 = 1, INEQ1 = 0, O_AMP = 0, VIN = 500mVP-P, INEQ0 = 0, INEQ1 = 1, O_AMP = 0, VIN = 500mVP-P, INEQ0 = 0, INEQ1 = 1, O_AMP = 0, VIN = 500mVP-P,
WITH 6in. STRIPLINE OEQ0 = OEQ1 = 0
WITH 19IN. STRIPLINE OEQ0 = OEQ1 = 0
WITH 19in. STRIPLINE OEQ0 = OEQ1 = 0
-150ps-100ps -50ps 0ps
50ps 100ps 150ps
-150ps-100ps -50ps 0ps
50ps 100ps 150ps
_______________________________________________________________________________________
5
MAX4950
Typical Operating Characteristics
(VCC = +3.3V and TA = +25°C, unless otherwise noted. All eye diagrams measured using K28.5 pattern.)
Typical Operating Characteristics (continued)
(VCC = +3.3V and TA = +25°C, unless otherwise noted. All eye diagrams measured using K28.5 pattern.)
200
100
0
-100
-200
-300
50
0
-50
-100
-150
-200
-150ps-100ps -50ps 0ps
50ps 100ps 150ps
500
400
300
200
100
0
-100
-200
-300
-400
-500
-250
-400
MAX4950 toc12
250
200
150
100
EYE DIAGRAM VOLTAGE (mV)
300
MAX4950 toc11
400
INEQ0 = INEQ1 = 0, O_AMP = 0, VIN = 200mVP-P,
INEQ0 = INEQ1 = 0, O_AMP = 0, VIN = 200mVP-P,
OEQ0 = 0, OEQ1 = 1, OUTPUT AFTER 19IN. STRIPLINE OEQ0 = 0, OEQ1 = 0, OUTPUT AFTER 19IN. STRIPLINE
EYE DIAGRAM VOLTAGE (mV)
MAX4950 toc10
INEQ0 = INEQ1 = 0, O_AMP = 1, VIN = 200mVP-P,
OEQ0 = 1, OEQ1 = 0, OUTPUT AFTER 6IN. STRIPLINE
EYE DIAGRAM VOLTAGE (mV)
MAX4950
Quad PCI Express Equalizer/Redriver
-150ps-100ps -50ps 0ps
50ps 100ps 150ps
-150ps-100ps -50ps 0ps
50ps 100ps 150ps
Pin Description
PIN
NAME
1, 9, 17, 22,
30, 38
VCC
Power-Supply Input. Bypass VCC to GND with 1µF and .01µF capacitors in parallel as close to the
device as possible.
2, 5, 8, 10,13,
16, 23, 26, 29,
31, 34, 37
GND
Ground
6
FUNCTION
3
IN0P
Noninverting Input 0
4
IN0N
Inverting Input 0
6
IN1P
Noninverting Input 1
7
IN1N
Inverting Input 1
11
IN2P
Noninverting Input 2
12
IN2N
Inverting Input 2
14
IN3P
Noninverting Input 3
15
IN3N
Inverting Input 3
18
INEQ1
19
INEQ0
Input Equalization Control LSB. INEQ0 is internally pulled down by 60kΩ (typ) resistor. See Table 2.
20
OEQ1
Output Deemphasis Control MSB. OEQ1 is internally pulled down by 60kΩ (typ) resistor. See Table 3.
21
OEQ0
Output Deemphasis Control LSB. OEQ0 is internally pulled down by 60kΩ (typ) resistor. See Table 3.
24
OUT3N
Inverting Output 3
25
OUT3P
Noninverting Output 3
27
OUT2N
Inverting Output 2
28
OUT2P
Noninverting Output 2
Input Equalization Control MSB. INEQ1 is internally pulled down by 60kΩ (typ) resistor. See Table 2.
_______________________________________________________________________________________
Quad PCI Express Equalizer/Redriver
PIN
NAME
32
OUT1N
Inverting Output 1
FUNCTION
33
OUT1P
Noninverting Output 1
35
OUT0N
Inverting Output 0
36
OUT0P
Noninverting Output 0
39
EN
40
RX_DET
41
O_AMP
Output Redrive Selection Input. O_AMP is internally pulled down by 60kΩ (typ) resistor.
42
P_SAV
Power-Save Mode Input. P_SAV is internally pulled down by 60kΩ (typ) resistor. See Table 6.
—
EP
Exposed Pad. Internally connected to GND. Connect EP to a large ground plane to maximize
thermal performance. EP is not intended as an electrical connection point.
Enable Input. Drive EN low for standby mode. Drive EN high for normal mode. EN is internally
pulled down by 60kΩ (typ) resistor.
Receiver Detection Control Bit. Drive RX_DET high to initiate receiver detection. Drive RX_DET low
for normal mode. RX_DET is internally pulled down by 60kΩ (typ) resistor.
Functional Diagram
EN
INEQ0
INEQ1
RECEIVER DETECT
MANAGER
EQUALIZER
IN_P
IN_N
O_AMP
EQUALIZER
GLOBAL
POWER SAVE
MAX4950
RX_DET
P_SAV
OUT_P
OUT_N
OUTPUT
ENABLE
RHI
ELECTRICAL IDLE
DETECTOR
OEQ0
OEQ1
_______________________________________________________________________________________
7
MAX4950
Pin Description (continued)
MAX4950
Quad PCI Express Equalizer/Redriver
Detailed Description
The MAX4950 quad equalizer/redriver is designed to
support both Gen I (2.5GT/s) and Gen II (5.0GT/s) PCIe
data rates. The device contains four identical drivers
with idle/receive detect on each lane and equalization to
compensate for circuit-board loss. Signal integrity at the
receiver is improved by the use of programmable input
equalization circuitry. The MAX4950 output features a
redrive output swing selection input, O_AMP (Table 1),
and programmable output deemphasis, permitting optimal placement of key PCIe components and longer runs
of stripline, microstrip, or cable.
Programmable Input Equalization
The MAX4950 features a programmable input equalizer
capable of providing 0dB, 3.5dB, or 6dB of high-frequency boost by setting 2 control bits, INEQ1 and
INEQ0 (see Table 2).
Programmable Output Deemphasis
The MAX4950 features programmable output deemphasis by setting two control bits, OEQ1 and OEQ0, for deemphasis ratios of 0dB, 3.5dB, and 6dB (see Table 3).
Receiver Detection
The MAX4950 features receiver detection on each channel. Upon initial power-up, if EN is high, receiver detection initializes. Receiver detection can also be initiated
on a rising edge of the RX_DET input when EN is high.
During this time, the part remains in low-power standby
mode and the outputs are disabled, despite the logichigh state of EN. Until a channel has detected a receiver, receiver detection repeats indefinitely on each
channel. If a channel detects a receiver, the other channels are limited to three retries. Upon receiver detection,
channel output and electrical idle detection are enabled.
Note: With a slowly rising power supply, it is recommended to toggle EN to avoid potential receiver detection timeout conditions.
Electrical Idle Detection
The MAX4950 features electrical idle detection to prevent
unwanted noise from being redriven at the output. If the
MAX4950 detects that the differential input has fallen
below VTX-IDLE-THRESH, the MAX4950 squelches the output. For differential input signals that are above
VTX-IDLE-THRESH, the MAX4950 turns on the output and
redrives the signal. There is little variation in output
common-mode voltage between electrical idle and
redrive modes.
Power-Saving Features
The MAX4950 features a power-save mode to reduce
quiescent supply current. In power-save mode, electri8
Table 1. Output Redrive Swing
O_AMP
DIFFERENTIAL OUTPUT VOLTAGE (mVP-P)
0
1000 (typ)
1
750 (typ)
Table 2. Input Equalization
INEQ1
INEQ0
INPUT EQUALIZATION (dB)
0
0
0 at 5.0GT/s
0
1
3.5 (typ) at 5.0GT/s
1
X
6 (typ) at 5.0GT/s
X = Don’t Care.
Table 3. Output Deemphasis
OEQ1
OEQ0
OUTPUT DEEMPHASIS RATIO (dB)
0
0
0 at 5.0GT/s
0
1
3.5 (typ) at 5.0GT/s
1
X
6 (typ) at 5.0GT/s
X = Don’t Care.
Table 4. Receiver Detection Input Function
RX_DET
EN
DESCRIPTION
X
0
Receiver Detection Inactive
0
1
Receiver Detection Inactive
Rising
Edge
1
Initiate Receiver Detection
1
1
Following a Rising Edge, Indefinite
Retry Until Receiver Detected
X = Don’t Care.
cal idle and receiver detection circuitry for channels 1,
2, and 3 are turned off, and all channel operation is
slaved to channel 0. This feature is useful for reducing
power consumption in applications where all channels
operate simultaneously. During normal operation, all
channels have independent electrical idle and receiver
detection. Drive P_SAV high to activate power-save
mode; drive P_SAV low for normal operation. To further
reduce power consumption, the MAX4950 features a
standby input (EN) when the device is not needed. To
place the device in standby mode, drive EN low. To
enable the device, drive EN high. Table 5 shows typical
power consumption differences between normal mode,
power-save mode, and standby mode with different
output redrive strengths.
_______________________________________________________________________________________
Quad PCI Express Equalizer/Redriver
MAX4950
Table 5. Power-Save Mode Quiescent Power Dissipation
EN
P_SAV
O_AMP
QUIESCENT POWER
SUPPLY CURRENT
(typ) (mA)
QUIESCENT POWER
SUPPLY CURRENT
(max) (mA)
QUIESCENT POWER
DISSIPATION
(3.3V, typ) (mW)
QUIESCENT POWER
DISSIPATION
(3.6V, max) (mW)
0
0
0
100
125
330
450
0
0
1
80
100
264
360
0
1
0
100
125
330
450
0
1
1
80
100
264
360
1
0
0
262
328
865
1181
1
0
1
242
303
799
1091
1
1
0
214
268
706
965
1
1
1
194
243
640
875
Applications Information
Figure 2 shows a typical application with two
MAX4950s, both residing on the main board, with input
and output equalization set individually for optimal performance. The receive equalizer is set to receive a
degraded signal coming from a remote board through
two sets of connectors, and a midplane stripline transmission. The output of the Rx section has little or no output equalization. The Tx section takes a high-quality
signal, and provides boost to the output (deemphasis).
Layout
Circuit-board layout and design can significantly affect
the performance of the MAX4950. Use good high-frequency design techniques, including minimizing
ground inductance and using controlled-impedance
transmission lines on data signals. Power-supply
decoupling should also be placed as close to VCC as
possible. Always connect VCC to a power plane. It is
recommended to run receive and transmit on different
layers to minimize crosstalk.
Exposed-Pad Package
The exposed-pad, 42-pin TQFN package incorporates
features that provide a very low thermal-resistance path
for heat removal from the IC. The exposed pad on the
MAX4950 must be soldered to the circuit-board ground
plane for proper thermal performance. For more information on exposed-pad packages, refer to Maxim
Application Note HFAN-08.1: Thermal Considerations of
QFN and Other Exposed-Paddle Packages.
Power-Supply Sequencing
Caution: Do not exceed the absolute maximum ratings because stresses beyond the listed ratings
may cause permanent damage to the device.
Proper power-supply sequencing is recommended for
all devices. Always apply GND then VCC before applying signals, especially if the signal is not current limited.
Chip Information
PROCESS: BiCMOS
MAIN BOARD
REMOTE BOARD
Tx
MAX4950
MIDPLANE
4 DIFFERENTIAL PAIRS
Rx
PCIe
PCIe
MAX4950
Rx
4 DIFFERENTIAL PAIRS
Tx
CONNECTORS
Figure 2. Typical Application Diagram
_______________________________________________________________________________________
9
MAX4950
Quad PCI Express Equalizer/Redriver
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
42 TQFN-EP
T423590+1
21-0181
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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