19-4139; Rev 1; 8/08
Overvoltage-Protection Controllers
with a Low RON Internal FET
The MAX4970/MAX4971/MAX4972 family of overvoltage protection devices features a low 40mΩ (typ) RON
internal FET and protect low-voltage systems against
voltage faults up to +28V. These devices also drive an
optional external pFET to protect against reverse-polarity input voltages. When the input voltage exceeds the
overvoltage threshold, the internal FET is turned off to
prevent damage to the protected components.
All switches feature a 2.3A (min) current-limit protection. During a short-circuit occurrence, the device operates in an autoretry mode where the internal MOSFET is
turned on to check if the fault has been removed. The
autoretry interval time is 15ms, and if the fault is
removed, the MOSFET remains on.
The MAX4970/MAX4971/MAX4972 feature an enable
input (EN) that controls the operation of the internal
nFET as well as the optional external pFET. The use of
EN allows the external pFET to block reverse voltages
independent of any signal present at the output.
The overvoltage thresholds (OVLO) are preset to
4.65V (MAX4972), 5.8V (MAX4970), or 6.35V (MAX4971).
The undervoltage thresholds (UVLO) are preset to 2.45V.
When the input voltage drops below the UVLO, the
devices enter a low-current standby mode.
All devices are offered in a small 12-bump, WLP package and operate over the -40°C to +85°C extended
temperature range.
Features
♦ Input Voltage Protection up to +28V
♦ Integrated nFET Switch
♦ Reverse Voltage Protection with External pFET
♦ Enable Input
♦ Preset Overvoltage Protection Trip Level
5.8V (MAX4970)
6.35V (MAX4971)
4.65V (MAX4972)
♦ Low-Current Undervoltage-Lockout Mode
♦ Short-Circuit Protection (Autoretry)
♦ Internal 15ms Startup Delay and Retry Times
♦ Input-Voltage Power-Good Logic Output
♦ Thermal-Shutdown Protection
♦ 2mm x 1.5mm, 12-Bump WLP Package
Pin Configuration
TOP VIEW (BUMPS ON BOTTOM)
1
2
3
4
MAX4970/MAX4971/MAX4972
A
ACOK
Applications
OUT
OUT
OUT
OUT
IN
GP
IN
IN
IN
B
GND
Cell Phones
Digital Still Cameras
C
PDAs and Palmtop Devices
EN
MP3 Players
WLP
Ordering Information/Selector Guide
PART
PIN-PACKAGE
TOP MARK
PACKAGE CODE
UVLO (V)
OVLO (V)
ACOK ACTION
AAA
W121A2+1
2.45
5.8
UVLO only
MAX4970EWC+T
12 WLP
MAX4971EWC+T
12 WLP
AAB
W121A2+1
2.45
6.35
UVLO only
MAX4972EWC+T
12 WLP
AAC
W121A2+1
2.45
4.65
UVLO and OVLO
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes a lead-free/RoHS-compliant package.
T = Tape-and-reel package.
Typical Operating Circuit appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX4970/MAX4971/MAX4972
General Description
MAX4970/MAX4971/MAX4972
Overvoltage-Protection Controllers
with a Low RON Internal FET
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
IN ............................................................................-0.3V to +30V
IN-GP.........................................................................(30V - 5.4V)
OUT.............................................................-0.3V to +(IN + 0.3)V
EN, ACOK.................................................................-0.3V to +6V
GP...........................................................................-0.3V to +30V
Continuous Power Dissipation (TA = +70°C) for
Multilayer Board:
12-Bump WLP (derate 8.5mW/°C above +70°C).....678mW
WLP Package Junction-to-Ambient Thermal
Resistance (θJA) (Note 1)...........................................118°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering) .........................................+300°C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +2.2V to +28V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
Input Voltage Range
SYMBOL
CONDITIONS
VIN
IIN
EN = 0V
VIN = 5V (MAX4970),
VIN = 5.5V (MAX4971),
VIN = 3.8V (MAX4972)
TA = +25°C
176
TA = TMIN to TMAX
IN Undervoltage Lockout
IUVLO
VUVLO
TA = +25°C
60
TA = TMIN to TMAX
230
107
100
40
VIN falling
2.20
2.45
2.65
VIN rising
2.25
2.5
2.7
5.6
5.9
1
VIN rising
VOVLO
VIN falling
2
V
50
VIN < VUVLO; VIN = 2.2V
MAX4970
IN Overvoltage Lockout Hysteresis
UNITS
28
µA
150
IN Undervoltage Lockout Hysteresis
Overvoltage Trip Level
MAX
250
EN = 1.4V
UVLO Supply Current
TYP
2.2
EN = 0V
VIN = 12V; GP clamp on
Input Supply Current
MIN
%
6.0
6.4
6.8
MAX4972
4.35
4.70
5.05
MAX4970
5.50
5.80
6.15
MAX4971
6.00
6.35
6.70
MAX4972
4.30
4.65
5.00
_______________________________________________________________________________________
V
6.2
MAX4971
1
µA
V
%
Overvoltage-Protection Controllers
with a Low RON Internal FET
(VIN = +2.2V to +28V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
40
90
mΩ
Switch On-Resistance
RON
VIN = 5V (MAX4970),
VIN = 5.5V (MAX4971),
VIN = 3.8V (MAX4972); IOUT = 400mA
Overcurrent Protection Threshold
ILIM
VIN = 5V (MAX4970),
VIN = 5.5V (MAX4971),
VIN = 3.8V (MAX4972)
2.30
3.36
VGPC
VIN - VGP, VIN up to 28V
5.4
7.0
8.5
V
GP Pulldown Resistor
RGPPD
EN = low,
VGP = VIN = 5V (MAX4970),
VGP = VIN = 5.5V (MAX4971),
VGP = VIN = 3.8V (MAX4972)
16
36
54
kΩ
GP Pullup Resistor to IN
RGPPU
EN = high, VIN = 5V
9
15
25
kΩ
GP Clamp Voltage
EN Input-Voltage High
VIH
EN Input-Voltage Low
VIL
EN Input Leakage Current
IEN
ACOK Output-Low Voltage
VOL
ACOK High Leakage Current
A
1.4
V
VEN = 5V
ISINK = 1mA
VACOK = 5.5V, ACOK deasserted
Thermal Shutdown
0.4
V
1
µA
0.4
V
1
µA
+150
Thermal-Shutdown Hysteresis
°C
40
Maximum Output Capacitance
COUT
°C
1000
µF
TIMING CHARACTERISTICS (Figure 1)
Debounce Time
tINDBC
Switch Turn-On Time
tON
ACOK Assertion Time
tACOK
Switch Turn-Off Time
tOFF
Time from VUVLO < VIN < VOVLO, RLOAD =
100Ω, CLOAD = 1µF to charge-pump enable
15
ms
VUVLO < VIN < VOVLO, RLOAD = 100Ω,
CLOAD = 1µF from EN low to 90% of VOUT
13
ms
VUVLO < VIN < VOVLO to ACOK low (MAX4972)
15
ms
VIN < VUVLO to internal switch off
4
8
VIN > VOVLO to internal switch off,
RLOAD = 100Ω
5
11
VUVLO < VIN to ACOK low (MAX4970/MAX4971)
µs
Current Limit Turn-Off Time
tBLANK
Overcurrent fault to internal switch off
10
µs
Autoretry Time
tRETRY
From overcurrent fault to internal switch
turn-on, Figure 2
15
ms
Note 2: All specifications are 100% production tested at TA = +25°C, unless otherwise noted. Specifications are over -40°C to +85°C
and are guaranteed by design.
_______________________________________________________________________________________
3
MAX4970/MAX4971/MAX4972
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
RON (mΩ)
166
145
124
103
48
32
82
16
61
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
40
0
19
0
7
14
21
0.990
-40
28
-15
10
35
60
85
-40
10
60
TEMPERATURE (°C)
NORMALIZED OVLO THRESHOLD
vs. TEMPERATURE
CURRENT LIMIT
vs. TEMPERATURE
NORMALIZED ACOK ASSERTION TIME
vs. TEMPERATURE
1.002
1.000
0.998
0.996
3.50
3.25
0.994
0.990
10
35
60
85
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
3.00
-15
MAX4970/71/72 toc06
3.75
CURRENT LIMIT (A)
1.004
NORMALIZED ACOK ASSERTION TIME
1.006
-40
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
NORMALIZED DEBOUNCE TIME
vs. TEMPERATURE
POWER-UP RESPONSE
85
-40
-15
10
35
MAX4970/71/72 toc07
1.04
1.03
1.02
60
85
TEMPERATURE (°C)
OVERVOLTAGE FAULT RESPONSE
MAX4970/71/72 toc09
AX4970/71/72 toc08
1.05
85
1.05
MAX4970/1/2 toc05
MAX4970/1/2 toc04
4.00
0.992
8V
VIN
5V/div
VIN
5V/div
3V
1.01
1.00
0.99
VOUT
5V/div
VOUT
5V/div
VACOK
5V/div
IOUT
1A/div
VACOK
5V/div
IOUT
500mA/div
0.98
0.97
0.96
0.95
-40
-15
10
35
60
85
10ms/div
20μs/div
TEMPERATURE (°C)
4
35
TEMPERATURE (°C)
1.008
-40
-15
VOLTAGE (V)
1.010
NORMALIZED OVLO THRESHOLD
AX4970/71/72 toc03
187
64
1.010
NORMALIZED UVLO THRESHOLD
208
AX4970/71/72 toc02
80
MAX4970/71/72 toc01
229
CURRENT (µA)
NORMALIZED UVLO THRESHOLD
vs. TEMPERATURE
RON vs. TEMPERATURE
250
NORMALIZED DEBOUNCE TIME
MAX4970/MAX4971/MAX4972
Overvoltage-Protection Controllers
with a Low RON Internal FET
_______________________________________________________________________________________
Overvoltage-Protection Controllers
with a Low RON Internal FET
UNDERVOLTAGE FAULT RESPONSE
OVERCURRENT DURATION TIME
(DURING AUTORETRY)
SHORT-CIRCUIT FAULT RESPONSE
MAX4970/71/72 toc10
MAX4970/71/72 toc12
MAX4970/71/72 toc11
RLOAD = 1Ω
CLOAD = 0.1µF
VIN
5V/div
VIN
5V/div
4V
VOUT
5V/div
VACOK
5V/div
IOUT
1A/div
4ms/div
VOUT
2V/div
VOUT
5V/div
VACOK
5V/div
IOUT
1A/div
IOUT
10A/div
4ms/div
4µs/div
Pin Description
PIN
NAME
FUNCTION
A1
ACOK
Active-Low Open-Drain Adapter-Voltage Indicator Output. ACOK is driven low after the adapter
voltage is stable between UVLO and OVLO for 15ms (typ) (MAX4972), or after the adapter voltage
is stable and greater than UVLO for 15ms (typ) (MAX4970/MAX4971). Connect a pullup resistor
from ACOK to the logic I/O voltage of the host system.
A2, A3,
A4, B2
OUT
B1
GND
Output Voltage. Output of the internal switch. Connect all the OUT outputs together for proper
operation.
Ground
B3, C2,
C3, C4
IN
Voltage Input. Bypass IN with a 1µF ceramic capacitor as close as possible to the device to
obtain ±15kV Human Body Model (HBM) ESD protection. No capacitor is required for ±2kV (HBM)
ESD protection. Connect all the IN inputs together for proper operation.
B4
GP
External pFET Gate-Drive Output. GP pulls the external pFET gate down when the input is above
UVLO and when EN is active (low).
C1
EN
Enable Input. Drive EN low to turn GP pulldown on, GP pullup off, and to turn on the charge pump.
Drive EN high to turn off the device.
_______________________________________________________________________________________
5
MAX4970/MAX4971/MAX4972
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Overvoltage-Protection Controllers
with a Low RON Internal FET
MAX4970/MAX4971/MAX4972
Functional Diagram
IN
OUT
OVERCURRENT
FAULT
CHARGE
PUMP
START
RGPPU
15ms
DEBOUNCE
TIMER AND
RETRY TIME
TEMPERATURE
FAULTS
GP
+
RGPPD
VBG
REFERENCE
-
EN
OSCILLATOR
+
-
ACOK
LOGIC
CONTROL
MAX4970
MAX4971
MAX4972
EN
GND
Detailed Description
Internal nFET
The MAX4970/MAX4971/MAX4972 overvoltage protection devices feature a low RON internal FET and protect
low-voltage systems against voltage faults up to +28V.
If the input voltage exceeds the overvoltage threshold,
the internal MOSFET is turned off to prevent damage to
the protected components. These devices also drive an
optional external pFET to protect against reverse-polarity input voltages. The 15ms debounce time prevents
false turn-on of the internal nFET during startup.
The MAX4970/MAX4971/MAX4972 incorporate an internal nFET with a 40mΩ (typ) RON. The nFET is internally
driven by a charge pump that generates a 5V voltage
above IN. The internal nFET is equipped with 2.3A (min)
current-limit protection that turns off the nFET within
10µs (typ) during an overcurrent fault condition.
Device Operation
The MAX4970/MAX4971/MAX4972 have timing logic
that control the turn-on of the internal nFET. The timing
logic controls the turn-on of the charge pump and the
state of the open-drain ACOK output. If VIN < VUVLO or
if VIN > VOVLO, the timing logic disables the charge
pump. If VUVLO < VIN < VOVLO, the internal charge
pump is enabled. The charge-pump startup, after a
15ms debounce delay, turns on the internal nFET (see
the Functional Diagram). ACOK is high impedance during startup until the ACOK 15ms debounce period
expires. At this point, the device is in its on state. At any
time, if VIN drops below VUVLO or rises above VOVLO,
the charge pump is disabled.
6
Autoretry
The MAX4970/MAX4971/MAX4972 have an overcurrent
autoretry function that turns on the nFET again after a
15ms (typ) retry time (see Figure 2). The fast turn-off
time and 15ms retry time result in a very low duty cycle
to keep power consumption low. If the faulty load condition is not present, the nFET remains on.
GP gate Drive
The GP gate drive is controlled by internal logic and by
the EN input. When EN is high, the internal pullup
between GP and IN is active, thus disabling the external pFET, and the load is protected against negative
voltages down to the voltage rating of the external
pFET. When EN is active (low), and the input voltage at
IN is above the UVLO threshold, the pulldown between
GP and IN is active, thus enabling the external pFET.
_______________________________________________________________________________________
Overvoltage-Protection Controllers
with a Low RON Internal FET
MAX4970/MAX4971/MAX4972
OVLO
UVLO
tOFF
IN
tOFF
tON
90% VOUT
10% VOUT
OUT
tINDBC
tINDBC
tINDBC
tOFF
tACOK
tACOK
GP
tACOK
tACOK
tACOK
*ACOK
tACOK
tACOK
**ACOK
*ACOK TIMING FOR THE MAX4972.
**ACOK TIMING FOR THE MAX4970/MAX4971.
Figure 1. MAX4970/MAX4971/MAX4972 Timing Diagram
tOFF
nFET ON
nFET ON
tRETRY
CURRENT
THROUGH
nFET
Note that the UVLO threshold is measured at IN, but the
input voltage is applied at the drain of the external
pFET. The body diode of the external pFET adds to the
UVLO threshold increasing its value to VBODYDIODE +
V UVLO . The internal clamp diode limits the gate to
source voltage on the external pFET to 7.0V (typ) for
protection of the pFET during an overvoltage fault.
Undervoltage Lockout (UVLO)
nFET OFF
The MAX4970/MAX4971/MAX4972 have a 2.45V undervoltage-lockout threshold (UVLO). When V IN is less
than VUVLO, ACOK is high impedance.
Overvoltage Lockout (OVLO)
ILIM
Figure 2. Autoretry Timing Diagram
The MAX4970 has a 5.8V (typ) overvoltage threshold (OVLO), the MAX4971 has a 6.35V (typ) OVLO
threshold, and the MAX4972 has a 4.65V (typ) OVLO
threshold. When VIN is greater than VOVLO, ACOK is
high impedance for the MAX4972.
_______________________________________________________________________________________
7
MAX4970/MAX4971/MAX4972
Overvoltage-Protection Controllers
with a Low RON Internal FET
ACOK
ESD Test Conditions
ACOK is an active-low, open-drain output that asserts
low when VUVLO < VIN < VOVLO for 15ms (typ) for the
MAX4972. ACOK asserts low when VIN > VUVLO for
15ms (typ) for the MAX4970 and MAX4971. Connect a
pullup resistor from ACOK to the logic I/O voltage of
the host system. During a short-circuit fault, ACOK
may deassert due to VIN dropping below VUVLO from
high current.
ESD performance depends on a number of conditions.
The MAX4970/MAX4971/MAX4972 are specified for
±15kV (HBM) typical ESD resistance on IN when IN is
bypassed to ground with a 1µF ceramic capacitor.
Thermal-Shutdown Protection
The MAX4970/MAX4971/MAX4972 feature thermalshutdown circuitry. The internal nFET turns off when the
junction temperature exceeds +150°C (typ). The device
exits thermal shutdown after the junction temperature
cools by 40°C (typ).
HBM ESD Protection
Figure 3 shows the Human Body Model, and Figure 4
shows the current waveform it generates when discharged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the device through a
1.5kΩ resistor.
RC
1MΩ
Applications Information
CHARGE-CURRENTLIMIT RESISTOR
RD
1.5kΩ
DISCHARGE
RESISTANCE
Reverse Polarity Protection
The optional external p-channel MOSFET can provide
reverse polarity protection down to the voltage rating of
the pFET.
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
IN Bypass Capacitor
For most applications, bypass IN to GND with a 1µF
ceramic capacitor as close as possible to the device to
enable ±15kV (HBM) ESD protection on the pin. If the
external pFET is used, the 1uF capacitor must be connected between the drain and ground. If ±15kV (HBM)
ESD is not required, there is no capacitor required at
IN. If the power source has significant inductance due
to long lead length, take care to prevent overshoots
due to the LC tank circuit and provide protection if necessary to prevent exceeding the +30V absolute maximum rating on IN.
OUT Output Capacitor
The slow turn-on time provides a soft-start function that
allows the MAX4970/MAX4971/MAX4972 to charge an
output capacitor up to 1000µF without turning off due to
an overcurrent condition.
Figure 3. Human Body ESD Test Model
IP 100%
90%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
36.8%
10%
0
0
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 4. Human Body Current Waveform
8
_______________________________________________________________________________________
Overvoltage-Protection Controllers
with a Low RON Internal FET
OPTIONAL pFET
CHARGER
OUT
IN
PHONE
LOAD
1μF
VI/O
GP
VBUS
USB
CONNECTOR
MAX4970
MAX4971
MAX4972
ACOK
EN
GND
Package Information
Chip Information
PROCESS: BiCMOS
MICROCONTROLLER
For the latest package outline information, go to
www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
12 WLP
W121A2+1
21-0009
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX4970/MAX4971/MAX4972
Typical Operating Circuit
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