19-1016; Rev 2; 2/96
CMOS, Quad, Serial-Interface
8-Bit DAC
The MAX500 is a quad, 8-bit, voltage-output digital-toanalog converter (DAC) with a cascadable serial interface. The IC includes four output buffer amplifiers and
input logic for an easy-to-use, two- or three-wire serial
interface. In a system with several MAX500s, only one
serial data line is required to load all the DACs by cascading them. The MAX500 contains double-buffered
logic and a 10-bit shift register that allows all four DACs
to be updated simultaneously using one control signal.
There are three reference inputs so the range of two of
the DACs can be independently set while the other two
DACs track each other.
The MAX500 achieves 8-bit performance over the full
operating temperature range without external trimming.
________________________Applications
Minimum Component Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
________________Functional Diagram
SRO
VREFC
AGND
DGND VSS VDD LDAC VREFA/B VREFD
VOUTA
INPUT
REG A
DAC
REG A
INPUT
REG B
DAC
REG B
DAC A
DATA BUS
DAC B
VOUTC
INPUT
REG C
DAC
REG C
DAC C
CONTROL
LOGIC
LOAD SDA
SCL
DAC
REG D
♦ Double-Buffered Digital Inputs
♦ Microprocessor and TTL/CMOS Compatible
♦ Requires No External Adjustments
♦ Two- or Three-Wire Cascadable Serial Interface
♦ 16-Pin DIP/SO Package and 20-Pin LCC
♦ Operates from Single or Dual Supplies
______________Ordering Information
TEMP. RANGE PIN-PACKAGE ERROR (LSB)
PART
MAX500ACPE
0°C to +70°C
16 Plastic DIP
±1
MAX500BCPE
MAX500ACWE
MAX500BCWE
MAX500BC/D
MAX500AEPE
MAX500BEPE
MAX500AEWE
MAX500BEWE
MAX500AEJE
MAX500BEJE
MAX500AMJE
MAX500BMJE
MAX500AMLP
MAX500BMLP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
DAC D
MAX500
16 Plastic DIP
16 Wide SO
16 Wide SO
Dice*
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
16 CERDIP
16 CERDIP
16 CERDIP
16 CERDIP
20 LCC
20 LCC
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2
±1
±2
±1
±2
*Contact factory for dice specifications.
TOP VIEW
V OUT B 1
16 V OUT C
V OUT A 2
15 V OUT D
V SS 3
V REF A/B 4
VOUTD
INPUT
REG D
♦ Buffered Voltage Outputs
_________________Pin Configurations
VOUTB
10/11BIT
SHIFT
REGISTER
____________________________Features
14 V DD
MAX500
13 V REF C
AGND 5
12 V REF D
DGND 6
11 SRO
LDAC 7
10 SCL
SDA 8
9
LOAD
DIP/SO
Pin Configurations continued on last page.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX500
_______________General Description
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
ABSOLUTE MAXIMUM RATINGS
Power Requirements
VDD to AGND...........................................................-0.3V, +17V
VDD to DGND ..........................................................-0.3V, +17V
VSS to DGND ..................................................-7V, (VDD + 0.3V)
VDD to VSS ...............................................................-0.3V, +24V
Digital Input Voltage to DGND ....................-0.3V, (VDD + 0.3V)
VREF to AGND .............................................-0.3V, (VDD + 0.3V)
VOUT to AGND (Note 1)...............................-0.3V, (VDD + 0.3V)
Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ............842mW
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C) ...............800mW
LCC (derate 9.09mW/°C above +70°C).......................727mW
Operating Temperature Ranges
MAX500_C_ _ ....................................................0°C to + 70°C
MAX500_E_ _...................................................-40°C to +85°C
MAX500_M_ _ ................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Note 1: The outputs may be shorted to AGND, provided that the power dissipation of the package is not exceeded.
Typical short-circuit current to AGND is 25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Dual Supplies
(VDD = +11.4V to +16.5V, VSS = -5V ±10%, AGND = DGND = 0V, VREF = +2V to (VDD - 4V), TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
8
VDD = 15V ±5%,
VREF = 10V
Total Unadjusted Error
±1
±2
±1/2
±1
±1
±1/2
±1
MAX500A
MAX500B
Guaranteed monotonic
MAX500A
MAX500B
VREF = 10V
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale Tempco
TA = +25°C
Zero-Code Error
TA = TMIN to TMAX
±5
MAX500A
MAX500B
MAX500A
MAX500B
±30
VREFC, VREFD
VREFA/B
TA = +25°C, code dependent (Note 2)
TA = +25°C (Notes 2, 3)
TA = +25°C (Notes 2, 3)
Reference Input Resistance
Reference Input Capacitance
Channel-to-Channel Isolation
AC Feedthrough
DIGITAL INPUTS
2
11
5.5
VIH
Digital Input Low Voltage
VIL
2.4
Digital Output High Voltage
VOH
IOUT = -1mA, SRO only
VDD - 1
Digital Output Low Voltage
VOL
IOUT = 1mA, SRO only
0.4
Digital Input Leakage Current
(Note 4)
Digital Input Capacitance
TA = +25°C (Note 2)
Excluding LOAD
LOAD = 0V
_______________________________________________________________________________________
LSB
LSB
LSB
mV
µV/°C
VDD - 4
V
kΩ
100
pF
dB
dB
5.5
V
0.8
V
-60
-70
Digital Input High Voltage
LSB
ppm/°C
±15
±20
±20
±30
Zero-Code Tempco
REFERENCE INPUT
Reference Input Range
2
Bits
MAX500A
MAX500B
V
V
±1
30
8
µA
pF
CMOS, Quad, Serial-Interface
8-Bit DAC
(VDD = +11.4V to +16.5V, VSS = -5V ±10%, AGND = DGND = 0V, VREF = +2V to (VDD - 4V), TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
3
8
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
TA = +25°C (Note 2)
V/µs
VOUT Settling Time
To ±1/2LSB, VREF = 10V, VDD = +15V,
2kΩ in parallel with 100pF load (Note 2)
2.5
Digital Feedthrough
(Note 5)
50
nV-s
Digital Crosstalk
(Note 5)
50
nV-s
Output Load Resistance
VOUT = 10V
4.5
2
µs
kΩ
Positive Supply
Voltage
POWER
SUPPLIES
VDD
For specified performance
11.4
16.5
V
Positive Supply Voltage
VDD
For specified performance
11.4
16.5
V
Positive Supply Current
IDD
Outputs unloaded
Negative Supply Current
ISS
Outputs unloaded
TA = +25°C
10
TA = TMIN to TMAX
12
TA = +25°C
-9
TA = TMIN to TMAX
-10
mA
mA
SWITCHING CHARACTERISTICS (TA = +25°C, Note 6)
3-Wire
Mode
SDA Valid
to SCL Setup
tS1
150
ns
SDA Valid to SCL Setup
tS1
150
ns
SDA Valid to SCL Hold
tH
0
ns
SCL High Time
t1
350
ns
SCL Low Time
t2
350
ns
SCL Rise Time
(Note 7)
50
µs
SCL Fall Time
(Note 7)
50
µs
LOAD Pulse Width
LOAD Delay from SCL
tLDW
150
ns
tLDS
150
ns
LDAC Pulse Width
tLDAC
150
ns
SRO Output Delay
tD1
CLOAD = 50pF
150
ns
2-Wire
Mode
SCL High
Time
t1
350
ns
SDA Valid to SCL Hold
tH
0
ns
SCL High Time
t1
350
ns
SCL Low Time
t2
350
ns
SCL Rise Time
(Note 7)
50
µs
SCL Fall Time
(Note 7)
50
µs
LDAC Pulse Width
tLDAC
150
ns
SCL Valid to SDA Setup
tS1
Start condition
150
ns
SDA Valid to SCL Setup
tS2
Stop condition
100
ns
SDA Valid to Rising SCL
tS3
SRO Output Delay
tD1
125
CLOAD = 50pF
ns
150
ns
_______________________________________________________________________________________
3
MAX500
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
ELECTRICAL CHARACTERISTICS—Single Supply
(VDD = +15V ±5%, VSS = AGND = DGND = 0V, VREF = 10V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
Relative Accuracy
Differential Nonlinearity
MAX
UNITS
Bits
MAX500A
MAX500B
MAX500A
MAX500B
±1
±2
±1/2
±1
±1
±1/2
±1
Guaranteed monotonic
MAX500A
MAX500B
Full-Scale Error
Full-Scale Tempco
VREF = 10V
TA = +25°C
Zero-Code Error
TA = TMIN to TMAX
LSB
LSB
LSB
LSB
±5
ppm/°C
MAX500A
MAX500B
MAX500A
MAX500B
±15
±20
±20
±30
Zero-Code Tempco
REFERENCE INPUT—All specifications are the same as for dual supplies.
DIGITAL INPUTS—All specifications are the same as for dual supplies.
DYNAMIC PERFORMANCE—All specifications are the same as for dual supplies.
POWER SUPPLIES
Positive Supply Voltage
VDD
For specified performance
TA = +25°C
Positive Supply Current
IDD
Outputs unloaded
TA = TMIN to TMAX
SWITCHING CHARACTERISTICS—All specifications are the same as for dual supplies.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
TYP
8
VDD = 15V ±5%,
VREF = 10V
Total Unadjusted Error
mV
±30
14.25
µV/°C
15.75
10
12
V
mA
Guaranteed by design. Not production tested.
TA = +25°C, VREF = 10kHz, 10V peak-to-peak sine wave.
LOAD has a weak internal pull-up resistor to VDD.
DAC switched from all 1s to all 0s, and all 0s to all 1s code.
Sample tested at +25°C to ensure compliance.
Slow rise and fall times are allowed on the digital inputs to facilitate the use of opto-couplers. Only timing for SCL is given
because the other digital inputs should be stable when SCL transitions.
__________________________________________Typical Operating Characteristics
0.5
VDD = 15V
0
VDD = 12V
-0.5
-1.0
TA = +25°C, VSS = -5V
0.5
0
-0.5
VDD = 12V
VDD = 15V
-1.0
0
2
4
6
VREF (V)
4
1.0
8
10
12
14
MAX500-05
MAX500-04
TA = +25°C, VSS = -5V
DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE
DIFFERENTIAL NONLINEARITY (LSB)
RELATIVE ACCURACY vs. REFERENCE VOLTAGE
1.0
RELATIVE ACCURACY (LSB)
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
0
2
4
6
8
10
VREF (V)
_______________________________________________________________________________________
12
14
CMOS, Quad, Serial-Interface
8-Bit DAC
SUPPLY CURRENT (mA)
RO ≅ 200Ω
12
ISINK (mA)
10
VSS = 0V
10
8
6
4
2.0
IDD
8
6
4
2
0
-2
ISS
1.0
0.0
-1.0
-4
0
-6
-2.0
4
8
6
-55
10
-25
VOUT (V)
0
_______________Detailed Description
The MAX500 has four matched voltage-output digital-toanalog converters (DACs). The DACs are “inverted”
R-2R ladder networks which convert 8 digital bits into
equivalent analog output voltages in proportion to the
applied reference voltage(s). Two DACs in the MAX500
have a separate reference input while the other two
DACs share one reference input. A simplified circuit
diagram of one of the four DACs is provided in Figure 1.
R
…
2R
R
2R
R
2R
VOUT
VREF DB0
AGND
DB5
DB5
…
50
75
DB6
DB6
100
125
VOUTD
VSS = -5V
-55
-25
0
25
50
75
100
125
TEMPERATURE (°C)
of the V REF inputs is code dependent. The lowest
value, approximately 11kΩ (5.5kΩ for VREFA/B), occurs
when the input code is 01010101. The maximum value
of infinity occurs when the input code is 00000000.
Because the input resistance at VREF is code dependent, the DAC’s reference sources should have an output impedance of no more than 20Ω (no more than
10Ω for VREFA/B). The input capacitance at VREF is
also code dependent and typically varies from 15pF to
35pF (30pF to 70pF for V REF A/B). V OUT A, V OUT B,
VOUTC, and VOUTD can be represented by a digitally
programmable voltage source as:
VOUT = Nb x VREF / 256
where N b is the numeric value of the DAC’s binary
input code.
Output Buffer Amplifiers
2R
2R
DB0
25
TEMPERATURE (°C)
VOUTC
-0.5
-1.5
2
VOUTB
0.5
2
0
VOUTA
1.5
ZERO-CODE ERROR (mV)
14
MAX500-02
VSS = -5V
ZERO-CODE ERROR
vs. TEMPERATURE
12
MAX500-01
16
SUPPLY CURRENT
vs. TEMPERATURE
MAX500-03
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
DB7
DB7
…
Figure 1. Simplified DAC Circuit Diagram
VREF Input
The voltage at the VREF pins (pins 4, 12, and 13) sets
the full-scale output of the DAC. The input impedance
All voltage outputs are internally buffered by precision
unity-gain followers, which slew at greater than 3V/µs.
When driving 2kΩ in parallel with 100pF with a full-scale
transition (0V to +10V or +10V to 0V), the output settles
to ±1/2LSB in less than 4µs. The buffers will also drive
2kΩ in parallel with 500pF to 10V levels without oscillation. Typical dynamic response and settling performance of the MAX500 is shown in Figures 2 and 3.
A simplified circuit diagram of an output buffer is
shown in Figure 4. Input common-mode range to
AGND is provided by a PMOS input structure. The output circuitry incorporates a pull-down circuit to actively
drive VOUT to within +15mV of the negative supply
(VSS). The buffer circuitry allows each DAC output to
_______________________________________________________________________________________
5
MAX500
____________________________Typical Operating Characteristics (continued)
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
POSITIVE STEP
(VSS = -5V or 0V)
NEGATIVE STEP
(VSS = -5V or 0V)
LDAC
5V/div
LDAC
5V/div
INPUT
(5V/div)
OUTPUT
100mV/div
OUTPUT
100mV/div
OUTPUT
(20mV/div)
1µs/div
1µs/div
Figure 2. Positive and Negative Settling Times
VDD
DYNAMIC RESPONSE
(VSS = -5V or 0V)
LDAC
5V/div
FROM
INVERTED
DAC
OUTPUT (+)
OUTPUT
5V/div
NPN
EMITTER
FOLLOWER
PULL-UP
PMOS
(-)
VOUT
INPUTS
CC
NMOS
ACTIVE
PULL-DOWN
CIRCUIT
2µs/div
Figure 3. Dynamic Response
VSS
Figure 4. Simplified Output Buffer Circuit
sink, as well as source up to 5mA. This is especially
important in single-supply applications, where V SS is
connected to AGND, so that the zero error is kept at or
under 1/2LSB (VREF = +10V). A plot of the Output Sink
Current vs. Output Voltage is shown in the Typical
Operating Characteristics section.
Digital Inputs
and Interface Logic
The digital inputs are compatible with both TTL and 5V
CMOS logic; however, the power-supply current (IDD)
is somewhat dependent on the input logic level. Supply
current is specified for TTL input levels (worst case) but
is reduced (by about 150µA) when the logic inputs are
driven near DGND or 4V above DGND.
Do not drive the digital inputs directly from CMOS logic
running from a power supply exceeding 5V. When driv6
ing SCL through an opto-isolator, use a Schmitt trigger
to ensure fast SCL rise and fall times.
The MAX500 allows the user to choose between a
3-wire serial interface and a 2-wire serial interface.
The choice between the 2-wire and the 3-wire interface is set by the LOAD signal. If the LOAD is allowed
to float (it has a weak internal pull-up resistor to VDD),
the 2-wire interface is selected. If the LOAD signal is
kept to a TTL-logic high level, the 3-wire interface
is selected.
3-Wire Interface
The 3-wire interface uses the classic Serial Data (SDA),
Serial Clock (SCL), and LOAD signals that are used
in standard shift registers. The data is clocked in on
the falling edge of SCL until all 10 bits (8 data bits and
2 address bits) are entered into the shift register.
_______________________________________________________________________________________
CMOS, Quad, Serial-Interface
8-Bit DAC
D7
MSB
A0
SCL
D6
D5
D4
D3
D0
LSB
D1
D2
MAX500
A1
SDA
LOAD
LDAC
SRO
(SERIAL OUTPUT)
t1
t2
SCL
SCL
tS1
SDA
tLDS
tH
tLDW
LOAD
LDAC
SRO
tLDS
tD1
tLDAC
Figure 5. 3-Wire Mode
A1
A0
SCL
D7
MSB
D6
D5
D4
D3
D2
D0
LSB
D1
SDA
LDAC
SRO
(SERIAL OUTPUT)
t2
t1
SCL
SCL
tS2
tS3
tS1
SDA
SDA
tD1
SRO
tD1
tLDS
LDAC
tLDAC
Figure 6. 2-Wire Mode
_______________________________________________________________________________________
7
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
A low level on LOAD line initiates the transfer of data
from the shift register to the addressed input register.
The data can stay in this register until all four of the
input registers are updated. Then all of the DAC registers can be simultaneously updated using the LDAC
(load DAC) signal. When LDAC is low, the input register’s data is loaded into the DAC registers (see Figure 5
for timing diagram). This mode is cascadable by connecting Serial Output (SRO) to the second chip’s SDA
pin. The delay of the SRO pin from SCL does not cause
setup/hold time violations, no matter how many
MAX500s are cascaded. Restrict the voltage at LDAC
and LOAD to +5.5V for a logic high.
2-Wire Interface
The 2-wire interface uses SDA and SCL only. LOAD
must be floating or tied to VDD. Each data frame (8 data
bits and 2 address bits) is synchronized by a timing
relationship between SDA and SCL (see Figure 6 for
the timing diagram). Both SDA and SCL should normally be high when inactive. A falling edge of SDA (while
SCL is high) followed by a falling edge of SCL (while
SDA is low) is the start condition. This always loads a 0
into the first bit of the shift register. The shift register is
extended to 11 bits so this “data” will not affect the
input register information. The timing now follows the 3wire interface, except the SDA line is not allowed to
change when SCL is high (this prevents the MAX500
from retriggering its start condition). After the last data
bit is entered, the SDA line should go low (while the
SCL line is low), then the SCL line should rise followed
by the SDA line rising. This is defined as the stop condition, or end of frame.
Cascading the 2-wire interface can be done, but the
user must be careful of both timing and formatting.
Timing must take into account the intrinsic delay of the
SRO pin from the internally generated start/stop conditions. The tS2 value should be increased by n times tD1
(where n = number of cascaded MAX500s). The tLDS
value should also be increased by n times tD1. No other
timing parameters need to be modified. A more serious
concern is one of formatting. Generally, since each
frame has a start/stop condition, each chip that has
data cascaded through it will accept that data as if it
were its own data. Therefore, to circumvent this limitation, the user should not generate a stop bit until all
DACs have been loaded. For example, if there are
three MAX500s cascaded in the 2-wire mode, the data
transfer should begin with a start condition, followed by
10 data bits, a zero bit, 10 data bits, a zero bit, 10 data
bits, and then a stop condition. This will prevent each
MAX500 from decoding the middle data for itself.
8
The data is entered into the shift register in the following order:
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
(First) (MSB)
(Last)
where address bits A1 and A0 select which DAC register receives data from the internal shift register. Table 1
lists the channel addresses. D7 (MSB) through D0 is
the data byte.
Since LDAC is asynchronous with respect to SCL, SDA,
and LOAD, care must be taken to assure that incorrect
data is not latched through to the DAC registers. If the
3-wire serial interface is used, LDAC can be either tied
low permanently or tied to LOAD as long as tLDS is
always maintained. However, if the 2-wire interface is
used, LDAC should not fall before the stop condition is
internally detected. (This is the reason for the t LDS
delay of LDAC after the last rising edge of SDA.)
Table 1. DAC Addressing
A1
A0
SELECTED INPUT REGISTER
L
L
DAC A Input Register
L
H
DAC B Input Register
H
L
DAC C Input Register
H
H
DAC D Input Register
Table 2. Logic Input Truth Table
SCL
SDA
LOAD LDAC
F
Data
VDD
H
H
Data
VDD
H
L
X
VDD
H
F
Data
M
H
H
X
M
H
L
X
M
H
H
X
L
H
H
X
L
L
Notes:
H = Logic High
L = Logic Low
M = TTL Logic High
X = Don’t Care
FUNCTION
Latching data into
shift register (2W)
Data should not be
changing (2W)
Data is allowed to
change (2W)
Latching data into
shift register (3W)
Data is allowed to
change (3W)
Data is allowed to
change (3W)
Loads input register
from shift register (3W)
DAC register reflects
data held in their respective
input registers
2W = 2-Wire
3W = 3-Wire
F = Falling Edge
_______________________________________________________________________________________
CMOS, Quad, Serial-Interface
8-Bit DAC
ground buses within one diode drop of each other. To
avoid parasitic device turn-on, AGND must not be
allowed to be more negative than DGND. DGND should
be used as supply ground for bypassing purposes.
REFERENCE INPUTS
4
12
13
+15V
14
VDD
VREFA/B VREFC VREFD
__________Applications Information
2
DAC A
Power-Supply and Reference
Operating Ranges
The MAX500 is fully specified to operate with V DD
between +12V ±5% and +15V ±10% (+11.4V to
+16.5V), and with VSS from 0V to -5.5V. 8-bit performance is also guaranteed for single-supply operation
(VSS = 0V), however, zero-code error is reduced when
VSS is -5V (see Output Buffer Amplifiers section).
For an adequate DAC and buffer operating range, the
VREF voltage must always be at least 4V below VDD.
The MAX500 is specified to operate with a reference
input range of +2V to VDD - 4V.
1
VOUTB
DAC B
DIGITAL
INPUTS
NOT
SHOWN
16
DAC C
VOUTC
15
DAC D
Ground Management
Digital or AC transient signals between AGND and
DGND will create noise at the analog outputs. It is recommended that AGND and DGND be tied together at
the DAC and that this point be tied to the highest quality ground available. If separate ground buses are used,
then two clamp diodes (1N914 or equivalent) should be
connected between AGND and DGND to keep the two
VOUTA
VOUTD
AGND
VSS
3
5
DGND
6
-5V (OR GND)
MAX500
Figure 8. MAX500 Unipolar Output Circuit
SYSTEM GND
VOUTB
VOUTC
VOUTA
VOUTD
VSS
VREF
R1
R2
+15V
VDD
VREFA/B
VREFC
AGND
VREFD
DAC
OUTPUT
FROM MAX500
VOUT
DGND
-15V
R1 = R2 = 10kΩ ±0.1%
COMPONENT SIDE (TOP VIEW)
Figure 7. Suggested MAX500 PC Board Layout for
Minimizing Crosstalk
NOTE: VREF IS THE REFERENCE INPUT FOR THE MAX500
Figure 9. Bipolar Output Circuit
_______________________________________________________________________________________
9
MAX500
The SRO output swings from VDD to DGND. Cascading
to other MAX500s poses no problem. If SRO is used to
drive a TTL-compatible input, use a clamp diode
between TTL +5V and VDD and the current-limiting
resistor to prevent potential latchup problems with
the 5V supply.
Table 2 shows the truth table for SDA, SCL, LOAD, and
LDAC operation. Figures 5 and 6 show the timing diagrams for the MAX500.
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
Table 3. Unipolar Code Table
DAC CONTENTS
Table 4. Bipolar Code Table
DAC CONTENTS
ANALOG
OUTPUT
MSB
LSB
1111
1111
255
+VREF ––––
256
1000
0001
129
+VREF ––––
256
1000
0000
1111
1111
––––
+VREF 127
128
(
)
1000
0001
1
+VREF ––––
128
1000
0000
0V
0111
1111
1
-VREF ––––
128
0000
0001
127
-VREF ––––
128
0000
0000
REF
128 = +V––––
+VREF ––––
256
2
(
)
0000
0001
1
+VREF ––––
256
0000
0000
0V
(
(
)
)
1
( –––
)
(
Unipolar Output
In unipolar operation, the output voltages and the reference input(s) are the same polarity. The unipolar circuit
configuration is shown in Figure 8 for the MAX500. The
device can be operated from a single supply with a
slight increase in zero error (see Output Buffer
Amplifiers section). To avoid parasitic device turn-on,
the voltage at V REF must always be positive with
respect to AGND. The unipolar code table is given in
Table 3.
Bipolar Output
Each DAC output may be configured for bipolar operation using the circuit in Figure 9. One op amp and two
resistors are required per channel. With R1 = R2:
VOUT = VREF (2DA - 1)
where DA is a fractional representation of the digital
word in Register A.
Table 4 shows the digital code versus output voltage
for the circuit in Figure 9.
(
)
(
)
(
)
(
)
)
128 = -V
-VREF ––––
REF
128
Note: 1LSB = (VREF) (2-8) = +VREF
256
Careful PC board ground layout techniques should be
used to minimize crosstalk between DAC outputs, the
reference input(s), and the digital inputs. This is particularly important if the reference is driven from an AC
source. Figure 7 shows suggested PC board layouts for
minimizing crosstalk.
10
ANALOG
OUTPUT
)
1111
Note: 1LSB = (VREF) (2-8) = +VREF
LSB
(
127
+VREF ––––
256
0111
MSB
1 )
( –––
256
+15V
4
VREFA/B
14
VDD
2
+
VIN
-
DAC A
5
VOUTA
AGND
MAX500
+
VBIAS
-
VSS
DGND
3
6
-5V (OR GND)
DIGITAL INPUTS NOT SHOWN
Figure 10. AGND Bias Circuit
Offsetting AGND
AGND can be biased above DGND to provide an arbitrary nonzero output voltage for a “zero” input code. This
is shown in Figure 10. The output voltage at VOUTA is:
VOUTA = VBIAS + DAVIN
where DA is a fractional representation of the digital
input word. Since AGND is common to all four DACs,
all outputs will be offset by VBIAS in the same manner.
Since AGND current is a function of the four DAC
codes, it should be driven by a low-impedance source.
VBIAS must be positive.
______________________________________________________________________________________
CMOS, Quad, Serial-Interface
8-Bit DAC
Generating VSS
The performance of the MAX500 is specified for both
dual and single-supply (VSS = 0V) operation. When the
improved performance of dual-supply operation is
desired, but only a single supply is available, a -5V VSS
supply can be generated using an ICL7660 in one of
the circuits of Figure 12.
MAX500
Using an AC Reference
+15V
In applications where VREF has AC signal components,
the MAX500 has multiplying capability within the limits
of the VREF input range specifications. Figure 11 shows
a technique for applying a sine-wave signal to the reference input, where the AC signal is biased up before
being applied to VREF. Output distortion is typically less
than 0.1% with input frequencies up to 50kHz, and the
typical -3dB frequency is 700kHz. Note that VREF must
never be more negative than AGND.
15k
AC
REFERENCE
INPUT
4
14
VDD
VREFA/B
10k
+4V
VOUTB 1 VOUTB
-4V
DAC B
AGND
5
VSS
3
MAX500
DGND
6
-5V (OR GND)
DIGITAL INPUTS NOT SHOWN
Figure 11. AC Reference Input Circuit
Digital Interface Applications
Figures 13 through 16 show examples of interfacing the
MAX500 to most popular microprocessors.
12V to 15V
10µF
10µF
2N2222
10k
2
8
6V
ZENER
10k
CAP-
V+
10µF
3
2
4
CAP+
ICL7660 VOUT 5
GND
-5V
VSS OUT
+5V
LOGIC
SUPPLY
4
CAP+
8
3
CAP-
V+
-5V
ICL7660 VOUT 5
VSS OUT
GND
10µF
10µF
Figure 12. Generating -5V for VSS
A15
80C51
A0
MAX500
P1.0
P1.1
SCL
SDA
P1.2
P1.3 . . . . . . .
LOAD*
LDAC
I/O REQ
EN ADDRESS
CODE
WR
INT
VOUTD
VREFA/B
VREFC
VREFD
Figure 13. 80C51 Interface
A1
Z80
SRO
VOUTA
VOUTB
VOUTC
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TO VDD FOR 2-WIRE MODE
ADDRESS BUS
D7
D0
A0
B/A Z8420
C/D
B0
CE
B1
RD
B2
INT
B3 . .
D7
D0
SCL MAX500
SDA
LDAC
LOAD*
DATA BUS
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TO VDD FOR 2-WIRE MODE
Figure 14. Z-80 with Z8420 PIO Interface
______________________________________________________________________________________
11
A15
A8
A15
A0
ADDRESS BUS
8085/
8088
A0 82C55
PA0
A1
PA1
CS
PA2
WR
ADDRESS
DECODE
WR
EN LATCH
ALE
AD7
AD0
D7
D0
PA3 . .
SCL
MAX500
SDA
LDAC
LOAD*
6809/
6502
R/W
Θ OR E
∆7
D0
ADDRESS AND DATA BUS
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TO VDD FOR 2-WIRE MODE
ADDRESS BUS
6821
6521 PA0
C32 PA1
R/W PA2
E
DB7 PA3 . .
DB0
ADDRESS
DECODE
SCL
MAX500
SDA
LDAC
LOAD*
DATA BUS
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TO VDD FOR 2-WIRE MODE
Figure 15. 8085/8088 with Programmable Peripheral Interface
Figure 16. 6809/6502 Interface
____Pin Configurations (continued)
___________________Chip Topography
V OUT B
V ss V OUT A
19 V OUT D
20 V OUT C
1 N.C.
2 V OUT B
3 V OUT A
TOP VIEW
V SS 4
18 V DD
V OUT D
V DD
V OUT C
V REF B
V REF A
V REF C
V REF D
AGND
V REF A/B 5
17 V REF C
AGND 6
SCL 13
14 N.C.
LOAD 12
N.C. 8
SDA 11
15 SRO
LDAC 10
N.C. 7
9
0.159"
(4.039mm)
16 V REF D
MAX500
DGND
MAX500
CMOS, Quad, Serial-Interface,
8-Bit DAC
SRO
DGND
SDA
SCL
LOAD
LDAC
0.150"
(3.810mm)
LCC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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