MAX509BCAP

19-0155; Rev 3; 12/10 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs The MAX509/MAX510 are quad, serial-input, 8-bit voltage-output digital-to-analog converters (DACs). They operate with a single +5V supply or dual ±5V supplies. Internal, precision buffers swing rail-to-rail. The reference input range includes both supply rails. The MAX509 has four separate reference inputs, allowing each DAC's full-scale range to be set independently. 20-pin DIP, SSOP, and SO packages are available. The MAX510 is identical to the MAX509 except it has two reference inputs, each shared by two DACs. The MAX510 is housed in space-saving 16-pin DIP and SO packages. The serial interface is double-buffered: A 12-bit input shift register is followed by four 8-bit buffer registers and four 8-bit DAC registers. A 12-bit serial word is used to load data into each register. Both input and DAC registers can be updated independently or simultaneously with single software commands. Two additional asynchronous control pins provide simultaneous updating (LDAC) or clearing (CLR) of input and DAC registers. The interface is compatible with MICROWIRE TM and SPI/QSPI TM . All digital inputs and outputs are TTL/CMOS compatible. A buffered data output provides for readback or daisy-chaining of serial devices. _______________Functional Diagrams DOUT CLR LDAC AGND DGND VSS VDD REFB DECODE CONTROL Single +5V or Dual ±5V Supply Operation Output Buffer Amplifiers Swing Rail-to-Rail Reference Input Range Includes Both Supply Rails Calibrated Offset, Gain, and Linearity (1LSB TUE) 10MHz Serial Interface, Compatible with SPI, QSPI (CPOL = CPHA = 0) and MICROWIRE ♦ Double-Buffered Registers for Synchronous Updating ♦ Serial Data Output for Daisy-Chaining ♦ Power-On Reset Clears Serial Interface and Sets All Registers to Zero ______________Ordering Information PART MAX509ACPP+ MAX509BCPP+ MAX509ACWP+ MAX509BCWP+ MAX509ACAP+ TEMP RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C DAC REG A DAC A OUTB DAC REG B DAC B OUTC INPUT REG C SR CONTROL INPUT REG D ±1 ±1.5 ±1 ±1.5 ±1 _________________Pin Configurations TOP VIEW OUTA INPUT REG B 20 PDIP 20 PDIP 20 Wide SO 20 Wide SO 20 SSOP TUE (LSB) Ordering Information continued on last page. **Contact factory for availability and processing to MIL-STD-883. +Denotes a lead(Pb)-free/RoHS-compliant package. OUTB 1 20 OUTC OUTA 2 19 OUTD VSS 3 12-BIT SHIFT REGISTER PIN-PACKAGE REFA MAX509 INPUT REG A ____________________________Features ♦ ♦ ♦ ♦ ♦ DAC REG C DAC C OUTD DAC REG D DAC D REFB 4 18 VDD MAX509 17 REFC REFA 5 16 REFD AGND 6 15 CS N.C. 7 14 N.C. DGND 8 13 SCLK LDAC 9 12 DIN DOUT 10 11 CLR DIP/SO/SSOP CS DIN SCLK REFC REFD Functional Diagrams continued at end of data sheet. Pin Configurations continued at end of data sheet. MICROWIRE is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX509/MAX510 _______________General Description MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs ABSOLUTE MAXIMUM RATINGS 20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW 20-Pin Wide SO (derate 10.00mW/°C above +70°C) .......800mW 20-Pin SSOP (derate 10.00mW/°C above +70°C) ............800mW 20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW Operating Temperature Ranges: MAX5_ _ _C_ _ .....................................................0°C to +70°C MAX5_ _ _E_ _ ..................................................-40°C to +85°C MAX5_ _ _MJ_ ................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) Lead (Pb)-free packages..............................................+260°C Packages containing lead (Pb).....................................+260°C VDD to DGND ..............................................................-0.3V, +6V VDD to AGND...............................................................-0.3V, +6V VSS to DGND ...............................................................-6V, +0.3V VSS to AGND ...............................................................-6V, +0.3V VDD to VSS .................................................................-0.3V, +12V Digital Input Voltage to DGND ......................-0.3V, (VDD + 0.3V) REF_....................................................(VSS - 0.3V), (VDD + 0.3V) OUT_..............................................................................VDD, VSS Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) ....842mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C) .........762mW 16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW Note: The outputs may be shorted to VDD, VSS, or AGND if the package power dissipation is not exceeded. Typical short-circuit current to AGND is 50mA. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution 8 Total Unadjusted Error TUE Differential Nonlinearity DNL VREF = +4V, VSS = 0V or -5V ±10% ±1 MAX5_ _B ±1.5 VREF = -4V, VSS = -5V ±10% MAX5_ _A ±1 MAX5_ _B ±1.5 Guaranteed monotonic Code = 00 hex, VSS = 0V Zero-Code Error ZCE Code = 00 hex, VSS = -5V ±10% ±1 MAX5_ _C 14 MAX5_ _E 16 MAX5_ _M 20 MAX5_ _C ±14 MAX5_ _E ±16 MAX5_ _M ±20 Zero-Code-Error Supply Rejection Code = 00 hex, VDD = 5V ±10%, VSS = 0V or -5V ±10% Zero-Code Temperature Coefficient Code = 00 hex Full-Scale Error Code = FF hex Full-Scale-Error Supply Rejection Full-Scale-Error Temperature Coefficient 2 Bits MAX5_ _A Code = FF hex, VDD = +5V ±10%, VSS = 0V or -5V ±10% Code = FF hex 1 2 ±10 ±14 1 MAX5_ _E 1 8 MAX5_ _M 1 12 _______________________________________________________________________________________ LSB mV mV µV/°C MAX5_ _C ±10 LSB mV 4 mV µV/°C Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510 ELECTRICAL CHARACTERISTICS (continued) (VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD V REFERENCE INPUTS Input Voltage Range VSS MAX509 16 24 MAX510 8 12 Input Resistance (Note 1) Code = 55 hex Input Capacitance (Note 2) Code = 00 hex Channel-to-Channel Isolation (Note 3) -60 dB AC Feedthrough (Note 4) -70 dB MAX509 15 MAX510 30 kΩ pF DAC OUTPUTS Full-Scale Output Voltage VSS Resistive Load VREF = 4V, load regulation ≤ 1/4LSB 2 VREF = -4V, VSS = -5V ±10%, load regulation ≤ 1/4LSB 2 VREF = VDD MAX5_ _C/E, load regulation ≤ 1LSB 10 VREF = VDD MAX5_ _M, load regulation ≤ 2LSB 10 VDD V kΩ DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL 2.4 V 0.8 V Input Current IIN VIN = 0V or VDD 1.0 µA Input Capacitance CIN (Note 5) 10 pF Output High Voltage VOH ISOURCE = 0.2mA Output Low Voltage VOL ISINK = 1.6mA DIGITAL OUTPUTS VDD - 0.5 V 0.4 V DYNAMIC PERFORMANCE MAX5_ _C 1.0 MAX5_ _E 0.7 MAX5_ _M 0.5 Voltage-Output Slew Rate Positive and negative Output Settling Time (Note 6) To 1/2LSB, 10kΩ II 100pF load 6 µs Digital Feedthrough Code = 00 hex, all digital inputs from 0V to VDD 5 nV-s Digital-to-Analog Glitch Impulse Code 128➝127 12 nV-s Signal-to-Noise + Distortion Ratio VREF = 4Vp-p at 1kHz, VDD = 5V, code = FF hex 87 VREF = 4Vp-p at 20kHz, VSS = -5V ±10% 74 VREF = 0.5Vp-p, 3dB bandwidth 1 60 Multiplying Bandwidth Wideband Amplifier Noise SINAD V/µs dB MHz µVRMS _______________________________________________________________________________________ 3 MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS POWER SUPPLIES Positive Supply Voltage Negative Supply Voltage VDD VSS For specified performance For specified performance Positive Supply Current IDD Outputs unloaded, all digital inputs = 0V or VDD Negative Supply Current ISS VSS = -5V ±10%, outputs unloaded, all digital inputs = 0V or VDD MIN TYP MAX UNITS V V MAX5_ _C/E 5 5.5 0 10 MAX5_ _M 5 12 MAX5_ _C/E 5 10 MAX5_ _M 5 12 4.5 -5.5 mA mA Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex. Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex. Note 3: VREF = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the code of all other DACs to 00 hex. Note 4: VREF = 4Vp-p, 10kHz. DAC code = 00 hex. Note 5: Guaranteed by design. Note 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex. TIMING CHARACTERISTICS (VDD = +5V ±10%, VSS = 0V to -5V, VREF = 4V, AGND = DGND = 0V, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL LDAC Pulse Width Low tLDW CS Rise to LDAC Fall Setup Time tCLL CLR Pulse Width Low tCLW MIN TYP MAX5_ _C/E MAX5_ _M CONDITIONS 40 50 20 25 (Notes 7, 8) MAX5_ _C/E MAX5_ _M 0 40 50 MAX5_ _C/E MAX5_ _M 40 50 0 40 0 40 50 0 MAX UNITS ns ns 20 25 ns SERIAL INTERFACE TIMING CS Fall to SCLK Setup Time tCSS SCLK Fall to CS Rise Hold Time SCLK Rise to CS Rise Hold Time SCLK Fall to CS Fall Hold Time tCSH2 tCSH1 tCSH0 DIN to SCLK Rise Setup Time tDS DIN to SCLK Rise Hold Time tDH SCLK Clock Frequency fCLK SCLK Pulse Width High tCH SCLK Pulse Width Low tCL SCLK to DOUT Valid tDO (Note 9) (Note 7) MAX5_ _C/E MAX5_ _M MAX5_ _C/E MAX5_ _M MAX5_ _C/E MAX5_ _M MAX5_ _C/E MAX5_ _M MAX5_ _C/E MAX5_ _M ns ns ns ns ns ns 20 20 40 50 40 50 10 10 Note 7: Guaranteed by design. Note 8: If LDAC is activated prior to CS's rising edge, it must stay low for tLDW or longer after CS goes high. Note 9: Minimum delay from 12th clock cycle to CS rise. 4 _______________________________________________________________________________________ 12.5 10 MHz ns ns 100 100 ns Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510 __________________________________________Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE VDD = VREF = +5V VSS = GND DIGITAL INPUT = FF HEX -20 6 SUPPLY CURRENT (mA) 6 -15 -10 4 VDD = VREF = +5V VSS = GND = 0V ALL DIGITAL INPUTS = 00 HEX 2 0.8 1.0 3.8 4.0 4.2 SUPPLY CURRENT vs. REFERENCE VOLTAGE -55 -60 0.1% -65 -70 FREQ = 20kHz -75 VDD = +5V ALL LOGIC INPUTS = +5V -20 1% 0.01% -3 -2 -1 0 1 2 3 4 5 0 0.01% VREF = 4Vp-p 2 4 8 6 10 10 100 1k 10k REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE VDD = +5V VSS = AGND VREF = 2.5VDC + 0.5Vp-p SINE WAVE 10k 100k FREQUENCY (Hz) 1M -10 -20 -30 VDD = +5V VSS = AGND VREF = 2.5VDC + 0.05Vp-p SINE WAVE -40 10M 0 RELATIVE OUTPUT (dB) RELATIVE OUTPUT (dB) 0 1k 10k 100k FREQUENCY (Hz) 1M -10 -20 -30 VDD = +5V VSS = -5V VREF = 2.5VDC + 4Vp-p SINE WAVE -40 10M 100k MAX509-FG08 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE MAX509-FG07 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE -20 1k VREF = 1Vp-p REFERENCE FREQUENCY (Hz) -10 -40 0.1% REFERENCE AMPLITUDE (Vp-p) 0 -30 VREF = 8Vp-p -60 VREF VOLTAGE (V) MAX509-FG06 -4 1% -90 -90 -5 -50 -80 -85 0 -40 -70 FREQ = 1kHz -80 10% VDD = +5V VSS = -5V INPUT CODE = FF HEX FREQ = SWEPT -30 THD + NOISE (dB) 3 THD + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY THD + NOISE (%) MAX509-FG03 VSS = -5V THD + NOISE (dB) IDD (mA) -45 20 40 60 80 100 120 140 -60 -40 -20 0 TEMPERATURE (°C) VDD = +5V VSS = -5V INPUT CODE = FF HEX -50 2 RELATIVE OUTPUT (dB) 5.0 4.8 -40 VSS = 0V 1 4.6 THD + NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE 6 4 4.4 VOUT (V) VOUT - VSS (V) 5 VDD = +5.5V VSS = -5.5V VREF = -4.75 ALL DIGITAL INPUTS = +5V 2 0 3.6 1.2 MAX509-FG04 0.6 ISS 3 1 0 0.4 0.2 IDD 4 -5 0 0 5 THD + NOISE (%) IOUT (mA) IOUT (mA) 8 MAX509-FG05 10 7 MAX509-FG10 -25 MAX509-FG01 12 SUPPLY CURRENT vs. TEMPERATURE MAX509-FG02 OUTPUT SINK CURRENT vs. (VOUT - VSS) 1k 10k 100k 1M 10M FREQUENCY (Hz) _______________________________________________________________________________________ 5 ____________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) ZERO-CODE ERROR vs. NEGATIVE SUPPLY VOLTAGE VDD = +5V VREF = +4V 4.8 REFERENCE FEEDTHROUGH AT 40kHz WORST-CASE 1LSB DIGITAL STEP CHANGE MAX509-FG09 5.0 ZERO-CODE ERROR (mV) MAX509/MAX510 Quad, Serial 8-DACs with Rail-to-Rail Outputs 2V 20mV A 4.6 A 4.4 4.2 4.0 B B 3.8 3.6 200nS 3.4 0 -1 -3 -2 -4 -5 A = REFA, 10Vp-p B = OUTA, 100μV/div, UNLOADED TIMEBASE = 10μs/div VDD = +5V, VSS = -5V CODE = ALL 0s A = CS, 2V/div B = OUTA, 20mV ˜ TIMEBASE = 200ns/div -6 VSS (V) REFERENCE FEEDTHROUGH AT 10kHz REFERENCE FEEDTHROUGH AT 4kHz 5V 50μV A B REFERENCE FEEDTHROUGH AT 400Hz 10 A A B B 100μS A = REFA, 10Vp-p B = OUTA, 50μV/div, UNLOADED TIMEBASE = 50μs/div 6 A = REFA, 10Vp-p B = OUTA, 50μV/div, UNLOADED TIMEBASE = 100μs/div A = REFA, 10Vp-p B = OUTA, 50μV/div, UNLOADED TIMEBASE = 1ms/div _______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs POSITIVE SETTLING TIME (VSS = AGND OR -5V) CLOCK FEEDTHROUGH 5V 100mV A A B B 1μS A = SCLK, 333kHz B = OUT_, 10mV/div TIMEBASE = 2μs/div A = DIGITAL INPUT, 5V/div B = OUT_ , 2V/div TIMEBASE = 1μs/div VDD = +5V REF_ = +4V ALL BITS OFF TO ALL BITS ON RL = 10kΩ, CL = 100pF NEGATIVE SETTLING TIME (VSS = AGND) 5V NEGATIVE SETTLING TIME (VSS = -5V) 100mV 5V 100mV A A B B 1μS A = DIGITAL INPUT, 5V/div B = OUT_ , 2V/div TIMEBASE = 1μs/div VDD = +5V REF_ = +4V ALL BITS ON TO ALL BITS OFF RL = 10kΩ, CL = 100pF 1μS A = DIGITAL INPUT, 5V/div B = OUT_ , 2V/div TIMEBASE = 1μs/div VDD = +5V REF_ = +4V ALL BITS ON TO ALL BITS OFF RL = 10kΩ, CL = 100pF _______________________________________________________________________________________ 7 MAX509/MAX510 ____________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs ______________________________________________________________Pin Description PIN MAX509 MAX510 8 NAME FUNCTION 1 1 OUTB DAC B Voltage Output 2 2 OUTA DAC A Voltage Output 3 3 VSS 4 – REFB – 4 REFAB 5 – REFA Reference Voltage Input for DAC A 6 5 AGND Analog Ground 7, 14 – N.C. 8 6 DGND Digital Ground 9 7 LDAC Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents of each input latch to its respective DAC latch. 10 8 DOUT Serial Data Output. Can sink and source current. Data at DOUT is adjustable to be clocked out on rising or falling edge of SCLK. 11 9 CLR Clear DAC input (active low). Driving CLR low causes an asynchronous clear of input and DAC registers and sets all DAC outputs to zero. 12 10 DIN Serial Data Input. TTL/CMOS-compatible input. Data is clocked into DIN on the rising edge of SCLK. CS must be low for data to be clocked in. 13 11 SCLK 15 12 CS 16 – REFD – 13 REFCD 17 – REFC Reference Voltage Input for DAC C 18 14 VDD Positive Power Supply, +5V ±10% 19 15 OUTD DAC D Output Voltage 20 16 OUTC DAC C Output Voltage Negative Power Supply, 0V to -5V ±10%. Connect to AGND for single-supply operation. Reference Voltage Input for DAC B Reference Voltage Input for DACs A and B Not Internally Connected Serial Clock Input. Data is clocked in on the rising edge and clocked out on either the rising (default) or the falling edge. Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are executed when CS rises. Reference Voltage Input for DAC D Reference Voltage Input for DACs C and D _______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs between updates. DOUT does not go into a highimpedance state if the clock or CS is high. Serial data is clocked into the data registers in MSBfirst format, with the address and configuration information preceding the actual DAC data. Data is clocked in on SCLK's rising edge while CS is low. Data at DOUT is clocked out 12 clock cycles later, either at SCLK's rising edge (default or mode 1) or falling edge (mode 0). Serial Interface At power-on, the serial interface and all DACs are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK's rising edge. The MAX509/MAX510 communicate with microprocessors through a synchronous, full-duplex, 3-wire interface (Figure 1). Data is sent MSB first and can be transmitted in one 4-bit and one 8-bit (byte) packet or in one 12-bit word. If a 16-bit control word is used, the first four bits are ignored. A 4-wire interface adds a line for LDAC and allows asynchronous updating. The serial clock (SCLK) synchronizes the data transfer. Data is transmitted and received simultaneously. Figure 2 shows a detailed serial interface timing. Please note that the clock should be low if it is stopped Chip select (CS) must be low to enable the DAC. If CS is high, the interface is disabled and DOUT remains unchanged. CS must go low at least 40ns before the first rising edge of the clock pulse to properly clock in the first bit. With CS low, data is clocked into the MAX509/MAX510's internal shift register on the rising edge of the external serial clock. SCLK can be driven at rates up to 12.5MHz. INSTRUCTION EXECUTED CS ••• ••• SCLK ••• DIN A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 MSB A1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 LSB MSB DACA DOUT MODE 1 (DEFAULT) D1 D0 A1 LSB DACD ••• A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 DATA FROM PREVIOUS DATA INPUT D7 D6 D5 D4 D3 D2 D1 D0 A1 DATA FROM PREVIOUS DATA INPUT DOUT MODE 0 ••• A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 Figure 1. MAX509/MAX510 3-Wire Interface Timing _______________________________________________________________________________________ 9 MAX509/MAX510 _______________Detailed Description MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs tCLL CS tCSH2 ••• tCSH0 tCSS tCH ••• SCLK tCL tDS tCSH1 tDH ••• DIN tDO ••• DOUT ••• LDAC NOTE: TIMING SPECIFICATION tCLL IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY. tLDW Figure 2. Detailed Serial Interface Timing (Mode 0 Shown) Table 1. Serial-Interface Programming Commands 12-Bit Serial Word 10 LDAC Function A1 A0 C1 C0 D7 . . . . . . . . D0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 1 1 1 1 Load DAC A input register, DAC output unchanged. Load DAC B input register, DAC output unchanged. Load DAC C input register, DAC output unchanged. Load DAC D input register, DAC output unchanged. 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 8-Bit DAC Data 1 1 1 1 Load input and DAC register A. Load input and DAC register B. Load input and DAC register C. Load input and DAC register D. X 0 0 0 8-Bit DAC Data X Update all DACs from shift register. X 1 0 0 XXXXXXXX X No Operation (NOP), shifts data in shift register. 0 X 1 0 XXXXXXXX X “LDAC” Command, all DACs updated from respective input registers. 1 1 1 0 XXXXXXXX X Mode 1, DOUT clocked out on rising edge of SCLK (default). All DACs updated from respective input registers. 1 0 1 0 XXXXXXXX X Mode 0, DOUT clocked out on falling edge of SCLK. All DACs updated from input registers. ______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs This is the first bit shifted in LSB MSB DOUT A1 A0 C1 C0 D7 D6 Control and Address bits ●●● D1 D0 DIN Update All DACs from Shift Registers A1 A0 C1 C0 x 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 8-Bit DAC Data (LDAC = x) All four DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog value within the reference range. This command can be used to substitute CLR if code 00 hex is programmed, which clears all DACs. No Operation (NOP) 8-bit DAC data Figure 3. Serial Input Format A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 x 1 0 0 x x x x x x x x (LDAC = x) Load Input Register, DAC Registers Unchanged (Single Update Operation) A1 A0 Address C1 0 C0 1 D7 D6 D5 D4 D3 D2 D1 D0 8-Bit Data (LDAC = H) When performing a single update operation, A1 and A0 select the respective input register. At the rising edge of CS, the selected input register is loaded with the current shift-register data. All DAC outputs remain unchanged. This preloads individual data in the input register without changing the DAC outputs. Load Input and DAC Registers A1 A0 Address C1 1 C0 1 D7 D6 D5 D4 D3 D2 D1 D0 8-Bit Data (LDAC = H) This command directly loads the selected DAC register at CS's rising edge. A1 and A0 set the DAC address. Current shift-register data is placed in the selected input and DAC registers. For example, to load all four DAC registers simultaneously with individual settings (DAC A = 1V, DAC B = 2V, DAC C = 3V and DAC D = 4V), five commands are required. First, perform four single input register update operations. Next, perform an “LDAC” command as a fifth command. All DACs will be updated from their respective input registers at the rising edge of CS. The NOP command (no operation) allows data to be shifted through the MAX509/MAX510 shift register without affecting the input or DAC registers. This is useful in daisy chaining (also see the Daisy-Chaining Devices section). For this command, the data bits are "Don't Cares." As an example, three MAX509/MAX510s are daisy-chained (A, B and C), and DAC A and DAC C need to be updated. The 36-bit-wide command would consist of one 12-bit word for device C, followed by an NOP instruction for device B and a third 12-bit word with data for device A. At CS's rising edge, only device B is not updated. “LDAC” Command (Software) A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 0 x 1 0 x x x x x x x x (LDAC = x) All DAC registers are updated with the contents of their respective input registers at CS's rising edge. With the exception of using CS to execute, this performs the same function as the asynchronous LDAC. Set DOUT Phase – SCLK Rising (Mode 1, Default) A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 x x x x x x x x (LDAC = x) Mode 1 resets the serial output DOUT to transition at SCLK's rising edge. This is the MAX509/MAX510’s default setting after the supply voltage has been applied. The command also loads all DAC registers with the contents of their respective input registers, and is identical to the “LDAC” command. ______________________________________________________________________________________ 11 MAX509/MAX510 Serial Input Data Format and Control Codes The 12-bit serial input format shown in Figure 3 comprises two DAC address bits (A1, A0), two control bits (C1, C0) and eight bits of data (D0...D7). The 4-bit address/control code configures the DAC as shown in Table 1. MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs Set DOUT Phase – SCLK Falling (Mode 0) A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 x x x x x x x x (LDAC = x) This command resets DOUT to transition at SCLK's falling edge. Once this command is issued, the phase of DOUT is latched and will not change except on power-up or if the specific command is issued that sets the phase to rising edge. The same command also updates all DAC registers with the contents of their respective input registers, identical to the “LDAC” command. LDAC Operation (Hardware) LDAC is typically used in 4-wire interfaces (Figure 7). LDAC allows asynchronous hardware control of the DAC outputs and is level-sensitive. With LDAC low, the DAC registers are transparent and any time an input register is updated, the DAC output immediately follows. Clear DACs with CLR Strobing the CLR pin low causes an asynchronous clear of input and DAC registers and sets all DAC outputs to zero. Similar to the LDAC pin, CLR can be invoked at any time, typically when the device is not selected (CS = H). When the DAC data is all zeros, this function is equivalent to the "Update all DACs from Shift Registers" command. Digital Inputs and Outputs Digital inputs and outputs are compatible with both TTL and 5V CMOS logic. The power-supply current (IDD) depends on the input logic levels. Using CMOS logic to drive CS, SCLK, DIN, CLR and LDAC turns off the internal level translators and minimizes supply currents. Serial Data Output DOUT is the output of the internal shift register. DOUT can be programmed to clock out data on SCLK's falling edge (mode 0) or rising edge (mode 1). In mode 0, output data lags the input data by 12.5 clock cycles, maintaining compatibility with Microwire, SPI, and QSPI. In mode 1, output data lags the input by 12 clock cycles. On power-up, DOUT defaults to mode 1 timing. DOUT never three-states; it always actively drives either high or low and remains unchanged when CS is high. Interfacing to the Microprocessor The MAX509/MAX510 are Microwire, SPI, and QSPI compatible. For SPI and QSPI, clear the CPOL and CPHA configuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA = 1 configuration can also be used if the DOUT output is ignored. 12 SCLK SK MAX509 DIN MAX510 SO DOUT SI CS I/0 MICROWIRE PORT THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES. Figure 4. Connections for MICROWIRE DOUT MISO MAX509 DIN MAX510 MOSI SCLK CS SCK SPI PORT I/0 CPOL = 0, CPHA = 0 THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES. Figure 5. Connections for SPI The MAX509/MAX510 can interface with Intel's 80C5X/80C3X family in mode 0 if the SCLK clock polarity is inverted. More universally, if a serial port is not available, three lines from one of the parallel ports can be used for bit manipulation. Digital feedthrough at the voltage outputs is greatly minimized by operating the serial clock only to update the registers. Also see the Clock Feedthrough photo in the Typical Operating Characteristics section. The clock idle state is low. Daisy-Chaining Devices Any number of MAX509/MAX510s can be daisy-chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain. The NOP instruction (Table 1) allows data to be passed from DIN to DOUT without changing the input or DAC registers of the passing device. A threewire interface updates daisy-chained or individual MAX509/MAX510s simultaneously by bringing CS high. ______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509 SCLK MAX510 SCLK MAX510 DIN DIN DIN CS CS MAX509 DOUT DOUT CS DIN MAX509/MAX510 MAX509 SCLK MAX510 SCLK DOUT CS TO OTHER SERIAL DEVICES MAX509 SCLK SCLK MAX510 DIN DIN CS CS Figure 6. Daisy-chained or individual MAX509/MAX510s are simultaneously updated by bringing CS high. Only three wires are required. DIN SCLK LDAC CS1 TO OTHER SERIAL DEVICES CS2 CS3 CS CS CS LDAC MAX509 LDAC MAX509 MAX510 MAX510 LDAC MAX509 MAX510 SCLK SCLK SCLK DIN DIN DIN Figure 7. Multiple MAX509/MAX510 DACs sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling individual CS. ______________________________________________________________________________________ 13 MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs R 2R R R OUT_ 2R 2R 2R 2R D0 D5 D6 D7 Output Buffer Amplifiers All MAX509/MAX510 voltage outputs are internally buffered by precision unity-gain followers that slew at up to 1V/µs. The outputs can swing from VSS to VDD. With a 0V to +4V (or +4V to 0V) output transition, the amplifier outputs will settle to 1/2LSB in typically 6µs when loaded with 10kΩ in parallel with 100pF. REF_ AGND SHOWN FOR ALL 1 ON DAC Figure 8. DAC Simplified Circuit Diagram If multiple devices share a common DIN line, Figure 7's configuration provides simultaneous update by strobing LDAC low. CS1, CS2, CS3... are driven separately, thus controlling which data are written to devices 1, 2, 3.... Analog Section DAC Operation The MAX509/MAX510 contain four matched voltageoutput DACs. The DACs are inverted R-2R ladder networks that convert 8-bit digital words into equivalent analog output voltages in proportion to the applied reference voltages. Each DAC in the MAX509 has a separate reference input, while the two reference inputs in the MAX510 each share a pair of DACs. The two reference inputs permit different full-scale output voltage ranges for each pair of DACs. A simplified diagram of one of the four DACs is shown in Figure 8. Reference Input The MAX509/MAX510 can be used for multiplying applications. The reference accepts both DC and AC signals. The voltage at each REF input sets the fullscale output voltage for its respective DAC(s). If the reference voltage is positive, both the MAX509 and MAX510 can be operated from a single supply. If dual supplies are used, the reference input can vary from VSS to VDD, but is always referred to AGND. The input impedance at REF is code dependent, with the lowest value (16kΩ for the MAX509 and 8kΩ for the MAX510) occurring when the input code is 55 hex or 0101 0101. The maximum value, practically infinity, occurs when the input code is 00 hex. Since the REF input impedance is code dependent, the DAC's reference sources must have a low output impedance (no more than 32Ω for the MAX509 and 16Ω for the MAX510) to maintain output linearity. The REF input capacitance is also code 14 dependent: 15pF typical for the MAX509 and 30pF typical for the MAX510. The output voltage for any DAC can be represented by a digitally programmable voltage source as: VOUT = (NB x VREF) / 256 where NB is the numerical value of the DAC's binary input code. The buffer amplifiers are stable with any combination of resistive loads ≥ 2kΩ and capacitive loads ≤ 300pF. __________Applications Information Power Supply and Reference Operating Ranges The MAX509/MAX510 are fully specified to operate with VDD = 5V ±10% and VSS = 0V to -5.5V. 8-bit performance is guaranteed for both single- and dual-supply operation. The zero-code output error is less than 14mV when operating from a single +5V supply. The DACs work well with reference voltages from VSS to VDD. The reference voltage is referred to AGND. The preferred power-up sequence is to apply VSS and then VDD, but bringing up both supplies at the same time is also acceptable. In either case, the voltage applied to REF should not exceed VDD during powerup or at any other time. If proper power sequencing is not possible, connect an external Schottky diode between VSS and AGND to ensure compliance with the Absolute Maximum Ratings. Do not apply signals to the digital inputs before the device is fully powered up. Power-Supply Bypassing and Ground Management In single-supply operation (AGND = DGND = VSS = 0V), AGND, DGND and V SS should be connected together in a "star" ground at the chip. This ground should then return to the highest quality ground available. Bypass VDD with a 0.1µF capacitor, located as close to VDD and DGND as possible. In dual-supply operation, bypass VSS to AGND with 0.1µF. Careful PC board layout minimizes crosstalk among DAC outputs, reference inputs, and digital inputs. Figures 9 and 10 show suggested circuit board layouts to minimize crosstalk. ______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510 SYSTEM GND SYSTEM GND OUTC OUTB OUTC OUTB OUTD OUTA OUTD OUTA VDD VSS REFC REFB REFD REFA VSS VDD REFCD REFAB AGND AGND Figure 9. Suggested MAX509 PC Board Layout for Minimizing Crosstalk (Bottom View) Figure 10. Suggested MAX510 PC Board Layout for Minimizing Crosstalk (Bottom View) Unipolar-Output, 2-Quadrant Multiplication Bipolar-Output, 2-Quadrant Multiplication In unipolar operation, the output voltages and the reference input(s) are the same polarity. Figures 11 and 12 show the MAX509/MAX510 unipolar configurations. Both devices can be operated from a single supply if the reference inputs are positive. If dual supplies are used, the reference input can vary from VSS to VDD. Table 2 shows the unipolar code. Bipolar-output, 2-quadrant multiplication is achieved by offsetting AGND positively or negatively. Table 3 shows the bipolar code. AGND can be biased above DGND to provide an arbitrary nonzero output voltage for a 0 input code, as shown in Figure 13. The output voltage at OUTA is: Table 2. Unipolar Code Table Table 3. Bipolar Code Table DAC CONTENTS VOUTA = VBIAS + (NB/256)(VIN), DAC CONTENTS ANALOG OUTPUT MSB LSB 1111 1111 255 +VREF –––– 256 1000 0001 1000 MSB LSB ANALOG OUTPUT ( ) ( ) ( ) 1111 1111 –––– +VREF 127 128 129 +VREF –––– 256 ( ) 1000 0001 1 +VREF –––– 128 128 = +V–REF ––– +VREF –––– 256 2 1000 0000 0V 0000 0111 1111 1 -VREF –––– 128 1111 127 +VREF –––– 256 0000 0001 127 -VREF –––– 128 0000 0001 1 +VREF –––– 256 0000 0000 0000 0000 0V 0111 ( ) ( ( ) ) ( ( ) ( ) ) 128 = -V -VREF –––– REF 128 1 ) Note: 1LSB = (VREF) (2-8) = +VREF (–––– 256 ______________________________________________________________________________________ 15 MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs REFERENCE INPUTS (VSS TO VDD) 5 4 17 16 REFA REFB REFC REFD +5V 18 VDD +5V 18 VDD 5 REFA 2 DAC A OUTA 2 DAC A VIN 1 6 AGND OUTB DAC B OUTA MAX509 SERIAL INTERFACE NOT SHOWN VBIAS VSS 3 20 DAC C DGND 8 -5V (OR GND) OUTC +5V 19 DAC D OUTD VSS 3 MAX509 DGND 8 AGND 6 2 OUTA 5 AGND MAX510 Figure 11. MAX509 Unipolar Output Circuit REFERENCE INPUTS (VSS TO VDD) 4 REFAB VBIAS OUTA 1 OUTB DAC B SERIAL INTERFACE NOT SHOWN 16 DAC C OUTC 15 DAC D OUTD 13 DGND 6 SERIAL INTERFACE NOT SHOWN 2 REFCD VSS 3 -5V (OR GND) +5V 14 VDD DAC A AGND 5 -5V (OR GND) MAX510 Figure 12. MAX510 Unipolar Output Circuit 16 DAC A VIN -5V (OR GND) VSS 3 14 VDD 4 REFAB DGND 6 Figure 13. MAX509/MAX510 AGND Bias Circuits (Positive Offset) where NB represents the digital input word. Since AGND is common to all four DACs, all outputs will be offset by VBIAS in the same manner. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND. Figures 14 and 15 illustrate the generation of negative offsets with bipolar outputs. In these circuits, AGND is biased negatively (up to -2.5V with respect to DGND) to provide an arbitrary negative output voltage for a 0 input code. The output voltage at OUTA is: OUTA = -(R2/R1)(2.5V) + (NB/256)(2.5V)(R2/R1+1) where NB represents the digital input word. Since AGND is common to all four DACs, all outputs will be offset by V BIAS in the same manner. Table 3, with VREF = 2.5V, shows the digital code vs. output voltage for Figure 14 and 15's circuits with R1 = R2. The ICL7612 op amp is chosen because its common-mode range extends to both supply rails. ______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs 5 +5V 4 17 16 0.1μF 18 VDD SERIAL INTERFACE NOT SHOWN MAX509 0.1μF 2 DAC A R1 330k 0.1% MAX873 R2 330k 0.1% 1 DAC B +2.5V MAX509/MAX510 +5V REFERENCE INPUTS OUTA OUTB +5V 0.1μF 2 20 DAC C 7 OUTC 6 3 ICL7611A 8 19 DAC D 1 OUTD 0.1μF VSS -5V 3 AGND DGND 6 8 0.1μF -5V Figure 14. MAX509 AGND Bias Circuit (Negative Offset) 4-Quadrant Multiplication Each DAC output may be configured for 4-quadrant multiplication using Figure 16 and 17's circuit. One op amp and two resistors are required per channel. With R1 = R2: VOUT = VREF [2(NB/256)-1] where NB represents the digital word in DAC register A. The recommended value for resistors R1 and R2 is 330kΩ (±0.1%). Table 3 shows the digital code vs. output voltage for Figure 16 and 17's circuit. ______________________________________________________________________________________ 17 MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs +5V REFERENCE INPUTS 4 +5V 13 14 0.1μF VDD SERIAL INTERFACE NOT SHOWN 0.1μF 2 R2 330k 0.1% OUTA 1 OUTB DAC B +2.5V 4 2 DAC A R1 330k 0.1% 6 MAX873 MAX510 +5V 0.1μF 7 2 16 DAC C OUTC 6 3 ICL7611A 8 15 DAC D 1 OUTD 0.1μF VSS 3 -5V AGND DGND 5 6 0.1μF -5V Figure 15. MAX510 AGND Bias Circuit (Negative Offset) REFERENCE INPUTS (VSS TO VDD) 5 4 17 +5V 0.1μF +5V 18 VDD 16 MAX509 ICL7612A* 2 DAC A R2 R1 0.1μF OUTA +5V 1 SERIAL INTERFACE NOT SHOWN VOUT DAC B 0.1μF -5V OUTB 0.1μF 20 DAC C R1 R2 OUTC 19 DAC D ICL7612A* VOUT OUTD VSS 3 AGND 6 DGND 8 0.1μF -5V 0.1μF *CONNECT ICL7612A PIN 8 TO AGND AGND OR -5V Figure 16. MAX509 Bipolar Output Circuit 18 ______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs MAX509/MAX510 REFERENCE INPUTS +5V 4 +5V 14 VDD 13 0.1μF 0.1μF R1 MAX510 R2 ICL7612A* 2 DAC A VOUT OUTA 0.1μF -5V 1 SERIAL INTERFACE NOT SHOWN DAC B OUTB +5V 0.1μF 16 DAC C R1 OUTC R2 ICL7612A* 15 DAC D VOUT OUTD VSS 3 AGND 5 0.1μF DGND 6 -5V 0.1μF *CONNECT ICL7612A PIN 8 TO AGND AGND OR -5V Figure 17. MAX510 Bipolar Output Circuit __Functional Diagrams (continued) DOUT CLR LDAC AGND DGND VSS VDD DECODE CONTROL REFAB TOP VIEW MAX510 OUTA INPUT REG A DAC REG A DAC A OUTB 12-BIT SHIFT REGISTER ____Pin Configurations (continued) INPUT REG B DAC REG B DAC REG C 16 OUTC OUTA 2 15 OUTD VSS 3 REFAB 4 DAC B OUTC INPUT REG C OUTB 1 DAC C 14 VDD MAX510 12 CS DGND 6 11 SCLK LDAC 7 10 DIN DOUT 8 SR CONTROL CS DIN SCLK INPUT REG D 13 REFCD AGND 5 9 CLR OUTD DAC REG D DAC D DIP/Wide SO REFCD ______________________________________________________________________________________ 19 MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs Package Information _Ordering Information (continued) PART TEMP RANGE MAX509BCAP+ MAX509AEPP+ MAX509BEPP+ MAX509AEWP+ MAX509BEWP+ MAX509AEAP+ MAX509BEAP+ MAX509AMJP MAX509BMJP MAX510ACPE+ MAX510BCPE+ MAX510ACWE+ MAX510BCWE+ MAX510AEPE+ MAX510BEPE+ MAX510AEWE+ MAX510BEWE+ MAX510AMJE MAX510BMJE 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C PIN-PACKAGE 20 SSOP 20 PDIP 20 PDIP 20 Wide SO 20 Wide SO 20 SSOP 20 SSOP 20 CERDIP** 20 CERDIP** 16 PDIP 16 PDIP 16 Wide SO 16 Wide SO 16 PDIP 16 PDIP 16 Wide SO 16 Wide SO 16 CERDIP** 16 CERDIP** TUE (LSB) ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 20 PDIP P20+3 21-0043 — 20 Wide SO W20+3 21-0042 90-0108 20 SSOP A20A+1 21-0056 90-0094 20 CERDIP J20-2 21-0045 — 16 PDIP P16+2 21-0043 — 16 Wide SO W16+3 21-0042 90-0107 16 CERDIP J16-3 21-0045 — **Contact factory for availability and processing to MIL-STD-883. +Denotes a lead(Pb)-free/RoHS-compliant package. 20 ______________________________________________________________________________________ Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs REVISION NUMBER REVISION DATE 3 12/10 DESCRIPTION Updated Ordering Information, added soldering temperature to Absolute Maximum Ratings, updated Figure 17 and Functional Diagrams PAGES CHANGED 1, 2, 19, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX509/MAX510 Revision History MAX509/MAX510 Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs Package Information _Ordering Information (continued) PART TEMP RANGE MAX509BCAP+ MAX509AEPP+ MAX509BEPP+ MAX509AEWP+ MAX509BEWP+ MAX509AEAP+ MAX509BEAP+ MAX509AMJP MAX509BMJP MAX510ACPE+ MAX510BCPE+ MAX510ACWE+ MAX510BCWE+ MAX510AEPE+ MAX510BEPE+ MAX510AEWE+ MAX510BEWE+ MAX510AMJE MAX510BMJE 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C PIN-PACKAGE 20 SSOP 20 PDIP 20 PDIP 20 Wide SO 20 Wide SO 20 SSOP 20 SSOP 20 CERDIP** 20 CERDIP** 16 PDIP 16 PDIP 16 Wide SO 16 Wide SO 16 PDIP 16 PDIP 16 Wide SO 16 Wide SO 16 CERDIP** 16 CERDIP** TUE (LSB) ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 ±1 ±1.5 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 20 PDIP P20+3 21-0043 — 20 Wide SO W20+3 21-0042 90-0108 20 SSOP A20A+1 21-0056 90-0094 20 CERDIP J20-2 21-0045 — 16 PDIP P16+2 21-0043 — 16 Wide SO W16+3 21-0042 90-0107 16 CERDIP J16-3 21-0045 — **Contact factory for availability and processing to MIL-STD-883. +Denotes a lead(Pb)-free/RoHS-compliant package. 20 ______________________________________________________________________________________