19-1675; Rev 0; 4/00
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
Features
♦ 32-Channel Sample/Hold
♦ Output Clamps on Each Channel
♦ 0.01% Accuracy of Acquired Signal
♦ 0.01% Linearity Error
♦ Fast Acquisition Time: 2.5µs
♦ Low Droop Rate: 1mV/s
♦ Low Hold Step: 0.25mV
♦ Wide Output Voltage Range: +7V to -4V
Ordering Information
PART
PINPACKAGE
TEMP. RANGE
ROUT (Ω)
MAX5167LCCM
0°C to +70°C
48 TQFP
50
MAX5167MCCM
0°C to +70°C
48 TQFP
500
MAX5167NCCM
0°C to +70°C
48 TQFP
1k
MAX5167LECM
-40°C to +85°C
48 TQFP
50
MAX5167MECM
-40°C to +85°C
48 TQFP
500
MAX5167NECM
-40°C to +85°C
48 TQFP
1k
Pin Configuration
________________________Applications
Automatic Test Systems (ATE)
37
38
39
40
41
42
43
44
45
48
Avionics Equipment
46
Arbitrary Function Generators
47
ADDR1
ADDR0
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
TOP VIEW
ADDR2
1
36
ADDR3
ADDR4
SELECT
2
35
3
34
4
33
S/H
CONFIG
VL
5
32
DGND
VSS
8
29
9
28
AGND
IN
CH
10
27
11
26
12
25
6
31
OUT18
OUT17
OUT16
VDD
OUT15
OUT14
OUT13
OUT12
OUT11
24
23
22
21
20
19
18
16
15
13
30
OUT21
OUT20
OUT19
CL
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
17
MAX5167
7
14
Industrial Process Controls
TQFP
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX5167
General Description
The MAX5167 contains 32 sample-and-hold amplifiers
driven by a single multiplexed input. The control logic
addressing the outputs is a simple 5-wire input to the
multiplexer. Additional logic allows two devices to function
as a single 64-channel unit. Clamping diodes on each
output allows clamping between two external
reference voltages. The MAX5167 is available with an
output impedance of 50Ω, 500Ω, or 1kΩ.
The MAX5167 operates with +10V and -5V supplies,
and a separate +5V digital logic supply. Manufactured
with a proprietary BiCMOS process, it provides high
accuracy, fast acquisition time, low droop rate, and a
low hold step. The MAX5167 has a typical linearity error
of less than 0.01% and can accurately acquire an 8V
step input signal to 0.01% accuracy in 2.5µs within the
+7V to -4V input signal range. Transitions from sample
mode to hold mode result in only a 0.5mV error. While
in hold mode, the output voltage slowly droops at a rate
of 1mV/s.
The MAX5167 is available in a 48-pin TQFP package and
is specified for both the commercial (0°C to +70°C) and
extended-industrial (-40°C to +85°C) temperature ranges.
MAX5167
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
ABSOLUTE MAXIMUM RATINGS
VDD to AGND.......................................................-0.3V to +11.0V
VSS to AGND .........................................................-6.0V to +0.3V
VDD to VSS ......................................................................+15.75V
VL to DGND ...........................................................-0.3V to +6.0V
VL to AGND ...........................................................-0.3V to +6.0V
DGND to AGND.....................................................-0.3V to +2.0V
IN, OUT_ ....................................................................VSS to VDD
Logic Inputs to DGND ...........................................-0.3V to +6.0V
CH, CL to AGND ..................................................-6.0V to +11.0V
Maximum Current into CL and CH ..................................± 80mA
Maximum Current into Out_.............................................± 10mA
Maximum Current into Logic Inputs ................................± 20mA
Continuous Power Dissipation (TA = +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Operating Temperature Ranges
MAX5167_CCM ..................................................0°C to +70°C
MAX5167_ECM................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +10.0V, VSS = -5.0V, VL = +5.0V ±5%, AGND = DGND = 0, RL = 5kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-4.0V < VIN < +7V RL = ∞
0.01
0.08
%
IN = AGND
0.25
1.00
mV
1
40
mV/s
-5
+30
mV
40
µV/°C
VDD 2.4
V
ANALOG SECTION
Linearity Error
Hold Step
VHS
Droop Rate
Offset Voltage
Output Voltage Range
VOS
VOUT_
DC Output Impedance
Output Source Current
TA = +25°C
IN = AGND
TA = +25°C
CIN
ROUT_
-30
+15°C ≤ TA ≤ +65°C (Note 1)
20
VSS +
0.75
RL = ∞
8V step with 500ns
rising edge (Note 1)
Analog Crosstalk
Input Capacitance
IN = AGND
CL = 250pF for
MAX5167L
-72
-76
CL = 10nF for
MAX5167M/67N
-72
-76
MAX5167L
35
MAX5167M
350
500
650
MAX5167N
700
1000
1300
dB
(Note 1)
RL = ∞,
CL = 250pF
10
20
50
65
2
pF
Ω
ISOURCE
VIN = 0, sample mode
mA
Output Sink Current
ISINK
VIN = 0, sample mode
Output Clamp High
VCH
VSS
VDD
V
Output Clamp Low
VCL
VSS
VDD
V
2
mA
TIMING PERFORMANCE
Acquisition Time
tAQ
8V step to 0.08%,
RL = ∞, Figure 2
TA = +25°C
2.5
100mV step to ±1mV,
RL = ∞, Figure 2
TA = +25°C
1
µs
Hold Mode Settling Time
tH
To ±1mV of final value Figure 2 (Note1)
Aperture Delay
tAP
Figure 2 (Note1)
2
4
1
_______________________________________________________________________________________
2
µs
200
ns
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
(VDD = +10.0V, VSS = -5.0V, VL = +5.0V ±5%, AGND = DGND = 0, RL = 5kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
S/H Pulse Width
tPW
Figure 2 (Note1)
200
ns
Data Setup Time
tDS
Figure 2 (Note1)
50
ns
Data Hold Time
tDH
Figure 2 (Note1)
150
ns
DIGITAL INPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
Input Current
II
2.0
IN = DGND or VCC
-1
V
0.8
V
+1
µA
POWER SUPPLIES
Positive Analog Supply
VDD
(Note 2)
9.5
10
10.5
V
Negative Analog Supply
VSS
(Note 2)
-4.75
-5
-5.45
V
Digital Logic Supply
VL
4.75
5
5.25
V
Positive Analog Supply Current
IDD
RL = ∞
36
mA
Negative Analog Supply Current
ISS
RL = ∞
36
mA
ADDR_ = DGND or VL, S/H =
DGND or VL
0.5
mA
5
mA
Digital Logic Supply Current
Power-Supply Rejection Ratio
IL
PSRR
ADDR_ = +0.8V or +2.0V, S/H =
+0.8V or +2.0V
For VDD and VSS, sample mode,
IN = AGND
-60
-75
dB
Note 1: Guaranteed by design.
Note 2: Do not exceed the absolute maximum rating for VDD to VSS of +15.75V (see Absolute Maximum Ratings).
_______________________________________________________________________________________
3
MAX5167
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VDD = +10V, VSS = -5V, VL = +5V, VIN = +5V, RL = ∞, CL = 0, AGND = DGND = 0, VCH = VDD, VCL = VSS, TA = +25°C, unless
otherwise noted.)
40
DROOP RATE (mV/s)
1.4
1.2
1.0
0.8
0.6
NEGATIVE SUPPLY (VSS)
-100
POSITIVE SUPPLY (VDD)
-80
PSRR (dB)
1.6
-120
MAX5167 TOC 02
MAX5167 TOC 01
1.8
DROOP RATE (mV/s)
PSRR SAMPLE MODE
DROOP RATE vs. TEMPERATURE
50
MAX5167 TOC 03
DROOP RATE vs. INPUT VOLTAGE
2.0
30
20
-60
-40
0.4
10
-20
0.2
0
0
0
0
1
2
3
4
5
6
7
-40
-15
10
INPUT VOLTAGE (V)
35
60
0.1
85
PSRR HOLD MODE
115
110
HOLD STEP (µV)
NEGATIVE SUPPLY (VSS)
-40
HOLD STEP (µV)
-120
-60
-100
-80
-60
-20
0
100
1000
95
90
-20
85
10,000
80
-4 -3 -2 -1
0
FREQUENCY (kHz)
1
2
3
4
5
6
-55
7
-35
INPUT VOLTAGE (V)
-1
OFFSET VOLTAGE (mV)
-3.4
-3.6
-3.8
-4.0
-4.2
-4.4
5
-2
-3
-4
-5
-4.6
-6
-4.8
-7
-5.0
-4 -3 -2 -1
0
1
2
3
INPUT VOLTAGE (V)
4
4
5
6
7
25
45
TEMPERATURE (°C)
0
MAX5167 TOC 07
-3.2
-15
OFFSET VOLTAGE vs. TEMPERATURE
OFFSET VOLTAGE vs. INPUT VOLTAGE
-3.0
OFFSET VOLTAGE (mV)
100
MAX5167 TOC 08
10
10,000
105
-40
0
1
1000
120
MAX5167 TOC 05
-140
-80
100
HOLD STEP vs. TEMPERATURE
-160
MAX5167 TOC 04
POSITIVE SUPPLY (VDD)
-100
10
FREQUENCY (kHz)
HOLD STEP vs. INPUT VOLTAGE
-120
0.1
1
TEMPERATURE (°C)
MAX5167 TOC 06
-4 -3 -2 -1
PSRR (dB)
MAX5167
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
65
85
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
PIN
NAME
FUNCTION
1
ADDR2
Bit 2 of the Address Decoder
2
ADDR3
Bit 3 of the Address Decoder
3
ADDR4
Bit 4 of the Address Decoder
4
SELECT
Enables the S/H pin. The polarity of SELECT is determined by the state of the CONFIG pin. If CONFIG
is low, then SELECT is active-high. If CONFIG is high, then SELECT is active-low. When SELECT is not
in its active state, all 32 channels are in hold mode independent of the S/H pin.
5
S/H
Puts the selected channel into sample mode when low. Places all channels into hold mode when high.
6
CONFIG
7
VL
8
DGND
9
VSS
10
AGND
11
IN
Input Pin
12
CH
Clamp High Pin
13
CL
Clamp Low Pin
14–29
OUT0–OUT15
Output 0–15 Pin
30
VDD
31–46
OUT16–OUT31
47
ADDR0
Bit 0 of the Address Decoder
48
ADDR1
Bit 1 of the Address Decoder
Sets the polarity of the SELECT pin.
+5V Logic Supply
Digital GND
-5V Analog Supply
Analog GND
+10V Analog Supply
Output 16–31 Pin
_______________________________________________________________________________________
5
MAX5167
Pin Description
MAX5167
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
ADDR0–ADDR4
CH
S/H
CS
SELECT
SW1
CONFIG
SW2
SW30 SW31
MAX5167
OUT0
OUT1
IN
OUT30
OUT31
CL
Figure 1. Functional Diagram
Detailed Description
Digital Interface
The MAX5167 has three logic control inputs and five
address lines. The address lines are inputs to a demultiplexer that selects one of the 32 outputs in a standard
addressing scheme (Table 1). The analog input is connected to the addressed sample/hold when directed by
the control logic (Table 2).
The three logic control lines determine the state of the
addressed sample/hold. The normal circuit connection
for this device is to hardwire CONFIG and SELECT to
opposing logic voltages. When SELECT and CONFIG
are in opposite states (one high and the other low), the
five address lines select one of the sample/holds. Use
the S/H line to place the selected channel into sample
or hold mode. The other 31 channels will remain in hold
mode.
If an active-high sampling mode is desired, tie S/H and
CONFIG low. In this case, SELECT controls the
addressed channel with a high state putting that channel into sample mode.
6
The SELECT and CONFIG pins allow the design of a
virtual 64-channel device using two of the MAX5167s.
See the Applications Information section for more information about the 64 output addressing scheme.
Sample/Hold
The MAX5167 contains 32 buffered sample/hold circuits
with internal hold capacitors. Internal hold capacitors
minimize leakage current, dielectric absorption,
feedthrough, and required board space. The value of
the hold capacitor affects acquisition time and droop
rate. Smaller capacitance allows faster acquisition times
but increases the droop rate. Larger values increase
hold acquisition time. The hold capacitor used in the
MAX5167 provides fast 2.5µs (typ) acquisition time while
maintaining a relatively low 1mV/s (typ) droop rate, making the sample/hold ideal for high-speed sampling.
Sample Mode
When SELECT and CONFIG are in opposing logic states,
the S/H line controls the mode of operation. Sample mode
is entered when S/H is low. During sample mode, the
selected multiplexer channel connects to IN, allowing the
_______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
MAX5167
Table 1. Channel/Output Selection
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
OUTPUT
0
0
0
0
0
VOUT0 is selected
0
0
0
0
1
VOUT1 is selected
0
0
0
1
0
VOUT2 is selected
0
0
0
1
1
VOUT3 is selected
0
0
1
0
0
VOUT4 is selected
0
0
1
0
1
VOUT5 is selected
0
0
1
1
0
VOUT6 is selected
0
0
1
1
1
VOUT7 is selected
0
1
0
0
0
VOUT8 is selected
0
1
0
0
1
VOUT9 is selected
0
1
0
1
0
VOUT10 is selected
0
1
0
1
1
VOUT11 is selected
0
1
1
0
0
VOUT12 is selected
0
1
1
0
1
VOUT13 is selected
0
1
1
1
0
VOUT14 is selected
0
1
1
1
1
VOUT15 is selected
1
0
0
0
0
VOUT16 is selected
1
0
0
0
1
VOUT17 is selected
1
0
0
1
0
VOUT18 is selected
1
0
0
1
1
VOUT19 is selected
1
0
1
0
0
VOUT20 is selected
1
0
1
0
1
VOUT21 is selected
1
0
1
1
0
VOUT22 is selected
1
0
1
1
1
VOUT23 is selected
1
1
0
0
0
VOUT24 is selected
1
1
0
0
1
VOUT25 is selected
1
1
0
1
0
VOUT26 is selected
1
1
0
1
1
VOUT27 is selected
1
1
1
0
0
VOUT28 is selected
1
1
1
0
1
VOUT29 is selected
1
1
1
1
0
VOUT30 is selected
1
1
1
1
1
VOUT31 is selected
Table 2. Logic Table for CONFIG, SELECT, and S/H
S/H (SAMPLE/HOLD)
CONFIG
SELECT
CHANNEL FUNCTION
0
0
0
Hold
0
0
1
Sampling
0
1
0
Sampling
0
1
1
Hold
1
X
X
Hold
_______________________________________________________________________________________
7
MAX5167
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
hold capacitor to acquire the input signal. To guarantee
an accurate sample, maintain sample mode for at least
4µs. The output of the sample/hold amplifier tracks the
input after 4µs. Only the addressed channel on the
selected multiplexer samples the input; all other channels
remain in hold mode.
Hold Mode
No matter what the condition of the other control lines,
S/H = high places the MAX5167 into an all-channel
hold mode. Hold mode disables the multiplexer and
disconnects all 32 sample/holds from the input. When a
channel is disconnected, the hold capacitor maintains
the sampled voltage at the output with a 1mV/s typical
droop rate (towards VDD).
Hold Step
When switching between sample mode and hold mode,
the voltage of the hold capacitor changes due to
charge injection from stray capacitance. This voltage
change, called hold step, is minimized by limiting the
amount of stray capacitance seen by the hold capacitor.
The MAX5167 limits the hold step to 0.25mV (typ). An
output capacitor to ground can be used to filter out this
small hold-step error.
Output
The MAX5167 contains an output buffer for each multiplexer channel (32 total), so the hold capacitor sees a
high-impedance input that reduces the droop rate. The
capacitor droops at 1mV/s (typ) while in hold mode. The
buffer also provides a low output impedance; however,
the device contains output resistors in series with the
buffer output (Figure 1) for selected output filtering. To
provide greater design flexibility, the MAX5167 is available with an output impedance of 50Ω, 500Ω, or 1kΩ.
Output loads increase the analog supply current (IDD
and ISS). Excessive loading of the output(s) drastically
increases power dissipation. Do not exceed the maximum
power dissipation specified in the Absolute Maximum
Ratings.
The resistor-divider formed by the output resistor (RO)
and load impedance (RL) scales the sampled voltage
(VSAMP). Determine the output voltage (VOUT_) as follows:
Voltage Gain = AV = RL / (RL + RO)
VOUT_ = VSAMP ✕ AV
The maximum output voltage range depends on the analog supply voltages available and the scaling factor used:
(VSS + 0.75V) ✕ AV ≤ VOUT_ ≤ (VDD - 2.4V) ✕ AV
when RL = ∞, then AV = 1, and this equation becomes:
8
(VSS + 0.75V) ≤ VOUT ≤ (VDD - 2.4V)
Output Clamp
The MAX5167 clamps the output between two externally
applied reference voltages. Internal diodes connect all
outputs to the clamping voltages, restricting the output
voltage to:
(VCH + 0.7V) ≤ VOUT_ ≤ (VCL - 0.7V)
When the clamping voltage exceeds the maximum output
voltage, the maximum output voltage will be the limiting
factor. To disable output clamping, connect CH to VDD
and CL to VSS to set the clamping voltages beyond the
maximum output voltage range. The clamping diodes
allow the MAX5167 to be used with other devices
requiring restricted input voltages.
Timing Definitions
Acquisition time (tAQ) is the time the MAX5167 must
remain in sample mode for the hold capacitor to
acquire an accurate sample. The hold-mode settling
time (tH) is the time necessary for the output voltage to
settle to its final value. Aperture delay (tAP) is the time
interval required to disconnect the input from the hold
capacitor. The hold pulse width (tPW) is the time the
MAX5167 must remain in hold mode while the address
is changed. Data setup time (t DS ) is the time an
address must be maintained at the digital input pins
before the address becomes valid. Data hold time (tDH)
is the time an address must be maintained after the
device is placed in hold mode (Figure 2).
Applications Information
Multiplexing a DAC
Figure 3 shows a typical demultiplexer application.
Different digital codes are converted by the digital-toanalog converter (DAC) and then stored on 32 different
channels of the MAX5167. The 40mV/s (max) droop
rate requires refreshing the hold capacitors every
250ms before the voltage droops by 1/2LSB for an 8-bit
DAC with a 5V full-scale voltage.
Virtual 64 Output Sample and Hold
Two MAX5167s can be configured to operate as a single
64 output sample and hold. The upper and lower
addressed devices are identified by CONFIG’s logic
level. Connect the CONFIG pin of the upper device low,
making its SELECT pin active-high. Connect the CONFIG
pin of the lower device high to make the SELECT pin
active-low. Figure 4 shows how to configure the devices.
The devices now use only six address lines and a single
S/H control to decode 64 outputs. Address lines A0–A4
from the control logic connect to ADDR0–ADDR4 on
_______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
MAX5167
tPW
S/H
tDS
tDH
ADDR_
SELECT, CONFIG
tH
HOLD STEP
OUT_
IN
tAQ
(CHANNEL x FROM HOLD TO SAMPLE)
tAP
(CHANNEL x FROM SAMPLE TO HOLD)
Figure 2. Timing Diagram
VL
SELECT
ADDRESS BUS
ADDR0–ADDR4
CS
MAX5167
SWITCHES 0–31
S/H
OUT0
OUT1
DATA BUS
DAC
IN
OUT30
OUT31
CONFIG
Figure 3. Multiplexing a DAC
_______________________________________________________________________________________
9
MAX5167
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
VL
OUT0
OUT1
CONFIG
A0–A4
ADDR0–ADDR4
A5
SELECT
WR
S/H
INPUT
MAX5167
IN
OUT30
OUT31
OUT32
ADDR0–ADDR4
OUT33
SELECT
S/H
IN
MAX5167
CONFIG
OUT62
OUT63
Figure 4. 64 Output Sample-and-Hold Circuit
both of the 32-channel devices. The A5 line toggles the
SELECT pins of both devices to select the active one.
The device that has CONFIG tied high responds to the
lower 32 addresses (000000 through 011111). The
device that has CONFIG grounded responds to the
upper 32 addresses (100000 through 111111).
IBIAS
10µA, INH = LOW
Input Drive Requirements
The input of the MAX5167 feeds the inputs of 32 highimpedance buffers. These buffers are what charge the
sample/hold capacitor through the multiplexer switch
resistance. The bias current of a selected buffer is
10µA, and this feeds into the 10pF input capacitance.
Figure 5 shows an equivalent input circuit. The bias currents of the other 31 sample and holds are very small in
comparison to the bias current of the selected channel.
Powering the MAX5167
CIN
10pF
Figure 5. Input Equivalent Circuit
Chip Information
TRANSISTOR COUNT: 6961
The MAX5167 does not require a special power-up
sequence to avoid latchup. The device requires three
separate supply voltages for operation. However, when
one or two of the voltages are not available, DC-DC
charge-pump (switched-capacitor) converters provide
a simple, efficient solution. The MAX860 provides voltage doubling or inversion, ideal for conversions from
+5V to +10V or from +5V to -5V.
10
______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
32L/48L,TQFP.EPS
______________________________________________________________________________________
11
MAX5167
Package Information
MAX5167
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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