19-1475; Rev 0; 4/99
Low-Power, Serial, 12-Bit DACs
with Voltage Output
The MAX5174/MAX5176 low-power, serial, voltage-output, 12-bit digital-to-analog converters (DACs) feature a
precision output amplifier in a space-saving 16-pin
QSOP package. The MAX5174 operates from a single
+5V supply, and the MAX5176 operates from a single
+3V supply. Both devices draw only 280µA of supply
current, which reduces to 1µA in shutdown. In addition,
the programmable power-up reset feature allows for a
user-selectable output voltage state of either 0 or midscale.
The 3-wire, digital, serial interface is compatible with
SPI™/QSPI™, and MICROWIRE™ standards. An input
register followed by a DAC register provides a doublebuffered input, allowing the input and DAC registers to
be updated independently or simultaneously with a 16bit serial word. Additional features include software and
hardware shutdown, shutdown lockout, a hardware
clear pin, and a reference input capable of accepting
DC and offset AC signals. These devices provide a programmable digital output pin for added functionality
and a serial-data output pin for daisy-chaining. All logic
inputs are TTL/CMOS compatible and are internally
buffered with Schmitt triggers to allow direct interfacing
to optocouplers.
The MAX5174/MAX5176 incorporate a proprietary onchip circuit that keeps the output voltage virtually
“glitch free,” limiting the glitches to a few millivolts during power-up.
Both devices are available in 16-pin QSOP packages
and are specified for the extended (-40°C to +85°C)
temperature range. The MAX5170/MAX5172 are pincompatible 14-bit upgrades to the MAX5174/MAX5176.
For 100% pin-compatible DACs with internal reference,
see the 13-bit MAX5130/MAX5131 and the 12-bit
MAX5120/MAX5121 data sheets.
Features
♦ ±1 LSB INL
♦ 1µA Shutdown Current
♦ “Glitch Free” Output Voltage at Power-Up
♦ Single-Supply Operation
+5V (MAX5174)
+3V (MAX5176)
♦ Full-Scale Output Range
+2.048V (MAX5176, VREF = +1.25V)
+4.096V (MAX5174, VREF = +2.5V )
♦ Rail-to-Rail® Output Amplifier
♦ Adjustable Output Offset
♦ Low THD (-80dB) in Multiplying Operation
♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial
Interface
♦ Programmable Shutdown Mode and Power-Up
Reset
♦ Buffered Output Capable of Driving 5kΩ || 100pF
Loads
♦ User-Programmable Digital Output Pin Allows
Serial Control of External Components
♦ 14-Bit Upgrades Available (MAX5170/MAX5172)
Ordering Information
TEMP. RANGE
PIN-PACKAGE
MAX5174AEEE
-40°C to +85°C
16 QSOP
±1
MAX5174BEEE
MAX5176AEEE
MAX5176BEEE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 QSOP
16 QSOP
16 QSOP
±2
±2
±4
Applications
Industrial Process Controls
Digital Offset and Gain Adjustment
Motion Control
Automatic Test Equipment (ATE)
Remote Industrial Controls
µP-Controlled Systems
Functional Diagram appears at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
INL
(LSB)
PART
Pin Configuration
TOP VIEW
OS 1
16 VDD
OUT 2
15 N.C.
RS 3
PDL 4
CLR 5
14 REF
MAX5174
MAX5176
13 AGND
12 SHDN
CS 6
11 UPO
DIN 7
10 DOUT
9
SCLK 8
DGND
QSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX5174/MAX5176
General Description
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ............................................-0.3V to +6.0V
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND..........................................-0.3V to +6.0V
DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V)
OUT, REF to AGND ...................................-0.3V to (VDD + 0.3V)
OS to AGND ...............................(AGND - 4.0V) to (VDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
16-Pin QSOP (derate 8mW/°C above +70°C)..............667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5174
(VDD = +5V ±10%, VREF = 2.5V, OS = AGND = DGND, RL = 5kΩ, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
12
Integral Nonlinearity (Note 1)
INL
Differential Nonlinearity
DNL
Offset Error (Note 2)
VOS
Gain Error
Power-Supply Rejection Ratio
GE
±1
MAX5174B
±2
LSB
±10
mV
-0.6
±4
RL = 5kΩ
-1.6
±8
10
120
f = 100kHz
Output Thermal Noise Density
LSB
±1
RL = ∞
PSRR
Output Noise Voltage
Bits
MAX5174A
LSB
µV/V
1
LSBp-p
80
nV/√Hz
REFERENCE
Reference Input Range
VREF
0
Reference Input Resistance
RREF
18
VDD - 1.4
V
kΩ
MULTIPLYING-MODE PERFORMANCE
Reference -3dB Bandwidth
VREF = 0.5Vp-p + 1.5VDC, slew-rate limited
350
kHz
Reference Feedthrough
VREF = 3.6Vp-p + 1.8VDC, f = 1kHz,
code = all 0s
-80
dB
VREF = 2Vp-p + 1.5VDC, f = 10kHz,
code = FFF hex
82
dB
Signal-to-Noise Plus Distortion
Ratio
SINAD
DIGITAL INPUTS
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
3
VHYS
Input Leakage Current
IIN
Input Capacitance
CIN
V
0.8
200
VIN = 0 or VDD
0.001
V
mV
±1
8
µA
pF
DIGITAL OUTPUTS
Output High Voltage
VOH
ISOURCE = 2mA
Output Low Voltage
VOL
ISINK = 2mA
2
VDD - 0.5
V
0.13
_______________________________________________________________________________________
0.4
V
Low-Power, Serial, 12-Bit DACs
with Voltage Output
(VDD = +5V ±10%, VREF = 2.5V, OS = AGND = DGND, RL = 5kΩ, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
Output Settling Time
0.6
To ±0.5LSB, from 10mV to full-scale
Output Voltage Swing (Note 3)
0
OS Pin Input Resistance
80
Time Required to Exit Shutdown
CS = VDD, fSCLK = 100kHz, VSCLK = 5Vp-p
Digital Feedthrough
V/µs
18
µs
VDD
120
V
kΩ
40
µs
1
nV-s
POWER SUPPLIES
Positive Supply Voltage
VDD
Power-Supply Current (Note 4)
IDD
4.5
Shutdown Current (Note 4)
5.5
V
0.35
0.4
mA
1
10
µA
TIMING CHARACTERISTICS
SCLK Clock Period
tCP
100
ns
SCLK Pulse Width High
tCH
40
ns
SCLK Pulse Width Low
tCL
40
ns
CS Fall to SCLK Rise Setup
Time
tCSS
40
ns
SCLK Rise to CS Rise Hold
Time
tCSH
0
ns
SDI Setup Time
tDS
40
ns
SDI Hold Time
tDH
0
ns
SCLK Rise to DOUT Valid
Propagation Delay
tDO1
CLOAD = 200pF
80
ns
SCLK Fall to DOUT Valid
Propagation Delay
tDO2
CLOAD = 200pF
80
ns
SCLK Rise to CS Fall Delay
tCS0
10
ns
CS Rise to SCLK Rise Hold Time
tCS1
40
ns
CS Pulse Width High
tCSW
100
ns
_______________________________________________________________________________________
3
MAX5174/MAX5176
ELECTRICAL CHARACTERISTICS—MAX5174 (continued)
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
ELECTRICAL CHARACTERISTICS—MAX5176
(VDD = +2.7V to +3.6V, VREF = 1.25V, OS = AGND = DGND, RL = 5kΩ, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
12
Bits
MAX5176A
±2
MAX5176B
±4
Integral Nonlinearity (Note 5)
INL
Differential Nonlinearity
DNL
±1
LSB
Offset Error (Note 2)
VOS
±10
mV
Gain Error
Power-Supply Rejection Ratio
GE
RL = ∞
-0.6
±4
RL = 5kΩ
-1.6
±8
10
120
PSRR
Output Noise Voltage
f = 100kHz
Output Thermal Noise Density
LSB
LSB
µV/V
2
LSBp-p
80
nV/√Hz
REFERENCE
Reference Input Range
VREF
0
Reference Input Resistance
RREF
18
VDD - 1.4
V
kΩ
MULTIPLYING-MODE PERFORMANCE
Reference -3dB Bandwidth
VREF = 0.5Vp-p + 0.75VDC, slew-rate limited
350
kHz
Reference Feedthrough
VREF = 1.6Vp-p + 0.8VDC, f = 1kHz,
code = all 0s
-80
dB
VREF = 0.6Vp-p + 0.9VDC, f = 10kHz,
code = FFF hex
78
dB
Signal-to-Noise Plus Distortion
Ratio
SINAD
DIGITAL INPUT
Input High Voltage
Input Low Voltage
Input Hysteresis
VIH
2.2
V
VIL
0.8
VHYS
Input Leakage Current
IIN
Input Capacitance
CIN
200
VIN = 0 or VDD
0.001
V
mV
±1
8
µA
pF
DIGITAL OUTPUT
Output High Voltage
VOH
ISOURCE = 2mA
Output Low Voltage
VOL
ISINK = 2mA
4
VDD - 0.5
V
0.13
_______________________________________________________________________________________
0.4
V
Low-Power, Serial, 12-Bit DACs
with Voltage Output
(VDD = +2.7V to +3.6V, VREF = 1.25V, OS = AGND = DGND, RL = 5kΩ, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
Output Settling Time
0.6
To ±0.5LSB, from 10mV to full-scale
Output Voltage Swing (Note 3)
0
OS Pin Input Resistance
80
Time Required to Exit Shutdown
CS = VDD, DIN = 50kHz; fSCLK = 100kHz,
VSCLK = 3Vp-p
Digital Feedthrough
V/µs
18
µs
VDD
V
120
kΩ
40
µs
1
nV-s
POWER SUPPLIES
Positive Supply Voltage
VDD
Power-Supply Current (Note 4)
IDD
2.7
Shutdown Current (Note 4)
3.6
V
0.35
0.4
mA
1
10
µA
TIMING CHARACTERISTICS
SCLK Clock Period
tCP
150
ns
SCLK Pulse Width High
tCH
75
ns
SCLK Pulse Width Low
tCL
75
ns
tCSS
60
ns
tCSH
0
ns
SDI Setup Time
tDS
60
ns
SDI Hold Time
tDH
0
ns
SCLK Rise to DOUT Valid
Propagation Delay
tDO1
CLOAD = 200pF
200
ns
SCLK Fall to DOUT Valid
Propagation Delay
tDO2
CLOAD = 200pF
200
ns
SCLK Rise to CS Fall Delay
tCS0
10
ns
CS Rise to SCLK Rise Hold Time
tCS1
75
ns
CSB Fall to SCLK Rise Setup
Time
SCLK Rise to CS Rise Hold Time
tCSW
150
CS Pulse
Width
High between codes
Note
1: INL
guaranteed
10 and 4095.
Note 2: Offset is measured at the code that comes closest to 10mV.
Note 3: Accuracy is better than 1 LSB for VOUT = 10mV to VDD - 180mV. Guaranteed by PSR test on end points.
Note 4: RL = open and digital inputs are either VDD or DGND.
Note 5: INL guaranteed between codes 20 and 4095.
ns
_______________________________________________________________________________________
5
MAX5174/MAX5176
ELECTRICAL CHARACTERISTICS—MAX5176 (continued)
Typical Operating Characteristics
(MAX5174: VDD = +5V, VREF = 2.5V; MAX5176: VDD = +3V, VREF = +1.25V; CL = 100pF, OS = AGND, code = FFF hex,
TA = +25°C, unless otherwise noted.)
MAX5174
300
290
280
270
260
250
288
240
286
284
282
280
278
276
274
272
1.4
MAX5174/6toc03
310
290
MAX5174/6toc02
320
NO-LOAD SUPPLY CURRENT (µA)
MAX5174/6 toc01
330
NO-LOAD SUPPLY CURRENT (µA)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT (µA)
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.3
1.2
1.1
1.0
0.9
270
0.8
268
230
4.4
4.6
4.8
5.0
5.2
5.4
5.6
-50
-30
-10
OUTPUT VOLTAGE vs. TEMPERATURE
4.0966
4.0964
50
70
-50
90
-30
-10
10
30
50
TEMPERATURE (°C)
OUTPUT VOLTAGE vs. LOAD RESISTANCE
DYNAMIC RESPONSE
70
90
MAX5174/6 toc06
MAX5174/6 toc05
4.0
3.5
OUTPUT VOLTAGE (V)
4.0968
30
4.5
MAX5174/6toc04
4.0970
10
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
5V
VCS
5V/div
0
3.0
4.096V
2.5
2.0
VOUT
1V/div
1.5
1.0
4.0962
10mV
0.5
4.0960
0
-30
-10
10
30
50
70
90
10
100
TEMPERATURE (°C)
10k
2µs/div
100k
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
DYNAMIC RESPONSE
MAX5174/6 toc07
-75
5V
-76
0
-77
4.096V
VOUT
1V/div
MAX5174/76 toc08
VCS
5V/div
1k
RL (Ω)
REFERENCE FEEDTHROUGH
0
VREF = 1.8 VDC + 3.6Vp-p at f = 1kHz
MAX5174/76 toc9
-50
THD + NOISE (dB)
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
-78
-79
VOUT/VREF
-80
12.5dB/div
-81
-82
10mV
-83
-84
2µs/div
6
10
100
1k
10k
FREQUENCY (Hz)
100k
20
FREQUENCY (Hz)
_______________________________________________________________________________________
10k
Low-Power, Serial, 12-Bit DACs
with Voltage Output
MAX5174/MAX5176
Typical Operating Characteristics (continued)
(MAX5174: VDD = +5V, VREF = 2.5V; MAX5176: VDD = +3V, VREF = +1.25V; CL = 100pF, OS = AGND, code = FFF hex,
TA = +25°C, unless otherwise noted.)
MAX5174
FFT PLOT
DIGITAL FEEDTHROUGH
MAJOR-CARRY TRANSITION
MAX5174/6 toc12
VREF = 1.25VDC + 1.13Vp-p at f = 10kHz
MAX5174/76 toc10
MAX5174/6 toc11
0
VOUT
2mV/div
VCS
V/div
AC-COUPLED
VOUT/VREF
12.5dB/div
VSCLK
5V/div
VOUT
100mV/div
20
100k
FREQUENCY (Hz)
400ns/div
5µs/div
START-UP GLITCH
REFERENCE INPUT FREQUENCY RESPONSE
MAX5174/6 toc14
MAX5174/6toc13
5
0
VDD
1V/div
GAIN (dB)
-5
-10
-15
VOUT
10mV/div
AC-COUPLED
-20
VREF = 0.67Vp-p + 1.5VDC
-25
0
500
1000
1500
2000
2500
5Oms/div
3000
FREQUENCY (kHz)
MAX5176
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
285
280
275
270
265
260
285
280
275
270
265
255
250
260
2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
SUPPLY VOLTAGE (V)
MAX5174/6 toc17
290
0.60
SHUTDOWN SUPPLY CURRENT (µA)
290
295
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5174/6toc16
NO-LOAD SUPPLY CURRENT (µA)
295
NO-LOAD SUPPLY CURRENT (µA)
MAX5174/6toc15
300
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
-50
-30
-10
10
30
50
TEMPERATURE (°C)
70
90
-50
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(MAX5174: VDD = +5V, VREF = 2.5V; MAX5176: VDD = +3V, VREF = +1.25V; CL = 100pF, OS = AGND, code = FFF hex,
TA = +25°C, unless otherwise noted.)
MAX5176
OUTPUT VOLTAGE vs. LOAD RESISTANCE
OUTPUT VOLTAGE vs. TEMPERATURE
2.0486
2.0484
MAX5170/72 toc19
2.0
OUTPUT VOLTAGE (V)
2.0488
DYNAMIC RESPONSE
MAX5174/6 toc20
2.5
MAX5174/6 toc18
2.0490
3V
VCS
3V/div
0
1.5
2.048V
1.0
VOUT
500mV/div
0.5
2.0482
0
2.0480
10mV
-0.5
-50
-30
-10
10
30
50
70
10
90
100
TEMPERATURE (°C)
10k
100k
2µs/div
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
DYNAMIC RESPONSE
MAX5174/6 toc21
3V
-78.5
0
-79.0
2.048V
VOUT
500mV/div
MAX5174/76 toc22
-78.0
THD + NOISE (dB)
VCS
3V/div
1k
RL (Ω)
REFERENCE FEEDTHROUGH
0
VREF = 0.8VDC + 1.6Vp-p at f = 1kHz
MAX5174/76 toc23
OUTPUT VOLTAGE (V)
-79.5
VOUT/VREF
12.5dB/div
-80.0
-80.5
-81.0
10mV
-81.5
-82.0
2µs/div
10
100
1k
10k
FREQUENCY (Hz)
20
100k
FREQUENCY (Hz)
MAJOR-CARRY TRANSITION
FFT PLOT
MAX5174/6 toc25
0
VREF = 0.9VDC + 0.424Vp-p at f = 10kHz
MAX5174/76 toc24
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
CS
2V/div
VOUT/VREF
12.5dB/div
OUT
100mV/div
20
8
FREQUENCY (Hz)
100k
AC-COUPLED
5µs/div
_______________________________________________________________________________________
10k
Low-Power, Serial, 12-Bit DACs
with Voltage Output
MAX5176
REFERENCE INPUT
FREQUENCY RESPONSE
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5174/6 toc26
MAX5174/6toc27
0
SCLK
2V/div
START-UP GLITCH
MAX5174/6 toc28
5
VDD
1V/div
GAIN (dB)
-5
OUT
500µV/div
-10
-15
VOUT
10mV/div
-20
-25
VREF = 0.67Vp-p + 0.75VDC
-30
2µs/div
0
500
1000
1500
2000
2500
3000
FREQUENCY (kHz)
AC-COUPLED
AC-COUPLED
50ms/div
Pin Description
PIN
NAME
FUNCTION
1
OS
2
OUT
Offset Adjustment. Connect to AGND for no offset.
3
RS
Reset Mode Select (digital input). Connect to VDD to select midscale reset output voltage. Connect to
DGND to select 0 reset output voltage.
4
PDL
Power-Down Lockout. (digital input). Connect to VDD to allow shutdown. Connect to DGND to disable
software and hardware shutdown.
5
CLR
Clear DAC. (digital input) Clears the DAC to either zero or midscale as determined by RS.
Voltage Output. High impedance when in shutdown. The output voltage is limited to VDD.
6
CS
Chip-Select Input (digital input). DIN ignored when CS is high.
7
DIN
Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK.
8
SCLK
Serial Clock Input (digital input).
9
DGND
Digital Ground
10
DOUT
Serial-Data Output
11
UPO
12
SHDN
Shutdown (digital input). Pulling SHDN high when PDL = VDD places the chip in shutdown with a maximum
shutdown current of 10µA.
13
AGND
Analog Ground
14
REF
Reference Input. Maximum VREF is VDD - 1.4V.
15
N.C.
No Connection
16
VDD
Positive Supply. Bypass to AGND with a 4.7µF capacitor in parallel with a 0.1µF capacitor.
User-Programmable Output. State is set by the serial input.
_______________________________________________________________________________________
9
MAX5174/MAX5176
Typical Operating Characteristics (continued)
(MAX5174: VDD = +5V, VREF = 2.5V; MAX5176: VDD = +3V, VREF = +1.25V; CL = 100pF, OS = AGND, code = FFF hex,
TA = +25°C, unless otherwise noted.)
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
Detailed Description
The MAX5174/MAX5176 12-bit, serial, voltage-output
DACs operate with a 3-wire serial interface. These
devices include a 16-bit shift register and a doublebuffered input composed of an input register and a
DAC register (see Functional Diagram). In addition,
these devices employ a rail-to-rail output amplifier and
internal trimmed resistors to provide a gain of
+1.638V/V, maximizing the output voltage swing. The
MAX5174/MAX5176’s offset adjust pin allows for a DC
shift in DAC outputs. The DACs are designed with an
inverted R-2R ladder network (Figure 1) that produces
a weighted voltage proportional to the reference voltage.
OS_
R
R
R
2R
2R
D0
R
2R
D9
OUT_
R
2R
2R
D10
D11
REF_
AGND
Reference Inputs
The reference input accepts both AC and DC values
with a voltage range extending from 0 to VDD - 1.4V.
The following equation represents the resulting output
voltage:
VOUT =
VREF ⋅ N ⋅ Gain
4096
where N is the numeric value of the DAC’s binary input
code (0 to 4095), VREF is the reference voltage, and
Gain is the internally set voltage gain (1.638V/V if OS =
AGND). The maximum output voltage is VDD. The reference pin has a minimum impedance of 18kΩ and is
code dependent.
Output Amplifier
With OS connected to AGND, the output amplifier
employs an internal trimmed resistor-divider, setting the
gain to 1.638V/V and minimizing gain error. The output
amplifier has a typical slew rate of 0.6V/µs, and settles
to ±0.5LSB from a full-scale transition within 18µs when
loaded with 5kΩ in parallel with 100pF. Loads less than
2kΩ degrade performance. For alternative output
amplifier setups, refer to the Applications Information
section.
Shutdown Mode
The MAX5174/MAX5176 feature a software- and hardware-programmable shutdown mode that reduces the
typical supply current to 1µA. Enter shutdown by writing
the appropriate input-control word as shown in Table 1
or by using the hardware shutdown. In shutdown mode,
the reference input and amplifier output both become
high impedance, and the serial interface remains
active. Data in the input register is saved, allowing the
MAX5174/MAX5176 to recall the prior output state
when returning to normal operation. Exit shutdown by
10
SHOWN FOR ALL 1s ON DAC
Figure 1. Simplified DAC Circuit Diagram
reloading the DAC register from the shift register, by
simultaneously loading the input and DAC registers, or
by toggling PDL. When returning from shutdown wait
40µs for the output to settle.
Power-Down Lockout
Power-down lockout disables the software/hardware
shutdown mode. A high-to-low transition on PDL brings
the device out of shutdown and returns the output to its
previous state.
Shutdown
Pulling SHDN high while PDL is high places the
MAX5174/MAX5176 in shutdown. Pulling SHDN low will
not return the device to normal operation. A high-to-low
transition on PDL or an appropriate command from the
serial data line (see Table 1 for commands) is required
to exit shutdown.
Serial-Interface
The MAX5174/MAX5176 3-wire serial interface is compatible with SPI and QSPI (Figure 2), and MICROWIRE
(Figure 3) interface standards. The 16-bit serial input
word consists of two control bits, 12 bits of data (MSB
to LSB), and two sub-bits.
The control bits determine the MAX5174/MAX5176’s
response as outlined in Table 1. The MAX5174/
MAX5176’s digital inputs are double buffered, which
allows any of the following:
• Loading the input register without updating the DAC
register.
• Updating the DAC register from the input register.
• Updating the input and DAC registers simultaneously.
______________________________________________________________________________________
Low-Power, Serial, 12-Bit DACs
with Voltage Output
SS
DIN
MAX5174
MAX5176
MOSI
SCLK
SCK
CS
SPI/QSPI
PORT
Specific commands for setting these are shown in
Table 1.
The general timing diagram in Figure 4 illustrates how
the MAX5174/MAX5176 acquires data. CS must go low
at least tCSS before the rising edge of the serial clock
(SCLK). With CS low, data is clocked into the register
on the rising edge of SCLK. The maximum serial clock
frequency guaranteed for proper operation is 10MHz
for the MAX5174 and 6MHz for the MAX5176. See
Figure 5 for a detailed timing diagram of the serial interface.
I/O
CPOL = 0, CPHA = 0
Figure 2. Connections for SPI and QSPI Standards
Serial Data Output (DOUT)
MAX5174
MAX5176
SCLK
SK
DIN
SO
CS
I/O
MICROWIRE
PORT
The serial-data output (DOUT) is the internal shift register’s output and allows for daisy-chaining of multiple
devices as well as data readback (see Applications
Information). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, then the output data
lags DIN by 16.5 clock cycles and is clocked out on the
serial clock’s rising edge. During shutdown, DOUT
retains its last digital state prior to shutdown.
Figure 3. Connections for MICROWIRE
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
S1, S0
FUNCTION
C1
C0
D11..................D0
0
0
12-bit DAC data
00
Load input register; DAC registers are unchanged.
0
1
12-bit DAC data
00
Load input register; DAC registers are updated (start-up DAC with
new data).
1
0
xxxxxxxxxxxx
xx
Update DAC register from input register (start-up DAC with data
previously stored in the input registers).
1
1
0 0 x x xxxx xxxx
xx
No operation (NOP).
1
1
0 1 x x xxxx xxxx
xx
Shut down DAC (provided PDL = 1).
1
1
1 0 0 x xxxx xxxx
xx
UPO goes low (default).
1
1
1 0 1 x xxxx xxxx
xx
UPO goes high.
1
1
1 1 0 x xxxx xxxx
xx
Mode 1, DOUT clocked out on SCLK’s rising edge.
1
1
1 1 1 x xxxx xxxx
xx
Mode 0, DOUT clocked out on SCLK’s falling edge (default).
______________________________________________________________________________________
11
MAX5174/MAX5176
The MAX5174/MAX5176 accepts one 16-bit packet or
two 8-bit packets sent while CS remains low. The
MAX5174/MAX5176 allow the following to be configured:
• Clock edge on which serial data output (DOUT) is
clocked.
• State of the user-programmable logic output.
• Configuration of the reset state.
+5V
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
CS
COMMAND
EXECUTED
SCLK
1
DIN
C2
8
C1
C0
D9
D8
D7
D6
9
D5
D4
16
D3
D2
D1
D0
S2
S1
S0
Figure 4. Serial-Interface Timing Diagram
tCSW
CS
tCSO
tCSS
tCSH
tCS1
SCLK
tCH
tCL
tCP
DIN
tDS
tD01
tD02
tDH
DOUT
Figure 5. Detailed Serial-Interface Timing Diagram
User-Programmable Logic Output (UPO)
The user-programmable logic output (UPO) allows control of an external device through the serial interface,
thereby reducing the number of microcontroller I/O pins
required. During power-down, this output will retain its
digital state prior to shutdown. When CLR is pulled low,
UPO will reset to its programmed default state. See
Table 1 for specific commands to control the UPO.
Reset (RS) and Clear (CLR)
The MAX5174/MAX5176 offers a clear pin (CLR), which
resets the output voltage. If RS = DGND, then CLR
resets the output voltage to 0. If RS = VDD, then CLR
resets the output voltage to mid-scale. In either case,
CLR will reset UPO to its programmed default state.
Applications Information
Table 2 lists the codes for unipolar output voltages. The
output voltage is limited to VDD. Use the OS pin to introduce an offset voltage as shown in Figure 7 and
described in the Offset and Buffer Configurations section.
Bipolar Output
Figure 8 shows the MAX5174/MAX5176 configured for
bipolar output operation. The output voltage is given by
the following equation (OS = AGND):
2 ⋅ N
VOUT = VREF
− 1
4096
where N represents the numeric value of the DAC’s
binary input code and VREF is the voltage of the external reference. Table 3 shows digital codes and the corresponding output voltage for Figure 8’s circuit.
Unipolar Output
Figure 6 shows the MAX5174/MAX5176 configured for
unipolar, rail-to-rail operation with a gain of 1.638V/V.
12
______________________________________________________________________________________
Low-Power, Serial, 12-Bit DACs
with Voltage Output
OS
+5V/+3V
REF
VDD
VOFFSET = VOS · (1- Gain)
MAX5174
MAX5176
where Gain = 1.638.
DAC
However, the total output voltage of the device cannot
exceed VDD, regardless of the voltage on the OS pin.
To set the gain of the output amplifier to 1, connect OS
to OUT.
OUT
AGND
DGND
Daisy-Chaining Devices
The serial-data output pin (DOUT) allows multiple
MAX5174/MAX5176s to be daisy-chained together as
shown in Figure 9. The advantage of this is that only two
lines are needed to control all the DACs. The disadvantage is that it takes n commands to program the DACs.
Figure 10 shows several MAX5174/MAX5176s sharing
one common DIN signal line. In this configuration the
data bus is common to all devices; however, more I/O
lines are required because each device needs a dedicated CS line. The advantage of this configuration is
that only one command is needed to program any DAC.
Figure 6. Unipolar Output Circuit (Rail-to-Rail)
OS
+5V/+3V
REF
VOS
VDD
MAX5174
MAX5176
DAC
OUT
AGND
Table 2. Unipolar Code Table
(Circuit of Figure 6)
DGND
Figure 7. Setting OS for Output Offset
+5V/+3V
REF
10k
10k
OS
V+
VOUT
DAC
OUT
DGND
AGND
TOLERANCES: 10kΩ ±0.1%
Figure 8. Bipolar Output Circuit
V-
ANALOG OUTPUT
11 1111 1111 11 (00)
+VREF (4095/4096) · 1.638
10 0000 0000 01 (00)
+VREF (2049/4096) · 1.638
10 0000 0000 00 (00)
+VREF (2048/4096) · 1.638
01 1111 1111 11 (00)
+VREF (2047/4096) · 1.638
00 0000 0000 01 (00)
+VREF (1/4096) · 1.638
00 0000 0000 00 (00)
0
Table 3. Bipolar Code Table
(Circuit of Figure 8)
VDD
MAX5174
MAX5176
DAC CONTENTS
MSB
LSB
DAC CONTENTS
MSB
LSB
ANALOG OUTPUT
11 1111 1111 11 (00)
+VREF [(2 · 4095/4096) - 1]
10 0000 0000 01 (00)
+VREF [(2 · 2049/4096) - 1]
10 0000 0000 00 (00)
+VREF [(2 · 2048/4096) - 1]
01 1111 1111 11 (00)
+VREF [(2 · 2047/4096) - 1]
00 0000 0000 01 (00)
+VREF [(2 · 1/4096) - 1]
00 0000 0000 00 00
-VREF
________________________________________________________________________________________13
MAX5174/MAX5176
Offset and Buffer Configurations
The simple circuit of Figure 7 illustrates how to introduce an offset to the output voltage. The amount of offset introduced by a voltage at the OS pin is shown in
the following equation:
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
Using an AC Reference
pins together and connecting that point to the system
analog ground plane. This is useful because if the
DAC’s DGND is connected to the system digital
ground, digital noise may infiltrate the DAC’s analog
portion.
Bypass the power supply with a 4.7µF capacitor in parallel with a 0.1µF capacitor to AGND. Minimize capacitor lead lengths to reduce inductance. If noise
becomes an issue, use shielding and/or ferrite beads to
increase isolation.
To maintain INL and DNL performance as well as gain
drift, it is extremely important to provide the lowest possible reference output impedance at the DAC reference
input pin. INL degrades if the series resistance on REF
pin exceeds 0.1Ω. The same consideration must be
made for the AGND pin.
The MAX5174/MAX5176 accept references with AC
components, as long as the reference voltage remains
between 0 and VDD - 1.4V. Figure 11 shows a technique for applying a sine-wave signal to the reference
input where the AC signal is offset before being applied
to REF. The reference voltage must remain above
AGND.
Power-Supply and Layout Considerations
Wire-wrap boards are not recommended. For optimum
system performance, use printed circuit boards with
separate analog and digital ground planes. Connect
the two ground planes together at the low-impedance
power-supply source. Connect DGND and AGND pins
together at the IC. The best ground connection is
achieved by connecting the DAC’s DGND and AGND
SCLK
SCLK
MAX5174
MAX5176
DIN
SCLK
MAX5174
MAX5176
DOUT
CS
DIN
DOUT
CS
MAX5174
MAX5176
DOUT
DIN
CS
TO OTHER
SERIAL DEVICES
Figure 9. Daisy-Chaining MAX5174/MAX5175 Devices
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
MAX5174
MAX5176
CS
MAX5174
MAX5176
MAX5174
MAX5176
SCLK
SCLK
SCLK
DIN
DIN
DIN
Figure 10. Multiple MAX5174/MAX5176s Sharing Common DIN and SCLK Lines
14
______________________________________________________________________________________
Low-Power, Serial, 12-Bit DACs
with Voltage Output
+5V/+3V
R1
AC
REFERENCE
INPUT
500mVp-p
TRANSISTOR COUNT: 3457
MAX495
R2
VDD
REF
OS
OUT
DAC
AGND
MAX5174
MAX5176
GND
Figure 11. AC Reference Input Circuit
Functional Diagram
CS
PDL
SHDN
VDD AGND DGND
DIN SCLK
SERIAL
CONTROL
DOUT
16-BIT
SHIFT REGISTER
RS
LOGIC
OUTPUT
UPO
OS
DECODE
CONTROL
CLR
MAX5174
MAX5176
INPUT
REGISTER
DAC
REGISTER
DAC
OUT
REF
______________________________________________________________________________________
15
MAX5174/MAX5176
Chip Information
+5V/
+3V
Low-Power, Serial, 12-Bit DACs
with Voltage Output
QSOP.EPS
MAX5174/MAX5176
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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