19-3563; Rev 1; 5/05
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
________________________Applications
MEMS Mirror Servo Control
Industrial Process Control
Automatic Test Equipment
Instrumentation
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5331UCB
0°C to +85°C
64 TQFP
MAX5331UTK*
0°C to +85°C
68 Thin QFN
MAX5332UCB
0°C to +85°C
64 TQFP
MAX5332UTK*
0°C to +85°C
68 Thin QFN
MAX5333UCB
0°C to +85°C
64 TQFP
MAX5333UTK*
0°C to +85°C
68 Thin QFN
*Future product—contact factory for availability.
CL
OUT21
OUT22
OUT24
OUT23
OUT25
AGND
63 62 61 60 59 58
OUT26
64
OUT27
OUT28
OUT29
OUT30
TOP VIEW
OUT31
Pin Configurations
VREF
These devices are controlled through a 20MHz
SPI™/QSPI™/MICROWIRE™-compatible 3-wire serial
interface. Immediate update mode allows any channel’s
output to be updated within 20µs. Burst mode allows
multiple values to be loaded into memory in a single,
high-speed data burst. All channels are updated within
330µs of data being loaded.
Each device features an output clamp and output resistors for filtering. The MAX5331 features a 50Ω output
impedance and is capable of driving up to 250pF of
output capacitance. The MAX5332 features a 500Ω output impedance and is capable of driving up to 10nF of
output capacitance. The MAX5333 features a 1kΩ output impedance and is capable of driving up to 10nF of
output capacitance.
The MAX5331/MAX5332/MAX5333 are available in 12mm
x 12mm, 64-pin TQFP and 10mm x 10mm, 68-pin thin
QFN packages.
AGND
The MAX5331/MAX5332/MAX5333 feature a -4.5V to
+9.2V output voltage range. Other features include a
3.2mV/step resolution, with output linearity error, typically 0.03% of full-scale range (FSR). The 100kHz
refresh rate updates each SHA every 320µs, resulting
in negligible output droop. Remote ground sensing
allows the outputs to be referenced to the local ground
of a separate device.
♦ Integrated 12-Bit DAC and 32-Channel SHA with
SRAM and Sequencer
♦ 32 Voltage Outputs
♦ 0.03% FSR (typ) Output Linearity
♦ 3.2mV Output Resolution
♦ Flexible Output Voltage Range
♦ Remote Ground Sensing
♦ Fast Sequential Loading: 1.3µs per Register
♦ Burst- and Immediate-Mode Addressing
♦ No External Components Required for Setting
Gain and Offset
♦ Integrated Output Clamp Diodes
♦ Three Output-Impedance Options
MAX5331 (50Ω), MAX5332 (500Ω), and
MAX5333 (1kΩ)
CH
The MAX5331/MAX5332/MAX5333 are 12-bit digital-toanalog converters (DACs) with 32 sample-and-hold
(SHA) outputs for applications where a high number of
programmable voltages are required. These devices
include a clock oscillator and a sequencer that updates
the DAC with codes from an internal SRAM. No external
components are required to set offset and gain.
Features
57 56 55 54 53 52 51 50 49
N.C.
1
48 VDD
N.C.
2
47 CH
GS
3
46 VSS
VLDAC
4
45 OUT20
RST
5
44 OUT19
CS
6
43 OUT18
DIN
7
SCLK
8
VLOGIC
42 OUT17
41 OUT16
MAX5331
MAX5332
MAX5333
9
IMMED 10
40 AGND
39 VDD
ECLK 11
38 OUT15
CLKSEL 12
37 OUT14
DGND 13
36 OUT13
VLSHA 14
35 OUT12
AGND 15
34 OUT11
VSS 16
33 CL
VSS
CH
OUT10
OUT9
OUT8
OUT7
OUT6
AGND
OUT5
OUT4
OUT3
OUT1
OUT2
OUT0
CL
VDD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5331/MAX5332/MAX5333
General Description
MAX5331/MAX5332/MAX5333
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ABSOLUTE MAXIMUM RATINGS
VDD to AGND.......................................................-0.3V to +12.2V
VSS to AGND .........................................................-6.0V to +0.3V
VDD to VSS ...........................................................................+15V
VLDAC, VLOGIC, VLSHA to AGND or DGND ..............-0.3V to +6V
REF to AGND............................................................-0.3V to +6V
GS to AGND................................................................VSS to VDD
CL and CH to AGND...................................................VSS to VDD
Logic Inputs to DGND ..............................................-0.3V to +6V
DGND to AGND........................................................-0.3V to +2V
Maximum Current into OUT_ ............................................±10mA
Maximum Current Into Logic Inputs .................................±20mA
Continuous Power Dissipation (TA = +70°C)
64-Pin TQFP (derate 13.3mW/°C above +70°C) ............1066mW
68-Pin Thin QFN (derate 28.6mW/°C above +70°C) ......2285mW
Operating Temperature Range...............................0°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0, RL ≥ 10MΩ, CL = 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Resolution
Output Range
N
12
VOUT_
VSS +
0.75
Offset Voltage
(Note 1)
Bits
VDD 2.4
±15
Code = 4F3 hex
±200
±50
Offset Voltage Tempco
Gain Error
(Note 2)
mV
µV/°C
±1
±5
Gain Tempco
V
%
ppm/°C
Integral Linearity Error
INL
VOUT_ = -3.25V to +7.6V
0.03
0.1
%FSR
Differential Linearity Error
DNL
VOUT_ = -3.25V to +7.6V, monotonicity
guaranteed to 12 bits
±0.5
±1
LSB
Maximum Output Drive Current
IOUT
Sinking and sourcing
±2
MAX5331
35
50
65
MAX5332
350
500
650
MAX5333
700
1000
1300
DC Output Impedance
ROUT
Maximum Capacitive Load
DC Crosstalk
Power-Supply Rejection Ratio
2
PSRR
mA
Ω
MAX5331
250
MAX5332
10
MAX5333
10
Internal oscillator enabled (Note 3)
-90
dB
Internal oscillator enabled
-80
dB
_______________________________________________________________________________________
pF
nF
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0, RL ≥ 10MΩ, CL = 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Sample-and-Hold Settling
(Note 4)
0.08
SCLK Feedthrough
0.5
%
nV•s
fSEQ Feedthrough
0.5
Hold Step
0.25
1
mV
1
300
µV/ms
µVRMS
Droop Rate
VOUT_ = 0 (Note 5)
Output Noise
nV•s
250
REFERENCE INPUT
Input Resistance
7
Reference Input Voltage
VREF
kΩ
2.5
V
GROUND-SENSE INPUT
Input Voltage Range
VGS
Input Bias Current
IGS
GS Gain
-0.5
-0.5V ≤ VGS ≤ 0.5V
(Note 6)
+0.5
-60
0.998
1
V
0
µA
1.002
V/V
DIGITAL-INTERFACE DC CHARACTERISTICS
Input High Voltage
VIH
Input Low Voltage
VIL
2.0
V
Input Current
0.8
V
±1
µA
120
kHz
TIMING CHARACTERISTICS (Figure 2)
Sequencer Clock Frequency
fSEQ
Internal oscillator
External Clock Frequency
fECLK
(Note 7)
SCLK Frequency
fSCLK
80
100
480
kHz
20
MHz
SCLK Pulse-Width High
tCH
15
ns
SCLK Pulse-Width Low
tCL
15
ns
CS-Low to SCLK-High Setup
Time
tCSSO
15
ns
CS-High to SCLK-High Setup
Time
tCSS1
15
ns
SCLK-High to CS-Low Hold Time
tCSH0
10
ns
_______________________________________________________________________________________
3
MAX5331/MAX5332/MAX5333
ELECTRICAL CHARACTERISTICS (continued)
MAX5331/MAX5332/MAX5333
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0, RL ≥ 10MΩ, CL = 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
SCLK-High to CS-High Hold Time
tCSH1
0
ns
DIN to SCLK High Setup Time
tDS
15
ns
DIN to SCLK High Hold Time
tDH
0
RST-to-CS Low
CONDITIONS
MIN
TYP
MAX
UNITS
ns
(Note 8)
500
µs
POWER SUPPLIES
Positive Supply Voltage
VDD
(Note 9)
8.55
10
11.60
V
Negative Supply Voltage
VSS
(Note 9)
-5.25
-4
-2.75
V
14.5
V
5
5.25
V
32
42
mA
Supply Difference
Logic Supply Voltage
VDD - VSS (Note 9)
VLOGIC,
VLDAC,
VLSHA
Positive Supply Current
IDD
Negative Supply Current
ISS
Logic Supply Current
ILOGIC
4.75
-40
-32
mA
(Note 10)
1
1.5
fSCLK = 20MHz (Note 11)
2
3
mA
Note 1: The nominal zero-scale voltage (code = 0) is -4.0535V. The nominal full-scale voltage (code = FFF hex) is +9.0503V. The
output voltage is limited by the output range specification, restricting the usable range of DAC codes. The nominal zeroscale voltage can be achieved when VSS < -4.9V, and the nominal full-scale voltage can be achieved when VDD > +11.5V.
Note 2: Gain is calculated from measurements:
for voltages VDD = 10V and VSS = -4V at codes C00 hex and 4F3 hex
for voltages VDD = 11.6V and VSS = -2.9V at codes FFF hex and 253 hex
for voltages VDD = 9.25V and VSS = -5.25V at codes D4F hex and 0 hex
for voltages VDD = 8.55V and VSS = -2.75V at codes C75 hex and 282 hex
Note 3: Steady-state change in any output with an 8V change in an adjacent output.
Note 4: Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
updates. Tested with an external sequencer clock frequency of 480kHz.
Note 5: External clock mode with the external clock not toggling.
Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F3 hex.
Note 7: The sequencer runs at fSEQ = fECLK / 4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
limited by acceptable droop and update time after a burst-mode update.
Note 8: VDD rise to CS low = 500µs maximum.
Note 9: Guaranteed by gain-error test.
Note 10: The serial interface is inactive. VIH = VLOGIC, VIL = 0.
Note 11: The serial interface is active. VIH = VLOGIC, VIL = 0.
4
_______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
INTEGRAL NONLINEARITY
vs. INPUT CODE
0.06
MAX5331 toc03
0.08
0.04
0.04
DNL (LSB)
0.030
0.025
0.02
0.03
INL (%)
INL (%)
0.05
MAX5331 toc02
0.035
INTEGRAL NONLINEARITY
VS. TEMPERATURE
0.10
MAX5331 toc01
0.040
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
0
-0.02
0.020
0.02
-0.04
-0.06
0.015
0.01
-0.08
0.010
-0.10
1610
2290
INPUT CODE
2970
3650
0
250
930
DIFFERENTIAL NONLINEARITY
VS. TEMPERATURE
0.10
VDD = +8.55V
VSS = -4V
CODE = 4F3 hex
-12
-14
-16
-18
0
35
60
60
CODE = 4F3 hex
EXTERNAL CLOCK MODE
NO CLOCK APPLIED
10
1
0.1
0.01
-15
10
35
60
-40
85
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
GAIN ERROR VS. TEMPERATURE
POSITIVE SUPPLY PSRR
VS. FREQUENCY
NEGATIVE SUPPLY PSRR
VS. FREQUENCY
-80
-70
-50
-40
CODE = C17 hex
OFFSET CODE = 4F3 hex
0
-15
10
35
TEMPERATURE (°C)
60
85
-50
-40
-30
-30
0.01
-70
PSRR (dB)
PSRR (dB)
0.02
-80
-60
-60
0.03
-90
85
MAX5331 toc09
-90
MAX5331 toc07
0.04
85
0.0001
-40
85
100
TEMPERATURE (°C)
0.05
-40
35
0.001
-20
10
10
DROOP RATE vs. TEMPERATURE
-10
0.05
-15
-15
TEMPERATURE (°C)
DROOP RATE (µV/ms)
0.15
-40
-40
MAX5331 toc08
DNL (LSB)
0.20
GAIN ERROR (%)
3650
OFFSET VOLTAGE
OFFSET VOLTAGE (mV)
0.25
2970
VS. TEMPERATURE
MAX5331 toc04
0.30
1610
2290
INPUT CODE
MAX5331 toc06
930
MAX5331 toc05
250
-20
-20
-10
-10
0
0.01
0.1
1
FREQUENCY (kHz)
10
100
0
0.001
0.01
0.1
1
10
100
FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX5331/MAX5332/MAX5333
Typical Operating Characteristics
(VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0, TA = +25°C, unless otherwise noted.)
LOGIC SUPPLY CURRENT
VS. LOGIC INPUT HIGH VOLTAGE
600
500
1000
34
SUPPLY CURRENT (mA)
700
36
MAX5331 toc11
800
SUPPLY CURRENT vs. TEMPERATURE
1200
LOGIC SUPPLY CURRENT (µA)
MAX5331 toc10
900
800
600
400
5.25
28
ISS
26
INTERFACE INACTIVE
0
5.00
30
22
fSCLK = 20MHz
INTERFACE INACTIVE
4.75
IDD
32
24
200
400
20
2.0
5.50
2.5
POSITIVE SETTLING TIME
(8V STEP)
3.0
3.5
4.0
4.5
5.0
-40
-15
10
35
60
LOGIC INPUT HIGH VOLTAGE (V)
TEMPERATURE (°C)
NEGATIVE SETTLING TIME
(8V STEP)
POSITIVE SETTLING TIME
(100mV STEP)
LOGIC SUPLY VOLTAGE (V)
MAX5331 toc14
MAX5331 toc13
85
MAX5331 toc15
3.5V
3.5V
3.5V
ECLK
ECLK
ECLK
MAX5331 toc12
LOGIC SUPPLY CURRENT
vs. LOGIC SUPPLY VOLTAGE
LOGIC SUPPLY CURRENT (µA)
MAX5331/MAX5332/MAX5333
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
0
0
0
5V/div VOUT_
50mV/div
AC-COUPLED
VOUT_
5V/div
VOUT_
1µs/div
1µs/div
NEGATIVE SETTLING TIME
(100mV STEP)
1µs/div
OUTPUT NOISE
MAX5331 toc17
MAX5331 toc16
3.5V
ECLK
0
OUT_
1mV/div
50mV/div
AC-COUPLED
VOUT_
1µs/div
6
250µs/div
_______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
PIN
NAME
FUNCTION
TQFP
THIN QFN
1, 2
1, 2, 17, 34, 51, 68
3
3
GS
4
4
VLDAC
5
5
RST
Reset Input
6
6
CS
Chip-Select Input
7
7
DIN
Serial-Data Input
8
8
SCLK
9
9
VLOGIC
+5V Logic Power Supply
10
10
IMMED
Immediate-Update Mode
11
11
ECLK
12
12
CLKSEL
13
13
DGND
N.C.
No Connection. Not internally connected.
Ground-Sensing Input
+5V DAC Power Supply
Serial-Clock Input
External Sequencer Clock Input
Clock-Select Input
Digital Ground
14
14
VLSHA
+5V Sample-and-Hold Power Supply
15, 25, 40, 55, 62
15, 26, 42, 58, 65
AGND
Analog Ground
16, 32, 46
16, 33, 48
VSS
17, 39, 48
18, 41, 50
VDD
Positive Power Supply
18, 33, 49
19, 35, 52
CL
Output Clamp Low Voltage
19
20
OUT0
Output 0
20
21
OUT1
Output 1
21
22
OUT2
Output 2
22
23
OUT3
Output 3
23
24
OUT4
Output 4
24
25
OUT5
Output 5
26
27
OUT6
Output 6
27
28
OUT7
Output 7
28
29
OUT8
Output 8
29
30
OUT9
Output 9
Negative Power Supply
30
31
OUT10
31, 47, 64
32, 49, 67
CH
Output 10
34
36
OUT11
Output 11
35
37
OUT12
Output 12
36
38
OUT13
Output 13
37
39
OUT14
Output 14
38
40
OUT15
Output 15
41
43
OUT16
Output 16
42
44
OUT17
Output 17
Output Clamp High Voltage
_______________________________________________________________________________________
7
MAX5331/MAX5332/MAX5333
Pin Description
MAX5331/MAX5332/MAX5333
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
TQFP
THIN QFN
43
45
OUT18
Output 18
44
46
OUT19
Output 19
45
47
OUT20
Output 20
50
53
OUT21
Output 21
51
54
OUT22
Output 22
52
55
OUT23
Output 23
53
56
OUT24
Output 24
54
57
OUT25
Output 25
56
59
OUT26
Output 26
57
60
OUT27
Output 27
58
61
OUT28
Output 28
59
62
OUT29
Output 29
60
63
OUT30
Output 30
61
64
Output 31
63
66
OUT31
VREF
Reference Voltage Input
CH
OUT0
ECLK
CLKSEL
CLOCK
SAMPLEAND-HOLD
ARRAY
R
E
G
I
S
T
E
R
SAMPLE
DATA READY
SEQUENCER
OUT31
CL
READ ENABLE
SEQUENTIAL
ADDRESS
LAST
ADDRESS
CS
SCLK
DIN
2: 1
M
U
X
ADDR SELECT
SERIAL
INTERFACE
IMMED
RST
WRITE ENABLE
12 x 32
SRAM
R
E
G
I
S
T
E
R
GAIN AND
OFFSET
CORRECTION
12-BIT
DAC
REF
MAX5331
MAX5332
MAX5333
D[11:0]
Figure 1. Functional Diagram
8
GS
_______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
tCSHO
tCSSO
tCH
tCSS1
tCL
SCLK
tDH
tDS
B23
DIN
B22
B0
Figure 2. Serial-Interface Timing Diagram
Detailed Description
Sample-and-Hold Amplifiers
The MAX5331/MAX5332/MAX5333 contain 32 buffered
SHA circuits with internal hold capacitors. Internal hold
capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. The
MAX5331/MAX5332/MAX5333 provide a very low
1µV/ms droop rate.
Output
The MAX5331/MAX5332/MAX5333 include output buffers
on each channel. The devices contain output resistors in
series with the buffer output (Figure 3) for ease of output
filtering and capacitive load driving stability.
Output loads increase the analog supply current (IDD
and ISS). Excessively loading the outputs drastically
increases power dissipation. Do not exceed the maximum power dissipation specified in the Absolute
Maximum Ratings.
The maximum output voltage range depends on the
analog supply voltages available and the output clamp
voltages (see the Output Clamp section):
(VSS + 0.75V) ≤ VOUT _ ≤ (VDD - 2.4 V)
The devices have a fixed theoretical output range
determined by the reference voltage, gain, and midscale offset. The output voltage for a given input code
is calculated as follows:
code
VOUT _ =
× VREF × 5.2428 4096
(1.6214
× VREF ) + VGS
where code is the decimal value of the DAC input
code, VREF is the reference voltage, and VGS is the
voltage at the ground-sense input. With a 2.5V reference, the nominal end points are -4.0535V and
+9.0503V (Table 1). Note that these are “virtual” internal
end-point voltages and cannot be reached with all
Table 1. Code Table
DAC INPUT CODE
MSB
LSB
1111 1111 1111
NOMINAL OUTPUT
VOLTAGE (V)
1100 0111 0101
6.15
Maximum output with VDD = 8.55V.
1000 0000 0000
2.5
Midscale output.
9.0503
0100 1111 0011
0
0010 1000 0010
-2.0
0000 0000 0000
-4.0535
VREF = +2.5V
Full-scale output.
VOUT_ = 0. All outputs default to this code after power-up.
Minimum output with VSS = -2.75V.
Zero-scale output.
_______________________________________________________________________________________
9
MAX5331/MAX5332/MAX5333
tCSH1
CS
MAX5331/MAX5332/MAX5333
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
combinations of negative and positive power-supply
voltages. The nominal, usable DAC end-point codes for
the selected power supplies can be calculated as:
Lower end-point code = 2048 - ((2.5V - (VSS + 0.75) /
3.2mV) (result ≥ 0)
Upper end-point code = 2048 + ((VDD - 2.4 - 2.5V) /
3.2mV) (result ≤ 4095)
(VCH + 0.7V) ≥ VOUT _ ≥ (VCL
The resistive voltage-divider formed by the output resistor (RO) and the load impedance (RL), scales the output voltage. Determine VOUT_ as follows:
Scaling factor =
Output Clamp
The MAX5331/MAX5332/MAX5333 clamp the output
between two externally applied voltages. Internal
diodes at each channel restrict the output voltage to:
−
0.7V
)
The clamping diodes allow the MAX5331/MAX5332/
MAX5333 to drive devices with restricted input ranges.
The diodes also allow the outputs to be clamped during
power-up or fault conditions. To disable output clamping,
connect CH to VDD and CL to VSS, setting the clamping
voltages beyond the maximum output voltage range.
RL
Serial Interface
RL + RO
VOUT _ = VCHOLD × scaling factor
Ground Sense
The MAX5331/MAX5332/MAX5333 include a groundsense input (GS), which allows the output voltages to
be referenced to a remote ground. The voltage at GS is
added to the output voltage with unity gain. Note that
the resulting output voltage must be within the valid
output voltage range set by the power supplies.
The MAX5331/MAX5332/MAX5333 are controlled by an
SPI-/QSPI-/MICROWIRE-compatible 3-wire interface.
Serial data is clocked into the 24-bit shift register in an
MSB-first format, with the 12-bit DAC data and S3–S0
(all zeros) preceding the 5-bit SRAM address, 2-bit
control, and a fill zero (Figure 4). The input word is
framed by CS. The first rising edge of SCLK after CS
goes low clocks in the MSB of the input word.
VREF
CH
GAIN
AND
OFFSET
12-BIT
DAC
DAC
DATA
RO
OUT_
AV = 1
CHOLD
RL
CL
ONE OF 32 SHA CHANNELS
GS
Figure 3. Analog Block Diagram
DATA
D11 D10
D9
D8
D7
D6
D5
D4
D3
ADDRESS
D2
D1
D0
S3
0
S2
0
S1
0
S0
0
A4
A3
A2
A1
MSB
Figure 4. Input-Word Sequence
10
______________________________________________________________________________________
CONTROL
A0
C1
C0
0
0
LSB
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
MAX5331/MAX5332/MAX5333
Table 2. Channel/Output Selection
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OUT0 selected
OUT1 selected
OUT2 selected
OUT3 selected
OUT4 selected
OUT5 selected
OUT6 selected
OUT7 selected
OUT8 selected
OUT9 selected
OUT10 selected
OUT11 selected
OUT12 selected
OUT13 selected
OUT14 selected
OUT15 selected
OUT16 selected
OUT17 selected
OUT18 selected
OUT19 selected
OUT20 selected
OUT21 selected
OUT22 selected
OUT23 selected
OUT24 selected
OUT25 selected
OUT26 selected
OUT27 selected
OUT28 selected
OUT29 selected
OUT30 selected
1
1
1
1
1
OUT31 selected
When each serial word is complete, the value is stored
in the SRAM at the address indicated and the control
bits are saved. Note that data may be corrupted if CS is
not held low for an integer multiple of 24 bits.
All the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. Their switching threshold is compatible with TTL and most CMOS logic levels.
OUTPUT
Serial-Input Data Format and
Control Codes
The 24-bit serial-input format, shown in Figure 4, comprises 16 bits (D12–D0 and S3–S0 = 0), 5 address bits
(A4–A0), 2 control bits (C1, C0), and a fill zero. The
address code selects the output channel as shown in
Table 2. The control code configures the device as follows:
1) If C1 = 1, immediate-update mode is selected.
If C1 = 0, burst mode is selected.
2) If C0 = 0, the internal sequencer clock is selected. If
C0 = 1, the external sequencer clock is selected.
This must be repeated with each data word to maintain external input.
______________________________________________________________________________________
11
MAX5331/MAX5332/MAX5333
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
The operating modes can also be selected externally
through CLKSEL and IMMED. If the control bit in the
serial word and the external signal conflict, the signal
that is a logic 1 is dominant.
Modes of Operation
The MAX5331/MAX5332/MAX5333 feature three modes
of operation:
• Sequence mode
• Immediate-update mode
• Burst mode
Table 3. Update Mode
UPDATE MODE
UPDATE TIME
Immediate-Update Mode
2/fSEQ
Burst Mode
33/fSEQ
Sequence Mode
Sequence mode is the default operating mode. The
internal sequencer continuously scrolls through the
SRAM, updating each of the 32 SHAs. At each SRAM
address location, the stored 12-bit DAC code is loaded
to the DAC. Once settled, the DAC output is acquired
by the corresponding SHA. Using the internal
sequencer clock, the process typically takes 320µs to
update all 32 SHAs (10µs per channel). Using an external sequencer clock, the update process takes 128
clock cycles (four clock cycles per channel).
Immediate-Update Mode
Immediate-update mode is used to change the contents of a single SRAM location, and update the corresponding SHA output. In immediate-update mode, the
selected output is updated before the sequencer
resumes operation. Select immediate-update mode by
driving either IMMED or C1 high.
The sequencer is interrupted when CS is taken low. The
input word is then stored in the proper SRAM address.
The DAC conversion and SHA sample in progress are
completely transparent to the serial bus activity. The
SRAM location of the addressed channel is then modified with the new data. The DAC and SHA are updated
with the new voltage. The sequencer then resumes
scrolling at the interrupted SRAM address.
This operation can take up to two cycles of the 10µs
sequencer clock. Up to one cycle is needed to allow the
sequencer to complete the operation in progress before
it is freed to update the new channel. An additional
cycle is required to read the new data from memory,
update the DAC, and strobe the sample-and-hold. The
sequencer resumes scrolling from the location at which
it was interrupted. Normal sequencing is suppressed
while loading data, thus preventing other channels from
being refreshed. Under conditions of extremely frequent
immediate updates (i.e., 1000 successive updates), this
can result in unacceptable droop.
Figure 5 shows an example of an immediate-update
operation. In this example, data for channel 20 is
loaded, while channel 7 is being refreshed. The
sequencer operation is interrupted, and no other channels are refreshed as long as CS is held low. Once CS
returns high, and the remainder of an fSEQ period (if
any) has expired, channel 20 is updated to the new
data. Once channel 20 has been updated, the
sequencer resumes normal operation at the interrupted
channel 7.
1/fSEQ
SHA ARRAY
UPDATE
SEQUENCE
1/fSEQ
1
2
3
7
SKIP
20
7
8
9
SHA ARRAY
UPDATE
SEQUENCE
CHANNEL 20
UPDATED
7
SKIP
SKIP SKIP
7
8
INTERRUPTED
CHANNEL REFRESHED
DIN
CS
LOAD MULTIPLE
ADDRESSES
DIN
24-BIT
WORD
Figure 5. Immediate-Update-Mode Timing Example
12
5
33 CYCLES TO UPDATE
ALL CHANNELS
CS
LOAD ADDRESS 20
6
Figure 6. Burst-Mode Timing Example
______________________________________________________________________________________
6
7
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
External Sequencer Clock
An external clock may be used to control the sequencer,
altering the output update rate. The sequencer runs at
1/4 the frequency of the supplied clock (ECLK). The
external clock option is selected by driving either C0 or
CLKSEL high.
When CLKSEL is asserted, the internal clock oscillator
is disabled. This feature allows synchronizing the
sequencer to other system operations, or shutting down
of the sequencer altogether during high-accuracy system measurements. The low 1µV/ms droop of these
devices ensures that no appreciable degradation of the
output voltages occurs, even during extended periods
of time when the sequencer is disabled.
Power-On Reset
A power-on reset (POR) circuit sets all channels to 0V
(code 4F3 hex) in sequence, requiring 320µs. This prevents damage to downstream ICs due to arbitrary reference levels being presented following system power-up.
This same function is available by driving RST low.
During the reset operation, the sequencer is run by the
internal clock, regardless of the state of CLKSEL. The
reset process cannot be interrupted, serial inputs are
ignored until the entire reset process is complete.
Applications Information
Power Supplies and Bypassing
Grounding and power-supply decoupling strongly influence device performance. Digital signals can couple
through the reference input, power supplies, and
ground connection. Proper grounding and layout can
reduce digital feedthrough and crosstalk. At the device
level, a 0.1µF capacitor is required for the VDD, VSS,
and VL_ inputs. They should be placed as close to the
pins as possible. More substantial decoupling at the
board level is recommended and is dependent on the
number of devices on the board (Figure 7).
The MAX5331/MAX5332/MAX5333 have three separate
+5V logic power supplies, VLDAC, VLOGIC, and VLSHA.
VLDAC powers the 12-bit DAC. VLSHA powers the control logic of the SHA array. VLOGIC powers the serial
interface, sequencer, internal clock, and SRAM.
Additional filtering of VLDAC and VLSHA improves the
overall performance of the device.
Chip Information
TRANSISTOR COUNT: 16,229
PROCESS: BiCMOS
______________________________________________________________________________________
13
MAX5331/MAX5332/MAX5333
Burst Mode
Burst mode allows multiple SRAM locations to be
loaded at high speed. During burst mode, the output
voltages are not updated until the data burst is complete and control returns to the sequencer. Select burst
mode by driving both IMMED and C1 low.
The sequencer is interrupted when CS is taken low. All
or part of the memory can be loaded while CS is low.
Each data word is loaded into its specified SRAM
address. The DAC conversion and SHA sample in
progress are completely transparent to the serial bus
activity. When CS is taken high, the sequencer resumes
scrolling at the interrupted SRAM address. New values
are updated when their turn comes up in the sequence.
After burst mode is used, it is recommended that at
least one full sequencer loop (320µs) is allowed to
occur before the serial port is accessed again. This
ensures that all outputs are updated before the
sequencer is interrupted.
Figure 6 shows an example of a burst-mode operation.
As with the immediate-update example, CS falls while
channel 7 is being refreshed. Data for multiple channels is loaded, and no channels are refreshed as long
as CS remains low. Once CS returns high, sequencing
resumes with channel 7 and continues normal refresh
operation. Thirty-three fSEQ cycles are required before
all channels have been updated.
+10V
+5V
0.1µF
0.1µF
VLOGIC
VLDAC
VDD
VLSHA
REF
+2.5V
OUT0
GS
OUT1
CS
DIN
MAX5331
MAX5332
MAX5333
SCLK
IMMED
CLKSEL
ECLK
RST
OUT31
AGND
DGND
VSS
CL
0.1µF
-4V
Figure 7. Typical Operating Circuit
35 CL
36 OUT11
39 OUT14
38 OUT13
37 OUT12
40 OUT15
42 AGND
41 VDD
43 OUT16
44 OUT17
46 OUT19
45 OUT18
49 CH
48 VSS
51 N.C.
50 VDD
TOP VIEW
47 OUT20
Pin Configurations (continued)
CL
OUT21
OUT22
OUT23
52
34 N.C.
53
33 VSS
OUT24
OUT25
AGND
OUT26
OUT27
OUT28
OUT29
OUT30
OUT31
AGND
VREF
56
30 OUT9
57
29 OUT8
54
32 CH
55
31 OUT10
58
28 OUT7
59
27 OUT6
MAX5331
MAX5332
MAX5333
60
61
62
26 AGND
25 OUT5
24 OUT4
23 OUT3
63
64
22 OUT2
65
21 OUT1
AGND 15
VSS 16
N.C. 17
VLSHA 14
12
DGND 13
11
10
9
VLOGIC
IMMED
ECLK
CLKSEL
RST
CS
DIN
SCLK
8
18 VDD
7
68
6
19 CL
N.C.
5
20 OUT0
67
VLDAC 4
66
CH
N.C. 1
N.C. 2
GS 3
MAX5331/MAX5332/MAX5333
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
THIN QFN
14
______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
64L TQFP.EPS
PACKAGE OUTLINE,
64L TQFP, 10x10x1.4mm
21-0083
B
1
2
PACKAGE OUTLINE,
64L TQFP, 10x10x1.4mm
21-0083
B
2
2
______________________________________________________________________________________
15
MAX5331/MAX5332/MAX5333
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
68L QFN THIN.EPS
MAX5331/MAX5332/MAX5333
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
21-0142
C
1
2
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
21-0142
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
