19-0230; Rev 3; 3/11
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
The MAX536/MAX537 combine four 12-bit, voltage-output
digital-to-analog converters (DACs) and four precision
output amplifiers in a space-saving 16-pin package.
Offset, gain, and linearity are factory calibrated to provide
the MAX536’s ±1 LSB total unadjusted error. The
MAX537 operates with ±5V supplies, while the MAX536
uses -5V and +10.8V to +13.2V supplies.
Each DAC has a double-buffered input, organized as
an input register followed by a DAC register. A 16-bit
serial word is used to load data into each input/DAC
register. The serial interface is compatible with either
SPI/QSPI™ or MICROWIRE™, and allows the input and
DAC registers to be updated independently or simultaneously with a single software command. The DAC registers can be simultaneously updated with a hardware
LDAC pin. All logic inputs are TTL/CMOS compatible.
________________________Applications
____________________________Features
♦ Four 12-Bit DACs with Output Buffers
♦ Simultaneous or Independent Control of Four
DACs via a 3-Wire Serial Interface
♦ Power-On Reset
♦ SPI/QSPI and MICROWIRE Compatible
♦ ±1 LSB Total Unadjusted Error (MAX536)
♦ Full 12-Bit Performance without Adjustments
♦ ±5V Supply Operation (MAX537)
♦ Double-Buffered Digital Inputs
♦ Buffered Voltage Output
♦ 16-Pin DIP/SO Packages
______________ Ordering Information
PART
TEMP RANGE
PINPACKAGE
INL
(LSB)
MAX536ACPE+
0°C to +70°C
16 PDIP
Industrial Process Controls
MAX536BCPE+
0°C to +70°C
16 PDIP
Automatic Test Equipment
MAX536ACWE+
0°C to +70°C
16 Wide SO
Digital Offset and Gain Adjustment
MAX536BCWE+
0°C to +70°C
Motion Control Devices
MAX536AEPE+
-40°C to +85°C
16 PDIP
±0.5
MAX536BEPE+
-40°C to +85°C
16 PDIP
±1
MAX536AEWE+
-40°C to +85°C
16 Wide SO
Remote Industrial Controls
Microprocessor-Controlled Systems
________________Functional Diagram
SDO
DECODE
CONTROL
16-BIT
SHIFT
REGISTER
INPUT
REG B
INPUT
REG C
INPUT
REG D
DAC
REG A
DAC
REG B
DAC
REG C
DAC
REG D
CS
SDI
SCK
OUTB 1
16 OUTC
OUTB
OUTA 2
15 OUTD
OUTC
AGND 4
DAC B
VSS 3
DAC C
OUTD
14 VDD
MAX536
MAX537
13 TP
REFAB 5
12 REFCD
DGND 6
11 SDO
LDAC 7
10 SCK
SDI 8
REFCD
±1
+
DAC A
SR
CONTROL
±0.5
TOP VIEW
OUTA
DAC D
±1
__________________Pin Configuration
MAX536/MAX537
INPUT
REG A
MAX536BEWE+
-40°C to +85°C
16 Wide SO
+Denotes a lead(Pb)-free/RoHS-compliant package.
±1
±0.5
Ordering Information continued at end of data sheet.
VDD
DGND
VSS
TP REFAB
AGND
LDAC
16 Wide SO
±0.5
9
CS
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX536/MAX537
_______________General Description
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ABSOLUTE MAXIMUM RATINGS
VDD to AGND or DGND
MAX536 ............................................................-0.3V to +13.2V
MAX537 .................................................................-0.3V to +7V
VSS to AGND or DGND ............................................-7V to +0.3V
SDI, SCK , CS, LDAC, TP, SDO
to AGND or DGND..................................-0.3V to (VDD + 0.3V)
REFAB, REFCD to AGND or DGND ..........-0.3V to (VDD + 0.3V)
OUT_ to AGND or DGND ..........................................VDD to VSS
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) .................842mW
Wide SO (derate 9.52mW/°C above +70°C).................762mW
Operating Temperature Ranges
MAX53_AC_E/BC_E.............................................0°C to +70°C
MAX53_AE_E/BE_E ..........................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX536
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N
12
TA = +25°C
Total Unadjusted Error (Note 1)
TUE
TA = TMIN to TMAX
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Bits
MAX536A
±1.0
MAX536B
±2.0
MAX536AC
±2.0
MAX536BC
±3.0
MAX536AE
±2.5
MAX536BE
±3.5
MAX536A
±0.15
±1
Guaranteed monotonic
±1
TA = +25°C
Offset Error
TA = TMIN to TMAX
MAX536A
±2.5
MAX536B
±5.0
MAX536AC
±5.0
MAX536BC
±7.5
MAX536AE
±6.1
MAX536BE
RL = ∞
Gain Error
VDD Power-Supply Rejection
Ratio
VSS Power-Supply Rejection Ratio
2
±0.50
MAX536B
RL = 5kΩ
MAX536_C/E
LSB
LSB
LSB
mV
±8.5
-0.1
±1.0
-0.6
±1.5
MAX536_M
LSB
±2.0
PSRR
TA = +25°C, 10.8V < VDD < 13.2V
±0.02
±0.125
LSB/V
PSRR
TA = +25°C, -5.5V < VDD < -4.5V
±0.03
±0.30
LSB/V
____________________________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536/MAX537
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MATCHING PERFORMANCE (TA = +25°C)
Total Unadjusted Error
TUE
MAX536A
±1.0
MAX536B
±2.0
Gain Error
Offset Error
Integral Nonlinearity
±0.1
±1.0
MAX536A
±1.2
±2.5
MAX536B
±1.2
±5.0
±0.2
±1.0
INL
LSB
LSB
mV
LSB
REFERENCE INPUT
Reference Input Range
REF
Reference Input Resistance
RREF
0
Code dependent, minimum at code 555
VDD - 4
5
V
kΩ
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth
VREF = 2VP-P
Reference Feedthrough
Input code =
all 0s
Total Harmonic Distortion Plus
Noise
THD+N
700
VREF = 10VP-P at 400Hz
-100
VREF = 10VP-P at 4kHz
-82
VREF = 2.0VP-P at 50kHz
kHz
dB
0.024
%
DIGITAL INPUTS (SDI, SCK, CS, LDAC)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
2.4
V
VIN = 0V or VDD
Input Capacitance (Note 2)
0.8
V
1.0
µA
10
pF
DIGITAL OUTPUT (SDO)
Output Low Voltage
VOL
Output Leakage Current
SDO sinking 5mA
0.13
SDO = 0V to VDD
0.40
V
±10
µA
DYNAMIC PERFORMANCE (RL = 5kΩ, CL = 100pF)
Voltage Output Slew Rate
Output Settling Time
5
V/µs
To ±0.5 LSB of full scale
3
µs
5
nV-s
VREF = 5V
8
nV-s
Digital Feedthrough
Digital Crosstalk (Note 3)
POWER SUPPLIES
Positive Supply Range
VDD
10.8
13.2
V
Negative Supply Range
VSS
-4.5
-5.5
V
Positive Supply Current
(Note 4)
IDD
Negative Supply Current
(Note 4)
ISS
TA = +25°C
8
18
-6
25
-16
TA = TMIN to TMAX
TA = +25°C
TA = TMIN to TMAX
-23
mA
mA
_______________________________________________________________________________________
3
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
20
µs
TIMING CHARACTERISTICS (Note 5)
Internal Power-On Reset
Pulse Width (Note 2)
tPOR
SCK Clock Period
tCP
100
ns
SCK Pulse Width High
tCH
30
ns
SCK Pulse Width Low
tCL
30
ns
CS Fall to SCK Rise
Setup Time
tCSS
20
ns
SCK Rise to CS Rise
Hold Time
tCSH
10
ns
SDI Setup Time
tDS
40
SDI Hold Time
tDH
0
SCK Rise to SDO Valid
Propagation Delay (Note 6)
tDO1
1kΩ pullup on SDO
to VDD, CLOAD = 50pF
SDO high
78
105
SDO low
50
80
SCK Fall to SDO Valid
Propagation Delay (Note 7)
tDO2
1kΩ pullup on SDO
to VDD, CLOAD = 50pF
SDO high
81
110
SDO low
53
85
26
ns
ns
ns
ns
CS Fall to SDO Enable
(Note 8)
tDV
27
45
ns
CS Rise to SDO Disable
(Note 9)
tTR
40
60
ns
SCK Rise to CS Fall Delay
tCS0
Continuous SCK, SCK edge ignored
20
ns
CS Rise to SCK Rise
Hold Time
tCS1
SCK edge ignored
20
ns
LDAC Pulse Width Low
tLDAC
30
ns
CS Pulse Width High
tCSW
40
ns
TUE is specified with no resistive load.
Guaranteed by design.
Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.
All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0 to 5V.
Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pullup.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 8: SDO changes from High-Z state to 90% of final value.
Note 9: SDO rises 10% toward High-Z state.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
4
_______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536/MAX537
ELECTRICAL CHARACTERISTICS—MAX537
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
±0.15
±0.50
UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
12
MAX537A
Bits
MAX537B
±1
Guaranteed monotonic
TA = +25°C
Offset Error
TA = TMIN to TMAX
±1
MAX537A
±3.0
MAX537B
±6.0
MAX537AC
±6.0
MAX537BC
±9.0
MAX537AE
±7.0
MAX537BE
Gain Error
LSB
LSB
mV
±11.0
RL = ∞
-0.3
±1.5
RL = 5kΩ
-0.8
±3.0
LSB
VDD Power-Supply Rejection Ratio
PSRR
TA = +25°C, 4.5V ≤ VDD ≤ 5.5V
±0.01
±0.5
LSB/V
VSS Power-Supply Rejection Ratio
PSRR
TA = +25°C, -5.5V ≤ VSS ≤ -4.5V
±0.02
±0.7
LSB/V
LSB
MATCHING PERFORMANCE (TA = +25°C)
Gain Error
Offset Error
Integral Nonlinearity
±0.1
±1.25
MAX537A
±0.3
±3.0
MAX537B
±0.3
±6.0
±0.35
±1.0
LSB
VDD - 2.2
V
INL
mV
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
REF
RREF
0
Code dependent, minimum at code 555 hex
5
kΩ
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth
VREF = 2VP-P
700
VREF = 10VP-P at
Reference Feedthrough
Input code = all 0s
-100
400Hz
dB
VREF = 10VP-P at
-82
4kHz
Total Harmonic Distortion Plus
Noise
THD+N
kHz
VREF = 850mVP-P at 100kHz
0.024
%
DIGITAL INPUTS (SDI, SCK, CS, LDAC)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
Input Capacitance (Note 2)
2.4
VIN = 0V or VDD
V
0.8
V
1.0
µA
10
pF
_______________________________________________________________________________________
5
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX537 (continued)
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
VDD -
VDD -
0.5
0.25
MAX
UNITS
DIGITAL OUTPUT (SDO)
Output High Voltage
VOH
SDO sourcing 2mA
Output Low Voltage
VOL
SDO sinking 2mA
0.13
V
0.40
V
DYNAMIC PERFORMANCE (RL = 5kΩ, CL = 100pF)
Voltage Output Slew Rate
5
Output Settling Time
To ±0.5 LSB of full scale
V/µs
5
µs
Digital Feedthrough
5
nV-s
Digital Crosstalk (Note 3)
5
nV-s
POWER SUPPLIES
Positive Supply Range
VDD
Negative Supply Range
VSS
Positive Supply Current (Note 4)
IDD
Negative Supply Current (Note 4)
ISS
4.5
-4.5
TA = +25°C
5.5
TA = TMIN to TMAX
5.5
V
-5.5
V
12
16
TA = +25°C
-4.7
TA = TMIN to TMAX
-10
-14
mA
mA
TIMING CHARACTERISTICS (Note 5)
Internal Power-On Reset Pulse
Width (Note 2)
50
tPOR
µs
SCK Clock Period
tCP
100
ns
SCK Pulse Width High
tCH
MAX537_C/E
35
ns
SCK Pulse Width Low
tCL
MAX537_C/E
35
ns
CS Fall to SCK Rise Setup Time
tCSS
MAX537_C/E
40
ns
SCK Rise to CS Rise Hold Time
tCSH
SDI Setup Time
tDS
SDI Hold Time
tDH
SCK Rise to SDO Valid
Propagation Delay (Note 6)
SCK Fall To SDO Valid
Propagation Delay (Note 7)
6
0
MAX537_C/E
40
ns
24
ns
0
ns
tDO1
CLOAD = 50pF, MAX537_C/E
116
200
ns
tDO2
CLOAD = 50pF, MAX537_C/E
123
210
ns
_______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
TYP
MAX
UNITS
CS Fall to SDO Enable
PARAMETER
SYMBOL
tDV
CLOAD = 50pF, MAX537_C/E
CONDITIONS
MIN
75
140
ns
CS Rise to DSO Disable (Note 10)
tTR
CLOAD = 50pF, MAX537_C/E
70
130
ns
SCK Rise to CS Fall Delay
tCSO
Continuous SCK, SCK edge ignored
35
ns
CS Rise to SCK Rise Hold Time
tCS1
SCK edge ignored, MAX537_C/E
35
ns
LDAC Pulse Width High
tLDAC
MAX537_C/E
50
ns
CS Pulse Width High
tCSW
MAX537_C/E
100
ns
Guaranteed by design.
Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.
All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0 to 5V.
Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pullup.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 10: When disabled, SDO is internally pulled high.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
_______________________________________________________________________________________
7
MAX536/MAX537
ELECTRICAL CHARACTERISTICS—MAX537 (continued)
__________________________________________Typical Operating Characteristics
MAX536
(TA = +25°C, unless otherwise noted.)
VDD = +15V
-0.2
10
VDD = +12V
0.200
0.175
0.150
0
-10
-20
-30
-40
0
4
8
12
REFERENCE VOLTAGE (V)
100k
1M
10
10M
RL = 10kΩ, CL = 100pF
0.075
RL = NO LOAD, CL = 0pF
10
0
6
SUPPLY CURRENT (mA)
0.125
-1
-2
-3
-5
0
100
200
10
1
-2
ISS
100
1000
-60
-20
20
60
100
TEMPERATURE (°C)
LOAD (kΩ)
MAX536
REFERENCE FEEDTHROUGH AT 400Hz
MAX536
REFERENCE FEEDTHROUGH AT 4kHz
REFAB,
5V/div
0V
REFAB,
5V/div
OUTA,
100µV/div
OUTA,
200µV/div
0V
500µs/div
8
2
-10
0.1
FREQUENCY (kHz)
INPUT CODE = ALL 0s
IDD
VDD = +15V
VSS = -5V
-6
-4
0.025
200
MAX536
SUPPLY CURRENT vs. TEMPERATURE
MAX536/7-04
1
FULL-SCALE ERROR (LSB)
0.150
10
100
FREQUENCY (kHz)
MAX536
FULL-SCALE ERROR vs. LOAD
MAX1536/7-03b
DAC CODE = ALL 1s
REFAB = 5VP-P
0.050
10k
FREQUENCY (Hz)
0.200
0.100
RL = NO LOAD, CL = 0pF
0.075
0
1k
MAX536
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. REFERENCE FREQUENCY
0.175
0.100
0.025
-50
16
RL = 10kΩ, CL = 100pF
0.125
0.050
--0.6
-1.0
DAC CODE = ALL 1s
REFAB = 10VP-P
MAX536/7-05
0.2
REFAB SWEPT 2VP-P
VOUTA MONITORED
THD + NOISE (%)
INL ERROR (LSB)
0.6
20
RELATIVE OUTPUT (dB)
VSS = -5V
MAX536/7-02
MAX536/7-01
1.0
MAX536
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. REFERENCE FREQUENCY
MAX536
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
MAX1536/7-03
MAX536
INTEGRAL NONLINEARITY
ERROR vs. REFERENCE VOLTAGE
THD + NOISE (%)
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
50µs/div
INPUT CODE = ALL 0s
_______________________________________________________________________________________
140
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536
MAX536
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON)
MAX536
NEGATIVE FULL-SCALE SETTLING TIME
(ALL BITS ON TO ALL BITS OFF)
CS,
5V/div
CS,
5V/div
OUTA,
5V/div
OUTA,
2V/div
5µs/div
OUTA,
5mV/div
1µs/div
VDD = +15V, VSS = -5V, REFAB = 5V, CL = 100pF, RL = 10kΩ
VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10kΩ
MAX536
POSITIVE FULL-SCALE SETTLING TIME
(ALL BITS OFF TO ALL BITS ON)
MAX536
DIGITAL FEEDTHROUGH
CS,
5V/div
SCK,
5V/div
OUTA,
5V/div
OUTA,
-10V OFFSET
5mV/div
OUTA,
AC-COUPLED,
10mV/div
1µs/div
VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10kΩ
VDD = +15V, VSS = -5V, REFAB = 10V, CS = HIGH,
DIN TOGGLING AT 1⁄2 THE CLOCK RATE,
OUTA = 5V
_______________________________________________________________________________________
9
MAX536/MAX537
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX537
MAX537
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
0.5
0
-0.5
-1.0
REFAB = 2.5VP-P
0.175
0.150
0
THD + NOISE (%)
RELATIVE OUTPUT (dB)
-10
-20
0.125
RL = 10kΩ, CL = 100pF
0.100
0.075
RL = NO LOAD, CL = 0pF
-30
0.050
-1.5
-40
-2.0
-50
0
1
2
3
4
5
0.025
0
1k
10k
100k
1M
10M
10
100
200
VREF (V)
FREQUENCY (Hz)
FREQUENCY (kHz)
MAX537
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX537
FULL-SCALE ERROR vs. LOAD
MAX537
SUPPLY CURRENT vs. TEMPERATURE
0.125
0.100
RL = 10kΩ, CL = 100pF
0.075
0.050
3
SUPPLY CURRENT (mA)
0.150
5
MAX536/7-11
1
FULL-SCALE ERROR (LSB)
REFAB = 1VP-P
0.175
2
MAX1536/7-09
0.200
MAX536/7-10
INL ERROR (LSB)
1.0
REFAB SWEPT 2VP-P
VOUTA MONITORED
10
0.200
MAX536/7-07
VDD = +5V
VSS = -5V
1.5
20
MAX536/7-06
2.0
MAX537
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX1536/7-14
MAX537
INTEGRAL NONLINEARITY
ERROR vs. REFERENCE VOLTAGE
THD + NOISE (%)
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
0
-1
-2
IDD
VDD = +5V
VSS = -5V
1
-1
ISS
-3
-3
0.025
RL = NO LOAD, CL = 0pF
-4
0
10
100
200
-5
0.1
1
10
100
1000
-60
LOAD (kΩ)
FREQUENCY (kHz)
-20
20
REFAB,
1V/div
REFAB,
1V/div
0V
0V
OUTA,
AC-COUPLED,
100µV/div
OUTA,
AC-COUPLED,
100µV/div
50µs/div
500µs/div
10
100
MAX537
REFERENCE FEEDTHROUGH AT 4kHz
MAX537
REFERENCE FEEDTHROUGH AT 400Hz
INPUT CODE = ALL 0s
60
TEMPERATURE (°C)
INPUT CODE = ALL 0s
______________________________________________________________________________________
140
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX537
MAX537
NEGATIVE FULL-SCALE SETTLING TIME
(ALL BITS ON TO ALL BITS OFF)
MAX537
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON)
CS,
5V/div
CS,
5V/div
OUTA,
5mV/div
OUTA,
1V/div
5µs/div
1µs/div
VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ
VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ
MAX537
POSITIVE FULL-SCALE SETTLING TIME
(ALL BITS OFF TO ALL BITS ON)
MAX537
DIGITAL FEEDTHROUGH
1µs/div
VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ
CS,
5V/div
SCK,
5V/div
OUTA,
5mV/div
OUTA,
AC-COUPLED,
20mV/div
100ns/div
VDD = +5V, VSS = -5V, REFAB = 2.5V, CS = HIGH,
DIN TOGGLING AT 1⁄2 THE CLOCK RATE,
OUTA = 1.25V
______________________________________________________________________________________
11
MAX536/MAX537
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1
OUTB
DAC B Output Voltage
2
OUTA
DAC A Output Voltage
3
VSS
Negative Power Supply
4
AGND
Analog Ground
5
REFAB
Reference Voltage Input for DAC A and DAC B
6
DGND
Digital Ground
7
LDAC
Load DAC Input (active low). Driving this asynchronous input low transfers the contents of all input
registers to their respective DAC registers.
8
SDI
Serial Data Input. Data is shifted into an internal 16-bit shift register on SCK's rising edge.
9
CS
Chip-Select Input (active low). A low level on CS enables the input shift register and SDO.
On CS’s rising edge, data is latched into the appropriate register(s).
10
SCK
Shift Register Clock Input
11
SDO
Serial Data Output. SDO is the output of the internal shift register. SDO is enabled when CS is low.
For the MAX536, SDO is an open-drain output. For the MAX537, SDO has an active pullup to VDD.
12
REFCD
Reference Voltage Input for DAC C and DAC D
13
TP
Test Pin. Connect to VDD for proper operation.
14
VDD
Positive Power Supply
15
OUTD
DAC D Output Voltage
16
OUTC
DAC C Output Voltage
_______________Detailed Description
The MAX536/MAX537 contain four 12-bit voltage-output
DACs that are easily addressed using a simple 3-wire
serial interface. They include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input composed of an input register and a DAC register
(see the Functional Diagram on the front page).
The DACs are “inverted” R-2R ladder networks that
convert 12-bit digital inputs into equivalent analog output voltages in proportion to the applied reference-voltage inputs. DAC A and DAC B share the REFAB reference input, while DAC C and DAC D share the REFCD
reference input. The two reference inputs allow different
full-scale output voltage ranges for each pair of DACs.
Figure 1 shows a simplified circuit diagram of one of
the four DACs.
Reference Inputs
The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets
the full-scale output voltage for its two corresponding DACs. The REFAB/REFCD voltage range is 0V to
(VDD - 4V) for the MAX536 and 0V to (VDD - 2.2V) for the
MAX537. The output voltages VOUT_ are represented by
12
R
2R
2R
D0
R
R
2R
2R
D9
D10
VOUT
2R
D11
REF
AGND
SHOWN FOR ALL 1s ON DAC
Figure 1. Simplified DAC Circuit Diagram
a digitally programmable voltage source as:
VOUT_ = NB (VREF)/4096
where NB is the numeric value of the DAC’s binary input
code (0 to 4095) and VREF is the reference voltage.
______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
is 5µs when loaded with 5kΩ in parallel with 100pF
(loads less than 5kΩ degrade performance).
Output dynamic responses and settling performances
of the MAX536/MAX537 output amplifier are shown in
the Typical Operating Characteristics.
The REFAB and REFCD reference inputs have a 5kΩ
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance becomes 2.5kΩ.
The reference input capacitance is also code dependent and typically ranges from 125pF to 300pF.
The MAX536/MAX537’s 3-wire or 4-wire serial interface is
compatible with both MICROWIRE (Figure 2) and
SPI/QSPI (Figure 3). In Figures 2 and 3, LDAC can be tied
either high or low for a 3-wire interface, or used as the
fourth input with a 4-wire interface. The connection
between SDO and the serial-interface port is not necessary, but may be used for data echo. (Data held in the
shift register of the MAX536/MAX537 can be shifted out
of SDO and returned to the microprocessor for data verification; data in the MAX536/MAX537 input/DAC registers cannot be read.)
With a 3-wire interface (CS, SCK, SDI) and LDAC tied
high, the DACs are double-buffered. In this mode,
depending on the command issued through the serial
interface, the input register(s) may be loaded
without affecting the DAC register(s), the DAC register(s)
can be loaded directly, or all four DAC registers may be
simultaneously updated from the input registers. With a 3wire interface (CS, SCK, SDI) and LDAC tied low (Figure
Output Buffer Amplifiers
All MAX536/MAX537 voltage outputs are internally
buffered by precision unity-gain followers with a typical
slew rate of 5V/µs for the MAX536 and 3V/µs for the
MAX537.
With a full-scale transition at the MAX536 output (0 to
8V or 8V to 0), the typical settling time to ±0.5 LSB is
3µs when loaded with 5kΩ in parallel with 100pF (loads
less than 5kΩ degrade performance).
With a full-scale transition at the MAX537 output (0 to
2.5V or 2.5V to 0), the typical settling time to ±0.5 LSB
Serial-Interface Configurations
5V
5V
†RP
1kΩ
MAX536
MAX537
†RP
1kΩ
SCK
SK
SDI
SO
SDO*
SI*
CS
I/O
LDAC**
I/O
SDO*
MICROWIRE
PORT
MAX536
MAX537
MISO*
SDI
MOSI
SCK
SCK
CS
I/O
LDAC**
I/O
SS
SPI/QSPI
PORT
CPOL = 0, CPHA = 0
*THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
*THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
†THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO VDD,
SO RP IS NOT NECESSARY.
Figure 2. Connections for MICROWIRE
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
†THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO VDD,
SO RP IS NOT NECESSARY.
Figure 3. Connections for SPI/QSPI
_______________________________________________________________________________________
13
MAX536/MAX537
The input impedance at each reference input is code
dependent, ranging from a low value of typically 6kΩ
(with an input code of 0101 0101 0101) to a high value
of 60kΩ (with an input code of 0000 0000 0000). Since
the input impedance at the reference pins is code
dependent, load regulation of the reference source is
important.
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
;;; ;;
; ;;;;
CS
COMMAND
EXECUTED
SCK
1
8
9
16
SDI
..........D2 D1 D0
D15 D14 D13..........
MSB
LSB
SDO
...........Q0
Q15..........
MSB FROM
PREVIOUS WRITE
LSB FROM
PREVIOUS WRITE
Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or VDD)
CS
INPUT REGISTER(S)
UPDATED
SCK
1
8
9
16
SDI
.......... D2 D1 D0
D15 D14 D13 ..........
MSB
LSB
SDO
Q15..........
.......... Q0
MSB FROM
PREVIOUS WRITE
LSB FROM
PREVIOUS WRITE
LDAC
DACs
UPDATED
Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC
tCSW
CS
tCSS
tCSO
tCL
tCP
tCH
tCSH
tCSI
SCK
tDS
tDH
SDI
tDV
SDO
tDO1
tDO2
tTR
LDAC*
*USE OF LDAC IS OPTIONAL
tLDAC
Figure 6. Detailed Serial-Interface Timing Diagram
14
______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Serial-Interface Description
The MAX536/MAX537 require 16 bits of serial data. Data is
sent MSB first and can be sent in two 8-bit packets or one
16-bit word (CS must remain low until 16 bits are transferred). The serial data is composed of two DAC address
bits (A1, A0), two control bits (C1, C0), and the 12 data bits
D11…D0 (Figure 7). The 4-bit address/control code determines the following: 1) the register(s) to be updated and/or
the status of the input and DAC registers (i.e., whether they
are in transparent or latch mode), and 2) the edge on which
data is clocked out of SDO.
Figure 6 shows the serial-interface timing requirements. The
chip-select pin (CS) must be low to enable the DAC’s serial
interface. When CS is high, the interface control circuitry is
disabled and the serial data output pin (SDO) is driven high
(MAX537) or is a high-impedance open drain (MAX536). CS
must go low at least tCSS before the rising serial clock (SCK)
edge to properly clock in the first bit. When CS is low, data is
clocked into the internal shift register via the serial data input
pin (SDI) on SCK’s rising edge. The maximum guaranteed
clock frequency is 10MHz. Data is latched into the appropriate MAX536/MAX537 input/DAC registers on CS’s rising
edge.
MSB ..................................................................................LSB
16 Bits of Serial Data
Address
Bits
A1
A0
Control
Bits
C1
4 Address/
Control Bits
C0
Data Bits
MSB.............................................LSB
D11................................................D0
12 Data Bits
Figure 7. Serial-Data Format (MSB Sent First)
Interface timing is optimized when serial data is clocked out
of the microcontroller/microprocessor on one clock edge
and clocked into the MAX536/MAX537 on the other edge.
Table 1 lists the serial-interface programming commands.
For certain commands, the 12 data bits are “don’t cares”.
The programming command Load-All-DACs-From-ShiftRegister allows all input and DAC registers to be simultaneously loaded with the same digital code from the input shift
register. The NOP (no operation) command allows the register contents to be unaffected and is useful when the
MAX536/MAX537 are configured in a daisy-chain (see the
Daisy-Chaining Devices section). The command to change
the clock edge on which serial data is shifted out of the
MAX536/MAX537 SDO pin also loads data from all input registers to their respective DAC registers.
Serial-Data Output
The serial-data output, SDO, is the internal shift register’s
output. The MAX536/MAX537 can be programmed so that
data is clocked out of SDO on SCK’s rising (Mode 1) or
falling (Mode 0) edge . In Mode 0, output data at SDO lags
input data at SDI by 16.5 clock cycles, maintaining compatibility with MICROWIRE, SPI/QSPI, and other serial interfaces.
In Mode 1, output data lags input data by 16 clock cycles.
On power-up, SDO defaults to Mode 1 timing.
For the MAX536, SDO is an open-drain output that should be
pulled up to +5V. The data sheet timing specifications for
SDO use a 1kΩ pullup resistor. For the MAX537, SDO is a
complementary output and does not require an external
pullup.
Test Pin
The test pin (TP) is used for pre-production analysis of the IC.
Connect TP to VDD for proper MAX536/MAX537 operation.
Failure to do so affects DAC operation.
Daisy-Chaining Devices
Any number of MAX536/MAX537s can be daisy-chained by
connecting the SDO pin of one device (with a pullup resistor,
if appropriate) to the SDI pin of the following device in the
chain (Figure 8).
Since the MAX537’s SDO pin has an internal active pullup,
the SDO sink/source capability determines the time required
to discharge/charge a capacitive load. Refer to the serial
data out V OH and V OL specifications in the Electrical
Characteristics.
______________________________________________________________________________________
15
MAX536/MAX537
4), the DAC registers remain transparent. Any time an
input register is updated, the change appears at the DAC
output with the rising edge of CS.
The 4-wire interface (CS, SCK, SDI, LDAC) is similar to
the 3-wire interface with LDAC tied high, except LDAC is
a hardware input that simultaneously and asynchronously
loads all DAC registers from their respective input registers when driven low (Figure 5).
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
D11…D0
LDAC
FUNCTION
A1
A0
C1
C0
0
0
0
1
12-bit DAC data
1
Load DAC A input register; DAC output unchanged.
0
1
0
1
12-bit DAC data
1
Load DAC B input register; DAC output unchanged.
1
0
0
1
12-bit DAC data
1
Load DAC C input register; DAC output unchanged.
1
1
0
1
12-bit DAC data
1
Load DAC D input register; DAC output unchanged.
0
0
1
1
12-bit DAC data
1
Load input register A; all DAC registers updated.
0
1
1
1
12-bit DAC data
1
Load input register B; all DAC registers updated.
1
0
1
1
12-bit DAC data
1
Load input register C; all DAC registers updated.
1
1
1
1
12-bit DAC data
1
Load input register D; all DAC registers updated.
X
0
0
0
12-bit DAC data
X
Load all DACs from shift register.
X
1
0
0
XXXXXXXXXXXX
X
No operation (NOP)
0
X
1
0
XXXXXXXXXXXX
1
Update all DACs from their respective input registers.
1
1
1
0
XXXXXXXXXXXX
X
Mode 1 (default condition at power-up), DOUT clocked out on
SCK’s rising edge. All DACs updated from their respective
input registers.
1
0
1
0
XXXXXXXXXXXX
X
Mode 0, DOUT clocked out on SCK’s falling edge. All DACs
updated from their respective input registers.
0
0
X
1
12-bit DAC data
0
Load DAC A input register; DAC A is immediately updated.
0
1
X
1
12-bit DAC data
0
Load DAC B input register; DAC B is immediately updated.
1
0
X
1
12-bit DAC data
0
Load DAC C input register; DAC C is immediately updated.
1
1
X
1
12-bit DAC data
0
Load DAC D input register; DAC D is immediately updated.
“X” = Don’t Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high,
the DAC registers are latched.
When daisy-chaining MAX536s, the delay from CS
low to SCK high (tCSS) must be the greater of:
tDV + tDS
or
tTR + tRC + tDS - tCSW
where tRC is the time constant of the external pullup resistor
(Rp) and the load capacitance (C) at SDO. For tRC < 20ns,
tCSS is simply tDV + tDS. Calculate tRC from the following
equation:
VPULLUP
tRC = Rp (C) ln
VPULLUP - 2.4V
[(
)]
where VPULLUP is the voltage to which the pullup resistor is
connected.
16
Additionally, when daisy-chaining devices, the maximum
clock frequency is limited to:
1
fSCK(max) = ——————————————
2 (tDO + tRC - 38ns + tDS)
For example, with t RC = 23ns (5V ±10% supply with
Rp = 1kΩ and C = 30pF), the maximum clock frequency is
8.7MHz.
Figure 9 shows an alternate method of connecting several
MAX536/MAX537s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy-chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is
required for each IC.
______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
+5V
RP*
1kΩ
+5V
RP*
1kΩ
RP*
1kΩ
MAX536
MAX536
MAX536
SCK
SCK MAX537
SCK MAX537
SCK MAX537
DIN
SDI
CS
CS
SDO
SDO
SDI
MAX536/MAX537
+5V
CS
SDI
SDO
CS
TO OTHER
SERIAL DEVICES
* THE MAX537 HAS AN ACTIVE INTERNAL PULLUP, SO RP IS NOT NECESSARY.
Figure 8. Daisy-Chaining MAX536/MAX537s with a 3-Wire Serial Interface
DIN
SCK
LDAC
CS1
TO OTHER
SERIAL DEVICES
CS2
CS3
CS
CS
CS
LDAC
LDAC
LDAC
MAX536
MAX536
MAX536
SCK MAX537
SCK MAX537
SCK MAX537
SDI
SDI
SDI
Figure 9. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3… are
driven separately, thus controlling which data are written to devices 1, 2, 3…
______________________________________________________________________________________
17
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
__________Applications Information
Interfacing to the M68HC11*
PORT D of the 68HC11 supports SPI. The four registers
used for SPI operation are the Serial Peripheral Control
Register, the Serial Peripheral Status Register, the Serial
Peripheral Data I/O Register, and PORT D’s Data Direction
Register. These registers have a default starting location of
$1000.
On reset, the PORT D register (memory location $1008) is
cleared and bits 5-0 are configured as general-purpose
inputs. Setting bit 6 (SPE) of the Serial Peripheral Control
Register (SPCR) configures PORT D for SPI as follows:
BIT
7
6
NAME
–
–
5
4
SS
3
2
SCK MOSI MISO
1
0
TXD
RXD
Bits 6 and 7 are not used. Writes to these bits are ignored.
The PORT D Data Direction Register (DDRD) determines whether the port bits are inputs or outputs. Its
configuration is shown below:
BIT
7
6
NAME
–
–
5
4
3
2
1
0
DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
Setting DDD_ = 0 configures the port bit as an input, while
setting DDD_ = 1 configures the port bit as an output. Writes
to bits 6 and 7 have no effect.
In SPI mode with MSTR = 1, when a PORT D bit is expected
to be an input (SS, MISO, RXD), the corresponding DDRD bit
(DDD_) is ignored. If the bit is expected to be an output
(SCK, MOSI, TXD), the corresponding DDRD bit must be
set for the bit to be an output.
Table 2. Serial Peripheral Control-Register Definitions
NAME
DEFINITION
SPIE
Serial Peripheral Interrupt Enable. Clearing SPIE disables the SPI hardware-interrupt request; the SPSR is polled to
determine when an SPI data transfer is complete. Setting SPIE requests a hardware interrupt when the Serial Peripheral
Status Register’s SPIF bit or MODF bit is set.
SPE
Setting SPE (Serial Peripheral System Enable) configures PORT D for SPI. Clearing SPE configures the port as a generalpurpose I/O port.
DWOM
When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary.
MSTR
Master/Slave select option
CPOL
Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the
clock idles low.
CPHA
Determines the clock phase.
SPI Clock-Rate Select
SPR1/0
SPR1
SPR0
0
0
µP clock divided by 2
0
1
µP clock divided by 4
1
0
µP clock divided by 16
1
1
µP clock divided by 32
Table 3. Serial Peripheral Status-Register Definitions
NAME
SPIF
DEFINITION
SPIF is set when an SPI data transfer is complete. It is cleared by reading the SPSR and then accessing the SPDR.
WCOL
The Write Collision flag is set when a write to the SPDR occurs while a data transfer is in progress. It is cleared by reading the SPSR and then accessing the SPDR.
MODF
The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the “master” controller
has its SS line (PORT D) pulled low, and cleared by reading the SPSR followed by a write to the SPCR.
*M68HC11 is a Motorola microcontroller. General information about the device was obtained from M68HC11 technical manuals.
18
______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536/MAX537
Table 4. M68HC11 Programming Code
______________________________________________________________________________________
19
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
SS is an input intended for use in a multimaster environment. However, SS or unused PORT D bit RXD, TXD, or
possibly MISO (if DAC readback is not used) should be
configured as a general-purpose output and used as CS by
setting the appropriate Data Direction Register bit.
The SPCR configuration (memory location $1028) is shown
below:
BIT
7
6
5
4
3
2
1
0
NAME
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0
SETTING AFTER RESET
0
0
0
0
0
U*
1
U*
SETTING FOR TYPICAL SPI COMMUNICATION
0
1
0
1
0
0
0**
1**
Unipolar Output
For a unipolar output, the output voltages and the reference
inputs are the same polarity. Figure 10 shows the
MAX536/MAX537 unipolar output circuit, which is also the typical operating circuit. Table 5 lists the unipolar output codes.
Bipolar Output
The MAX536/MAX537 outputs can be configured for
bipolar operation using Figure 11’s circuit. One op amp
and two resistors are required per DAC. With R1 = R2:
VOUT = VREF [(2NB/4096) - 1]
where NB is the numeric value of the DAC’s binary input
code. Table 6 shows digital codes and corresponding
output voltages for Figure 11’s circuit.
Table 5. Unipolar Code Table
DAC CONTENTS
MSB
LSB
*U = Unknown
**Depends on µP clock frequency.
ANALOG OUTPUT
Always configure the 68HC11 as the “master” controller
and the MAX536/MAX537 as the “slave” device.
1111
1111
1111
4095
+VREF ( ——— )
4096
When MSTR = 1 in the SPCR, a write to the Serial
Peripheral Data I/O Register (SPDR), located at memory
location $102A, initiates the transmission/reception of
data. The data transfer is monitored and the appropriate flags are set in the Serial Peripheral Status
Register (SPSR).
1000
0000
0001
2049
+VREF ( ——— )
4096
1000
0000
0000
2048
+VREF
+VREF ( ——— ) = ————
4096
2
0111
1111
1111
2047
+VREF ( ——— )
4096
0000
0000
0001
1
+VREF ( ——— )
4096
0000
0000
0000
0V
The SPSR configuration is shown below:
BIT
7
6
NAME
SPIF WCOL
5
4
3
2
1
0
–
MODF
–
–
–
–
0
0
0
0
RESET CONDITIONS
0
0
0
0
An example of 68HC11 programming code for a
two-byte SPI transfer to the MAX536/MAX537 is given in
Table 4. SS is used for CS, the high byte of MAX536/
MAX537 digital data is stored in memory location $0100,
and the low byte is stored in memory location $0101.
Interfacing to Other Controllers
When using MICROWIRE, refer to the section on Interfacing to the M68HC11 for guidance, since MICROWIRE
can be considered similar to SPI when CPOL = 0 and
CPHA = 0. When interfacing to Intel’s 80C51/80C31
microcontroller family, use bit-pushing to configure a
desired port as the MAX536/MAX537 interface port. Bitpushing involves arbitrarily assigning I/O port bits as
interface control lines, and then writing to the port each
time a signal transition is required.
Table 6. Bipolar Code Table
DAC CONTENTS
MSB
LSB
2047 )
+VREF ( ———
2048
1111
1111
1111
1000
0000
0001
1000
0000
0000
0111
1111
1111
1 )
-VREF ( ———
2048
0000
0000
0001
2047 )
-VREF ( ———
2048
0000
0000
0000
2048 ) = -V
-VREF ( ———
REF
2048
NOTE: 1 LSB = (VREF) (
20
ANALOG OUTPUT
1 )
+VREF ( ———
2048
0V
1
)
4096
______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
5
+12V (+5V)
REFERENCE INPUTS
12
REFAB
MAX536/MAX537
MAX536
MAX537
13
14
MAX536
MAX537
TP
VDD
REFCD
R1
2
DAC A
R2
VREF
OUTA
+12V (+5V)
1
DAC B
OUTB
VOUT
16
DAC C
OUTC
DAC
OUTPUT
–5V
15
DAC D
VSS
AGND
4
3
-5V
R1 = R2 = 10kΩ 0.1%
OUTD
DGND
6
NOTES: ( ) ARE FOR MAX537.
VREF IS THE SELECTED REFERENCE INPUT FOR THE MAX536/MAX537.
NOTE: ( ) ARE FOR MAX537.
Figure 10. Unipolar Output Circuit
Figure 11. Bipolar Output Circuit
+12V
(+5V)
+12V (+5V)
AC
15kΩ
REFERENCE
INPUT
5
+4V (+750mV)
-4V
(-750mV)
13
REFAB
5
10kΩ
13
TP
REFAB
14
VDD
TP
14
VDD
+
VIN
2
DAC A
-
OUTA
1
DAC B
OUTB
4
MAX536/MAX537
VSS
3
-5V
NOTES: ( ) ARE FOR MAX537.
DIGITAL INPUTS NOT SHOWN.
Figure 12. AC Reference Input Circuit
AGND
4
+
DGND
6
VBIAS
-
AGND
MAX536/MAX537
VSS
3
DGND
6
-5V
NOTES: ( ) ARE FOR MAX537.
DIGITAL INPUTS NOT SHOWN.
Figure 13. AGND Bias Circuit
______________________________________________________________________________________
21
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536/MAX537
Offsetting AGND
AGND can be biased from DGND to the reference voltage
to provide an arbitrary nonzero output voltage for a zero
input code (Figure 13). The output voltage VOUTA is:
3
VOUTA = VBIAS + NB (VIN)
VSS
MAX536
MAX537
1N5817
4
AGND
where VBIAS is the positive offset voltage (with respect
to DGND) applied to AGND, and NB is the numeric
value of the DAC’s binary input code. Since AGND is
common to all four DACs, all outputs will be offset by
VBIAS in the same manner. As the voltage at AGND
increases, the DAC’s resolution decreases because its
full-scale voltage swing is effectively reduced. AGND
should not be biased more negative than DGND.
Power-Supply Considerations
Figure 14. When VSS and VDD cannot be sequenced, tie a
Schottky diode between VSS and AGND.
Using an AC Reference
In applications where the reference has AC signal components, the MAX536/MAX537 have multiplying capability
within the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to the
reference input where the AC signal is offset before being
applied to REFAB/REFCD. The reference voltage must
never be more negative than DGND.
The MAX536’s total harmonic distortion plus noise
(THD+N) is typically less than 0.012%, given a 5VP-P signal
swing and input frequencies up to 35kHz, or given a 2VP-P
swing and input frequencies up to 50kHz. The typical -3dB
frequency is 700kHz as shown in the Typical Operating
Characteristics graphs.
For the MAX537, with an input signal amplitude of
0.85mVP-P, THD+N is typically less than 0.024% with a
5kΩ load in parallel with 100pF and input frequencies up
to 100kHz, or with a 2kΩ load in parallel with 100pF and
input frequencies up to 95kHz.
22
On power-up, VSS should come up first, VDD next, then
REFAB or REFCD. If supply sequencing is not possible,
tie an external Schottky diode between VSS and AGND
as shown in Figure 14. On power-up, all input and DAC
registers are cleared (set to zero code) and SDO is in
Mode 0 (serial data is shifted out of SDO on the clock’s
rising edge).
For rated MAX536 performance, V DD should be 4V
higher than REFAB/REFCD and should be between
10.8V and 13.2V. When using the MAX537, VDD should
be at least 2.2V higher than REFAB/REFCD and should
be between 4.75V and 5.5V. Bypass both VDD and VSS
with a 4.7µF capacitor in parallel with a 0.1µF capacitor
to AGND. Use short lead lengths and place the bypass
capacitors as close to the supply pins as possible.
Grounding and Layout Considerations
Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest quality ground available.
Good PCB ground layout minimizes crosstalk between
DAC outputs, reference inputs, and digital inputs.
Reduce crosstalk by keeping analog lines away from
digital lines. Wire-wrapped boards are not recommended.
______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
PART
TEMP RANGE
PINPACKAGE
INL
(LSB)
±0.5
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
MAX537ACPE+
0°C to +70°C
16 PDIP
MAX537BCPE+
0°C to +70°C
16 PDIP
MAX537ACWE+
0°C to +70°C
16 Wide SO
±0.5
MAX537BCWE+
0°C to +70°C
16 Wide SO
±1
PACKAGE
TYPE
MAX537AEPE+
-40°C to +85°C
16 PDIP
±0.5
MAX537BEPE+
-40°C to +85°C
16 PDIP
±1
MAX537AEWE+
-40°C to +85°C
16 Wide SO
±0.5
MAX537BEWE+
-40°C to +85°C
16 Wide SO
±1
±1
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 PDIP
P16+9
21-0043
—
16 SO
W16+7
21-0042
90-0107
+Denotes a lead(Pb)-free/RoHS-compliant package.
______________________________________________________________________________________
23
MAX536/MAX537
Ordering Information (continued)
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Revision History
REVISION
NUMBER
REVISION
DATE
0
1/94
Initial release
3/11
Removed dice and ceramic SB packages and changed voltage supply
specifications
3
DESCRIPTION
PAGES
CHANGED
—
1–7, 13, 21, 22, 23
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
工商网监
湘ICP备2023018690号
