EVALUATION KIT AVAILABLE
MAX5391/MAX5393
General Description
The MAX5391/MAX5393 dual 256-tap, volatile, lowvoltage linear taper digital potentiometers offer three
end-to-end resistance values of 10kΩ, 50kΩ, and 100kΩ.
Operating from a single +1.7V to +5.5V power supply,
these devices provide a low 35ppm/°C end-to-end temperature coefficient. The devices feature an SPI interface.
The small package size, low supply voltage, low supply current, and automotive temperature range of the
MAX5391/MAX5393 make the devices uniquely suitable
for the portable consumer market and battery backup
industrial applications.
The MAX5391/MAX5393 include two digital potentiometers in a voltage-divider configuration. The MAX5391/
MAX5393 are specified over the -40°C to +125°C automotive temperature range and are available in a 16-pin,
3mm x 3mm TQFN and a 14-pin TSSOP package,
respectively.
Applications
●●
●●
●●
●●
●●
Low-Voltage Battery Applications
Portable Electronics
Mechanical Potentiometer Replacement
Offset and Gain Control
Adjustable Voltage References/Linear Regulators
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Features
●● Dual 256-Tap Linear Taper Positions
●● Single +1.7V to +5.5V Supply Operation
●● Low 12μA Quiescent Supply Current
●● 10kΩ, 50kΩ, and 100kΩ End-to-End Resistance
Values
●● SPI-Compatible Interface
●● Wiper Set to Midscale on Power-Up
●● -40°C to +125°C Operating Temperature Range
Ordering Information
PART
PIN-PACKAGE
END-TO-END
RESISTANCE (kΩ)
MAX5391LATE+
16 TQFN-EP*
MAX5391MATE+
16 TQFN-EP*
50
MAX5391NATE+
16 TQFN-EP*
100
MAX5393LAUD+
14 TSSOP
10
MAX5393MAUD+
14 TSSOP
50
MAX5393NAUD+
14 TSSOP
100
10
Note: All devices are specified in the -40°C to +125°C temperature range.
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.
Functional Diagram
VDD
WA
HA
BYP
LA
CHARGE
PUMP
CS
SCLK
DIN
SPI
LATCH
256 DECODER
POR
MAX5391
MAX5393
LATCH
256 DECODER
HB
WB
LB
GND
19-5035; Rev 3; 10/14
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Absolute Maximum Ratings
VDD to GND.............................................................-0.3V to +6V
H_, W_, L_ to GND..................................... -0.3V to the lower of
(VDD + 0.3V) or +6V
All Other Pins to GND..............................................-0.3V to +6V
Continuous Current into H_, W_, and L_
MAX5391L/MAX5393L........................................................±5mA
MAX5391M/MAX5393M......................................................±2mA
MAX5391N/MAX5393N.......................................................±1mA
Continuous Power Dissipation (TA = +70°C)
14-Pin TSSOP (derate 10mW/°C above +70°C).......796.8mW
16-Pin TQFN (derate 14.7mW/°C above +70°C).... 1176.5mW
Operating Temperature Range.......................... -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V,
TA = +25°C.) (Note 1)
PARAMETER
Resolution
SYMBOL
CONDITIONS
N
MIN
TYP
MAX
256
UNITS
Tap
DC PERFORMANCE (Voltage-Divider Mode)
Integral Nonlinearity
INL
(Note 2)
-0.5
+0.5
LSB
Differential Nonlinearity
DNL
(Note 2)
-0.5
+0.5
LSB
Dual-Code Matching
Register A = Register B
-0.5
+0.5
LSB
Ratiometric Resistor Tempco
(ΔVW/VW)/ΔT, no load
MAX5391L/MAX5393L
Full-Scale Error
Code = FFh
Zero-Scale Error
Code = 00h
5
-3
-2.2
MAX5391M/MAX5393M
-1
-0.6
MAX5391N/MAX5393N
-0.5
-0.3
ppm/°C
LSB
MAX5391L/MAX5393L
2.2
3
MAX5391M/MAX5393M
0.6
1
MAX5391N/MAX5393N
0.3
0.5
LSB
DC PERFORMANCE (Variable Resistor Mode)
Integral Nonlinearity (Note 3)
Differential Nonlinearity
R-INL
R-DNL
MAX5391L/MAX5393L
-1.5
+1.5
MAX5391M/MAX5393M
-0.75
+0.75
MAX5391N/MAX5393N
-0.5
+0.5
(Note 3)
-0.5
+0.5
LSB
200
Ω
LSB
DC PERFORMANCE (Resistor Characteristics)
Wiper Resistance
Terminal Capacitance
RWL
(Note 4)
CH_, CL_
Measured to GND
10
Wiper Capacitance
CW_
Measured to GND
50
pF
End-to-End Resistor Tempco
TCR
No load
35
ppm/°C
End-to-End Resistor Tolerance
ΔRHL
Wiper not connected
-25
pF
+25
%
AC PERFORMANCE
Crosstalk
-3dB Bandwidth
Total Harmonic Distortion Plus Noise
www.maximintegrated.com
(Note 5)
BW
THD+N
Code = 80H,
10pF load,
VDD = 1.8V
-90
MAX5391L/MAX5393L
600
MAX5391M/MAX5393M
100
MAX5391N/MAX5393N
50
Measured at W, VH_ = 1VRMS at 1kHz
0.02
dB
kHz
%
Maxim Integrated │ 2
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Electrical Characteristics (continued)
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V,
TA = +25°C.) (Note 1)
PARAMETER
Wiper Settling Time (Note 6)
Charge-Pump Feedthrough at W_
SYMBOL
tS
VRW
CONDITIONS
MIN
TYP
MAX5391L/MAX5393L
400
MAX5391M/MAX5393M
1200
MAX5391N/MAX5393N
2200
fCLK = 600kHz, COUT = 0nF
200
MAX
UNITS
ns
nVP-P
POWER SUPPLIES
Supply Voltage Range
VDD
Standby Current
1.7
VDD = 5.5V
27
VDD = 1.7V
12
VDD = 2.6V to 5.5V
70
VDD = 1.7V to 2.6V
75
5.5
V
µA
DIGITAL INPUTS
Minimum Input High Voltage
VIH
Maximum Input Low Voltage
VIL
Input Leakage Current
% x VDD
VDD = 2.6V to 5.5V
30
VDD = 1.7V to 2.6V
25
-1
Input Capacitance
+1
5
% x VDD
µA
pF
TIMING CHARACTERISTICS—SPI (Note 7)
SCLK Frequency
fMAX
10
MHz
SCLK Clock Period
tCP
100
ns
SCLK Pulse-Width High
tCH
40
ns
SCLK Pulse-Width Low
tCL
40
ns
CS Fall to SCK Rise Setup Time
tCSS
40
ns
SCLK Rise to CS Rise Hold Time
tCSH
0
ns
tDS
40
ns
DIN Setup Time
DIN Hold Time
tDH
0
ns
SCLK Rise to CS Fall Delay
tCS0
10
ns
SCLK Rise to SCLK Rise Hold Time
tCS1
40
ns
CS Pulse-Width High
tCSW
100
ns
Note 1: All devices are 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design and
characterization.
Note 2: DNL and INL are measured with the potentiometer configured as a voltage-divider (Figure 1) with H_ = VDD and L_ = GND.
The wiper terminal is unloaded and measured with a high-input-impedance voltmeter.
Note 3: R-DNL and R-INL are measured with the potentiometer configured as a variable resistor (Figure 1). DNL and INL are measured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ = GND. For VDD = +5V, the wiper
terminal is driven with a source current of 400µA for the 10kΩ configuration, 80µA for the 50kΩ configuration, and 40µA for
the 100kΩ configuration. For VDD = +1.7V, the wiper terminal is driven with a source current of 150µA for the 10kΩ configuration, 30µA for the 50kΩ configuration, and 15µA for the 100kΩ configuration.
Note 4: The wiper resistance is the value measured by injecting the currents given in Note 3 into W_ with L_ = GND.
RW_ = (VW_ - VH_)/IW_.
Note 5: Drive HA with a 1kHz GND to VDD amplitude tone. LA = LB = GND. No load. WB is at midscale with a 10pF load. Measure
WB.
Note 6: The wiper-settling time is the worst-case 0 to 50% rise time, measured between tap 0 and tap 127. H_ = VDD, L_ = GND,
and the wiper terminal is loaded with 10pF capacitance to ground.
Note 7: Digital timing is guaranteed by design and characterization, not production tested.
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Maxim Integrated │ 3
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
H
N.C.
W
W
L
L
Figure 1. Voltage-Divider and Variable Resistor Configurations
Typical Operating Characteristics
(VDD = 1.8V, TA = +25°C, unless otherwise noted.)
20
VDD = 2.6V
15
10
VDD = 1.8V
5
25
VDD = 2.6V
100
20
15
10
0
1.7
2.2
2.7
3.2
3.7
4.2
4.7
VDD (V)
RESISTANCE (W_-TO-L_)
vs. TAP POSITION (10kΩ)
RESISTANCE (W_-TO-L_)
vs. TAP POSITION (50kΩ)
RESISTANCE (W_-TO-L_)
vs. TAP POSITION (100kΩ)
6
5
4
3
2
1
40
35
30
25
20
15
10
5
51
102
153
TAP POSITION
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204
255
0
100
5.2
MAX5391 toc06
45
90
W-TO-L RESISTANCE (kΩ)
7
50
MAX5391 toc05
MAX5391 toc04
DIGITAL INPUT VOLTAGE (V)
8
0
10
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE (°C)
9
W-TO-L RESISTANCE (kΩ)
1000
1
-40 -25 -10 5 20 35 50 65 80 95 110 125
10
0
30
VDD = 1.8V
W-TO-L RESISTANCE (kΩ)
0
MAX5391 toc03
VDD = 5V
SUPPLY CURRENT (µA)
SUPPLY CURRENT (μA)
25
10,000
IDD (μA)
VDD = 5V
MAX5391 toc02
MAX5391 toc01
30
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
80
70
60
50
40
30
20
10
0
51
102
153
TAP POSITION
204
255
0
0
51
102
153
204
255
TAP POSITION
Maxim Integrated │ 4
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Typical Operating Characteristics (continued)
(VDD = 1.8V, TA = +25°C, unless otherwise noted.)
100
VDD = 5V
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
10kΩ
0.02
0
-0.02
-0.04
-0.01
-0.06
-0.02
-0.08
-0.10
-40 -25 -10 5 20 35 50 65 80 95 110 125
0.10
0.08
1.0
0.06
153
204
0.8
0.6
0
-0.02
INL (LSB)
0.2
DNL (LSB)
0.4
0
-0.02
0
-0.04
-0.4
-0.06
-0.06
-0.6
-0.08
-0.08
IWIPER = 30μA
51
102
153
204
-0.10
255
-0.8
IWIPER = 15μA
0
51
102
153
204
-1.0
255
IWIPER = 150μA
0
51
102
153
204
TAP POSITION
TAP POSITION
TAP POSITION
VARIABLE RESISTOR INL
vs. TAP POSITION (50kΩ)
VARIABLE RESISTOR INL
vs. TAP POSITION (100kΩ)
VOLTAGE-DIVIDER DNL
vs. TAP POSITION (10kΩ)
0.3
0.10
MAX5391 toc14
0.5
MAX5391 toc13
0.4
0.4
0.3
0.08
0.06
0.04
0.1
0.1
0.02
-0.1
DNL (LSB)
0.2
INL (LSB)
0.2
0
0
-0.1
0
-0.2
-0.04
-0.3
-0.3
-0.06
-0.4
-0.4
51
102
153
TAP POSITION
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204
255
-0.5
-0.08
IWIPER = 15μA
0
51
255
-0.02
-0.2
IWIPER = 30μA
255
-0.2
-0.04
0
102
VARIABLE RESISTOR INL
vs. TAP POSITION (10kΩ)
0.02
-0.5
51
VARIABLE RESISTOR DNL
vs. TAP POSITION (100kΩ)
0.02
0.5
0
VARIABLE RESISTOR DNL
vs. TAP POSITION (50kΩ)
0.04
0
IWIPER = 150μA
TAP POSITION
0.04
-0.10
MAX5391 toc09
MAX5391 toc08
50kΩ
TEMPERATURE (°C)
0.06
DNL (LSB)
0.01
WIPER VOLTAGE (V)
0.08
INL (LSB)
0.06
0.04
0.02
-0.03
MAX5391 toc10
0.10
VDD = 2.6V
0.03
0.08
MAX5391 toc12
60
VDD = 1.8V
100kΩ
MAX5391 toc15
80
0.04
VARIABLE RESISTOR DNL
vs. TAP POSITION (10kΩ)
0.10
DNL (LSB)
120
END-TO-END RESISTANCE PERCENTAGE
CHANGE vs. TEMPERATURE
MAX5391 toc11
WIPER RESISTANCE (Ω)
140
0.05
END-TO-END RESISTANCE % CHANGE
MAX5391 toc07
WIPER RESISTANCE
vs. WIPER VOLTAGE
102
153
TAP POSITION
204
255
-0.10
0
51
102
153
204
255
TAP POSITION
Maxim Integrated │ 5
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Typical Operating Characteristics (continued)
(VDD = 1.8V, TA = +25°C, unless otherwise noted.)
0.08
0.06
0.4
0.3
0.04
0.2
0.02
0.02
0.1
0
-0.02
INL (LSB)
0.04
DNL (LSB)
0
-0.02
0
-0.1
-0.04
-0.04
-0.2
-0.06
-0.06
-0.3
-0.08
-0.08
-0.4
-0.10
0
102
153
204
-0.10
255
102
153
204
-0.5
255
0
51
102
153
204
255
TAP POSITION
VOLTAGE-DIVIDER INL
vs. TAP POSITION (50kΩ)
VOLTAGE-DIVIDER INL
vs. TAP POSITION (100kΩ)
TAP-TO-TAP SWITCHING TRANSIENT
(CODE 127 TO CODE 128) (10kΩ)
0.3
0.5
0.3
0.1
0.1
INL (LSB)
0.2
0
-0.1
0
-0.2
-0.3
-0.3
-0.4
-0.4
102
153
204
-0.5
255
CS
5V/div
0
51
102
153
204
255
TAP POSITION
TAP POSITION
TAP-TO-TAP SWITCHING TRANSIENT
(CODE 127 TO CODE 128) (50kΩ)
TAP-TO-TAP SWITCHING TRANSIENT
(CODE 127 TO CODE 128) (100kΩ)
MAX5391M P0WER-ON TRANSIENT
MAX5391 toc24
VW_-L_
20mV/div
VW_-L_
20mV/div
CS
5V/div
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400ns/div
MAX5391 toc23
MAX5391 toc22
1µs/div
VW_-L_
20mV/div
-0.1
-0.2
51
MAX5391 toc21
0.4
0.2
0
51
TAP POSITION
0.4
-0.5
0
TAP POSITION
MAX5391 toc19
0.5
51
MAX5391 toc20
DNL (LSB)
0.06
VOLTAGE-DIVIDER INL
vs. TAP POSITION (10kΩ)
0.5
MAX5391 toc17
0.08
INL (LSB)
0.10
MAX5391 toc16
0.10
VOLTAGE-DIVIDER DNL
vs. TAP POSITION (100kΩ)
MAX5391 toc18
VOLTAGE-DIVIDER DNL
vs. TAP POSITION (50kΩ)
VW_-L_
1V/div
CS
5V/div
1µs/div
VDD
5V/div
2µs/div
Maxim Integrated │ 6
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Typical Operating Characteristics (continued)
(VDD = 1.8V, TA = +25°C, unless otherwise noted.)
-10
VDD = 1.8V
-10
-10
VDD = 1.8V
VDD = 1.8V
-20
-20
-20
VIN = 1VP-P
1
0.01
100
-30
10k
VIN = 1VP-P
0.01
FREQUENCY (kHz)
100
10k
0.20
0.18
0.16
THD+N (%)
50kΩ
10k
100kΩ
0.12
0.10
0.08
0.06
-100
0.04
-120
0.01
0.1
1
50kΩ
0.02
10kΩ
10
100
0
1000
0.01
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
BYP RAMP vs. CBYP
CHARGE-PUMP FEEDTHROUGH
AT W_ vs. CBYP
700
MAX5391 toc30
120
600
VOLTAGE (nVRMS)
100
RAMP TIME (ms)
10kΩ
0.14
-80
80
60
40
20
0
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
100kΩ
-40
-140
1
0.01
FREQUENCY (kHz)
MAX5391 toc28
-20
-60
VIN = 1VP-P
FREQUENCY (kHz)
CROSSTALK vs. FREQUENCY
0
CROSSTALK (dB)
1
-30
MAX5391 toc31
-30
MAX5391 toc27
VDD = 5V
0
MAX5391 toc29
GAIN (dB)
GAIN (dB)
VDD = 5V
0
MIDSCALE FREQUENCY
RESPONSE (100kΩ)
10
GAIN (dB)
VDD = 5V
0
10
MAX5391 toc25
10
MIDSCALE FREQUENCY
RESPONSE (50kΩ)
MAX5391 toc26
MIDSCALE FREQUENCY
RESPONSE (10kΩ)
500
400
300
200
100
0
0.02
0.04
0.05
CAPACITANCE (µF)
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0.08
0.10
0
0
200
400
600
800
CAPACITANCE (pF)
Maxim Integrated │ 7
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Pin Configurations
VDD
N.C.
SCLK
DIN
TOP VIEW
12
11
10
9
TOP VIEW
GND 1
N.C. 13
HA 14
MAX5391
CS
7
BYP
HB 3
*EP
6
N.C.
5
GND
I.C. 5
BYP 6
1
2
3
4
WB
LB
I.C.
+
HB
CS 7
14 LA
13 HA
LB 2
WB 4
WA 15
LA 16
8
+
MAX5393
12 WA
11 VDD
10 N.C.
9 SCLK
8 DIN
*EP = EXPOSED PAD
Pin Description
PIN
MAX5391
(TQFN-EP)
MAX5393
(TSSOP)
NAME
FUNCTION
1
3
HB
Resistor B High Terminal. The voltage at HB can be higher or lower than the voltage at LB.
Current can flow into or out of HB.
2
4
WB
Resistor B Wiper Terminal
3
2
LB
Resistor B Low Terminal. The voltage at LB can be higher or lower than the voltage at HB.
Current can flow into or out of LB.
4
5
I.C.
Internally Connected. Connect to GND.
5
1
GND
Ground
6, 11, 13
10
N.C.
No Connection. Not internally connected.
7
6
BYP
Internal Power-Supply Bypass. For additional charge-pump filtering, bypass to GND with a
capacitor close to the device.
8
7
CS
Active-Low Chip-Select Input
9
8
DIN
Serial-Interface Data Input
10
9
SCLK
Serial-Interface Clock Input
12
11
VDD
14
13
HA
Resistor A High Terminal. The voltage at HA can be higher or lower than the voltage at LA.
Current can flow into or out of HA.
15
12
WA
Resistor A Wiper Terminal
16
14
LA
Resistor A Low Terminal. The voltage at LA can be higher or lower than the voltage at HA.
Current can flow into or out of LA.
—
—
EP
Exposed Pad (MAX5391 Only). Connect to GND.
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Power-Supply Input. Bypass VDD to GND with a 0.1µF capacitor close to the device.
Maxim Integrated │ 8
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Detailed Description
to the wiper. The value of CBYP does affect the startup
time of the charge pump; however, CBYP does not impact
the ability to communicate with the device, nor is there a
minimum CBYP requirement. The maximum wiper impedance specification is not guaranteed until the charge
pump is fully settled. See the BYP Ramp vs. CBYP graph
in the Typical Operating Characteristics for CBYP impact
on charge-pump settling time.
The potentiometers in each device are programmable
independently of each other. The MAX5391/MAX5393
feature an SPI interface.
SPI Digital Interface
The MAX5391/MAX5393 dual 256-tap, volatile, lowvoltage linear taper digital potentiometers offer three endtoend resistance values of 10kΩ, 50kΩ, and 100kΩ. Each
potentiometer consists of 255 fixed resistors in series
between terminals H_ and L_. The potentiometer wiper,
W_, is programmable to access any one of the 256 tap
points on the resistor string.
The MAX5391/MAX5393 include a SPI interface that provides a 3-wire write-only serial-data interface to control
the wiper tap position through inputs chip select (CS),
data in (DIN), and data clock (SCLK). Drive CS low to load
data from DIN synchronously into the serial shift register
on the rising edge of each SCLK pulse. The MAX5391/
MAX5393 load the last 10 bits of clocked data into the
appropriate potentiometer control register once CS transitions high. See Figures 2 and 3. Data written to a memory
register immediately updates the wiper position. Keep CS
low during the entire data stream to prevent the data from
being terminated.
Charge Pump
The MAX5391/MAX5393 contain an internal charge pump
that guarantees the maximum wiper resistance, RWL, to
be less then 200Ω for supply voltages down to 1.7V. Pins
H_, W_, and L_ are still required to be less than VDD +
0.3V. A bypass input, BYP, is provided to allow additional
filtering of the charge-pump output, further reducing clock
feed through that may occur on H_, W_, or L_. The nominal clock rate of the charge pump is 600kHz. BYP should
remain resistively unloaded as any additional load would
produce a ripple of approximately IBYP/(600kHz x CBYP)
volts. See the Charge-Pump Feedthrough at W_ vs.
CBYP graph in the Typical Operating Characteristics for
CBYP sizing guidelines with respect to clock feedthrough
The first two bits A1:A0 (address bits) address one of
the two potentiometers. See Table 1. The power-on reset
(POR) circuitry sets the wiper to midscale.
Table 1. SPI Register Map
Bit Number
Bit Name
1
2
3
4
5
6
7
8
9
10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write Wiper Register A
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Write Wiper Register B
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Write to Both A and B
1
1
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
STARTED 10-BIT
WIPER REGISTER
LOADED
CS
SCLK
DIN
A0
A1
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2. SPI Digital Interface Format
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Maxim Integrated │ 9
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
tCSW
CS
tCS1
tCSO
tCSS
tCL
tCH
tCP
tCSH
tDH
SCLK
tDS
DIN
Figure 3. SPI Timing Diagram
REG A: The data byte writes to register A, and the wiper
of potentiometer A moves to the appropriate position at
the rising edge of CS. D[7:0] indicates the position of the
wiper. D[7:0] = 00h moves the wiper to the position closest to LA. D[7:0] = FFh moves the wiper closest to HA.
D[7:0] is 80h following power-on.
Applications Information
REG B: The data byte writes to register B, and the wiper
of potentiometer B moves to the appropriate position at
the rising edge of CS. D[7:0] indicates the position of the
wiper. D[7:0] = 00h moves the wiper to the position closest to LB. D[7:0] = FFh moves the wiper to the position
closest to HB. D[7:0] is 80h following power-on.
Adjustable Dual Regulator
REG A and B: The data byte writes to registers A and
B, and the wipers of potentiometers A and B move to the
appropriate position. D[7:0] indicates the position of the
wiper. D[7:0] = 00h moves the wiper to the position closest to L_. D[7:0] = FFh moves the wiper to the position
closest to H_. D[7:0] is 80h following power-on.
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Variable Gain Amplifier
Figure 4 shows a potentiometer adjusting the gain of a
noninverting amplifier. Figure 5 shows a potentiometer
adjusting the gain of an inverting amplifier.
Figure 6 shows an adjustable dual linear regulator using a
dual potentiometer as two variable resistors.
Adjustable Voltage Reference
Figure 7 shows an adjustable voltage reference circuit
using a potentiometer as a voltage divider.
Maxim Integrated │ 10
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
H_
VIN
L_
VOUT
W_
VIN
VOUT
W_
H_
L_
Figure 4. Variable-Gain Noninverting Amplifier
VOUT1
OUT1
VOUT2
OUT2
IN
H_
H_
W_
SET1
+2.5V
IN
MAX8866
V+
Figure 4. Variable-Gain Noninverting Amplifier
W_
L_
VREF
OUT
MAX6037
H_
W_
L_
GND
L_
SET2
Figure 6. Adjustable Dual Linear Regulator
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Figure 7. Adjustable Voltage Reference
Maxim Integrated │ 11
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Variable-Gain Current-to-Voltage Converter
Offset Voltage Adjustment Circuit
LCD Bias Control
Chip Information
Figure 8 shows a variable-gain current-to-voltage converter using a potentiometer as a variable resistor.
Figure 9 shows a positive LCD bias control circuit using a
potentiometer as a voltage-divider.
Figure 11 shows an offset voltage adjustment circuit using
a dual potentiometer.
PROCESS: BiCMOS
Programmable Filter
Figure 10 shows a programmable filter using a dual
potentiometer.
R3
+1.8V
H_
H_
W_
R1
IS
W_
R2
VOUT
L_
L_
VOUT
VOUT = -IS x ((R3 x (1 + R2/R1)) + R2)
Figure 8. Variable Gain I-to-V Converter
Figure 9. Positive LCD Bias Control Using a Voltage-Divider
+1.8V
WA
WB
VIN
LB
HB
LA
HA
VIN
VOUT
R3
VOUT
R1
HA
WA
HB
R2
LA
WB
LB
Figure 10. Programmable Filter
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Figure 11. Offset Voltage Adjustment Circuit
Maxim Integrated │ 12
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
14 TSSOP
U14+1
21-0066
90-0113
16 TQFN-EP
T1633+5
21-0136
90-0032
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Maxim Integrated │ 13
MAX5391/MAX5393
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
10/09
Initial release
—
1
4/10
Added Soldering Temperature in Absolute Maximum Ratings; corrected code in
Conditions of -3dB Bandwidth specification and corrected Integral Nonlinearity
specifications in Electrical Characteristics
2
2
11/10
Changed Electrical Characteristics heading and changed Figures 5, 8, 10, 11
3
10/14
Removed automotive reference from Applications and General Description
DESCRIPTION
2, 3, 11, 12
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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