MAX5480BEEE

19-1300; Rev 0; 10/97 8-Bit Parallel DAC in QSOP-16 Package The MAX5480 can be operated in either voltage-output or current-output mode. It is available in a small 16-pin QSOP package. ____________________________Features ♦ QSOP-16 Package (same footprint as SO-8) ♦ Single +5V Supply Operation ♦ VOUT or IOUT Operation ♦ 8-Bit Parallel Interface ♦ Guaranteed Monotonic Over Temperature ♦ Low Power Consumption—100µA max ♦ ±1/2LSB Linearity Over Temperature ________________________Applications ______________Ordering Information Digitally Adjusted Power Supplies Programmable Gain Automatic Test Equipment Portable, Battery-Powered Instruments VCO Frequency Control PINPACKAGE ERROR (LSB) PART TEMP. RANGE MAX5480ACEE 0°C to +70°C 16 QSOP ±1/2 MAX5480BCEE 0°C to +70°C 16 QSOP ±1/2 MAX5480AEEE -40°C to +85°C 16 QSOP ±1/2 MAX5480BEEE -40°C to +85°C 16 QSOP ±1/2 RF Transmit Control in Portable Radios __________Typical Operating Circuit VREF REF 14 VDD RFB DATA INPUTS 4–11 D7–D0 12 13 TOP VIEW VDD R1 2k 15 R2 1k 16 OUT1 1 10pF WR MAX5480 OUT2 OUT1 1 16 RFB OUT2 2 15 REF GND 3 14 VDD D7 (MSB) 4 MAX4330 CS __________________Pin Configuration 2 GND 3 R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. VOUT MAX5480 13 WR D6 5 12 CS D5 6 11 D0 (LSB) D4 7 10 D1 D3 8 9 D2 QSOP ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX5480 _______________General Description The MAX5480 is a CMOS, 8-bit digital-to-analog converter (DAC) that interfaces directly with most microprocessors. On-chip input latches make the DAC load cycle interface similar to a RAM write cycle, where CS and WR are the only control inputs required. Linearity of ±1/2LSB is guaranteed, and power consumption is less than 500µW. Monotonicity is guaranteed over the full operating temperature range. MAX5480 8-Bit Parallel DAC in QSOP-16 Package ABSOLUTE MAXIMUM RATINGS VDD to GND ............................................................-0.3V to +17V REF to GND .........................................................................±25V RFB to GND .........................................................................±25V Digital Inputs to GND .................................-0.3V to (VDD + 0.3V) OUT1, OUT2 to GND................................................-0.3V to VDD Operating Temperature Ranges MAX5480_CEE....................................................0°C to +70°C MAX5480_EEE .................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Continuous Power Dissipation (TA = +70°C) MAX5480_ _EE (derate 8.3mW/°C above +70°C) ........667mW Lead Temperature (soldering 10sec) ..............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +5V, VREF = +10V, VOUT1 = VOUT2 = 0V, Circuit of Figure 1, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1/2 LSB ±1 LSB DC ACCURACY Resolution 8 Relative Accuracy INL Differential Nonlinearity DNL Gain Error (Note 1) All grades guaranteed monotonic over temperature TA = TMIN to TMAX Gain Temperature Coefficient (Note 2) MAX5480A (Note 3) Supply Rejection Bits PSR MAX5480B Output Leakage Current (IOUT1) VREF = ±10V DAC code = full scale Output Leakage Current (IOUT2) VREF = ±10V DAC code = zero scale ±1 LSB ±2 ppm/°C TA = +25°C 0.002 0.08 TA = TMIN to TMAX 0.01 0.16 TA = +25°C 0.002 TA = TMIN to TMAX 0.01 TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX ±50 ±400 ±50 ±400 %FSR/% nA nA REFERENCE INPUT Input Resistance RREF pin 15 to GND 5 10 20 kΩ DYNAMIC PERFORMANCE D0–D7 = 0V to VDD or VDD to 0V, WR = CS = 0V, OUT1 load = 100Ω || 13pF Output Current Settling Time to 1/2LSB VREF = ±10V, 100kHz sine wave, WR = CS = 0V AC Feedthrough (OUT1 or OUT2) MAX5480A (Note 3) TA = +25°C 400 TA = TMIN to TMAX 500 MAX5480B TA = +25°C 250 MAX5480A TA = +25°C (Note 3) TA = TMIN to TMAX MAX5480B TA = +25°C ns 0.25 0.5 ns 0.1 ANALOG OUTPUTS OUT1 Capacitance (Note 3) COUT1 OUT2 Capacitance (Note 3) COUT2 2 D0–D7 = VDD, WR = CS = 0V 120 D0–D7 = 0V, WR = CS = 0V 30 D0–D7 = VDD, WR = CS = 0V 30 D0–D7 = 0V, WR = CS = 0V 120 _______________________________________________________________________________________ pF pF 8-Bit Parallel DAC in QSOP-16 Package (VDD = +5V, VREF = +10V, VOUT1 = VOUT2 = 0V, Circuit of Figure 1, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Current IIN Input Capacitance (Note 3) CIN 2.4 V 0.8 TA = +25°C; VIN = 0V to VDD ±1 TA = TMIN to TMAX ±10 D0–D7 8 WR, CS 20 V µA pF POWER REQUIREMENTS Supply Current IDD Digital inputs at 0V or VDD TA = +25°C 100 TA = TMIN to TMAX 500 µA SWITCHING CHARACTERISTICS (Figure 4) Chip-Select to WriteSetup Time tCS Chip-Select to WriteHold Time tCH Write Pulse Width tWR Data-Setup Time tDS Data-Hold Time tDH MAX5480A 220 MAX5480B 35 MAX5480A 0 MAX5480B 0 MAX5480A 220 MAX5480B 35 MAX5480A 170 MAX5480B 55 MAX5480A 10 MAX5480B -7 ns ns ns ns ns Note 1: Gain error is measured using internal feedback resistor. Full-scale range (FSR) = VREF. Note 2: Gain TempCo measured from +25°C to TMAX and from +25°C to TMIN. Note 3: Guaranteed by design. ______________________________________________________________Pin Description PIN NAME FUNCTION 1 OUT1 R-2R Ladder Output 2 OUT2 R-2R Ladder Output, complement of OUT1 3 GND Ground 4–11 D7–D0 12 CS Chip Select Input. Active Low. 13 WR Write Control Input. Active Low. 14 VDD Power Supply Input, +5V 15 REF Reference Voltage Input 16 RFB Feedback Resistor Connection Data Inputs, D7 is the most significant bit. _______________________________________________________________________________________ 3 MAX5480 ELECTRICAL CHARACTERISTICS (continued) MAX5480 8-Bit Parallel DAC in QSOP-16 Package _______________Detailed Description The MAX5480 is an 8-bit multiplying digital-to-analog converter (DAC) that consists of a thin-film R-2R resistor array with CMOS current steering switches. Figure 3 shows a simplified schematic of the DAC. The inverted R-2R ladder divides the voltage or current reference in a binary manner among the eight steering switches. The magnitude of the current appearing at either OUT terminal depends on the number of switches selected; therefore, the output is an analog representation of the digital input. The two OUT terminals must be held at the same potential so a constant current is maintained in each ladder leg. This makes the REF input current independent of switch state and also ensures that the MAX5480 maintains its excellent linearity performance. VREF VDD R1 2k 15 14 VDD RFB REF DATA INPUTS 4–11 D7–D0 OUT1 Write Mode When CS and WR are both low, the MAX5480 is in write mode, and its analog output responds to data activity at the D0–D7 data-bus inputs. In this mode, the data latches are transparent (see Tables 2 and 3). Hold Mode In hold mode, the MAX5480 retains the data that was present on D0–D7 just prior to CS or WR assuming a high state. The analog output remains at the value corresponding to the digital code locked in the data latch. CS 13 OUT2 MAX5480 WR The MAX5480 can be used either as a current-output DAC (Figures 1 and 6) or as a voltage-output DAC (Figures 2 and 5). To use the MAX5480 in voltage mode, connect OUT1 to the reference input and connect OUT2 to ground. REF, now the DAC output, is a voltage source with a constant output resistance of 10kΩ (nominally). This output is often buffered with an op amp (Figure 5). An advantage of voltage-mode operation is singlesupply operation for the complete circuit; i.e., a negative reference is not required for a positive output. It is important to note that the range of the reference is restricted in voltage mode. The reference input (voltage at OUT1) must always be positive and is limited to no more than VDD - 3V. If the reference voltage exceeds this value, linearity is degraded. 4 10pF VOUT 2 GND 3 R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. Figure 1. Unipolar Binary Operation (Two-Quadrant Multiplication) +5V 14 16 REF INPUT* 1 RFB VDD OUT1 REF MAX5480 2 15 OUTPUT VOLTAGE (10kΩ OUTPUT RESISTANCE) OUT2 WR CS 13 12 __________Applications Information Using the MAX5480 in VoltageOutput Mode (Single Supply) 1 MAX4330 12 Interface-Logic Information Mode Selection The inputs CS and WR control the MAX5480’s operating mode (see Table 1). R2 1k 16 GND 3 D7–D0 4–11 DATA IN *(VDD - 3V, max) Figure 2. Typical Operating Circuit (Voltage Mode—Unbuffered) Table 1. Mode-Selection Table CS WR MODE L L Write H X X H Hold Hold DAC Response DAC responds to data bus (D0–D7) inputs. Data bus (D0–D7) is locked out; DAC holds last data present when CS or WR assumed high state. L = Low State, H = High State, X = Don’t Care _______________________________________________________________________________________ 8-Bit Parallel DAC in QSOP-16 Package DIGITAL INPUT MSB LSB Table 3. Bipolar (Offset Binary) Code Table DIGITAL INPUT MSB LSB ANALOG OUTPUT ANALOG OUTPUT 1 1 1 1 1 1 1 1  255  -VREF    256  1 1 1 1 1 1 1 1  127  +VREF    128  1 0 0 0 0 0 0 1  129  -VREF    256  1 0 0 0 0 0 0 1  1  +VREF    128  1 0 0 0 0 0 0 0 0  128  VREF -VREF   = − 2  256  1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1  127  -VREF    256  0 1 1 1 1 1 1 1  1  -VREF    128  0 0 0 0 0 0 0 1  1  -VREF    256  0 0 0 0 0 0 0 1  127  -VREF    128  0 0 0 0 0 0 0 0  0  -VREF   = 0  256  0 0 0 0 0 0 0 0  128  -VREF    128  ( ) ( 1 NOTE : 1 LSB =  2 −8  VREF = VREF 256 ) ( ) ( 1 NOTE : 1 LSB =  2 −7  VREF = VREF 128 tCS 10kΩ 10kΩ 10kΩ S8 20kΩ S7 20kΩ S6 VDD CS REF 20kΩ tCH ) 20kΩ 0 20kΩ tWR S1 VDD WR 0 OUT2 tDS tDH OUT1 RFB 10kΩ CS WR INTERFACE LOGIC D7 (MSB) D6 D5 Figure 3. MAX5480 Functional Diagram D0 (LSB) DATA IN (D7–D0) VIH VIL VDD DATA IN STABLE 0 NOTES: 1. FOR THE MAX5480, ALL INPUT SIGNAL RISE AND FALL TIMES ARE MEASURED FROM 10% TO 90% OF VDD. VDD = +5V, tr = tf = 20ns. 2. TIMING MEASUREMENT REFERENCE LEVEL IS (VIH + VIL) / 2. Figure 4. Write-Cycle Timing Diagram _______________________________________________________________________________________ 5 MAX5480 Table 2. Unipolar Binary Code Table MAX5480 8-Bit Parallel DAC in QSOP-16 Package 0.1µF +5V VIN N.C. 16 MAX6120 RFB GND +1.2V VOUT 1 14 VDD OUT1 REF 15 MAX4330 0V ≤ VOUT ≤ 2.4V (255/256) MAX5480 2 OUT2 WR 13 GND CS 12 3 D7–D0 10k 4–11 10k DATA IN Figure 5. Single-Supply Voltage-Output Mode (Buffered) ±10V (AC OR DC) VREF VDD R5 20kΩ R1 2kΩ 15 REF 14 DATA INPUTS 4–11 D7–D0 12 13 CS 16 VDD RFB OUT1 MAX5480 WR OUT2 R3 20kΩ R2 1kΩ C1 1 2 A1 1/2 MXL1013 R4 10kΩ A1 1/2 MXL1013 R6 5kΩ 0 TO -VREF GND 3 VOUT GND NOTES: 1. ADJUST R1 FOR VOUT = 0V AT CODE 10000000. 2. C1 PHASE COMPENSATION (10pF to 15pF) MAY BE REQUIRED IF A1 IS A HIGH-SPEED AMPLIFIER. Figure 6. Bipolar (Four-Quadrant) Operation Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.