MAX5631/MAX5632/
MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
General Description
Ordering Information
PART
TEMP RANGE*
MAX5631UCB+D
0°C to +85°C
64 TQFP
MAX5631UTK+
0°C to +85°C
68 TQFN-EP**
0°C to +85°C
64 TQFP
MAX5632UTK+
0°C to +85°C
68 TQFN-EP**
MAX5633UCB+D
0°C to +85°C
64 TQFP
MAX5633UTK+
0°C to +85°C
68 TQFN-EP**
+Denotes a lead(Pb)-free/RoHS-compliant package.
*For other temperature-range options, contact factory.
**EP = Exposed pad.
Industrial Process Control
Automatic Test Equipment
Instrumentation
CL
OUT21
OUT22
OUT24
OUT23
OUT25
AGND
OUT26
63 62 61 60 59 58
OUT27
64
57 56 55 54 53 52 51 50 49
+
N.C.
1
N.C.
2
47 CH
48 VDD
GS
3
46 VSS
VLDAC
4
45 OUT20
RST
5
44 OUT19
CS
6
43 OUT18
DIN
7
42 OUT17
SCLK
8
41 OUT16
VLOGIC
9
MAX5631
MAX5632
MAX5633
IMMED 10
Pin Configurations continued at end of data sheet.
OUT28
OUT29
OUT30
TOP VIEW
OUT31
Pin Configurations
________________________Applications
MEMS Mirror Servo Control
PIN-PACKAGE
MAX5632UCB+D
AGND
These devices are controlled through a 20MHz
SPI/QSPI™/MICROWIRE ® -compatible 3-wire serial
interface. Immediate Update Mode allows any channel’s output to be updated within 20µs. Burst Mode
allows multiple values to be loaded into memory in a
single, high-speed data burst. All channels are updated
within 330µs after data has been loaded.
Each device features an output clamp and output resistors for filtering. The MAX5631 features a 50Ω output
impedance and is capable of driving up to 250pF of output capacitance. The MAX5632 features a 500Ω output
impedance and is capable of driving up to 10nF of output
capacitance. The MAX5633 features a 1kΩ output impedance and is capable of driving up to 10nF of output
capacitance.
The MAX5631/MAX5632/MAX5633 are available in 12mm
x 12mm, 64-pin TQFP, and 10mm x 10mm, 68-pin thin
QFN packages.
CH
The MAX5631/MAX5632/MAX5633 feature a -4.5V to
+9.2V output voltage range. Other features include a
200µV/step resolution, with output linearity error, typically 0.005% of full-scale range (FSR). The 100kHz
refresh-rate updates each SHA every 320µs, resulting
in negligible output droop. Remote ground sensing
allows the outputs to be referenced to the local ground
of a separate device.
Features
o Integrated 16-Bit DAC and 32-Channel SHA with
SRAM and Sequencer
o 32 Voltage Outputs
o 0.005% Output Linearity
o 200µV Output Resolution
o Flexible Output Voltage Range
o Remote Ground Sensing
o Fast Sequential Loading: 1.3µs per Register
o Burst and Immediate Mode Addressing
o No External Components Required for Setting
Gain and Offset
o Integrated Output Clamp Diodes
o Three Output Impedance Options:
MAX5631 (50Ω), MAX5632 (500Ω), and
MAX5633 (1kΩ)
VREF
The MAX5631/MAX5632/MAX5633 are 16-bit digital-toanalog converters (DACs) with 32 sample-and-hold
(SHA) outputs for applications where a high number of
programmable voltages are required. These devices
include a clock oscillator and a sequencer that updates
the DAC with codes from an internal SRAM. No external
components are required to set offset and gain.
40 AGND
39 VDD
ECLK 11
38 OUT15
CLKSEL 12
37 OUT14
DGND 13
36 OUT13
VLSHA 14
35 OUT12
AGND 15
34 OUT11
33 CL
VSS 16
VSS
CH
OUT10
OUT9
OUT8
OUT7
OUT6
AGND
OUT5
OUT4
OUT3
OUT2
OUT1
CL
OUT0
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor, Corp.
VDD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-2171; Rev 4; 9/12
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ABSOLUTE MAXIMUM RATINGS
VDD to AGND.......................................................-0.3V to +12.2V
VSS to AGND .........................................................-6.0V to +0.3V
VDD to VSS ...........................................................................+15V
VLDAC, VLOGIC, VLSHA to AGND or DGND ..............-0.3V to +6V
REF to AGND............................................................-0.3V to +6V
GS to AGND................................................................VSS to VDD
CL and CH to AGND...................................................VSS to VDD
Logic Inputs to DGND ..............................................-0.3V to +6V
DGND to AGND........................................................-0.3V to +2V
Maximum Current Into OUT_ ............................................±10mA
Maximum Current Into Logic Inputs .................................±20mA
Continuous Power Dissipation (TA = +70°C)
64-Pin TQFP (derate 13.3mW/°C above +70°C) ............1066mW
68-Pin TQFN-EP (derate 28.6mW/°C above +70°C) ......2285mW
Operating Temperature Range...............................0°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, VAGND = VDGND = VGS = 0V, RL ≥ 10MΩ, CL = 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Resolution
Output Range
N
VOUT_
Offset Voltage
16
(Note 1)
±15
Code = 4F2C hex
±200
±50
Gain Error
(Note 2)
Integral Linearity Error
INL
VOUT_ = -3.25V to +7.6V
Differential Linearity Error
DNL
VOUT_ = -3.25V to +7.6V. Monotonicity
guaranteed to 14 bits
Maximum Output Drive Current
IOUT
Sinking and sourcing
DC Output Impedance
ROUT
Maximum Capacitive Load
DC Crosstalk
PSRR
V
mV
µV/°C
±1
±5
Gain Tempco
2
VDD 2.4
VSS +
0.75
Offset Voltage Tempco
Power-Supply Rejection Ratio
Bits
%
ppm/°C
0.005
0.015
%FSR
±1
±4
LSB
±2
mA
MAX5631
35
50
65
MAX5632
350
500
650
MAX5633
700
1000
1300
Ω
MAX5631
250
MAX5632
10
pF
MAX5633
10
Internal oscillator enabled (Note 3)
-90
dB
Internal oscillator enabled
-80
dB
nF
Maxim Integrated
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, VAGND = VDGND = VGS = 0V, RL ≥ 10MΩ, CL = 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.08
%
DYNAMIC CHARACTERISTICS
Sample-and-Hold Settling
(Note 4)
SCLK Feedthrough
0.5
nV-s
fSEQ Feedthrough
0.5
nV-s
Hold-Step
Droop Rate
VOUT_ = 0V (Note 5), TA = +25°C
Output Noise
0.25
1
mV
1
40
mV/s
µVRMS
250
REFERENCE INPUT
Input Resistance
Reference Input Voltage
7
VREF
kΩ
2.5
V
GROUND-SENSE INPUT
Input Voltage Range
VGS
Input Bias Current
IGS
GS Gain
-0.5V ≤ VGS ≤ 0.5V
(Note 6)
-0.5
0.5
V
-60
0
µA
1.002
V/V
0.998
1
DIGITAL INTERFACE DC CHARACTERISTICS
Input High Voltage
VIH
Input Low Voltage
VIL
2.0
V
Input Current
0.8
V
±1
µA
120
kHz
TIMING CHARACTERISTICS (FIGURE 2)
Sequencer Clock Frequency
fSEQ
Internal oscillator
External Clock Frequency
fECLK
(Note 7)
SCLK Frequency
fSCLK
80
100
480
kHz
20
MHz
SCLK Pulse Width High
tCH
15
ns
SCLK Pulse Width Low
tCL
15
ns
CS Low to SCLK High Setup
Time
tCSSO
15
ns
CS High to SCLK High Setup
Time
tCSS1
15
ns
SCLK High to CS Low Hold Time
tCSH0
10
ns
Maxim Integrated
3
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, VAGND = VDGND = VGS = 0V, RL ≥ 10MΩ, CL = 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
SCLK High to CS High Hold Time
CONDITIONS
MIN
TYP
MAX
UNITS
tCSH1
0
ns
DIN to SCLK High Setup Time
tDS
15
ns
DIN to SCLK High Hold Time
tDH
0
ns
RST to CS Low
(Note 8)
500
µs
POWER SUPPLIES
Positive Supply Voltage
VDD
(Note 9)
8.55
10
11.6
V
Negative Supply Voltage
VSS
(Note 9)
-5.25
-4
-2.75
V
14.5
V
5
5.25
V
32
42
mA
mA
Supply Difference
Logic Supply Voltage
VDD - VSS (Note 9)
VLOGIC,
VLDAC,
VLSHA
Positive Supply Current
IDD
Negative Supply Current
ISS
Logic Supply Current
ILOGIC
4.75
32
40
(Note 10)
1
1.5
fSCLK = 20MHz (Note 11)
2
3
mA
Note 1: The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The
output voltage is limited by the Output Range specification, restricting the useable range of DAC codes. The nominal zeroscale voltage may be achieved when VSS < -4.9V, and the nominal full-scale voltage may be achieved when VDD > +11.5V.
Note 2: Gain is calculated from measurements
for voltages VDD = 10V and VSS = -4V at codes C000 hex and 4F2C hex,
for voltages VDD = 11.6V and VSS = -2.9V at codes FFFF hex and 252E hex,
for voltages VDD = 9.25V and VSS = -5.25V at codes D4F6 hex and 0 hex, and
for voltages VDD = 8.55V and VSS = -2.75V at codes C74A hex and 281C hex.
Note 3: Steady-state change in any output with an 8V change in an adjacent output.
Note 4: Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
updates. Tested with an external sequencer clock frequency of 480kHz.
Note 5: External clock mode with the external clock not toggling.
Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex.
Note 7: The sequencer runs at fSEQ = fECLK/4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
limited by acceptable droop and update time after a Burst Mode Update.
Note 8: VDD rise to CS low = 500µs maximum.
Note 9: Guaranteed by gain-error test.
Note 10: The serial interface is inactive. VIH = VLOGIC, VIL = 0V.
Note 11: The serial interface is active. VIH = VLOGIC, VIL = 0V.
4
Maxim Integrated
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Typical Operating Characteristics
(VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0V, TA = +25°C, unless otherwise noted.)
-0.001
-0.003
-0.005
-0.007
-0.6
-1.0
-1.4
INPUT CODE
INPUT CODE
DIFFERENTIAL NONLINEARITY VS.
TEMPERATURE
OFFSET VOLTAGE VS.
TEMPERATURE
0.6
-40
MAX5631 toc05
-15
10
35
60
-16
85
-15
10
35
60
GAIN ERROR VS. TEMPERATURE
POSITIVE SUPPLY PSRR VS.
FREQUENCY
0.100
0.010
85
-40
-80
-70
0
-15
10
35
TEMPERATURE (°C)
Maxim Integrated
60
85
35
60
85
-90
-80
-70
-60
-50
-40
-50
-40
-30
-30
-20
-20
-10
-10
0
-40
10
NEGATIVE SUPPLY PSRR VS.
FREQUENCY
PSRR (dB)
PSRR (dB)
CODE = C168 hex
OFFSET CODE = 4F2C hex
0.01
-15
TEMPERATURE (°C)
-90
MAX5631 toc07
0.02
85
1
-60
0.03
60
0.0001
-40
TEMPERATURE (°C)
0.04
35
0.001
TEMPERATURE (°C)
0.05
10
CODE = 4F2C hex
EXTERNAL CLOCK MODE
NO CLOCK APPLIED
10
DROOP RATE (mV/s)
-14
-20
-40
-15
100
-18
0.5
0.002
DROOP RATE vs. TEMPERATURE
VDD = +8.55V
VSS = -4V
CODE = 4F2C hex
-12
OFFSET VOLTAGE (mV)
0.7
0.004
TEMPERATURE (°C)
-10
MAX5631 toc04
0.8
0.006
0
4018 11769 19520 27271 35021 42723 58268
0.9
MAX5631 toc03
MAX5631 toc02
-0.2
4018 11769 19520 27271 35021 42723 58268
1.0
DIFFERENTIAL NONLINEARITY (LSB)
0.2
0.008
MAX5631 toc06
0.001
0.6
MAX5631 toc09
0.003
1.0
0.010
MAX5361 toc08
INTEGRAL NONLINEARITY (%)
0.005
1.4
DIFFERENTIAL NONLINEARITY (LSB)
MAX5631 toc01
0.007
GAIN ERROR (%)
INTEGRAL NONLINEARITY VS.
TEMPERATURE
DIFFERENTIAL NONLINEARITY vs. CODE
INTEGRAL NONLINEARITY (%)
INTEGRAL NONLINEARITY vs. CODE
0.01
0.1
1
FREQUENCY (kHz)
10
100
0
0.001
0.01
0.1
1
10
100
FREQUENCY (kHz)
5
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Typical Operating Characteristics (continued)
(VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0V, TA = +25°C, unless otherwise noted.)
LOGIC SUPPLY CURRENT VS.
LOGIC INPUT HIGH VOLTAGE
600
500
1000
34
SUPPLY CURRENT (mA)
700
36
MAX5631 toc11
LOGIC SUPPLY CURRENT (µA)
800
SUPPLY CURRENT vs. TEMPERATURE
1200
MAX5631 toc10
LOGIC SUPPLY CURRENT (µA)
900
800
600
400
5.25
28
ISS
26
INTERFACE INACTIVE
0
5.00
30
22
fSCLK = 20MHz
INTERFACE INACTIVE
4.75
IDD
32
24
200
400
MAX5631 toc12
LOGIC SUPPLY CURRENT vs.
LOGIC SUPPLY VOLTAGE
20
2.0
5.50
2.5
LOGIC SUPLY VOLTAGE (V)
POSITIVE SETTLING TIME
(8V STEP)
3.0
3.5
4.0
4.5
5.0
-40
-15
10
35
TEMPERATURE (°C)
NEGATIVE SETTLING TIME
(8V STEP)
POSITIVE SETTLING TIME
(100mV STEP)
MAX5631 toc14
MAX5631 toc13
85
MAX5631 toc15
3.5V
3.5V
3.5V
ECLK
ECLK
ECLK
60
LOGIC INPUT HIGH VOLTAGE (V)
0
0
0
5V/div VOUT_
50mV/div
AC COUPLED
VOUT_
5V/div
VOUT_
1µs/div
1µs/div
NEGATIVE SETTLING TIME
(100mV STEP)
1µs/div
OUTPUT NOISE
MAX5631 toc16
MAX5631 toc17
3.5V
ECLK
0
OUT_
1mV/div
50mV/div
AC COUPLED
VOUT_
1µs/div
6
250µs/div
Maxim Integrated
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Pin Description
PIN
NAME
FUNCTION
TQFP
TQFN
1, 2
1, 2, 17, 34, 51, 68
N.C.
3
3
GS
4
4
VLDAC
5
5
RST
Reset Input
6
6
CS
Chip-Select Input
7
7
DIN
Serial Data Input
8
8
SCLK
9
9
VLOGIC
10
10
IMMED
11
11
ECLK
12
12
CLKSEL
13
13
DGND
Digital Ground
14
14
VLSHA
+5V Sample-and-Hold Power Supply
15, 25, 40, 55, 62
15, 26, 42, 58, 65
AGND
Analog Ground
16, 32, 46
16, 33, 48
VSS
17, 39, 48
18, 41, 50
VDD
Positive Power Supply
18, 33, 49
19, 35, 52
CL
Output Clamp Low Voltage
19
20
OUT0
Output 0
20
21
OUT1
Output 1
21
22
OUT2
Output 2
22
23
OUT3
Output 3
23
24
OUT4
Output 4
24
25
OUT5
Output 5
26
27
OUT6
Output 6
27
28
OUT7
Output 7
28
29
OUT8
Output 8
29
30
OUT9
Output 9
30
31
OUT10
Output 10
31, 47, 64
32, 49, 67
CH
34
36
OUT11
Output 11
35
37
OUT12
Output 12
36
38
OUT13
Output 13
37
39
OUT14
Output 14
38
40
OUT15
Output 15
41
43
OUT16
Output 16
42
44
OUT17
Output 17
43
45
OUT18
Output 18
44
46
OUT19
Output 19
45
47
OUT20
Output 20
Maxim Integrated
No Connection. Not internally connected.
Ground-Sensing Input
+5V DAC Power Supply
Serial Clock Input
+5V Logic Power Supply
Immediate Update Mode
External Sequencer Clock Input
Clock-Select Input
Negative Power Supply
Output Clamp High Voltage
7
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
TQFP
TQFN
50
53
OUT21
Output 21
51
54
OUT22
Output 22
52
55
OUT23
Output 23
53
56
OUT24
Output 24
54
57
OUT25
Output 25
56
59
OUT26
Output 26
57
60
OUT27
Output 27
58
61
OUT28
Output 28
59
62
OUT29
Output 29
60
63
OUT30
Output 30
61
64
OUT31
63
66
REF
—
—
Output 31
Reference Voltage Input
Exposed Pad (TQFN Only). Internally connected
to GND. Connect to a large ground plane to
maximize thermal performance. Not intended as
a electrical connection point.
EP
CH
OUT0
ECLK
CLKSEL
CLOCK
SAMPLEAND-HOLD
ARRAY
R
E
G
I
S
T
E
R
SAMPLE
DATA READY
SEQUENCER
OUT31
CL
READ ENABLE
SEQUENTIAL
ADDRESS
LAST
ADDRESS
CS
SCLK
DIN
IMMED
RST
2: 1
M
U
X
ADDR SELECT
SERIAL
INTERFACE
WRITE ENABLE
16 x 32
SRAM
R
E
G
I
S
T
E
R
GAIN AND
OFFSET
CORRECTION
16-BIT
DAC
GS
REF
MAX5631
MAX5632
MAX5633
D[15:0]
Figure 1. Functional Diagram
8
Maxim Integrated
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
tCSH1
CS
tCSHO
tCSSO
tCH
tCSS1
tCL
SCLK
tDH
tDS
B23
DIN
B22
B0
Figure 2. Serial Interface Timing Diagram
Detailed Description
Digital-to-Analog Converter
The MAX5631/MAX5632/MAX5633 16-bit digital-to-analog converters (DAC) are composed of two matched
sections. The four MSBs are derived through 15 identical matched resistors and the lower 12 bits are derived
through a 12-bit inverted R-2R ladder.
Sample-and-Hold Amplifiers
The MAX5631/MAX5632/MAX5633 contain 32 buffered
sample/hold circuits with internal hold capacitors.
Internal hold capacitors minimize leakage current,
dielectric absorption, feedthrough, and required board
space. MAX5631/MAX5632/MAX5633 provide a very low
1mV/s droop rate.
Output
The MAX5631/MAX5632/MAX5633 include output buffers
on each channel. The device contains output resistors in
series with the buffer output (Figure 3) for ease of output
filtering and capacitive load driving stability.
Output loads increase the analog supply current (IDD
and ISS). Excessively loading the outputs drastically
increases power dissipation. Do not exceed the maximum power dissipation specified in the Absolute
Maximum Ratings.
The maximum output voltage range depends on the
analog supply voltages available and the output clamp
voltages (see Output Clamp).
(VSS + 0.75V) ≤ VOUT _ ≤ (VDD - 2.4V)
The device has a fixed theoretical output range determined by the reference voltage, gain, and midscale offset.
The output voltage for a given input code is calculated
with the following:
⎛ code ⎞
VOUT = ⎜
⎟ × VREF × 5.2428 ⎝ 65535 ⎠
(1.6214 × VREF ) + VGS
where code is the decimal value of the DAC input
code, VREF is the reference voltage, and VGS is the
Table 1. Code Table
DAC INPUT CODE
MSB
LSB
1111 1111 1111 1111
NOMINAL OUTPUT
VOLTAGE (V)
1100 0111 0100 1010
6.15
Maximum output with VDD = 8.55V
1000 0000 0000 0000
2.5
Midscale output
9.0535
0100 1111 0010 1100
0
0010 1000 0001 1100
-2.0
0000 0000 0000 0000
-4.0535
Maxim Integrated
VREF = +2.5V
Full-scale output
VOUT_ = 0. All outputs default to this code after power-up
Minimum output with VSS = -2.75V
Zero-scale output
9
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
voltage at the ground-sense input. With a 2.5V reference, the nominal endpoints are -4.0535V and
+9.0535V (Table 1). Note that these are “virtual” internal endpoint voltages and cannot be reached with all
combinations of negative and positive power-supply
voltages. The nominal, useable DAC endpoint codes
for the selected power supplies may be calculated as:
lower endpoint code = 32768 - ((2.5V - (VSS + 0.75) /
200µV) (result ≥ 0)
upper endpoint code = 32768 + ((VDD - 2.4 - 2.5V) /
200µV) (result ≤ 65535)
The resistive voltage-divider formed by the output resistor (RO) and the load impedance (RL), scales the output voltage. Determine VOUT_ as follows:
RL
RL + RO
VOUT _ = VCHOLD × scaling factor
Scaling Factor =
Ground Sense
The MAX5631/MAX5632/MAX5633 include a groundsense input (GS), which allows the output voltages to
be referenced to a remote ground. The voltage at GS is
added to the output voltage with unity gain. Note that
the resulting output voltage must be within the valid
output voltage range set by the power supplies.
Output Clamp
The MAX5631/MAX5632/MAX5633 clamps the output
between two externally applied voltages. Internal
diodes at each channel restrict the output voltage to:
(VCH + 0.7V) ≥ VOUT _ ≥ (VCL − 0.7V)
The clamping diodes allow the MAX5631/MAX5632/
MAX5633 to drive devices with restricted input ranges.
The diodes also allow the outputs to be clamped during
power-up or fault conditions. To disable output clamping, connect CH to V DD and CL to V SS, setting the
clamping voltages beyond the maximum output voltage
range.
Serial Interface
The MAX5631/MAX5632/MAX5633 are controlled by an
SPI, QSPI, and MICROWIRE-compatible 3-wire interface. Serial data is clocked into the 24-bit shift register
in an MSB-first format, with the 16-bit DAC data preceding the 5-bit SRAM address, 2-bit control, and a fill
0 (Figure 4). The input word is framed by CS. The first
VREF
DAC
DATA
CH
GAIN
AND
OFFSET
16-BIT
DAC
RO
OUT_
AV = 1
CHOLD
RL
CL
ONE OF 32 SHA CHANNELS
GS
Figure 3. Analog Block Diagram
DATA
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01
MSB
ADDRESS
D0
A4
A3
A2
A1
CONTROL
A0
C1
C0
0
LSB
Figure 4. Input Word Sequence
10
Maxim Integrated
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Table 2. Channel/Output Selection
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OUT0 selected
OUT1 selected
OUT2 selected
OUT3 selected
OUT4 selected
OUT5 selected
OUT6 selected
OUT7 selected
OUT8 selected
OUT9 selected
OUT10 selected
OUT11 selected
OUT12 selected
OUT13 selected
OUT14 selected
OUT15 selected
OUT16 selected
OUT17 selected
OUT18 selected
OUT19 selected
OUT20 selected
OUT21 selected
OUT22 selected
OUT23 selected
OUT24 selected
OUT25 selected
OUT26 selected
OUT27 selected
OUT28 selected
OUT29 selected
OUT30 selected
1
1
1
1
1
OUT31 selected
rising edge of SCLK after CS goes low will clock in the
MSB of the input word.
When each serial word is complete, the value is stored
in the SRAM at the address indicated and the control
bits are saved. Note that data may be corrupted if CS is
not held low for an integer multiple of 24 bits.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. Their switching
threshold is compatible with TTL and most CMOS logic
levels.
Maxim Integrated
OUTPUT
Serial Input Data Format and
Control Codes
The 24-bit serial input format, shown in Figure 4, comprises of 16 data bits (D15–D0), five address bits (A4–A0),
two control bits (C1, C0), and a fill zero. The address
code selects the output channel as shown in Table 2. The
control code configures the device as follows:
1) If C1 = 1, Immediate Update Mode is selected.
If C1 = 0, Burst Mode is selected.
2) If C0 = 0, the internal sequencer clock is selected. If
C0 = 1, the external sequencer clock is selected.
This must be repeated with each data word to maintain external input.
11
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
The operating modes can also be selected externally
through CLKSEL and IMMED. In the case where the
control bit in the serial word and the external signal
conflict, the signal that is a logic “1” is dominant.
Modes of Operation
The MAX5631/MAX5632/MAX5633 feature three modes
of operation:
1) Sequence Mode
2) Immediate Update Mode
3) Burst Mode
Table 3. Update Mode
UPDATE MODE
UPDATE TIME
Immediate Update Mode
2/fSEQ
Burst Mode
33/fSEQ
Sequence Mode
Sequence mode is the default operating mode. The
internal sequencer continuously scrolls through the
SRAM, updating each of the 32 SHAs. At each SRAM
address location, the stored 16-bit DAC code is loaded
to the DAC. Once settled, the DAC output is acquired
by the corresponding SHA. Using the internal
sequencer clock, the process typically takes 320µs to
update all 32 SHAs (10µs per channel). Using an external sequencer clock the update process takes 128
clock cycles (four clock cycles per channel).
Immediate Update Mode
Immediate update mode is used to change the contents of a single SRAM location, and update the corresponding SHA output. In Immediate Update Mode, the
selected output is updated before the sequencer
resumes operation. Select Immediate Update Mode by
driving either IMMED or C1 high.
The sequencer is interrupted when CS is taken low. The
input word is then stored in the proper SRAM address.
The DAC conversion and SHA sample in progress are
completed transparent to the serial bus activity. The
SRAM location of the addressed channel is then modified with the new data. The DAC and SHA are updated
with the new voltage. The sequencer then resumes
scrolling at the interrupted SRAM address.
This operation can take up to two cycles of the 10µs
sequencer clock. Up to one cycle is needed to allow the
sequencer to complete the operation in progress before
it is freed to update the new channel. An additional
cycle is required to read the new data from memory,
update the DAC, and strobe the sample-and-hold. The
sequencer resumes scrolling from the location at which
it was interrupted. Normal sequencing is suppressed
while loading data, thus preventing other channels from
being refreshed. Under conditions of extremely frequent
Immediate Updates (i.e., 1000 successive updates), this
can result in unacceptable droop.
Figure 5 shows an example of an immediate update
operation. In this example, data for channel 20 is
loaded while channel 7 is being refreshed. The
sequencer operation is interrupted, and no other channels are refreshed as long as CS is held low. Once CS
returns high, and the remainder of an fSEQ period (if
any) has expired, channel 20 is updated to the new
data. Once channel 20 has been updated, the
sequencer resumes normal operation at the interrupted
channel 7.
1/fSEQ
SHA ARRAY
UPDATE
SEQUENCE
1/fSEQ
1
2
3
7
SKIP
20
7
8
9
SHA ARRAY
UPDATE
SEQUENCE
CHANNEL 20
UPDATED
7
SKIP
SKIP SKIP
7
8
5
6
7
33 CYCLES TO UPDATE
ALL CHANNELS
CS
INTERRUPTED
CHANNEL REFRESHED
LOAD ADDRESS 20
6
CS
LOAD MULTIPLE
ADDRESSES
DIN
DIN
24-BIT
WORD
Figure 5. Immediate Update Mode Timing Example
12
Figure 6. Burst Mode Timing Example
Maxim Integrated
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Burst Mode
Burst Mode allows multiple SRAM locations to be
loaded at high speed. During Burst Mode, the output
voltages are not updated until the data burst is complete and control returns to the sequencer. Select Burst
Mode by driving both IMMED and C1 low.
The sequencer is interrupted when CS is taken low. All
or part of the memory can be loaded while CS is low.
Each data word is loaded into its specified SRAM
address. The DAC conversion and SHA sample in
progress are completely transparent to the serial bus
activity. When CS is taken high, the sequencer resumes
scrolling at the interrupted SRAM address. New values
are updated when their turn comes up in the sequence.
After Burst Mode is used, it is
least one full sequencer loop
occur before the serial port is
ensures that all outputs are
sequencer is interrupted.
recommended that at
(320µs) is allowed to
accessed again. This
updated before the
Figure 6 shows an example of a burst mode operation.
As with the immediate update example, CS falls while
channel 7 is being refreshed. Data for multiple channels is loaded, and no channels are refreshed as long
as CS remains low. Once CS returns high, sequencing
resumes with channel 7 and continues normal refresh
operation. Thirty-three fSEQ cycles are required before
all channels have been updated.
External Sequencer Clock
An external clock may be used to control the
sequencer, altering the output update rate. The
sequencer runs at 1/4 the frequency of the supplied
clock (ECLK). The external clock option is selected by
driving either C0 or CLKSEL high.
When CLKSEL is asserted, the internal clock oscillator
is disabled. This feature allows synchronizing the
sequencer to other system operations, or shutting down
of the sequencer altogether during high-accuracy system measurements. The low 1mV/s droop of these
devices ensures that no appreciable degradation of the
output voltages occurs, even during extended periods
of time when the sequencer is disabled.
Maxim Integrated
Power-On Reset
A power-on reset (POR) circuit sets all channels to 0V
(code 4F2C hex) in sequence, requiring 320µs. This
prevents damage to downstream ICs due to arbitrary
reference levels being presented following system
power-up. This same function is available by driving
RST low. During the reset operation, the sequencer is
run by the internal clock, regardless of the state of
CLKSEL. The reset process cannot be interrupted, serial inputs will be ignored until the entire reset process is
complete.
Applications Information
Power Supplies and Bypassing
Grounding and power-supply decoupling strongly influence device performance. Digital signals may couple
through the reference input, power supplies, and
ground connection. Proper grounding and layout can
reduce digital feedthrough and crosstalk. At the device
level, a 0.1µF capacitor is required for the VDD, VSS,
and VL_ pins. They should be placed as close to the
pins as possible. More substantial decoupling at the
board level is recommended and is dependent on the
number of devices on the board (Figure 7).
The MAX5631/MAX5632/MAX5633 have three separate
+5V logic power supplies, VLDAC, VLOGIC, and VLSHA.
VLDAC powers the 16-bit digital-to-analog converter,
VLSHA powers the control logic of the SHA array, and
VLOGIC powers the serial interface, sequencer, internal
clock and SRAM. Additional filtering of V LDAC and
VLSHA improves the overall performance of the device.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
64 TQFP
C64+8
21-0083
90-0141
68 TQFN-EP
T6800+3
21-0142
90-0100
13
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
+10V
+5V
0.1µF
0.1µF
VLOGIC
VLDAC
VDD
VLSHA
REF
+2.5V
OUT0
GS
OUT1
CS
DIN
MAX5631
MAX5632
MAX5633
SCLK
IMMED
CLKSEL
ECLK
RST
OUT31
AGND
DGND
VSS
CL
0.1µF
-4V
Figure 7. Typical Operating Circuit
N.C. 1
N.C. 2
GS 3
52 CL
53 OUT21
54 OUT22
55 OUT23
56 OUT24
57 OUT25
58 AGND
59 OUT26
60 OUT27
61 OUT28
62 OUT29
63 OUT30
64 OUT31
65 AGND
66 VREF
68 N.C.
TOP VIEW
67 CH
Pin Configurations (continued)
51 N.C.
50 VDD
+
49 CH
48 VSS
VLDAC 4
47 OUT20
RST 5
CS 6
DIN 7
46 OUT19
45 OUT18
SCLK 8
VLOGIC
IMMED
ECLK
CLKSEL
44 OUT17
9
43 OUT16
MAX5631
MAX5632
MAX5633
10
11
42 AGND
41 VDD
12
40 OUT15
DGND 13
39 OUT14
VLSHA 14
38 OUT13
37 OUT12
AGND 15
VSS 16
N.C. 17
36 OUT11
34
33
32
31
OUT10
CH
VSS
N.C.
OUT7 28
OUT8 29
OUT9 30
OUT5 25
AGND 26
OUT6 27
OUT2 22
OUT3 23
OUT4 24
CL 19
OUT0 20
OUT1 21
VDD 18
35 CL
TQFN-EP
14
Maxim Integrated
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Revision History
REVISION
NUMBER
REVISION
DATE
0
10/01
Initial release
3
1/05
Updated the operating temperature range in the Ordering Information and updated
the Typical Operating Characteristics.
4
9/12
Removed leaded options and added lead-free notation in Ordering Information.
DESCRIPTION
PAGES
CHANGED
—
1, 2, 6
1
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 15
© 2012 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
