MAX5661GCB+

19-0741; Rev 1; 5/09 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules The MAX5661 single 16-bit DAC with precision highvoltage amplifiers provides a complete solution for programmable current and voltage-output applications. The output amplifiers swing to industry-standard levels of ±10V (voltage output) or source from 0mA (or from 4mA) to 20mA (current output). The voltage output (OUTV) drives resistive loads greater than 2kΩ and capacitive loads of up to 1.2µF. Voltage-output forcesense connections compensate for series protection resistors and field-wiring resistance. Short-circuit protection on the voltage output limits output current to 10mA (typ) sourcing or -11.5mA (typ) sinking. The current output (OUTI) drives resistive loads up to 37.5V (max) and inductive loads up to 1H. The MAX5661 provides either a current output or a voltage output. Only one output is active at any given time, regardless of the configuration. The MAX5661 voltage output operates with ±13.48V to ±15.75V supplies (VDDV, VSSV) and the current output operates with a single +13.48V to +40V supply (V DDI). A +4.75V to +5.25V digital supply (VCC) powers the rest of the internal circuitry. A buffered reference input accepts an external +4.096V reference voltage. Update the DAC outputs using software commands or the asynchronous LDAC input. An asynchronous CLR input sets the DAC outputs to the value stored in the clear register or to zero. The FAULT output asserts when the DAC’s current output is an open circuit, the DAC’s voltage output is a short circuit, or when the CLR input is low. The MAX5661 communicates through a 4-wire 10MHz SPI™-/QSPI™-/MICROWIRE™-compatible serial interface. The DOUT output allows daisy chaining of multiple devices. The MAX5661 is available in a 10mm x 10mm, 64-pin, LQFP package and operates over the -40°C to +105°C temperature range. Features ♦ 10-Bit Programmable Full-Scale Output Adjustment for Up to ±25% Over Range ♦ Programmable Voltage Output Unipolar Range: 0 to +10.24V ±25% Bipolar Range: ±10.24V ±25% ♦ Programmable Current Output Unipolar Low Range: 0 to 20.45mA Unipolar High Range: 3.97mA to 20.45mA ♦ Flexible Analog Supplies (See Table 16) ±13.48V to ±15.75V for Voltage Output +13.48V to +40V for Current Output ♦ Force-Sense Connections (Voltage Output) for Differential Voltage-Output Remote Sensing ♦ Voltage-Output Current Limit ♦ Dropout Detector Senses Out-of-Regulation Current Output ♦ CLR and LDAC Inputs for Asynchronous DAC Updates ♦ CLR Input Resets Output to Programmed Value or Zero Code ♦ FAULT Output Indicates Open-Circuited Current Output, Short-Circuited Voltage Output, or Clear State ♦ Temperature Drift Voltage Output: ±0.4ppm FSR/°C Current Output: ±7.9ppm FSR/°C ♦ Small 64-Pin LQFP Package (10mm x 10mm) Ordering Information SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Applications PART TEMP RANGE PIN-PACKAGE MAX5661GCB+ -40°C to +105°C 64 LQFP +Denotes a lead(Pb)-free/RoHS-compliant package. Industrial Analog Output Modules Industrial Instrumentation Programmable Logic Controls/Distributed Control Systems Process Control Pin Configuration and Typical Operating Circuit appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX5661 General Description MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules ABSOLUTE MAXIMUM RATINGS VDDCORE to VSSV ...................................................-0.3V to +42V VDDI to AGND.........................................................-0.3V to +42V VDDV to AGND........................................................-0.3V to +17V VSSV to AGND ........................................................-17V to +0.3V VDDI to VSSV ...........................................................-0.3V to +59V VCC to DGND ...........................................................-0.3V to +6V DGND, DUTGND, DUTGNDS, DACGND, DACGNDS to AGND ............................................-0.3V to +6V Digital Inputs (CS, DIN, SCLK, CLR, LDAC, CNF_) to DGND .....................................-0.3V to (VCC + 0.3V) Digital Outputs (DOUT, FAULT) to DGND.................................... ...............................-0.3V to the lesser of (VCC + 0.3V) or +6V REF to AGND............................................................-0.3V to +6V OUTV, SVP, SVN, COMPV to VSSV ...........-0.3V to (VDDV + 0.3V) OUTI, COMPI, OUTI4/0 to AGND ..............-0.3V to (VDDI + 0.3V) Maximum Current into Any Pin .......................................±100mA Continuous Power Dissipation (TA = +70°C) 64-Pin, 10mm x 10mm TQFP (derate 25mW/°C above +70°C)............................................................ 2000mW Junction-to-Ambient Thermal Resistance in Still Air (θJA) ...………………………………………….40°C/W Junction-to-Case Thermal Resistance (θJC)...................... 8°C/W Operating Temperature Range .........................-40°C to +105°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering,10s) ..................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = VDUTGND = VDACGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C. See the Typical Operating Circuit.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX ±0.2 ±4 UNITS STATIC PERFORMANCE Resolution 16 VOUT Integral Nonlinearity INL IOUT, VDDI = 40V, VSSV = VDDV = 0 (Note 2) 4–20mA IOUT, VDDI = VDDV = +15V, VSSV = -15V (Note 2) 4–20mA ±2 0 to 20mA ±6 DNL Guaranteed monotonic (Note 3) Zero-Scale Voltage Error VZSE OUTV 0 to 20mA mode Zero-Scale Current (Note 4) 4–20mA mode 0 to 20mA mode IZSE 4–20mA mode Voltage-Offset Error Drift 2 TCVOS OUTV ±6 0 to 20mA Differential Nonlinearity Zero-Scale Current Error (Note 4) Bits -1.0 ±10 LSB +1.0 LSB Unipolar ±0.01 ±3 Bipolar ±2.0 ±10 TA = +25°C -45 -30 -15 TA = TMIN to TMAX -60 -30 0 TA = +25°C 3.955 3.97 3.985 TA = TMIN to TMAX 3.94 3.97 4.00 TA = +25°C -15 ±2.0 +15 TA = TMIN to TMAX -30 ±2.0 +30 TA = +25°C -15 ±3.0 +15 TA = TMIN to TMAX -30 ±7.0 +30 Unipolar ±0.5 Bipolar ±0.2 ________________________________________________________________________________________ mV µA mA µA ppm of FSR/oC Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules (VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = VDUTGND = VDACGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C. See the Typical Operating Circuit.) (Note 1) PARAMETER Current-Offset Error Drift SYMBOL TCIOS CONDITIONS OUTI OUTV Gain Error GE OUTI OUTV Gain-Error Drift TCGE OUTI Power-Supply Rejection Ratio PSRR MIN TYP 0 to 20mA ±4 4–20mA ±4 MAX ppm of FSR/oC Unipolar ±2.5 ±10 Bipolar ±4.5 ±20 TA = +25°C ±8.0 ±70 TA = TMIN to TMAX ±40 ±130 Unipolar ±0.4 Bipolar ±0.4 0 to 20mA -7.9 4–20mA -8.6 UNITS mV µA ppm of FSR/oC OUTV, unipolar output, full-scale code, VDDV from +13.48V to +15.75V 20 200 OUTV, bipolar output, zero-scale code, VSSV from -13.48V to -15.75V 20 200 OUTI, full-scale code, VDDI from +13.48V to +40V, VSSV = -15.75V, VDDV = +15.75V 0.013 5 OUTI, full-scale code, VDDI from +13.48V to +40V, VDDV = VSSV = 0 0.017 5 0.050 1 µA 4.096 4.2 V µV/V µA/V REFERENCE INPUT Reference Input Current IREF Reference Input Voltage Range VREF 4.0 DYNAMIC PERFORMANCE Unipolar output, VOUTV = +10.48V 230 Bipolar output, VOUTV = ±10.48V 300 0 to 20mA range 132 4–20mA range 120 Voltage-Output Slew Rate COUTV = 100pF, ROUTV = 2kΩ, step = 20V, CEXT = 0nF 0.1 V/µs Current-Output Slew Rate LOUTI = 0, ROUTI = 500Ω, step = 20mA 0.15 mA/µs 1 µV•s Output-Voltage Noise at 10kHz en Output-Current Noise at 10kHz in OUTV Major Code Transition Glitch Digital Feedthrough From code 7FFFh to code 8000h Outputs set to zero scale, all digital inputs from 0V to VCC and back to 0V OUTI 0 to 20mA 2.0 4–20mA 2.0 nV/√Hz pA/√Hz nA•s OUTV 0.1 nV•s OUTI, RL = 500Ω 0.2 pA•s _______________________________________________________________________________________ 3 MAX5661 ELECTRICAL CHARACTERISTICS (continued) MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules ELECTRICAL CHARACTERISTICS (continued) (VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = VDUTGND = VDACGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C. See the Typical Operating Circuit.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SETTLING TIME Bipolar output, CCOMPV = 3.3nF, to 0.1% Voltage-Output Settling Time Bipolar output, CCOMPV = 0nF, to 0.1% Unipolar output, CCOMPV = 3.3nF, to 0.1% Unipolar output, CCOMPV = 0nF, to 0.1% 0 to 20.45mA range to 0.1% Current-Output Settling Time 3.97mA to 20.45mA range to 0.1% 4 COUTV = 1nF, ROUTV = 2kΩ 3 ms COUTV = 1.2µF, ROUTV = 2kΩ 5.44 COUTV = 100pF, ROUTV = 2kΩ 244 COUTV = 1nF, ROUTV = 2kΩ 1.8 COUTV = 1.2µF, ROUTV = 2kΩ 3.64 COUTV = 100pF, ROUTV = 2kΩ 130 µs ms ROUTI = 500Ω 1.5 LOUTI = 1mH 1.66 LOUTI = 10mH 1.66 LOUTI = 1H 1.97 ROUTI = 500Ω 1.43 LOUTI = 1mH 1.58 LOUTI = 10mH 1.58 LOUTI = 1H 1.73 ________________________________________________________________________________________ µs ms Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules (VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = VDUTGND = VDACGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C. See the Typical Operating Circuit.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VSSV + 3.0 VDDV 3.0 V Unipolar, VDDV = +13.48V, VSSV = -13.48V 0 +10.48 Bipolar, VDDV = +13.48V, VSSV = -13.48V -10.48 +10.48 OUTV OUTPUT OUTV Linear Output Voltage Range Default OUTV Output Voltage Ranges (0V to Full Scale) VOUT Minimum OUTV Output Voltage Range (FS to ADJ) VOUT Maximum OUTV Output Voltage Range (FS to ADJ) VOUT Unipolar +7.68 Bipolar ±7.68 Unipolar +12.8 Bipolar ±12.8 DC Output Impedance V V Ω 0.1 OUTV off or disabled, output leakage current from OUTV to AGND OUTV Off-State Leakage Current OUTV Short-Circuit Output Current ISC Minimum OUTV Resistive Load ROUTV Maximum OUTV Capacitive Load COUTV Sourcing Sinking 2.5 10 7 10 13 -18.0 -11.5 -9.0 Full-scale code 2 CCOMPV = 3.3nF CCOMPV = 0nF V µA mA kΩ 1.2 µF 1 nF OUTI OUTPUT OUTI Voltage Compliance Full-scale output, ROUTI = 1500Ω (Note 5) OUTI Output Current Range 0 to 20mA mode includes FS calibration (Note 4) 4–20mA mode includes FS calibration VDDI - 2.5 0 20.45 3.97 20.45 DC Output Impedance OUTI = full scale 45 OUTI Off-State Leakage Current OUTI off or disabled, 0V < VOUTI < VDDI 0.1 Current-Mode Dropout Detection VDDI - VOUTI, FAULT does not assert 1.3 V mA MΩ 10 µA V FEEDBACK SENSE BUFFER INPUTS Input Current VSSV + 1.7V < SVP, SVN < VDDV - 1.7V Input Voltage Range 0.05 VSSV + 1.7 SVP, SVN 1 µA VDDV - 1.7 V DIGITAL INPUTS Input High Voltage VIH VCC = 4.75V to 5.25V Input Low Voltage VIL VCC = 4.75V to 5.25V Input Capacitance CIN Input Leakage Current IIN 2.4 V 0.8 10 VIN = 0V or VCC -1 V pF +1 µA DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 400µA, except FAULT Output Low Voltage VOL VCC = 4.75V VCC - 0.5 V ISINK = 1.6mA 0.4 ISINK = 10mA 1 V _______________________________________________________________________________________ 5 MAX5661 ELECTRICAL CHARACTERISTICS (continued) MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules ELECTRICAL CHARACTERISTICS (continued) (VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = VDUTGND = VDACGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C. See the Typical Operating Circuit.) (Note 1) TYP MAX UNITS Output High Leakage Current PARAMETER SYMBOL FAULT only CONDITIONS MIN 0.1 2 µA Three-State Output Leakage Current DOUT only ±0.1 ±2 µA +5.25 V POWER SUPPLIES (see Table 16) VCC Supply Range VCC VDDV Supply Range VDDV +4.75 Only OUTV powered VSSV Supply Range VSSV +13.48 Only OUTI powered Both OUTV and OUTI powered +13.48 Only OUTV powered -15.75 Only OUTI powered Both OUTV and OUTI powered VDDI Only OUTI powered Both OUTV and OUTI powered VDDCORE IVDDV + IVDDI + Analog and Digital Supply Currents (OUTV Active) IVDDCORE IVSSV IAGND Analog and Digital Supply Currents (OUTI Active), 0 to 20mA Mode IVDDCORE IVSSV IAGND +13.48 +40.00 VDDV +40 VDDI Both OUTV and OUTI powered VDDV OUTI powered, VDDV = VSSV = AGND, VDDI = VDDCORE = +12V to +40V, VCC = +5.25V, zero code Analog and Digital Supply Currents (OUTI Active), 4–20mA Mode IVDDCORE IVSSV IAGND OUTI powered, VDDV = VSSV = AGND, VDDI = VDDCORE = +12V to +40V, VCC = +5.25V, zero code 4.5 -5 -3.0 -1.0 -4.0 -1.0 -4.0 IVCC IVDDV + IVDDCORE Analog and Digital Supply Currents (Either OUTV or OUTI Active) 6 IVSSV IAGND Both OUTV and OUTI powered, VDDV = VDDCORE = +15.75V, VSSV = -15.75V, VDDI = +40V, VCC = +5.25V, OUTV unloaded at zero code, all ditgital inputs at VCC or DGND IVCC V VDDV IVCC IVDDV + IVDDI + -13.48 Only OUTI powered OUTV powered, VDDV = VDDI = VDDCORE = +15.75V, VSSV = -15.75V, VCC = +5.25V, OUTV unloaded, all ditgital inputs at VCC or DGND V VDDV IVCC IVDDV + IVDDI + -13.48 -15.75 Only OUTV powered VDDCORE Supply Range V +15.75 AGND Only OUTV powered VDDI Supply Range +15.75 AGND V 6.5 mA -2.5 -1.6 0.03 0.2 2.8 5.5 mA -0.03 -2.1 0.03 0.2 6.8 9.5 mA -0.03 -2.1 0.03 0.2 4.2 6 -4.0 2.6 -4.0 -2.0 0.03 mA 0.2 IVDDI 0 to 20mA at zero code 1.3 2 IVDDI 4–20mA at zero code 5.3 6.5 ________________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules (VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, AGND = DGND = DUTGND = DACGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C. See Figure 1.) (Notes 1, 6) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Rise or Fall to CS Fall Setup Time tCSO 45 ns CS Fall to SCLK Rise or Fall Setup Time tCSS 40 ns SCLK Pulse-Width High tCH 45 ns SCLK Pulse-Width Low tCL 45 ns DIN to SCLK High Setup Time tDS 40 ns DIN to SCLK High Hold Time tDH 0 ns SCLK Period tCP 100 ns CS Pulse-Width High tCSW 100 ns CS High to SCLK High or Low Setup Time tCS1 45 ns SCLK High to CS Hold Time tCSH 45 ns SCLK Fall to DOUT Valid Propagation Delay tDO CDOUT = 100pF 100 ns CS Transitions to DOUT Enable/Disable Delay tDV CDOUT = 100pF 100 ns SCLK Fall or Rise to CS Rise Time tSCS 15 ns tLDL 40 ns tCSLD 80 ns LDAC Pulse-Width Low CS Rise to LDAC Rise Time Note 1: Devices are 100% production tested at TA = +25°C and +105°C. Operation to -40°C is guaranteed by design. Note 2: IOUT INL 100% production tested from 0 to 20mA only. Note 3: IOUT DNL guaranteed by VOUT DNL. Note 4: 0 to 20mA zero-scale current extrapolated by interpolation from full scale and code 192. See the Measuring Zero-Code Current (0 to 20mA Mode) section. Note 5: OUTI voltage compliance measured at VDDI = +33.22V. Note 6: When updating the DAC registers, allow 5µs before sending the next command. _______________________________________________________________________________________ 7 MAX5661 TIMING CHARACTERISTICS MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules CS tCSO tCL tCSH tCH tCSW tCP tSCS tCSS SCLK tDH tDS tCS1 DIN tDO tDV tDV DOUT tLDL tCSLD LDAC Figure 1. Serial-Interface Timing Diagram Typical Operating Characteristics (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) 0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 16,384 32,768 49,152 DIGITAL INPUT CODE 65,536 MAX5661 toc03 MAX5661 toc02 4 3 0 -0.2 5 INL (LSB) 0.4 0.2 0 8 0.6 0.4 0 BIPOLAR VOLTAGE OUTPUT 0.8 INL (LSB) INL (LSB) 0.6 1.0 MAX5661 toc01 UNIPOLAR VOLTAGE OUTPUT 0.8 INL vs. DIGITAL INPUT CODE INL vs. DIGITAL INPUT CODE INL vs. DIGITAL INPUT CODE 1.0 2 1 0 -1 0 TO 20mA CURRENT OUTPUT -2 0 16,384 32,768 49,152 DIGITAL INPUT CODE 65,536 0 16,384 32,768 49,152 DIGITAL INPUT CODE ________________________________________________________________________________________ 65,536 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules INL vs. DIGITAL INPUT CODE 2 3 0 -1 0 -2 16,384 32,768 49,152 4–20mA CURRENT OUTPUT -2 0 65,536 16,384 32,768 49,152 65,536 0 0.4 -0.1 INL (LSB) INL (LSB) 0 0 MIN INL -0.1 -0.2 0.2 MAX INL 0.1 -0.3 49,152 -50 65,536 -25 0 1.5 INL (LSB) INL (LSB) 2.0 MAX INL 1.0 0.5 MIN INL -0.5 -1.0 0 25 50 75 TEMPERATURE (°C) 75 100 -50 125 -25 0 100 125 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 25 50 75 100 125 TEMPERATURE (°C) INL vs. TEMPERATURE 0 to 20mA CURRENT OUTPUT VDDI = VDDCORE = +40V VDDV = VSSV = 0V 3.0 4–20mA CURRENT OUTPUT 2.5 2.0 INL (LSB) MAX5661 toc09 0 TO 20mA CURRENT OUTPUT 2.5 -25 50 INL vs. TEMPERATURE INL vs. TEMPERATURE 3.0 -50 25 TEMPERATURE (°C) DIGITAL INPUT CODE 0 BIPOLAR VOLTAGE OUTPUT -0.4 MAX5661 toc10 32,768 MIN INL -0.3 UNIPOLAR VOLTAGE OUTPUT -0.4 16,384 0 -0.2 -0.3 -0.5 0.1 -0.1 -0.2 -0.4 MAX INL 0.3 0.2 0.1 65,536 0.5 MAX5661 toc07 0.3 0.2 49,152 INL vs. TEMPERATURE 0.4 MAX5661 toc06 ALL MODES 0.3 32,768 DIGITAL INPUT CODE INL vs. TEMPERATURE DNL vs. DIGITAL INPUT CODE 0.5 0 16,384 DIGITAL INPUT CODE DIGITAL INPUT CODE 0.4 4–20mA CURRENT OUTPUT VDDI = VDDCORE = +40V VDDV = VSSV = 0V -1 -3 -2 0 1 MAX5661 toc08 0 TO 20mA CURRENT OUTPUT VDDI = VDDCORE = +40V VDDV = VSSV = 0V 2 MAX5661 toc11a 4 3 2 1 INL (LSB) 5 0 -1 DNL (LSB) 4 1 INL (LSB) INL (LSB) 7 6 5 MAX5661 toc05a MAX5661 toc04 9 8 INL vs. DIGITAL INPUT CODE 3 MAX5661 toc05b INL vs. DIGITAL INPUT CODE 10 MAX INL 1.5 1.0 MAX INL 0.5 MIN INL 0 MIN INL -0.5 -1.0 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) _______________________________________________________________________________________ 9 MAX5661 Typical Operating Characteristics (continued) (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) Typical Operating Characteristics (continued) (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) ALL MODES 0.3 0.1 MAX DNL 0 MIN DNL -0.1 MIN INL 2 CURRENT OUTPUT = 0 TO 20mA ZERO-SCALE ERROR (LSB) DNL (LSB) 0.2 MAX INL 3 -0.2 -0.3 -25 0 25 50 75 100 125 1 0 -1 -2 UNIPOLAR VOLTAGE OUTPUT -3 BIPOLAR VOLTAGE OUTPUT -4 -0.4 -50 -5 -50 -25 0 25 50 75 100 125 -50 -25 0 25 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) VOLTAGE-OUTPUT FULL-SCALE VOLTAGE vs. TEMPERATURE CURRENT-OUTPUT FULL-SCALE CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE (UNIPOLAR VOLTAGE OUTPUT) BIPOLAR VOLTAGE OUTPUT 10.4775 4.0 20.55 20.50 20.45 20.40 MAX5661 toc16 CURRENT OUTPUT = 0 TO 20mA 3.6 3.2 SUPPLY CURRENT (mA) 10.4800 20.60 MAX5661 toc15 MAX5661 toc14 UNIPOLAR VOLTAGE OUTPUT 10.4825 IVSSV 2.8 IVDDV 2.4 2.0 1.6 1.2 0.4 20.30 10.4750 -50 -25 0 25 50 75 100 IVDDI 0 -50 125 IVDDCORE 0.8 20.35 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) SUPPLY CURRENT vs. TEMPERATURE (BIPOLAR VOLTAGE OUTPUT) SUPPLY CURRENT vs. TEMPERATURE (0 TO 20mA CURRENT OUTPUT) SUPPLY CURRENT vs. TEMPERATURE (4–20mA CURRENT OUTPUT) 3.2 2.8 2.4 2.0 1.6 1.2 0.8 2.8 IVSSV IVDDV IVDDCORE 2.4 2.0 1.6 1.2 0.8 0.4 0 -25 0 25 50 75 TEMPERATURE (°C) 100 125 IVDDI 4.0 3.5 3.0 IVSSV 2.5 2.0 1.5 0 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 IVDDV IVDDCORE IOUTI = 4mA RL = 500Ω 0.5 IVDDI 0 -50 4.5 1.0 0.4 IVDDI MAX5661 toc18b IVDDCORE SUPPLY CURRENT (mA) IVDDV 3.6 SUPPLY CURRENT (mA) IVSSV 3.2 5.5 5.0 MAX5661 toc18a 3.6 4.0 MAX5661 toc17 4.0 SUPPLY CURRENT (mA) 50 TEMPERATURE (°C) 10.4850 10 MAX5661 toc13 4–20mA CURRENT OUTPUT VDDI = VDDCORE = +40V VDDV = VSSV = 0V MAX5661 toc12 0.4 MAX5661 toc11b 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 ZERO-SCALE ERROR vs. TEMPERATURE DNL vs. TEMPERATURE FULL-SCALE CURRENT (mA) INL (LSB) INL vs. TEMPERATURE FULL-SCALE VOLTAGE (V) MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules 0 25 50 75 TEMPERATURE (°C) _______________________________________________________________________________________ 100 125 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules SUPPLY CURRENT vs. TEMPERATURE (0 TO 20mA CURRENT OUTPUT) 2.8 IVDDCORE 2.4 2.0 1.6 1.2 IOUTI = 0mA VDDI = VDDCORE = +40V -50 -25 0 25 IVDDI 34 32 3.5 3.0 2.5 2.0 50 1.0 0.5 0 75 100 125 TEMPERATURE (°C) IOUTI = 4mA VDDI = VDDCORE = +40V CL = 0.47µF 26 -50 -25 0 25 20 18 50 75 100 125 VCC = +5.25V ALL INPUTS CONNECTED TO VCC -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) UNIPOLAR VOLTAGE-OUTPUT, ZS-TO-FS TRANSITION vs. CL (CCOMP = 3.3nF) UNIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 0nF) MAX5661 toc21 CS 5V/div CL = 100nF 28 22 IVDDI MAX5661 toc20 CL = 100pF 30 24 TEMPERATURE (°C) UNIPOLAR VOLTAGE-OUTPUT, ZS-TO-FS TRANSITION vs. CL (CCOMP = 0nF) MAX5661 toc19 IVDDCORE 36 1.5 0.8 0 5.0 4.5 4.0 38 IVCC (μA) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 3.2 DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX5661 toc18d 3.6 0.4 6.0 5.5 MAX5661 toc18c 4.0 SUPPLY CURRENT vs. TEMPERATURE (4–20mA CURRENT OUTPUT) MAX5661 toc22 CS 5V/div CS 5V/div OUTV 2V/div OUTV 100mV/div CL = 100pF OUTV 2V/div CL = 0.47µF CL = 1µF CL = 1µF CL = 1.8µF CL = 1.8µF CL = 100pF CL = 100nF RL = 2kΩ RL = 2kΩ 400µs/div 400µs/div 100μs/div UNIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 3.3nF) UNIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 0nF) RL = 2kΩ ZS-TO-FS TRANSITION UNIPOLAR VOLTAGE-OUTPUT, FS-TO-ZS TRANSITION (CCOMP = 0nF) MAX5661 toc25 MAX5661 toc24 MAX5661 toc23 RL = 2kΩ CS 5V/div CS 5V/div OUTV 100mV/div OUTV 100mV/div CL = 100pF CL = 1μF CL = 1μF RL = 2kΩ ZS-TO-FS TRANSITION 400μs/div CS 5V/div CL = 100nF CL = 0.47μF OUTV 2V/div CL = 1μF RL = 2kΩ ZS-TO-FS TRANSITION 400μs/div CL = 1.8μF 400μs/div ______________________________________________________________________________________ 11 MAX5661 Typical Operating Characteristics (continued) (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules Typical Operating Characteristics (continued) (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) UNIPOLAR VOLTAGE-OUTPUT, FS-TO-ZS TRANSITION (CCOMP = 3.3nF) UNIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 3.3nF) UNIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 0nF) MAX5661 toc26 MAX5661 toc28 MAX5661 toc27 CS 5V/div CS 5V/div CL = 100pF CS 5V/div CL = 100pF RL = 2kΩ CL = 1μF OUTV 2V/div CL = 100pF CL = 0.47µF OUTV 100mV/div OUTV 100mV/div CL = 100nF CL = 1µF RL = 2kΩ FS-TO-ZS TRANSITION RL = 2kΩ FS-TO-ZS TRANSITION CL = 1.8µF 400µs/div UNIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 0nF) MAX5661 toc29 100μs/div 400μs/div BIPOLAR VOLTAGE-OUTPUT, ZS-TO-FS TRANSITION (CCOMP = 0nF) BIPOLAR VOLTAGE-OUTPUT, ZS-TO-FS TRANSITION (CCOMP = 3.3nF) MAX5661 toc31 MAX5661 toc30 CS 5V/div CS 5V/div CS 5V/div CL = 1μF RL = 2kΩ FS-TO-ZS TRANSITION CL = 100nF CL = 0.47µF OUTV 100mV/div CL = 100pF OUTV 5V/div CL = 0.47µF CL = 1µF CL = 1µF CL = 1.8µF CL = 1.8µF RL = 2kΩ RL = 2kΩ 400μs/div 1.0ms/div BIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 0nF) BIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 3.3nF) 1.0ms/div CL = 100nF CS 5V/div OUTV 100mV/div CL = 100pF 12 MAX5661 toc34 CS 5V/div CS 5V/div OUTV 100mV/div OUTV 100mV/div CL = 1μF RL = 2kΩ ZS-TO-FS TRANSITION 100μs/div BIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 0nF) MAX5661 toc33 MAX5661 toc32 CL = 100pF RL = 2kΩ 1.0ms/div OUTV 5V/div CL = 1μF RL = 2kΩ ZS-TO-FS TRANSITION 1.0ms/div _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules BIPOLAR VOLTAGE-OUTPUT, FS-TO-ZS TRANSITION (CCOMP = 0nF) BIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 0nF) BIPOLAR VOLTAGE-OUTPUT, FS-TO-ZS TRANSITION (CCOMP = 3.3nF) MAX5661 toc35 MAX5661 toc37 MAX5661 toc36 CS 5V/div CS 5V/div CL = 100pF CL = 100pF CL = 100pF OUTV 5V/div CL = 0.47μF CL = 1μF CL = 0.47µF CL = 1µF CS 5V/div OUTV 5V/div CL = 100nF OUTV 100mV/div CL = 1.8µF CL = 1.8μF RL = 2kΩ RL = 2kΩ FS-TO-ZS TRANSITION RL = 2kΩ 1.0ms/div 1.0ms/div 100μs/div BIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 3.3nF) BIPOLAR VOLTAGE-OUTPUT SETTLING TIME (CCOMP = 0nF) 0 TO 20mA CURRENT-OUTPUT, ZS-TO-FS TRANSITION vs. INDUCTIVE LOAD MAX5661 toc39 MAX5661 toc38 MAX5661 toc40 CS 5V/div CS 5V/div CS 5V/div OUTI 4mA/div LL = 1H CL = 1μF RL = 2kΩ FS-TO-ZS TRANSITION CL = 100pF CL = 1μF LL = 0mH, LL = 100mH OUTV 100mV/div OUTV 100mV/div RL = 2kΩ FS-TO-ZS TRANSITION 1.0ms/div 1.0ms/div 0 TO 20mA CURRENT-OUTPUT, ZS-TO-FS SETTLING TIME 0 TO 20mA CURRENT-OUTPUT, FS-TO-ZS TRANSITION vs. INDUCTIVE LOAD 400µs/div MAX5661 toc42a MAX5661 toc41 MAX5661 toc42b CS 5V/div CS 5V/div OUTI 4mA/div OUTV 200µA/div LL = 0mH, LL = 100mH 0 TO 20mA CURRENT-OUTPUT, FS-TO-ZS SETTLING TIME CS 5V/div LL = 0mH LL = 100mH LL = 0mH LL = 1H 400µs/div OUTI 200µA/div LL = 1H LL = 100mH LL = 1H 2ms/div 2ms/div ______________________________________________________________________________________ 13 MAX5661 Typical Operating Characteristics (continued) (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules Typical Operating Characteristics (continued) (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) 0 TO 20mA CURRENT-OUTPUT, ZS-TO-FS TRANSITION vs. INDUCTIVE LOAD 0 TO 20mA CURRENT-OUTPUT, FS-TO-ZS TRANSITION vs. INDUCTIVE LOAD 0 TO 20mA CURRENT-OUTPUT, ZS-TO-FS SETTLING TIME MAX5661 toc43a MAX5661 toc43c MAX5661 toc43b CS 5V/div CS 5V/div CS 5V/div VDDI = VDDCORE = +40V VDDV = VSSV = 0V LL = 1H LL = 0mH, 100mH LL = 1H OUTI 4mA/div OUTI 200µA/div OUTI 4mA/div LL = 1H LL = 100mH LL = 0mH, LL = 100mH LL = 0mH VDDI = VDDCORE = +40V VDDV = VSSV = 0V VDDI = VDDCORE = +40V VDDV = VSSV = 0V 400µs/div 2ms/div OUTV OUTPUT VOLTAGE vs. LOAD CURRENT (SOURCING) OUTV OUTPUT VOLTAGE vs. LOAD CURRENT (SINKING) 0 TO 20mA CURRENT-OUTPUT, FS-TO-ZS SETTLING TIME MAX5661 toc43d UNIPOLAR OUTV MODE CS 5V/div 10.482 LL = 0mH 80 60 VDDI = VDDCORE = +40V VDDV = VSSV = 0V BIPOLAR OUTV MODE 10.478 20 10.474 0 10.472 -20 UNIPOLAR OUTV MODE 0 1 OUTI OUTPUT CURRENT vs. OUTPUT VOLTAGE 10 5 3 4 5 6 7 8 9 10 11 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 SOURCE CURRENT (mA) SINK CURRENT (mA) OUTI OUTPUT CURRENT vs. OUTPUT VOLTAGE UNIPOLAR VOLTAGE-OUTPUT, POSITIVE MAJOR CARRY TRANSITION GLITCH (CCOMP = 3.3nF) MAX5661 toc48 MAX5661 toc47 20 IOUTI (mA) 15 2 25 MAX5661 toc46 20 40 10.476 2ms/div 25 VOUTV (V) OUTI 200µA/div LL = 1H VOUTV (V) 10.480 LL = 100mH IOUTI (mA) 100 MAX5661 toc44 10.484 MAX5661 toc45 400µs/div CS 5V/div 15 10 OUTV 1mV/div 5 VDDCORE = VDDI = +24V 0 0 5 10 15 OUTPUT VOLTAGE (V) 14 VDDCORE = VDDI = +40V 0 20 25 0 5 10 15 20 25 30 35 40 45 OUTPUT VOLTAGE (V) _______________________________________________________________________________________ 100µs/div Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules UNIPOLAR VOLTAGE-OUTPUT, NEGATIVE MAJOR CARRY TRANSITION GLITCH (CCOMP = 3.3nF) MAX5661 toc49 BIPOLAR VOLTAGE-OUTPUT, POSITIVE MAJOR CARRY TRANSITION GLITCH (CCOMP = 3.3nF) MAX5661 toc50 BIPOLAR VOLTAGE-OUTPUT, NEGATIVE MAJOR CARRY TRANSITION GLITCH (CCOMP = 3.3nF) MAX5661 toc51 CS 5V/div CS 5V/div CS 5V/div OUTV 1mV/div OUTV 1mV/div OUTV 1mV/div 100µs/div 100µs/div 100µs/div UNIPOLAR VOLTAGE-OUTPUT, POSITIVE MAJOR CARRY TRANSITION GLITCH (CCOMP = 0nF) UNIPOLAR VOLTAGE-OUTPUT, NEGATIVE MAJOR CARRY TRANSITION GLITCH (CCOMP = 0nF) BIPOLAR VOLTAGE-OUTPUT, POSITIVE MAJOR CARRY TRANSITION GLITCH (CCOMP = 0nF) MAX5661 toc53 MAX5661 toc52 MAX5661 toc54 CS 5V/div CS 5V/div CS 5V/div OUTV 50mV/div OUTV 50mV/div OUTV 50mV/div 4µs/div 4µs/div 4µs/div BIPOLAR VOLTAGE-OUTPUT, NEGATIVE MAJOR CARRY TRANSITION GLITCH (CCOMP = 0nF) 0 TO 20mA CURRENT-OUTPUT, NEGATIVE MAJOR CARRY TRANSITION GLITCH 0 TO 20mA CURRENT-OUTPUT, POSITIVE MAJOR CARRY TRANSITION GLITCH MAX5661 toc55 MAX5661 toc57 MAX5661 toc56 CS 5V/div OUTV 50mV/div 4µs/div MAX5661 Typical Operating Characteristics (continued) (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) 100µs/div CS 5V/div CS 5V/div OUTI 2µA/div OUTI 2µA/div 100µs/div ______________________________________________________________________________________ 15 Typical Operating Characteristics (continued) (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) VCC SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE 4–20mA CURRENT-OUTPUT, NEGATIVE MAJOR CARRY TRANSITION GLITCH MAX5661 toc58 MAX5661 toc59 10,000 MAX5661 toc60 4–20mA CURRENT-OUTPUT, POSITIVE MAJOR CARRY TRANSITION GLITCH VCC = 5.25V CS 5V/div CS 5V/div OUTI 2µA/div OUTI 2µA/div IVCC (µA) 1000 100 10 100µs/div 100µs/div 0 1 2 3 4 DIGITAL INPUT VOLTAGE (V) BIPOLAR VOLTAGE-OUTPUT DIGITAL FEEDTHROUGH UNIPOLAR VOLTAGE-OUTPUT DIGITAL FEEDTHROUGH MAX5661 toc62 MAX5661 toc61 CS = VCC DIN = SCLK f = 1MHz CS = VCC DIN = SCLK f = 1MHz DIN, SCLK 5V/div DIN, SCLK 5V/div OUTV 2mV/div OUTV 1mV/div 200ns/div 200ns/div CURRENT-OUTPUT DIGITAL FEEDTHROUGH FULL-SCALE CURRENT vs. FULL-SCALE OUTPUT CURRENT TRIM CODE DIN, SCLK 5V/div OUTI 2µA/div 200ns/div 27 26 25 24 23 22 21 20 19 18 17 16 15 14 MAX5661 toc64 MAX5661 toc63 CS = VCC DIN = SCLK f = 1MHz FULL-SCALE CURRENT (mA) MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules 0 256 512 768 1024 CODE 16 _______________________________________________________________________________________ 5 6 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules NEGATIVE FULL-SCALE VOLTAGE vs. FULL-SCALE OUTPUT TRIM CODE POSITIVE FULL-SCALE VOLTAGE vs. FULL-SCALE OUTPUT TRIM CODE 12 11 10 9 8 MAX5661 toc66 -7 FULL-SCALE VOLTAGE (V) 13 FULL-SCALE VOLTAGE (V) -6 MAX5661 toc65 14 -8 -9 -10 -11 -12 -13 7 UNIPOLAR OR BIPOLAR MODE -14 6 0 256 512 768 1024 0 256 512 768 1024 CODE CODE Pin Description PIN NAME 1, 3, 5, 7, 8, 10, 15–20, 29–34, 36, 38, 42, 44, 46–52, 58, 61–64 FUNCTION N.C. 2 OUTI DAC Current-Source Output. OUTI sources either from 0 to 20mA or from 4–20mA. 4 VDDI DAC Current-Output Positive Supply. Connect VDDI to a power supply between +13.48V and +40V to power the DAC current-output (OUTI) buffer. Bypass VDDI with a 0.1µF capacitor to AGND, as close as possible to the device. 6 COMPI OUTI Noise-Limiting Capacitor Connection. Connect a 22nF capacitor from COMPI to VDDI to reduce transient noise at OUTI. 9 OUTI4/0 Current-Output Range Selection Input. Connect OUTI4/0 to AGND to select the 0 to 20mA OUTI current-output range. Connect OUTI4/0 to VDDI to select the 4–20mA OUTI current-output range. The OUTI current range can also be set by software. When using software to set the OUTI current range, connect OUTI4/0 to AGND. 11 REF Buffered Voltage Reference Input. Connect an external +4.096V voltage reference to REF. Bypass REF with a 0.1µF capacitor to DACGND, as close as possible to the device. Use a 1kΩ resistor in series to the reference input for optimum performance. 12 DACGND 13 DACGNDS 14 CNF1 Voltage/Current Configuration Input. CNF1 and CNF0 control the OUTV and OUTI outputs. See Tables 13 and 14. 21 CNF0 Voltage/Current Configuration Input. CNF0 and CNF1 control the OUTV and OUTI outputs. See Tables 13 and 14. No Connection. Not internally connected. DAC Analog Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together on a low-noise ground plane with a star connection. DAC Analog Sense Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together on a low-noise ground plane with a star connection. ______________________________________________________________________________________ 17 MAX5661 Typical Operating Characteristics (continued) (Typical Operating Circuit, VCC = +5V, CCOMPI = 22nF, VDDV = VDDCORE = +15V, VSSV = -15V, VDDI = +24V, VREF = +4.096V, VAGND = VDGND = 0V, RSERIES = 47Ω, OUTV loaded with 2kΩ || 100pF to AGND, OUTI loaded with 500Ω to AGND, TA = +25°C.) Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules MAX5661 Pin Description (continued) PIN 18 NAME 22 DIN 23 SCLK 24 CS 25 DGND FUNCTION Serial-Data Input. Data is clocked into the serial interface on the rising edge of SCLK. Serial-Clock Input Active-Low Chip-Select Input. Drive CS low to enable the serial interface. Drive CS high to disable the serial interface. DOUT is high impedance when CS is high. Digital Ground 26 VCC Digital Power Supply. Connect VCC to a power supply between +4.75V and +5.25V. Bypass VCC with a 0.1µF capacitor to DGND, as close as possible to the device. 27 LDAC Active-Low Asynchronous Load DAC Input. Drive LDAC low to transfer the contents of the input register to the DAC register to immediately update the output. Connect LDAC to VCC if unused. 28 FAULT Active-Low Open-Drain Fault Output. FAULT asserts low for an OUTI open-circuit condition, an OUTV short-circuit condition, or when the CLR input is low (see Table 12 and Figure 9). Ignore the FAULT pin function in single supply mode. 35 DOUT Serial Data Output. Data transitions at DOUT on SCLK’s falling edge. DOUT is high impedance when CS is high. Use DOUT to read the shift register contents or for daisy chaining multiple MAX5661 devices. 37 CLR Active-Low Clear Input. Drive CLR low to set the DAC code to the value stored in the clear register, to 0V in voltage mode, or 0mA/4mA depending on the output current mode. Program the contents of the clear register through the serial interface. Enable and disable the CLR input through the control register’s CLREN bit (see Table 4). 39 VDDCORE DAC Core Positive Supply. Connect VDDCORE to VDDI or VDDV (see Table 16). Bypass VDDCORE with a 0.1µF capacitor to AGND, as close as possible to the device. 40 DUTGNDS DUT Analog Sense Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together on a low-noise ground plane with a star connection. 41 DUTGND 43 COMPV 45 AGND DUT Analog Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together on a low-noise ground plane with a star connection. OUTV Amplifier Compensation Feedback Node. Connect a 3.3nF capacitor from OUTV to COMPV when OUTV drives capacitive loads of up to 1.2µF. Leave COMPV open for faster response time. Analog Ground 53 SVP Remote Ground Sense Input. Connect SVP to the bottom terminal of ROUTV. See the Typical Operating Circuit. 54, 59 I.C. Internal Connection. Leave unconnected. 55 VSSV DAC Voltage-Output Negative Power Supply. Always connect VSSV to a power supply between -13.48V and -15.75V. Bypass VSSV with a 0.1µF capacitor to AGND, as close as possible to the device. 56 OUTV DAC Unipolar/Bipolar Voltage Output. OUTV provides 0 to +10.48V in unipolar mode and -10.48V to +10.48V in bipolar mode. 57 VDDV DAC Voltage-Output Positive Power Supply. Connect VDDV to a power supply between +13.48V and +15.75V. Bypass VDDV with a 0.1µF capacitor to AGND, as close as possible to the device. 60 SVN Remote Voltage Sense Input. Connect to the top terminal of ROUTV. See the Typical Operating Circuit. _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules The MAX5661 single 16-bit DAC with precision high-voltage amplifiers provides a complete solution for programmable current and voltage-output applications. The programmable output amplifiers swing to industry-standard voltage levels of ±10V or current levels from 0mA (or from 4mA) to 20mA. The OUTV voltage output drives resistive loads greater than 2kΩ and capacitive loads up to 1.2µF. Force and sense connections on the voltage output compensate for series protection resistors and field wiring resistance. Short-circuit protection on the voltage output limits output current. The OUTI current output drives resistive loads from 0Ω and higher, up to a compliance voltage of (VDDI - 2.5V). The OUTI current output also drives inductive loads up to 1H. The MAX5661 provides a current output or a voltage output, with only one output active at any given time. The MAX5661 operates with ±13.48V to ±15.75V dual supplies (V DDV , V SSV ) for the voltage output and a +13.48V to +40V single supply (VDDI) for the current output (see Table 16). The +4.75V to +5.25V digital supply (VCC) powers the digital circuitry and VDDCORE powers the rest of the internal analog circuitry. A buffered reference input accepts a +4.096V reference voltage. The LDAC and CLR inputs asynchronously update the DAC outputs. CLR sets the DAC code to the value stored in the clear register (software clear), or to zero scale (hardware clear). The FAULT output asserts for an open-circuit current output, a short-circuit voltage output, or a clear state condition when CLR is low. The power-on reset circuitry guarantees the outputs remain off at power-up and all register bits are set to zero to ensure a glitchless power-up sequence. A 10MHz SPI-/QSPI-/MICROWIRE-compatible serial interface programs the DAC outputs and configures the device. The DOUT output allows shift-register reads or daisy chaining of several devices. The double-buffered interface includes an input register and a DAC register. Use software commands or the asynchronous LDAC input to transfer the input register contents to the DAC register and update the DAC outputs. 4-Wire SPI-Compatible Serial Interface The MAX5661 communicates through a serial interface compatible with SPI, QSPI, and MICROWIRE devices. For SPI, ensure that the SPI bus master (typically a microcontroller (µC)) runs in master mode to generate the serial-clock signal. Set the SCLK frequency to 10MHz or less, and set the clock polarity (CPOL) and phase (CPHA) in the µC control registers to the same value. The MAX5661 operates with SCLK idling high or low, and thus operates with CPOL = CPHA = 0 (see Figure 2) or CPOL = CPHA = 1 (see Figure 3). Force CS low to input data at DIN on the rising edge of SCLK. Output data at DOUT updates on the falling edge of SCLK (see Figure 1). A high-to-low transition on CS initiates the 24-bit data input cycle. Once CS is low, write an 8-bit command byte (MSB first) at DIN to send data to the appropriate internal register (see Tables 1, 2, and 3). C7 is the MSB of the command byte and C0 is the LSB. Following the command byte, write 2 data bytes containing bits D15–D0. D15 is the MSB of the 2 data bytes and D0 is the LSB (see Figure 4 and the Register Descriptions section). Data loads into the shift register 1 bit at a time. Write the data as one continuous 24-bit stream, always keeping CS low throughout the entire 24-bit word. The MAX5661 stores the 24 most recent bits received, including bits from previous transmission(s). Ensure SCLK has 24 rising and falling edges between CS falling low to CS returning high. Data loads into the shift register on the rising edge of SCLK. Once CS returns high, data transfers from the shift register into the appropriate internal register. When reading data, write an 8-bit command byte and 16 data bits at DIN. On the following 24-bit sequence, read out the shift register’s contents (command byte and the 16 data bits) at DOUT (see Figure 5). Data transitions at DOUT on the falling edge of SCLK. While reading data at DOUT on the second 24-bit sequence, load another command byte and 2 data bytes at DIN or write a no-operation command. DOUT three-states when CS is high. The DAC outputs update on the rising edge of CS after writing to the DAC register or by pulling LDAC low. Daisy chain multiple devices by connecting the first DOUT to the second DIN, and so forth. Daisy chaining allows communication with multiple MAX5661 devices using single CS and SCLK signals. See the Daisy Chaining Multiple MAX5661 Devices section. ______________________________________________________________________________________ 19 MAX5661 Detailed Description MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules CS SCLK DIN C7 DOUT c7 C6 C5 c6 C4 c5 D3 c4 D2 d3 D1 d2 D0 d1 d0 C7 BITS WITH CAPITAL LETTERS REPRESENT DATA BEING WRITTEN TO THE SHIFT REGISTER. BITS WITH LOWERCASE LETTERS REPRESENT DATA IN THE SHIFT REGISTER FROM THE PREVIOUS 24-BIT CYCLE. Figure 2. MICROWIRE- or SPI-Interface Timing Diagram (CPOL = CPHA = 0) CS SCLK DIN DOUT C7 p c7 C6 c6 C5 c5 C4 c4 D3 d3 D2 d2 D1 d1 D0 d0 p IS DATA LEFT FROM THE PREVIOUS INSTRUCTION CYCLE. BITS WITH CAPITAL LETTERS REPRESENT DATA BEING WRITTEN TO THE SHIFT REGISTER. BITS WITH LOWERCASE LETTERS REPRESENT DATA IN THE SHIFT REGISTER FROM THE PREVIOUS 24-BIT CYCLE. Figure 3. SPI-Interface Timing Diagram (CPOL = CPHA = 1) 20 _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules 24-BIT SERIAL INPUT WORD COMMAND BYTE DATA BITS MSB LSB C7 C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 2. Register Description COMMAND BITS OPERATION C7 X C6 X C5 X C4 X C3 0 C2 0 C1 0 C0 0 X X X X 0 0 0 1 Write control register. X X X X 0 0 1 0 Read control register. X X X X 0 0 1 1 Load input register. DAC register unchanged. X X X X 0 1 0 0 Load DAC and input register. X X X X 0 1 0 1 Load DAC register. Transfer input register data to DAC register. DAC outputs update on CS’s rising edge. X X X X 0 1 1 0 Write clear register. X X X X 0 1 1 1 Read input register. X X X X 1 0 0 0 Read DAC register. X X X X 1 0 0 1 Read clear register. X X X X 1 1 1 1 No operation. Transfer shift register’s data to DOUT. No operation. Transfer shift register’s data to DOUT. X = Don’t care. All other commands are reserved for factory use. Do not use. Register Descriptions The MAX5661 communicates between its internal registers and the external bus lines through the 4-wire SPI-/QSPI-/MICROWIRE-compatible serial interface. Table 1 details the command bits (C7–C0) and the data bits (D15–D0) of the serial input word. Tables 2 and 3 detail the command byte and the subsequent register accessed. Tables 4–8 detail the various read/write internal registers and their power-on reset states. When updating the DAC register, allow 5µs before sending the next command. Control Register (Read/Write) Write to the control register to enable the current or voltage output, set the voltage output for unipolar or bipolar mode, and set the current-output range. The control register also initializes the clear and fault modes. Set the command byte to 0x01 to write to the control register. Set the command byte to 0x02 to read from the control register. Write or read data bits D15–D5. D4–D0 are don’t-care bits for a write operation. D4, D3, and D2 are read-only bits. D1 and D0 are don’t-care bits for a read operation (see Table 4). Set the OUTVON bit (D15) to 1 to enable the OUTV DAC voltage output. Set the OUTION bit (D14) to 1 to enable the OUTI DAC current output. Always set bit D13 to 0. Set the B/U bit (D12) to determine whether the OUTV output operates in bipolar mode (B/U = 0) or unipolar mode (B/U = 1). ______________________________________________________________________________________ 21 MAX5661 Table 1. Input Command Bits Table 3. Register Bit Descriptions D15 X X X X 0 0 0 0 X Data in shift register after CS driven high and command executed X X 22 1 1 1 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X RCLR FAULTEN CLRFLAGEN X X X X X X X X X X X X FAULTEN 0 X CLRMODE 1 RCLR 0 CLRMODE 0 CLREN 0 14 to 20 BIT X CLREN X 0 0 1 0 Same as line above. X X X X 0 0 1 X X X 0 X X 1 CLEARST X FAULTI X FAULTV X X X X X X X X X X X X X X X X X X X X X X X X X X MSB LSB Same as line above. Shift-register data not changed by this operation. X X X X 0 1 0 MSB LSB 0 Same as line above. Shift-register data not changed by this operation. X X X X 0 1 0 1 X X X X X X X X X X Same as line above. Shift-register data not changed by this operation. X X X X 0 1 1 0 MSB LSB Same as line above. Shift-register data not changed by this operation. X X X X 0 1 1 1 X X X X X X X X X 1 0 0 0 X X X X X X X X 1 0 0 1 X X X X 1 Same as line above. X X X X X X X X X X X 0 1 0 1 X X X X X X X X X X X X X X X X X X X X FS_ BIT 0 (LSB) X X FS_ BIT 1 X X FS_ BIT 2 X X MSB LSB Same as line above. X X MSB LSB Same as line above. X X MSB LSB Same as line above. Data in shift register after CS driven high and command executed Data in shift register after CS driven high and command executed D5 Same as line above. Shift-register data not changed by this operation. Data in shift register after CS driven high and command executed Data in shift register before CS driven high and command executed D6 FS_ BIT 3 Data in shift register before CS driven high and command executed D7 14 to 20 BIT X Data in shift register after CS driven high and command executed Data in shift register before CS driven high and command executed D8 CLRFLAGEN Data in shift register before CS driven high and command executed D9 B/U X Data in shift register after CS driven high and command executed Data in shift register before CS driven high and command executed Write full-scale output trim register 1 Data in shift register after CS driven high and command executed Data in shift register before CS driven high and command executed D10 FS_ BIT 4 Read clear register X Data in shift register after CS driven high and command executed Data in shift register before CS driven high and command executed D11 OUTI4/0 EN X Data in shift register after CS driven high and command executed Data in shift register before CS driven high and command executed D12 Same as line above. Shift-register data not changed by this operation. Data in shift register after CS driven high and command executed Read DAC register X Data in shift register after CS driven high and command executed Data in shift register before CS driven high and command executed 2ND DATA BYTE D13 Same as line above. Shift-register data not changed by this operation. Data in shift register after CS driven high and command executed Data in shift register before CS driven high and command executed X OUTION Data in shift register before CS driven high and command executed D14 FS_ BIT 5 Read input register C0 FS_ BIT 6 Write clear register C1 FS_ BIT 7 Load DAC register from input register C2 FS_ BIT 8 Load input register and DAC register from shift register. C3 FS_ BIT 9 (MSB) Load input register from shift register. DAC register unchanged. C4 B/U Read control register C5 OUTI4/0 EN Write control register C6 OUTION No operation. Transfer shiftregister data to DOUT. Data in shift register before CS driven high and command executed 1ST DATA BYTE C7 OUTVON No operation. Transfer shiftregister data to DOUT. COMMAND BYTE DESCRIPTION OUTVON OPERATION FS_ EN MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules MAX5661 DIN CLOCKED IN ON THE SCLK RISING EDGE WRITE COMMAND EXECUTED CS SCLK DIN C7 C6 C5 C4 C0 D15 D14 D13 D0 Figure 4. Write Timing READ COMMAND EXECUTED CS SCLK DIN C7 C6 C5 C4 C0 DOUT D15 D14 D13 D0 DOUT READY CS SCLK DIN X X X X X X X X X DOUT C7 C6 C5 C4 C0 D15 D14 D13 D0 DOUT TRANSITIONS ON THE FALLING SCLK EDGE X = DON'T CARE. Figure 5. Read Timing Set the OUTI4/0EN bit (D11) low to enable the OUTI4/0 hardware input. Set the I4TO20BIT bit (D10) high to select the current-output range through the software. Set the CLREN bit (D9) low to enable the CLR hardware input. Set the CLRMODE bit (D8) high to force the output to the value in the clear register or the zero state when the CLR hardware input is pulled low. Set the RCLR bit (D7) high to remain in the clear state. Set the FAULTEN bit (D6) high to enable the FAULT output functionality. Set the CLRFLAGEN bit (D5) high to activate the FAULT output when the MAX5661 is in the clear state. Bits D4, D3, and D2 are read-only bits. The FAULTV bit (D4) is set to 1 when OUTV is short circuited. The FAULTI bit (D3) is set to 1 when OUTI is open circuited. The CLEARST bit (D2) is set to 1 when the MAX5661 is in the clear state. ______________________________________________________________________________________ 23 MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules Table 4. Control Register (Read/Write) BIT NAME DATA BIT RESET STATE OUTVON D15 0 FUNCTION DAC OUTV output enable bit. Set to 1 to enable the OUTV output. OUTION D14 0 DAC OUTI output enable bit. Set to 1 to enable the OUTI output. — D13 0 Reserved. Always set to 0. B/U D12 0 Voltage-output unipolar/bipolar mode select bit. Set to 0 (default power-up state) to select the bipolar output range (±10.48V). Set to 1 to select the unipolar output range (0 to +10.48V). OUTI4/0EN D11 0 OUTI4/0 enable bit. Set to 0 (default power-up state) to enable the OUTI4/0 hardware input. Set to 1 to disable the OUTI4/0 hardware input, thereby controlling the current-output range through software commands. I4TO20BIT D10 0 OUTI current range bit. Set to 0 to set the OUTI current range from 0 to 20mA. Set to 1 to set the OUTI current range from 4–20mA. CLREN D9 0 Clear enable bit. Set to 0 to enable the external CLR input. Set to 1 to disable the external CLR input. CLRMODE D8 0 Clear mode bit. Set to 1 and drive the external CLR input low to force the DAC output to the value stored in the clear register. Set to 0 and drive the external CLR input low to force the DAC output to 0V in voltage mode or 0mA/4mA depending on output-current mode. RCLR D7 0 Remain in clear bit. Set to 1 to remain in the clear state. The RCLR bit determines the steps required to exit the clear state. See the CLR Input section. FAULTEN D6 0 Fault output enable. Set to 1 to enable the FAULT output functionality. Set to 0 to disable the FAULT output functionality. In single supply mode, set to 0 to disable the FAULT pin function. CLRFLAGEN D5 0 Clear flag enable. Set to 1 to enable the FAULT output to report when the device is in the clear state. FAULTV D4 0 Output voltage fault bit (read only). The FAULTV bit is set to 1 when FAULT triggers due to an OUTV short-circuit condition. The FAULTV bit is a don’t-care bit for control-register write commands. In single supply mode, FAULTV = 1 must be ignored. FAULTI D3 0 Output-current fault bit (read only). The FAULTI bit is set to 1 when FAULT triggers due to an OUTI open-circuit condition. The FAULTI bit is a don’t-care bit for the control register write commands. In single supply mode, monitor the FAULTI bit for any FAULTI condition. CLEARST D2 0 Clear state bit (read only). The CLEARST bit is set to 1 when CLR is low and CLREN = 0. The CLRST bit is a don’t-care bit for control register write commands. X D1, D0 0 Not used. 24 _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules DAC Register (Read/Write) Write to the DAC register to update the OUTV and OUTI outputs after CS returns high. Set the command byte to 0x04 to write to the DAC register. Set the command byte to 0x08 to read from the DAC register. Bits D15–D0 contain the straight binary data (see Table 6). put. Set the command byte to 0x05 to write to the load DAC register. Bits D15–D0 are don’t-care bits. Clear Register (Read/Write) Write to the clear register to set the DAC output value when the CLR hardware input is pulled low (forcing the MAX5661 into the clear state). Set the command byte to 0x06 to write to the clear register. Set the command byte to 0x09 to read the clear register. Bits D15–D0 contain the straight binary data (see Table 7). No Operation Set the command byte to 0x0F or 0x00 to perform a nooperation command. After writing the command byte and 2 data bytes (16 don’t-care bits), read out the shift register’s contents on the following 24-bit cycle. Load DAC Register (Write) Write to the load DAC register to transfer the input register data to the DAC register and update the DAC out- Table 5. Input Register (Read/Write) BIT NAME IN15–IN0 DATA BIT RESET STATE FUNCTION D15–D0 0000 0000 0000 0000 (unipolar/current) 1000 0000 0000 0000 (bipolar) IN15 is the MSB and IN0 is the LSB. Data format is straight binary. Table 6. DAC Register (Read/Write) BIT NAME DAC15–DAC0 DATA BIT RESET STATE D15–D0 0000 0000 0000 0000 (unipolar/current) 0000 0000 0000 0000 (bipolar) FUNCTION DAC15 is the MSB and DAC0 is the LSB. Data format is straight binary. Table 7. Clear Register (Read/Write) BIT NAME CLR15–CLR0 DATA BIT RESET STATE D15–D0 0000 0000 0000 0000 (unipolar/current) 1000 0000 0000 0000 (bipolar) FUNCTION CLR15 is the MSB and CLR0 is the LSB. Data format is straight binary. Table 8. Full-Scale Output Trim Register (Write) BIT NAME DATA BIT RESET STATE FS_EN + FS_BIT9– FS_BIT0 D9–D0 0000 0000 0000 0000 FUNCTION FS_EN (D15) enables the full-scale output adjustment feature. D9 is the MSB and D0 is the LSB. D9 is straight binary, D8–D0 are inverted binary. ______________________________________________________________________________________ 25 MAX5661 Input Register (Read/Write) Write to the input register to store the DAC code. Transfer the value written to the input register to the DAC register by pulling the LDAC input low or by writing to the load DAC register (0x05). Set the command byte to 0x03 to write to the input register. Set the command byte to 0x07 to read from the input register. Bits D15–D0 contain the straight binary data (see Table 5). Full-Scale Output Current Trim Register (Write) Write to the full-scale output trim register to adjust the output voltage or current ±25%. Set command bits to 0x06 to write to the output trim register. Bit 15 enables the output trim register. Bits D9–D0 program the 10-bit trim DAC (Table 8). Table 9. N to D: Full-Scale Output Trim Register Bits Map N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 10. Full-Scale Output Variation vs. N and B BIT DECIMAL VALUE (B) MAX5661 fig06 1100 % CHANGE 0 511 -25 256 255 -12.5 511 0 0- 512 1023 0+ 767 768 +12.5 1023 512 +25 +25% 1000 900 800 +12.5% 700 600 0% 500 400 300 -12.5% 200 100 0 -25% 0 100 200 300 400 500 600 700 800 900 1000 1100 BITS (B) Figure 6. Transfer Function of Bits (B) to Numerical (N) Representation 26 _______________________________________________________________________________________ % CHANGE FULL-SCALE OUTPUT DECIMAL VALUE (N) BITS (B) TO NUMERICAL (N) TRANSFER FUNCTION NUMBER (N) MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules MAX5661 LDAC SOFTWARE LOAD DAC CONTROL REGISTER CS SCLK FULL-SCALE OUTPUT ADJUST FULL-SCALE ADJUST REGISTER SHIFT REGISTER INPUT REGISTER OUTI DAC REGISTER TO OUTPUT CIRCUITRY DAC DIN OUTV 2-TO-1 MUX DOUT CLEAR REGISTER MAX5661 Figure 7. Functional Diagram Reference Input Connect an external voltage reference in the +4V to +4.2V range through a 1kΩ series resistor to the buffered REF input. Use a high-accuracy, lownoise +4.096V voltage reference such as the MAX6126AASA41 (3ppm/°C temperature drift and 0.02% initial accuracy) for best 16-bit static accuracy. REF does not accept AC signals. See Table 17 for a listing of +4.096V references. tLDL LDAC ± 2 LSB LDAC Input The MAX5661 features an active-low load DAC (LDAC) logic input that allows asynchronous updates to the DAC outputs. Drive LDAC high to VCC during normal operation while controlling the MAX5661 using only the serial interface. Drive LDAC low to update the DAC output with the input register data. Hold LDAC low to make the input register transparent and immediately update the DAC output with the input register data. Figure 8 shows the LDAC timing with respect to OUT_. tDELAY OUT_ Figure 8. LDAC Timing ______________________________________________________________________________________ 27 MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules CLR Input The active-low external CLR input asynchronously sets the DAC code to the value in the clear register (software clear) or to the zero state (hardware clear), depending on the control register’s CLRMODE bit setting (see Tables 4 and 11). Set the CLRMODE bit to 1 and drive external CLR low to force the output to the value stored in the clear register. Set the CLRMODE bit to 0 and drive the external CLR input low to force the output to the zero state. The zero state value is 0mA in 0 to 20mA current mode, 3.97mA in 4–20mA current mode, or 0V in voltage mode (unipolar or bipolar). Disable the external CLR input functionality by setting the control register’s CLREN bit to 1. Set the CLREN bit to 0 to enable the external CLR input functionality. After setting the CLREN bit to 0, force the external CLR input low to set the MAX5661 into the clear state. The control register’s read-only CLEARST bit is set to 1 while in the clear state. The RCLR (remain in clear) bit determines the steps required to exit the clear state. With the RCLR bit set to 1, exit the clear state in one of three ways: 1) Pull the external CLR input high and then write to the DAC register (0x04) or the load DAC register (0x05) or force LDAC low. 2) Pull the external CLR input high and set the RCLR bit low. 3) Initiate a power-on reset (POR) to reset the RCLR bit to 0. With the RCLR bit set to 0, exit the clear state one of three ways: 1) Set the CLREN bit high. 2) Pull the external CLR input high. 3) Initiate a power-on reset (POR). FAULT Output The open-drain active-low FAULT output asserts low for a current-output open circuit or dropout condition, for a voltage-output short circuit, or when the MAX5661 is in the clear state (see the CLR Input section). Enable and disable the FAULT output with the control register’s FAULTEN and CLRFLAGEN bits (see Tables 4, 12, and Figure 9). Set the FAULTEN bit to 1 to enable the FAULT output to report fault conditions on OUTV and OUTI. Set FAULTEN to 0 to disable the FAULT output for fault conditions on OUTV and OUTI. Set the CLRFLAGEN bit to 1 to enable the FAULT output to report when the device is in the clear state. Set CLRFLAGEN to 0 to disable a hardware indication of the clear state. The FAULT output asserts low if CLRFLAGEN = 1 and CLEARST = 1. Read the control register to determine the source of a FAULT output condition. The FAULTV read-only bit is set to 1 when the voltage output (OUTV) is shortcircuited. The FAULTI bit is set to 1 when the current output (OUTI) is open circuited or in a dropout condition (VDDI - VOUTI at 1.3V typ). The FAULT output asserts low if FAULTEN is set to 1 and either the FAULTV bit or FAULTI bit is set to 1. Table 11. Hardware-Clear and Software-Clear Truth Table CLEARST BIT (READ) CLRMODE BIT (READ/WRITE) 0 (not in clear state) X X X 1 (in clear state) 0 DAC code set to zero state* — 1 (in clear state) 1 — DAC code set by clear register data HARDWARE CLEAR SOFTWARE CLEAR X = Don’t care. *Zero state is 0V in unipolar voltage mode, -10.48V in bipolar voltage mode, and 0mA/4mA depending on output-current mode. 28 _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules FAULT_AT_ OUTPUT INTERNAL FAULT SIGNAL X 0 0 0 X 0 1 1 1 MAX5661 FAULTEN BIT INTERNAL FAULT SIGNAL FAULTEN BIT FAULT OUTPUT FAULT_AT_OUTPUT (INTERNALLY GENERATED, CANNOT BE READ) FAULTI BIT INTERNAL FAULT SIGNAL CLEAR_ FLAG FAULT OUTPUT 1 X 0 X 1 0 0 0 1 FAULTV BIT FAULTI BIT FAULTV BIT FAULT_AT_ OUTPUT 1 X 1 X 1 1 0 0 0 CLEAR_FLAG (INTERNALLY GENERATED, CANNOT BE READ) CLRFLAGEN CLRFLAGEN BIT CLEARST BIT CLEAR_ FLAG CLEARST BIT 0 X 0 X 0 0 1 1 1 X = DON'T CARE. Figure 9. FAULT Output Logic Diagram Table 12. FAULT Output Truth Table OUTV SHORT CIRCUITED OUTI OPEN CIRCUITED OR IN DROPOUT CLEARST BIT FAULTEN BIT CLRFLAGEN BIT FAULT OUTPUT No No 0 X X High No No X X 0 High X X 1 X 1 Low High X X 0 0 X No Yes X 1 X Low X X X 0 0 High Yes No X 1 X Low X = Don’t care. Only one output (OUTV or OUTI) is active at a time. ______________________________________________________________________________________ 29 MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules Output Configurations The CNF0, CNF1, and OUTI4/0 hardware inputs determine whether the hardware or software controls the MAX5661 DAC outputs (see Table 13). The CNF0 and CNF1 inputs enable and disable the DAC outputs or allow software control of the outputs (see Table 14). The OUTI4/0 input sets the current range of the OUTI output. Hardware inputs take precedence over the software commands. The VCC digital supply powers the CNF1, CNF0, and OUTI4/0 inputs. If VCC = 0V, the DAC outputs enter the zero state and all register bits are set to 0. The zero state of the voltage output (OUTV) is 0V. The zero state of the current output (OUTI) is 0mA when OUTI4/0 = AGND or 4mA when OUTI4/0 = VDDI. Table 13. Output Configuration CONTROL SIGNAL HARDWARE INPUT/SOFTWARE BIT CNF1 Hardware input DESCRIPTION Enables/disables the DAC OUTV and OUTI outputs. CNF0 Hardware input OUTI4/0 Hardware input OUTI4/0EN Software bit OUTVON Software bit DETAILS CNF1, CNF0: 00 = both outputs disabled 01 = OUTI active, set to 0 to 20mA range 10 = OUTV active, set to bipolar mode 11 = outputs controlled by serial interface Set the OUTI4/0EN bit to 0 (default power-up state) to enable the OUTI4/0 hardware input. Connect the OUTI4/0 hardware input to AGND to set the OUTI current range to 0 to 20mA. Sets the OUTI current range. Connect the OUTI4/0 hardware input to VDDI to set the OUTI current range to 4–20mA. Set the OUTI4/0EN bit to 1 to disable the OUT14/0 hardware input. Connect OUTI4/0 to AGND when controlling the current output through software. Enables and disables the OUTI4/0 input. Set the OUTI4/0EN bit to 0 (default power-up state) to enable the OUTI4/0 hardware input. Set to 1 to disable the OUTI4/0 hardware input. Enables and disables the DAC OUTV and OUTI outputs. When the CNF1 and CNF0 hardware inputs are high, the OUTION and OUTVON bits control the DAC output OUTI and OUTV settings. OUTVON, OUTION: 00 = both outputs powered down 01 = OUTI active 10 = OUTV active 11 = both outputs powered down OUTION Software bit B/U Software bit Sets the voltage output to unipolar mode or bipolar mode. Set B/U to 0 to set the OUTV output to bipolar mode (±10.48V). Set B/U to 1 to set the OUTV output to unipolar mode (0 to +10.48V). I4TO20BIT Software bit Sets the OUTI current range through software. Set I4TO20BIT to 0 to set the OUTI current range from 0 to 20mA. Set I4TO20BIT to 1 to set the OUTI current range from 4–20mA. 30 _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules OUTI Current-Output Configuration Drive CNF0 high and CNF1 low to enable the OUTI output through the hardware. Alternatively, drive CNF0 and CNF1 high to control OUTI with the serial interface. With CNF1 and CNF0 high, the control register’s OUTION bit enables the OUTI output. Set OUTION to 1 to enable the OUTI output. Set OUTION to 0 (default power-up state) to disable the OUTI output. The OUTI current output derives power from VDDI and V DDCORE (+13.48V to +40V). Connect V DDCORE to VDDI when using the OUTI output. The control register’s OUTI4/0EN bit (see Tables 4 and 13) determines whether the OUTI4/0 hardware input or the control register’s I4TO20BIT bit controls the OUTI current range. Set the OUTI4/0EN bit to 0 (default power-up state) to control the current range through the OUTI4/0 hardware input. Connect the OUTI4/0 hardware input to AGND to select the 0 to 20mA mode. Connect the OUTI4/0 hardware input to VDDI to select the 4–20mA mode. Set the OUTI4/0EN bit to 1 to allow software control of the OUTI current range through the I4TO20BIT bit (see Table 13). Set I4TO20BIT to 0 to select the 0 to 20mA mode. Set I4TO20BIT to 1 to select the 4–20mA mode. OUTV Voltage-Output Configuration Drive CNF0 low and CNF1 high to enable the OUTV output through the hardware (see Table 14). Alternatively, drive CNF0 and CNF1 high to control OUTV with the serial interface. With CNF1 and CNF0 high, the control register’s OUTVON bit enables the OUTV output. Set OUTVON to 1 to enable the OUTV output. Set OUTVON to 0 (default power-up state) to disable the OUTV output. The OUTV output derives power from VDDV, VSSV, and V DDCORE . Connect V DDCORE to V DDV (+13.48V to +15.75V) when using the OUTV output. Always connect a negative supply to VSSV (-13.48V to -15.75V) (see Table 16). The control register’s B/U bit sets OUTV for bipolar or unipolar mode. Set B/U to 0 (default power-up state) to select the bipolar output range (±10.48V). Set B/U to 1 to select the unipolar output range (0 to +10.48V). Output Transfer Functions The DAC output voltage/current is a function of the various hardware control inputs and digital inputs in the control register (see Table 13). The transfer functions below assume that the outputs are on, and a reference voltage of +4.096V is applied to the reference input. For the voltage output, the sense input is at the same potential as the DAC output (OUTV = SVP and AGND = SVN). Table 15a details the bipolar output voltage transfer function. Table 15b details the unipolar output voltage transfer function. Table 15c details the 0 to 20mA current-range transfer function. Table 15d details the 4mA to 20mA current-range transfer function. Table 14. CNF1/CNF0 Hardware Settings CNF1 CNF0 DGND DGND DGND VCC VCC DGND VCC VCC OUTV, OUTI SETTING Both DAC outputs disabled. OUTI enabled. OUTV disabled. OUTV enabled. OUTI disabled. DAC outputs controlled by the serial interface. ______________________________________________________________________________________ 31 MAX5661 CNF0/CNF1 Hardware Inputs The CNF0 and CNF1 inputs enable the DAC’s voltage (OUTV) or current (OUTI) outputs. Drive CNF0 and CNF1 low to disable both the OUTV and OUTI outputs. Drive CNF0 high and CNF1 low to enable the OUTI output. Drive CNF0 low and CNF1 high to enable the OUTV output. Drive CNF0 and CNF1 high to control the OUTV and OUTI outputs through the serial interface. Table 14 summarizes the output behavior when programmed by the CNF0/CNF1 hardware inputs. MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules Table 15a. Bipolar Voltage Output DAC CODE (DECIMAL VALUE) OUTPUT VOLTAGE (V) RANGE 65535 10.47984 Overrange 64769 10.23485 Overrange 64768 10.23453 Nominal range 64767 10.23421 Nominal range 48769 5.117585 Nominal range 48768 5.117266 Nominal range 48767 5.116946 Nominal range 35969 1.023773 Nominal range 35968 1.023453 Nominal range 35967 1.023133 Nominal range 32769 0.00032 Nominal range 32768 0 Nominal range 32767 -0.00032 Nominal range 29569 -1.02313 Nominal range 29568 -1.02345 Nominal range 29567 -1.02377 Nominal range 16769 -5.11695 Nominal range 16768 -5.11727 Nominal range 16767 -5.11759 Nominal range 769 -10.2342 Nominal range 768 -10.2345 Nominal range 767 -10.2349 Underrange 0 -10.4802 Underrange OUTPUT VOLTAGE (V) RANGE Table 15b. Unipolar Voltage Output DAC CODE (DECIMAL VALUE) 32 65535 10.48 Overrange 64001 10.23469 Overrange 64000 10.23453 Nominal range 32001 5.117425 Nominal range 32000 5.117266 Nominal range 31999 5.117106 Nominal range 6401 1.023613 Nominal range 6400 1.023453 Nominal range 6399 1.023293 Nominal range 1 0.00016 Nominal range 0 0 Nominal range _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules DAC CODE (DECIMAL) ACTUAL OUTPUT CURRENT (mA) RANGE EXTENSION OF OUTPUT CURRENT LINEAR RANGE (mA) 65535 20.449688 Overrange 20.449688 64001 19.970313 Overrange 19.970313 64000 19.970000 Nominal range 19.970000 63999 19.969688 Nominal range 19.969688 32001 9.970313 Nominal range 9.970313 32000 9.970000 Nominal range 9.970000 31999 9.969688 Nominal range 9.969688 12801 3.970313 Nominal range 3.970313 12800 3.970000 Nominal range 3.970000 12799 3.969688 Nominal range 3.969688 97 0.000313 Nominal range 0.000313 96 0.000000 Nominal range 0.000000 95 0.000000 Underrange -0.000313 80 0.000000 Underrange -0.005000 60 0.000000 Underrange -0.011250 40 0.000000 Underrange -0.017500 30 0.000000 Underrange -0.020625 0 0.000000 Underrange -0.030000 Table 15d. 4–20mA Current Output DAC CODE (DECIMAL) OUTPUT CURRENT (mA) RANGE 65535 20.449688 Overrange 64000 20.063690 Overrange 63634 19.971655 Nominal range 60000 19.057835 Nominal range 50000 16.543196 Nominal range 40000 14.028556 Nominal range 30000 11.513917 Nominal range 20000 8.999278 Nominal range 16000 7.993423 Nominal range 5000 5.227320 Nominal range 500 4.095732 Nominal range 238 4.029848 Nominal range 200 4.020293 Underrange 100 3.970000 Underrange 80 3.970000 Underrange 60 3.970000 Underrange 30 3.970000 Underrange 0 3.970000 Underrange ______________________________________________________________________________________ 33 MAX5661 Table 15c. 0 to 20mA Current Output MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules Measuring Zero-Code Current (0 to 20mA Mode) After setting the MAX5661 for 0 to 20mA current-range mode, determine the LSB size as follows: 1) Measure IOUT at full scale (FS). 2) Measure IOUT at code 192. 3) Measure IOUT at code 193: ILSB = IOUT at FS − IOUT at 192 16 (2 − 1) − 192 If IOUT (code 193) - IOUT (code 192) > 0.5 ILSB, IOUT (code 192) is inside the linear region of the IOUT transfer curve. Obtain the straight-line equation from IOUT (FS) and IOUT (192) and substituting code 0 for IOUT (zero scale) in the equation: ⎛I at FS − IOUT at 192 ⎞ (I − IOUT at 192) = ⎜ OUT ⎟ x (code − 192) 65535 − 192 ⎝ ⎠ 29383 + IOUT at 192 IOUT at ZS = (IOUT at 192 − IOUT at FS) x 0.002 The expected current is -30µA (typ). Applications Information Power-Supply Sequencing and Bypassing After connecting all ground inputs, apply the analog supply voltages VSSV first followed by the most positive supply, the second most positive supply, etc. Before applying power, connect the VDDCORE supply to either VDDV or VDDI, as shown in Table 16, depending on whether the current output or voltage output is used. Do not apply V DDCORE separate from the main supply (V DDV /V SSV or V DDI ) in the preferred configuration (Table 16). Ensure that there are no unconnected power-supply connections when powering the MAX5661. If VSSV cannot be powered first, connect a Schottky diode between VSSV and AGND. Daisy Chaining Multiple MAX5661 Devices In standard SPI-/QSPI-/MICROWIRE-compatible systems, a microcontroller (µC) communicates with its slave devices through a 3- or 4-wire serial interface. The typical interface includes a chip select signal (CS), a serial clock (SCLK), a data input signal (DIN), and sometimes a data signal output (DOUT). In this system, the µC allots an independent chip-select signal to each slave device so that they can be addressed individually (see Figure 10). Only the slaves with their CS inputs asserted low acknowledge and respond to the activity on the serial clock and data lines. This is simple to implement when there are very few slave devices in the system. An alternative programming method is daisy chaining. Daisy chaining, in serial-interface applications, is a method of propagating commands through multiple devices connected in series (see Figure 11). Daisy chaining reduces CS and DIN line routing, and saves board space when using the MAX5661. Daisy chain multiple MAX5661 devices by connecting the DOUT of one device to the DIN of the next. Connect the SCLK of all devices to a common clock and connect the CS from all devices to a common chip-select line. Data shifts out of DOUT 24.5 clock cycles after it is shifted into DIN on the falling edge of SCLK. Hold CS low until each slave in the chain receives its 24-bit word (8 command bits and 16 data bits). In this configuration, the µC only needs three signals (CS, SCLK, and DIN) to control all the slaves in the network. The SPI-/QSPI/MICROWIRE-compatible serial interface normally works at up to 10MHz, but must be slowed to 6MHz if daisy chaining. DOUT is high impedance when CS is high. Figure 10 details a method of controlling multiple MAX5661 devices using separate CS lines. This method allows writes to and reads from each device without shifting data through the other device’s shift register. Figure 10 shows the FAULT outputs shorted together. This configuration requires a read from each device to determine which one has the fault condition and saves an optocoupler in isolated applications. It is not necessary to short the FAULT outputs together. Table 16. Application Modes and Supply-Voltage Limits APPLICATION MODE VDDV VSSV VDDI VDDCORE Voltage from OUTV +13.48V to +15.75V -13.48V to -15.75V VDDV VDDV Current from OUTI (Single Supply) AGND AGND +13.48V to +40V VDDI +13.48V to +15.75V -13.48V to -15.75V VDDV to +40V VDDV Voltage from OUTV and Current from OUTI* *On-the-fly switching. Only one output is active at a time. 34 _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules CS1 CS DIN DIN IC3. Hold CS low for three 24-bit write cycles to load data into all three devices. Due to the latency of reading and writing to the different devices, using separate lines for each FAULT output does not save time. MAX5661 IC1 SCLK SCLK LDAC LDAC FAULT CLR CLR DOUT CS2 CS MAX5661 IC2 DIN SCLK LDAC FAULT CLR DOUT DOUT FAULT Figure 10. Address Two MAX5661 Devices Through Separate CS Lines Driving Inductive Loads from IOUT When driving inductive loads > 275µH with the current output (IOUT), connect a 1nF capacitor between VDDI and IOUT for optimal performance. ______________________________________________________________________________________ 35 MAX5661 Figure 11 shows a method of daisy chaining multiple MAX5661 devices using a single CS and SCLK line with the FAULT outputs shorted together. Connect DOUT from IC1 to DIN of IC2, and DOUT from IC2 to DIN of MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules CS CS DIN DIN MAX5661 IC1 SCLK SCLK LDAC LDAC FAULT CLR CLR DOUT CS MAX5661 IC2 DIN SCLK LDAC FAULT CLR DOUT CS MAX5661 IC3 DIN SCLK LDAC FAULT CLR DOUT DOUT FAULT Figure 11. Address Three MAX5661 Devices Through Separate CS Lines 36 _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules MAX5661 Table 17. +4.096V Reference Selector Guide SUPPLY VOLTAGE RANGE (V) TEMPERATURE DRIFT (ppm/°C max) INITIAL ACCURACY (%) MAX6341 +8 to +36 1 0.02 MAX6241 +8 to +36 3 0.02 Low drift, 2.4µVP-P output noise PART FEATURES Ultra-low drift, 2.4µVP-P output noise MAX6174 +4.3 to +40 3 0.06 High-precision reference with temperature sensor MAX6133_41 +4.3 to +12.6 3 0.04 Ultra-low drift, µMAX® MAX6126_41 +4.3 to +12.6 3 0.02 Ultra-low noise, µMAX MAX6043_41 +6 to +40 3 0.05 High voltage, low drift MAX6143_41 +6 to +40 8 0.1 High precision MAX6033_41 +4.3 to +12.6 10 0.04 10mA output current, ultra-low drift, SOT23 MAX6041 +4.3 to +12.6 20 0.2 Low power, low drift, low dropout MAX6064 +4.3 to +12.6 20 0.2 5mA current output, precision SOT23 MAX6220 +8 to +40 20 0.1 -40°C to +125°C, 15mA output +4.3 to +5.5 25 0.2 SOT23 with shutdown MAX6037_41 MAX6034_41 +4.3 to +5.5 30 0.2 Low supply current in SC70 MAX6029 +4.3 to +12.6 30 0.15 Ultra-low supply current, SOT23 Chip Information PROCESS: BiCMOS N.C. N.C. SVP N.C. I.C. N.C. VSSV VDDV N.C. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 I.C. 64 SVN N.C. N.C. N.C. N.C. TOP VIEW OUTV Pin Configuration + N.C. 1 OUTI 2 48 N.C. 47 N.C. N.C. 3 46 N.C. VDDI 4 45 AGND N.C. 5 44 N.C. COMPI 6 43 COMPV N.C. 7 42 N.C. N.C. 8 41 DUTGND OUTI4/0 9 MAX5661 40 DUTGNDS N.C. 10 39 VDDCORE REF 11 38 N.C. DACGND 12 37 CLR DACGNDS 13 36 N.C. 35 DOUT CNF1 14 N.C. 15 34 N.C. N.C. 16 33 N.C. N.C. N.C. N.C. N.C. FAULT LDAC VCC DGND CS SCLK DIN CNF0 N.C. N.C. N.C. N.C. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LQFP µMAX is a registered trademark of Maxim Integrated Products, Inc. ______________________________________________________________________________________ 37 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules MAX5661 Typical Operating Circuit VDDV OR VDDI +13.48V TO +15.75V -13.48V TO -15.75V +4.75V TO +5.25V +13.48V TO +40V VCC VDDCORE VDDV VSSV DOUT DIN SCLK UNIPOLAR CURRENT BLOCK (SOURCE ONLY) SERIAL INTERFACE* VDDI CS DETAIL OF OPTIONAL SURGE PROTECTION 22nF CLR MICROCONTROLLER VDDV LDAC COMPI OUTI4/0 16-BIT DAC VDDI CNF0 CNF1 VSSV R IDAC FAULT OUTI AGND FULL-SCALE OUTPUT ADJUST VOLTAGETO-CURRENT CONVERTER +5V +4.096V REFERENCE 1kΩ LOUTI* R REF REFERENCE BUFFER R UNIPOLAR OR BIPOLAR VOLTAGE BLOCK R OPTIONAL SURGE PROTECTION SVN R 2.5R COMPV CCOMPV 3.3nF** VDDV OUTV OPTIONAL SURGE PROTECTION SVP OPTIONAL SURGE PROTECTION VSSV MAX5661 R R DAC DACGNDS DACGND DUTGND DUTGNDS DGND 38 AGND * SEE THE DAC FUNCTIONAL DIAGRAM IN FIGURE 7. ** REQUIRED TO DRIVE COUTV < 1nF. _______________________________________________________________________________________ Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 64 LQFP C64-8 21-0083 ______________________________________________________________________________________ 39 MAX5661 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. MAX5661 Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules Revision History REVISION NUMBER REVISION DATE 0 8/08 Initial release 1 5/09 Clarified how the part operates in single supply mode DESCRIPTION PAGES CHANGED — 18, 24 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 40 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.