MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
General Description
The MAX5723/MAX5724/MAX5725 8-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal 3ppm/°C
reference that is selectable to be 2.048V, 2.500V, or
4.096V. The MAX5723/MAX5724/MAX5725 accept a
wide supply voltage range of 2.7V to 5.5V with extremely
low power (6mW) consumption to accommodate most
low-voltage applications. A precision external reference
input allows rail-to-rail operation and presents a 100kI
(typ) load to an external reference.
The MAX5723/MAX5724/MAX5725 have a fast 50MHz,
4-wire SPI/QSPI™/MICROWIRE/DSP-compatible serial
interface that operates at clock rates up to 50MHz. The
DAC output is buffered and has a low supply current
of less than 250FA per channel and a low offset error
of Q0.5mV (typ). On power-up, the MAX5723/MAX5724/
MAX5725 reset the DAC outputs to zero or midscale
based on the status of M/Z logic input, providing flexibility for a variety of control applications. The internal
reference is initially powered down to allow use of an
external reference. The MAX5723/MAX5724/MAX5725
allow simultaneous output updates using software LOAD
commands or the hardware load DAC logic input (LDAC).
Benefits and Features
●● Eight High-Accuracy DAC Channels
• 12-Bit Accuracy Without Adjustment
• ±1 LSB INL Buffered Voltage Output
• Guaranteed Monotonic Over All Operating
Conditions
• Independent Mode Settings for Each DAC
●● Three Precision Selectable Internal References
• 2.048V, 2.500V, or 4.096V
●● Internal Output Buffer
• Rail-to-Rail Operation with External Reference
• 4.5µs Settling Time
• Outputs Directly Drive 2kΩ Loads
●● Small 6.5mm x 4.4mm 20-Pin TSSOP or Ultra-Small
2.5mm x 2.3mm 20-Bump WLP Package
●● Wide 2.7V to 5.5V Supply Range
●● Separate 1.8V to 5.5V VDDIO Power-Supply Input
●● Fast 50MHz 4-Wire SPI/QSPI/MICROWIRE/DSPCompatible Serial Interface
●● Programmable Interface Watchdog Timer
●● Pin-Selectable Power-On-Reset to Zero-Scale or
Midscale DAC Output
The MAX5723/MAX5724/MAX5725 feature a programmable watchdog function which can be enabled to monitor the I/O interface for activity and integrity.
●● LDAC and CLR for Asynchronous DAC Control
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
simultaneously sets the DAC outputs to the programmable default value. The MAX5723/MAX5724/MAX5725
are available in a 20-pin TSSOP and an ultra-small,
20-bump WLP package and are specified over the -40NC
to +125NC temperature range.
Functional Diagram
Applications
Programmable Voltage and Current Sources
Gain and Offset Adjustment
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
QSPI is a trademark of Motorola, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
19-6243; Rev 2; 2/13
●● Three Selectable Power-Down Output Impedances
• 1kΩ, 100kΩ, or High Impedance
VDDIO
VDD
REF
MAX5723
MAX5724
MAX5725
INTERNAL REFERENCE/
EXTERNAL BUFFER
CSB
SCLK
DIN
DOUT
1 OF 8 DAC CHANNELS
CODE
REGISTER
SPI
SERIAL
INTERFACE
DAC
LATCH
8 -/10-/12-BIT
DAC
OUT0
BUFFER
OUT1
CLR
OUT2
LDAC
CODE
IRQ
CLEAR/
RESET
LOAD
(GATE/
CLEAR/
RESET)
OUT3
OUT4
100kI
WATCHDOG
TIMER
DAC CONTROL LOGIC
POWER-DOWN
1kI
OUT5
OUT6
OUT7
M/Z
POR
GND
Ordering Information appears at end of data sheet.
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Absolute Maximum Ratings
VDD, VDDIO to GND.................................................-0.3V to +6V
OUT_, REF to GND.......................................0.3V to the lower of
(VDD + 0.3V) and +6V
SCLK, CSB, IRQ, M/Z, LDAC, CLR to GND............-0.3V to +6V
DIN, DOUT to GND......................................-0.3V to the lower of
(VDDIO + 0.3V) and +6V
Continuous Power Dissipation (TA = +70NC)
TSSOP (derate at 13.6mW/NC above 70NC)...............1084mW
WLP (derate at 21.3mW/NC above 70NC)...................1700mW
Maximum Continuous Current into Any Pin..................... Q50mA
Operating Temperature..................................... -40NC to +125NC
Storage Temperature........................................ -65NC to +150NC
Lead Temperature (TSSOP only) (soldering, 10s)...........+300NC
Soldering Temperature (reflow)..................................... +260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 1)
TSSOP
Junction-to-Ambient Thermal Resistance (θJA) .......73.8NC/W
Junction-to-Case Thermal Resistance (θJC) ...............20NC/W
WLP
Junction-to-Ambient Thermal Resistance (θJA)
(Note 2)....................................................................47NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Note 2: Visit www.maximintegrated.com/app-notes/index.mvp/id/1891 for information about the thermal performance of WLP packaging.
Electrical Characteristics
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC PERFORMANCE (Note 4)
Resolution and Monotonicity
Integral Nonlinearity (Note 5)
Differential Nonlinearity (Note 5)
Offset Error (Note 6)
N
INL
DNL
MAX5723
8
MAX5724
10
MAX5725
12
MAX5723
-0.25
Q0.05
+0.25
MAX5724
-0.5
Q0.2
+0.5
MAX5725
-1
Q0.5
+1
MAX5723
-0.25
Q0.05
+0.25
MAX5724
-0.5
Q0.1
+0.5
MAX5725
-1
Q0.2
+1
-5
Q0.5
+5
OE
Offset Error Drift
Gain Error (Note 6)
Gain Temperature Coefficient
www.maximintegrated.com
Bits
Q10
GE
-1.0
With respect to VREF
Q0.1
Q3.0
LSB
LSB
mV
FV/NC
+1.0
%FS
ppm of
FS/NC
Maxim Integrated │ 2
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Electrical Characteristics (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
Zero-Scale Error
Full-Scale Error
With respect to VREF
MIN
TYP
MAX
UNITS
0
+10
mV
-0.5
+0.5
%FS
DAC OUTPUT CHARACTERISTICS
Output Voltage Range (Note 7)
Load Regulation
No load
0
VDD
2kI load to GND
0
VDD 0.2
2kI load to VDD
0.2
VDD
VOUT = VFS/2
DC Output Impedance
VOUT = VFS/2
Maximum Capacitive Load
Handling
CL
Resistive Load Handling
RL
Short-Circuit Output Current
300
VDD = 5V Q10%,
|IOUT| P 10mA
300
VDD = 3V Q10%,
|IOUT| P 5mA
0.3
VDD = 5V Q10%,
|IOUT| P 10mA
0.3
FV/mA
I
500
2
VDD = 5.5V
DC Power-Supply Rejection
VDD = 3V Q10%,
|IOUT| P 5mA
V
pF
kI
Sourcing (output
shorted to GND)
30
Sinking (output shorted
to VDD)
50
mA
VDD = 3V Q10% or 5V Q10%
100
FV/V
Positive and negative
1.0
V/Fs
¼ scale to ¾ scale, to P 1 LSB, MAX5723
2.2
¼ scale to ¾ scale, to P 1 LSB, MAX5724
2.6
¼ scale to ¾ scale, to P 1 LSB, MAX5725
4.5
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
SR
DAC Glitch Impulse
Major code transition (code x7FF to x800)
Channel-to-Channel
Feedthrough (Note 8)
Internal reference
3.3
External reference
4.07
Midscale code, all digital inputs from 0V to
VDDIO
0.2
nV*s
Startup calibration time (Note 9)
200
Fs
50
Fs
Digital Feedthrough
Power-Up Time
www.maximintegrated.com
From power-down
7
Fs
nV*s
nV*s
Maxim Integrated │ 3
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Electrical Characteristics (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
External reference
Output Voltage-Noise Density
(DAC Output at Midscale)
82
112
f = 10kHz
102
2.5V internal
reference
f = 1kHz
125
f = 10kHz
110
4.096V internal
reference
f = 1kHz
160
f = 10kHz
145
f = 0.1Hz to 10Hz
12
2.048V internal
reference
2.5V internal
reference
76
f = 0.1Hz to 300kHz
385
f = 0.1Hz to 10Hz
14
f = 0.1Hz to 10kHz
91
f = 0.1Hz to 300kHz
450
f = 0.1Hz to 10Hz
15
99
f = 0.1Hz to 300kHz
470
f = 0.1Hz to 10Hz
16
f = 0.1Hz to 10kHz
124
f = 0.1Hz to 300kHz
490
f = 1kHz
114
f = 10kHz
99
2.048V internal
reference
f = 1kHz
175
f = 10kHz
153
2.5V internal
reference
f = 1kHz
200
f = 10kHz
174
4.096V internal
reference
f = 1kHz
295
f = 10kHz
255
f = 0.1Hz to 10Hz
13
2.048V internal
reference
2.5V internal
reference
4.096V internal
reference
www.maximintegrated.com
f = 0.1Hz to 10kHz
f = 0.1Hz to 10kHz
External reference
MAX
UNITS
90
f = 1kHz
External reference
Integrated Output Noise
(DAC Output at Full Scale)
TYP
f = 10kHz
4.096V internal
reference
Output Voltage-Noise Density
(DAC Output at Full Scale)
MIN
2.048V internal
reference
External reference
Integrated Output Noise
(DAC Output at Midscale)
f = 1kHz
f = 0.1Hz to 10kHz
94
f = 0.1Hz to 300kHz
540
f = 0.1Hz to 10Hz
19
f = 0.1Hz to 10kHz
143
f = 0.1Hz to 300kHz
685
f = 0.1Hz to 10Hz
21
f = 0.1Hz to 10kHz
159
f = 0.1Hz to 300kHz
705
f = 0.1Hz to 10Hz
26
f = 0.1Hz to 10kHz
213
f = 0.1Hz to 300kHz
750
nV/√Hz
FVP-P
nV/√Hz
FVP-P
Maxim Integrated │ 4
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Electrical Characteristics (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
V
REFERENCE INPUT
Reference Input Range
VREF
Reference Input Current
IREF
Reference Input Impedance
RREF
1.24
VREF = VDD = 5.5V
55
74
75
100
VREF = 2.048V, TA = +25NC
2.043
2.048
2.053
VREF = 2.5V, TA = +25NC
2.494
2.500
2.506
VREF = 4.096V, TA = +25NC
4.086
4.096
4.106
FA
kI
REFERENCE OUTPUT
Reference Output Voltage
VREF
Reference Temperature
Coefficient (Note 10)
MAX5725A
Q3
Q10
MAX5723/MAX5724/MAX5725B
Q10
Q25
Reference Drive Capacity
External load
Reference Capacitive Load
Handling
Reference Load Regulation
ISOURCE = 0 to 500FA
Reference Line Regulation
V
ppm/NC
25
kI
200
pF
2
mV/mA
0.05
mV/V
POWER REQUIREMENTS
Supply Voltage
I/O Supply Voltage
VDD
VREF = 4.096V
4.5
5.5
All other options
2.7
5.5
VDDIO
1.8
Internal reference
Supply Current (Note 11)
IDD
External reference
Power-Down Mode Supply
Current
Digital Supply Current
IPD
IDDIO
5.5
VREF = 2.048V
1.6
2
VREF = 2.5V
1.7
2.1
VREF = 4.096V
2.0
2.5
VREF = 3V
1.6
2.0
1.9
2.5
VREF = 5V
All DACs off, internal reference ON
140
All DACs off, internal reference OFF,
TA = -40NC to +85NC
0.7
2
All DACs off, internal reference OFF,
TA = +125NC
2
4
Static logic inputs, all outputs unloaded
V
V
mA
FA
1
FA
Q1
FA
DIGITAL INPUT CHARACTERISTICS (SCLK, DIN, CSB, LDAC, CLR, M/Z)
Input Leakage Current
IIN
VIN = 0V or VDDIO, all inputs except M/Z
(Note 11)
Q0.1
VIN = 0V or VDD, for M/Z (Note 11)
www.maximintegrated.com
Maxim Integrated │ 5
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Electrical Characteristics (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
Input High Voltage
SYMBOL
VIH
CONDITIONS
(All inputs except
M/Z)
2.2V < VDDIO < 5.5V
0.7 x
VDDIO
1.8V < VDDIO < 2.2V
0.8 x
VDDIO
2.7V < VDD < 5.5V (for M/Z)
Input Low Voltage
VIL
(All inputs except
M/Z)
MIN
TYP
CIN
Hysteresis Voltage
VH
UNITS
V
V
0.7 x
VDD
2.2V < VDDIO < 5.5V
0.3 x
VDDIO
1.8V < VDDIO < 2.2V
0.2 x
VDDIO
0.3 x
VDD
2.7V < VDD < 5.5V (for M/Z)
Input Capacitance (Note 10)
MAX
10
0.15
V
V
pF
V
DIGITAL OUTPUT (IRQ)
Output Low Voltage
VOL
Output Inactive Leakage
IOFF
Output Inactive Capacitance
(Note 10)
COFF
ISINK = 3mA
Q0.1
0.2
V
Q1
FA
10
pF
DIGITAL OUTPUT (DOUT)
Output High Voltage
VDDIO > 2.5V, ISOURCE = 3mA
VDDIO
- 0.2
VDDIO > 1.8V, ISOURCE = 2mA
VDDIO
- 0.2
VOH
Output Low Voltage
VOL
V
VDDIO > 2.5V, ISINK = 3mA
0.2
VDDIO > 1.8V, ISINK = 2mA
0.2
Output Short-Circuit Current
IOSS
Output Three-State Leakage
IOZ
ISINK, ISOURCE
±100
±0.1
Output Three-State
Capacitance
COZ
10
V
mA
±1
µA
pF
WATCHDOG TIMER CHARACTERISTICS
Watchdog Timer Period
tWDOSC
VDD = 3V, TA = +25°C
Watchdog Timer Period Supply
Drift
VDD = 2.7V to 5.5V, TA = +25°C
Watchdog Timer Period
Temperature Drift
VDD = 3V
www.maximintegrated.com
0.95
1
1.05
ms
0.6
%/V
0.0375
%/°C
Maxim Integrated │ 6
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Electrical Characteristics (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING CHARACTERISTICS
2.7V < VDDIO < 5.5V
SCLK Frequency
fSCLK
1.8V < VDDIO < 2.7V
SCLK Period
tSCLK
Write mode
0
50
Read mode,
strobing on 1 SCLK
0
25
Read mode,
strobing on ½ SCLK
0
12.5
Write mode
0
33
Read mode,
strobing on 1 SCLK
0
20
Read mode,
strobing on ½ SCLK
0
10
2.7V < VDDIO < 5.5V, write mode
20
1.8V < VDDIO < 2.7V, write mode
30
MHz
ns
SCLK Pulse Width High
tCH
8
ns
SCLK Pulse Width Low
tCL
8
ns
2.7V < VDDIO < 5.5V
8
1.8V < VDDIO < 2.7V
12
CSB Fall to SCLK Fall Setup Time
tCSS0
To first SCLK falling
edge
CSB Fall to SCLK Fall Hold Time
tCSH0
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
0
ns
CSB Rise to SCLK Fall Hold Time
tCSH1
Applies to the 24th SCLK falling edge
0
ns
12
ns
100
ns
Applies to the 24th SCLK falling edge,
ns
CSB Rise to SCLK Fall
tCSA
SCLK Fall to CSB Fall
tCSF
CSB Pulse Width High
tCSPW
20
ns
tDS
5
ns
tDH
4.5
ns
CLR Pulse Width Low
tCLPW
20
ns
CLR Rise to CSB Fall
tCSC
20
ns
20
ns
20
ns
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
LDAC Pulse Width Low
aborted sequence
Applies to 24th SCLK falling edge
Required for command to be executed
tLDPW
LDAC Fall to SCLK Fall Hold
tLDH
Applies to 24th SCLK falling edge
SCLK Fall to DOUT Transition
tDOT
DPHA = 0,
CLOAD = 20pF
2.7V < VDDIO < 5.5V
35
1.8V < VDDIO < 2.7V
40
SCLK Rise to DOUT Transition
tDOT
DPHA = 1,
CLOAD = 20pF
2.7V < VDDIO < 5.5V
35
1.8V < VDDIO < 2.7V
40
www.maximintegrated.com
ns
ns
Maxim Integrated │ 7
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Electrical Characteristics (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Fall to DOUT Hold
tDOH
DPHA = 0, CLOAD = 0pF
2
ns
SCLK Rise to DOUT Hold
tDOH
DPHA = 1, CLOAD = 0pF
2
ns
CSB Fall to DOUT Fall
tDOE
Enable time, CLOAD = 20pF
tDOZ
CSB Rise to DOUT Hi-Z
Disable time
20
2.7V < VDDIO < 5.5V
20
1.8V < VDDIO < 2.7V
40
ns
ns
Note 3: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range
are guaranteed by design and characterization. Typical specifications are at TA = +25°C.
Note 4: DC performance is tested without load, VREF = VDD.
Note 5: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 6: Gain and offset calculated from measurements made with VREF = VDD at codes 30 and 4065 for MAX5725, codes 8 and
1016 for MAX5724, and codes 2 and 254 for MAX5723.
Note 7: Subject to zero- and full-scale error limits and VREF settings.
Note 8: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 9: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 10: Guaranteed by design.
Note 11: All channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDDIO for all inputs.
DIN23
DIN
DIN22
DIN21
DIN20
1
tCSH0
2
3
tCSS0
4
tCH
DIN18
DIN17
DIN16
DIN15
DIN14
7
8
9
10
DIN1
DIN0
DIN23’
tSCLK
tDH
tDS
SCLK
DIN19
5
6
23
24
tCSA
tCL
1
tCSH1
CSB
tCSPW
DOUT
(DPHA = 1)
DO15
DOUT
(DPHA = 0)
CLR
Z
tCLPW
DO1
tDOT
tDOE
DO15
DO14
tCSF
tDOH
tDOT
Z
DO0
tDOH
D O1
Z
tDOZ
Z
DO0
tCSC
tLDH
tLDPW
LDAC
Figure 1. SPI Serial Interface Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 8
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Typical Operating Characteristics
(MAX5725, 12-bit performance, TA = +25°C, unless otherwise noted.)
INL vs. CODE
VDD = VREF = 5V
NO LOAD
0.8
0.6
1.0
MAX5723 toc02
0.6
0.4
0.2
0.2
0.2
-0.2
DNL (LSB)
0.4
INL (LSB)
0.4
0
0
-0.2
0
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
-1.0
512 1024 1536 2048 2560 3072 3584 4096
0
CODE (LSB)
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
DNL vs. CODE
VDD = VREF = 5V
NO LOAD
0.6
INL AND DNL vs. SUPPLY VOLTAGE
1.0
MAX5723 toc04
1.0
0.8
0.6
ERROR (LSB)
DNL (LSB)
0
-0.2
-0.4
-0.6
-0.8
-0.8
MIN DNL
MIN INL
-1.0
512 1024 1536 2048 2560 3072 3584 4096
2.7
3.1
3.5
3.9
4.3
4.7
5.1
CODE (LSB)
SUPPLY VOLTAGE (V)
INL AND DNL vs. TEMPERATURE
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
VDD = VREF = 3V
0.6
1.0
MAX5723 toc06
0
0.6
ERROR (mV)
0
-0.2
-0.4
MIN INL
MIN DNL
-0.8
5.5
ZERO-SCALE ERROR
0.4
MAX DNL
0.2
VREF = 2.5V (EXTERNAL)
NO LOAD
0.8
MAX INL
0.4
ERROR (LSB)
0
-0.2
-0.6
-1.0
MAX DNL
0.2
-0.4
-0.6
MAX INL
0.4
0.2
0.8
VDD = VREF
0.8
0.4
1.0
512 1024 1536 2048 2560 3072 3584 4096
0
CODE (LSB)
MAX5723 toc05
0
VDD = VREF = 3V
NO LOAD
0.8
MAX5723 toc07
0.6
INL (LSB)
MAX5723 toc01
VDD = VREF = 3V
NO LOAD
0.8
DNL vs. CODE
1.0
MAX5723 toc03
INL vs. CODE
1.0
0.2
0
-0.2
OFFSET ERROR
-0.4
-0.6
-0.8
-1.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
www.maximintegrated.com
-1.0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
Maxim Integrated │ 9
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5725, 12-bit performance, TA = +25°C, unless otherwise noted.)
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
0.016
0.012
GAIN ERROR
0.008
OFFSET ERROR (VDD = 5V)
0.2
ERROR (%fs)
0
-0.2
OFFSET ERROR (VDD = 3V)
-0.4
0.004
0
-0.004
FULL-SCALE ERROR
-0.008
-0.6
-0.012
-0.8
-0.016
-1.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
VREF = 2.5V (EXTERNAL)
NO LOAD
-0.020
2.7
3.1
TEMPERATURE (°C)
1.8
SUPPLY CURRENT (mA)
ERROR (%fsr)
GAIN ERROR (VDD = 5V)
0
FULL-SCALE ERROR
GAIN ERROR (VDD = 3V)
-0.05
5.1
5.5
VREF (INTERNAL) =
4.096V, VDD = 5V
1.4
VREF (INTERNAL) =
2.5V, VDD = 5V
VREF (INTERNAL) =
2.048V, VDD = 5V
VREF (EXTERNAL) = VDD = 3V
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
POWER-DOWN MODE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VREF (INTERNAL) = 4.096V
1.8
VREF (INTERNAL) = 2.5V
1.6
1.4
1.2
VREF (INTERNAL) =
2.048V
0.6
VREF = 2.5V (EXTERNAL)
VDD = VDDIO
VOUT_ = FULL SCALE
ALL DACS ENABLED
NO LOAD
0.4
0.2
0
2.7
3.1
3.5
3.9
4.3
4.7
SUPPLY VOLTAGE (V)
www.maximintegrated.com
5.1
5.5
2.0
POWER-DOWN SUPPLY CURRENT (µA)
MAX5723 toc12
TEMPERATURE (°C)
2.0
SUPPLY CURRENT (mA)
4.7
VREF (EXTERNAL) = VDD = 5V
1.6
1.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
0.8
VDD = VDDIO
VOUT_ = FULL SCALE
ALL DACS ENABLED
NO LOAD
1.2
-0.10
1.0
4.3
SUPPLY CURRENT vs. TEMPERATURE
2.0
MAX5723 toc10
VREF = 2.5V (EXTERNAL)
NO LOAD
0.05
3.9
SUPPLY VOLTAGE (V)
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
0.10
3.5
1.6
MAX5723 toc13
ERROR (mV)
0.4
MAX5723 toc11
0.6
MAX5723 toc09
VREF = 2.5V (EXTERNAL)
NO LOAD
ZERO-SCALE ERROR
0.8
0.020
MAX5723 toc08
1.0
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
VDD = VDDIO
VREF = 2.5V (EXTERNAL)
POWER-DOWN MODE WITH HI-Z
NO LOAD
TA = +125°C
1.2
0.8
TA = +85°C
TA = +25°C
TA = -40°C
0.4
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
Maxim Integrated │ 10
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5725, 12-bit performance, TA = +25°C, unless otherwise noted.)
IVDD vs. CODE
SUPPLY CURRENT (mA)
1.6
VDD = VREF = 5V
1.2
VDD = 5V,
VREF = 2.048V
0.8
VDD = 5V,
VREF = 2.5V
VDD = VREF = 3V
0.4
VDD = VREF
NO LOAD
50
REFERENCE CURRENT (µA)
VDD = 5V, VREF = 4.096V
MAX5723 toc15
IREF (EXTERNAL) vs. CODE
60
MAX5723 toc14
2.0
40
VREF = 5V
30
VREF = 3V
20
10
NO LOAD
0
0
512 1024 1536 2048 2560 3072 3584 4096
0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
CODE (LSB)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5723 toc17
MAX5723 toc16
VOUT
0.5V/div
3/4 SCALE TO 1/4 SCALE
1/4 SCALE TO 3/4 SCALE
4.3µs
ZOOMED VOUT
1 LSB/div
ZOOMED VOUT
1 LSB/div
3.75µs
VOUT
0.5V/div
TRIGGER PULSE
5V/div
TRIGGER PULSE
5V/div
4µs/div
4µs/div
MAJOR CODE TRANSITION GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAJOR CODE TRANSITION GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5723 toc19
MAX5723 toc18
VOUT
3.3mV/div
1 LSB CHANGE
(MIDCODE TRANSITION
FROM 0x800 TO 0x7FF)
GLITCH ENERGY = 6nV*s
1 LSB CHANGE
(MIDCODE TRANSITION
FROM 0x7FF TO 0x800)
GLITCH ENERGY = 6.7nV*s
TRIGGER PULSE
5V/div
VOUT
3.3mV/div
TRIGGER PULSE
5V/div
2µs/div
www.maximintegrated.com
Maxim Integrated │ 11
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5725, 12-bit performance, TA = +25°C, unless otherwise noted.)
VOUT vs. TIME TRANSIENT
EXITING POWER-DOWN
POWER-ON RESET TO 0V
MAX5723 toc21
MAX5723 toc20
VSCLK
5V/div
0V
24TH EDGE
DAC OUTPUT
500mV/div
VDD = VREF = 5V
10kI LOAD TO VDD
VDD
2V/div
0V
VOUT
2V/div
0V
VDD = 5V, VREF = 2.5V
EXTERNAL
0V
10µs/div
20µs/div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC, NO LOAD)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V, TA = +25NC, NO LOAD)
MAX5723 toc23
MAX5723 toc22
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 2.6nV*s
VOUT4
0.585 LSB/div
NO LOAD
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*s
VOUT0
5V/div
NO LOAD
VOUT4
0.585 LSB/div
NO LOAD
VOUT0
5V/div
NO LOAD
4µs/div
4µs/div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC,
RL = 2kI, CL = 200pF)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, RL = 2kI, CL = 200pF)
MAX5723 toc24
MAX5723 toc25
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 4.07nV*s
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*S
VOUT4
0.585 LSB/div
NO LOAD
VOUT4
0.585 LSB/div
NO LOAD
VOUT0
5V/div
LOADED
VOUT0
5V/div
LOADED
4µs/div
www.maximintegrated.com
4µs/div
Maxim Integrated │ 12
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5725, 12-bit performance, TA = +25°C, unless otherwise noted.)
DIGITAL FEEDTHROUGH
(VDD = VREF = 5V, RL = 10kI)
OUTPUT LOAD REGULATION
MAX5723 toc26
VREF = 4.096V (INTERNAL)
DIGITAL CROSSTALK = 0.2nV*S
MAX5723 toc27
10
VDD = VREF
8
6
VDD = 5V
DVOUT (mV)
4
2.5mV/div
2
0
VDD = 3V
-2
-4
-6
-8
-10
-30 -20 -10
20ns/div
0
10
20
30
40
50
60
IOUT (mA)
HEADROOM AT RAILS
vs. OUTPUT CURRENT (VDD = VREF)
OUTPUT CURRENT LIMITING
VDD = VREF
300
4.50
3.50
VDD = 5V
0
-100
2.50
VDD = 3V, SOURCING
2.00
VDD = 3V
-200
1.50
-300
1.00
-400
0.50
-500
0
-30 -20 -10 0
DAC = FULL SCALE
3.00
VOUT (V)
DVOUT (mV)
VDD = 5V, SOURCING
4.00
200
100
MAX5723 toc29
400
5.00
MAX5723 toc28
500
VDD = 3V AND 5V
SINKING
DAC = ZERO SCALE
0
10 20 30 40 50 60 70
1
2
3
4
5
6
7
8
9
10
IOUT (mA)
IOUT (mA)
NOISE-VOLTAGE DENSITY vs. FREQUENCY
(DAC AT MIDSCALE)
MAX5723 toc30
NOISE-VOLTAGE DENSITY (nV/√Hz)
350
VDD = 5V, VREF = 4.096V
INTERNAL
300
VDD = 5V, VREF = 2.5V
INTERNAL
250
200
VDD = 5V, VREF = 2.048V
INTERNAL
150
100
50
VDD = 5V, VREF = 3.5V
(EXTERNAL)
0
100
1k
10k
100k
FREQUENCY (Hz)
www.maximintegrated.com
Maxim Integrated │ 13
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5725, 12-bit performance, TA = +25°C, unless otherwise noted.)
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
REFERENCE (VDD = 5V, VREF = 4.5V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.048V)
MAX5723 toc31
MAX5723 toc32
MIDSCALE UNLOADED
VP-P = 12µV
MIDSCALE UNLOADED
VP-P = 13µV
2µV/div
2µV/div
4s/div
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.5V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 4.096V)
MAX5723 toc33
MAX5723 toc34
MIDSCALE UNLOADED
VP-P = 16µV
MIDSCALE UNLOADED
VP-P = 15µV
2µV/div
4s/div
www.maximintegrated.com
2µV/div
4s/div
Maxim Integrated │ 14
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5725, 12-bit performance, TA = +25°C, unless otherwise noted.)
MAX5723 toc35
20
15
10
VDD = 5V
INTERNAL REFERENCE
-0.2
DVREF (mV)
-0.4
-0.6
VREF = 2.048V, 2.5V, AND 4.096V
-0.8
5
-1.0
0
0
2.8 2.9 3.0 3.2 3.3 3.4 3.6 3.7 3.9 4.0 4.1 4.3 4.4
TEMPERATURE DRIFT (ppm/°C)
WATCHDOG TIMER PERIOD HISTOGRAM
2500
2000
1500
1000
VDDIO = 3V
12
10
8
6
4
2
500
0
1
2
3
4
5
INPUT LOGIC VOLTAGE (V)
FREQUENCY (Hz)
WATCHDOG TIMER FREQUENCY
vs. TEMPERATURE
WATCHDOG TIMER FREQUENCY
vs. SUPPLY VOLTAGE
1000
995
990
985
980
1010
WATCHDOG TIMER FREQUENCY (Hz)
MAX5723 toc39
1005
VDD = 3V
1000
990
MAX5723 toc40
0
988
VDDIO = 1.8V
0
WATCHDOG TIMER FREQUENCY (Hz)
MAX5723 toc38
VDDIO = 5V
14
PERCENT OF POPULATION (%)
SUPPLY CURRENT (µA)
VDD = 3V
SCLK, CSB, DIN,
CLR, AND LDAC
SWEPT FROM 0V
TO VDDIO AND
VDDIO TO 0V
3000
MAX5723 toc37
SUPPLY CURRENT vs. SUPPLY VOLTAGE
3500
50 100 150 200 250 300 350 400 450 500
REFERENCE OUTPUT CURRENT (µA)
990
992
994
996
998
1000
1002
1004
1006
1008
1010
1012
1014
PERCENT OF POPULATION (%)
0
MAX5723 toc36
REFERENCE LOAD REGULATION
VREF DRIFT vs. TEMPERATURE
25
980
970
960
950
940
930
920
975
2.7
3.1
3.5
3.9
4.3
4.7
SUPPLY VOLTAGE (V)
www.maximintegrated.com
5.1
5.5
910
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Maxim Integrated │ 15
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Pin Configurations
TOP VIEW
TOP VIEW
REF
1
OUT0
2
OUT1
3
OUT2
4
OUT3
5
OUT4
6
MAX5723/MAX5724/MAX5725
+
MAX5723
MAX5724
MAX5725
20
M/Z
19
GND
18
LDAC
17
CLR
16
IRQ
15
CSB
OUT5
7
14
SCLK
OUT6
8
13
DIN
OUT7
9
12
DOUT
VDD
10
11
VDDIO
1
2
3
4
5
+ OUT6
OUT7
VDDIO
DOUT
DIN
OUT5
OUT4
VDD
CSB
SCLK
OUT2
OUT3
M/Z
CLR
IRQ
OUT1
OUT0
REF
GND
LDAC
A
B
C
D
WLP
TSSOP
Pin Description
PIN
NAME
FUNCTION
TSSOP
WLP
1
D3
REF
Reference Voltage Input/Output
2
D2
DAC0
DAC Channel 0 Voltage Output
3
D1
OUT1
DAC Channel 1 Voltage Output
4
C1
OUT2
DAC Channel 2 Voltage Output
5
C2
OUT3
DAC Channel 3 Voltage Output
6
B2
OUT4
DAC Channel 4 Voltage Output
7
B1
OUT5
DAC Channel 5 Voltage Output
8
A1
OUT6
DAC Channel 6 Voltage Output
9
A2
OUT7
DAC Channel 7 Voltage Output
10
B3
VDD
Analog Supply Voltage
11
A3
VDDIO
Digital Supply Voltage
12
A4
DOUT
SPI Serial Data Output
13
A5
DIN
SPI Serial Data Input
14
B5
SCLK
SPI Serial Clock Input
15
B4
CSB
SPI Chip-Select Input
16
C5
IRQ
17
C4
CLR
Active-Low Open Drain Interrupt Output. IRQ low indicates watchdog timeout.
Active-Low Asynchronous DAC Clear Input
18
D5
19
D4
LDAC
GND
20
C3
M/Z
www.maximintegrated.com
Active-Low Asynchronous DAC Load Input
Ground
DAC Output Reset Selection. Connect M/Z to GND for zero-scale and connect M/Z to
VDD for midscale.
Maxim Integrated │ 16
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Detailed Description
Internal Register Structure
The MAX5723/MAX5724/MAX5725 are 8-channel, lowpower, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and lowvoltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software-selectable options of 2.048V,
2.500V, or 4.096V. The devices feature a fast 4-wire
SPI/QSPI/MICROWIRE/DSP-compatible serial interface
to save board space and reduce the complexity in isolated applications interface. The MAX5723/MAX5724/
MAX5725 include a serial-in/parallel-out shift register,
internal CODE and DAC registers, a power-on-reset
(POR) circuit to initialize the DAC outputs to zero scale
(M/Z = 0) or midscale (M/Z = 1), and control logic.
CLR is available to asynchronously clear the DAC outputs to a user-programmable default value, independent
of the serial interface. LDAC is available to simultaneously update selected DACs on one or more devices.
The MAX5723/MAX5724/MAX5725 also feature userconfigurable interface watchdog, with status indicated
by the IRQ output.
DAC Outputs (OUT_)
The MAX5723/MAX5724/MAX5725 include internal buffers on all DAC outputs, which provide improved load
regulation for the DAC outputs. The output buffers slew
at 1V/Fs (typ) and drive resistive loads are as low as 2kI
in parallel with as much as 500pF of capacitance. The
analog supply voltage (VDD) determines the maximum
output voltage range of the devices since it powers the
output buffers. Under no-load conditions, the output buffers drive from GND to VDD, subject to offset and gain
errors. With a 2kω load to GND, the output buffers drive
from GND to within 200mV of VDD. With a 2kω load to
VDD, the output buffers drive from VDD to within 200mV
of GND.
The DAC ideal output voltage is defined by:
VOUT
= VREF ×
D
2N
where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
www.maximintegrated.com
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user commands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands or the LDAC
logic input.
The contents of both CODE and DAC registers are maintained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents.
Once the device is powered up, each DAC channel can
be independently programmed with a desired RETURN
value using the RETURN command. This becomes the
value the CODE and DAC registers will use in the event
of any watchdog, clear or gate activity, as selected by
the DEFAULT command.
Hardware CLR operations and SW_CLEAR commands
return the contents of all CODE and DAC registers to their
user-selected defaults. SW_RESET commands will reset
CODE and DAC register contents to their M/Z selected
initial codes. A SW_GATE state can be used to momentarily hold selected DAC outputs in their DEFAULT positions. The contents of CODE and DAC registers can
be manipulated by watchdog timer activity, enabling a
variety of safety features.
Internal Reference
The MAX5723/MAX5724/MAX5725 include an internal
precision voltage reference that is software selectable to
be 2.048V, 2.500V, or 4.096V. When an internal reference
is selected, that voltage is available on the REF output
for other external circuitry (see the Typical Operating
Circuits) and can drive loads down to 25kI.
Maxim Integrated │ 17
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
External Reference
The external reference input has a typical input impedance
of 100kI and accepts an input voltage from +1.24V to VDD.
Apply an external voltage between REF and GND to use
an external reference. The MAX5723/MAX5724/MAX5725
power up and reset to external reference mode. Visit
www.maximintegrated.com/products/references for a
list of available external voltage-reference devices.
M/Z Input
The MAX5723/MAX5724/MAX5725 feature a pin-selectable DAC reset state using the M/Z input. Upon a poweron reset, all CODE and DAC data registers are reset to
zero scale (M/Z = GND) or midscale (M/Z = VDD). M/Z is
referenced to VDD (not VDDIO). In addition, M/Z must be
valid at the time the device is powered up—connect M/Z
directly to VDD or GND.
Load DAC (LDAC) Input
The MAX5723/MAX5724/MAX5725 feature an active-low
asynchronous LDAC logic input that allows DAC outputs
to update simultaneously. Connect LDAC to VDDIO or
keep LDAC high during normal operation when the
device is controlled only through the serial interface.
Drive LDAC low to update the DAC outputs with data
from the CODE registers. Holding LDAC low causes the
DAC registers to become transparent and CODE data is
passed through to the DAC registers immediately updating the DAC outputs. A software CONFIG command can
be used to configure the LDAC operation of each DAC
independently.
mand can be used to configure the clear operation of
each DAC independently.
Watchdog Feature
The MAX5723/MAX5724/MAX5725 feature an interface
watchdog timer with programmable timeout duration. This
monitors the I/O interface for activity and integrity. If the
watchdog is enabled, the host processor must write a valid
command to the device within the timeout period to prevent
a timeout. If the watchdog is allowed to timeout, selected
DAC outputs are returned to the programmable DEFAULT
state, protecting the system against control faults.
By default, all watchdog features are disabled; users
wishing to activate any watchdog feature must configure
the device accordingly. Individual DAC channels can
be configured using the CONFIG command to accept
the watchdog alarm and to gate, clear, or hold their outputs in response to an alarm. A watchdog refresh event
and watchdog behavior upon timeout is defined by a
programmable safety level using the WDOG_CONFIG
command.
IRQ Output
The MAX5723/MAX5724/MAX5725 feature an active-low
open-drain interrupt output indicating to the host when a
watchdog timeout has occurred.
Interface Power Supply (VDDIO)
The MAX5723/MAX5724/MAX5725 feature a separate
supply input (VDDIO) for the digital interface (1.8V to 5.5V).
Connect VDDIO to the I/O supply of the host processor.
Clear (CLR) Input
SPI Serial Interface
The MAX5723/MAX5724/MAX5725 feature an asynchronous active-low CLR logic input that simultaneously
sets all selected DAC outputs to their programmable
DEFAULT states. Driving CLR low clears the contents of
both the CODE and DAC registers and also ignores any
on-going SPI command which modifies registers associated with a DAC configured to accept clear operations.
To allow a new SPI command, drive CLR high, satisfying
the tCSC timing requirement. A software CONFIG com-
The MAX5723/MAX5724/MAX5725 4-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and
DSPs. The interface provides three inputs, SCLK, CSB,
and DIN. The chip-select input (CSB, active-low) frames
the data loaded through the serial data input (DIN).
Following a CSB input high-to-low transition, the data
is shifted in synchronously and latched into the input
register on each falling edge of the serial clock input
(SCLK). Each serial operation word is 24-bits long. The
DAC data is left justified as shown in Table 1. The serial
Table 1. Format DAC Data Bit Positions
PART
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MAX5723
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
MAX5724
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
MAX5725
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
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Maxim Integrated │ 18
MAX5723/MAX5724/
MAX5725
input register transfers its contents to the destination
registers after loading 24 bits of data on the 24th SCLK
falling edge. To initiate a new SPI operation, drive CSB
high and then low to begin the next operation sequence,
being sure to meet all relevant timing requirements.
During CSB high periods, SCLK is ignored, allowing
communication to other devices on the same bus. SPI
operations consisting of more than 24 SCLK cycles are
executed on the 24th SCLK falling edge, using the first
three bytes of data available. SPI operations consisting
of less than 24 SCLK cycles will not be executed. The
content of the SPI operation consists of a command
byte followed by a two-byte data word.
The DOUT phase for all SPI_READ commands is determined by the readback command used, allowing the
selection of the SCLK DOUT update edge best suited to
the digital I/O implementation, maximizing data transfer
speed and/or timing margin.
Guaranteed non-zero DOUT hold times allow the microprocessor to strobe DOUT on the same edge as the
MAX5723/MAX5724/MAX5725 updates for fastest SPI
read mode transfers. For example, if DPHA = 0 is used,
the MAX5723/MAX5724/MAX5725 update DOUT in
response to SCLK falling edges 8-23, while a microprocessor (µP) with low data hold time requirements can
strobe in the DOUT data on SCLK falling edges 9-24.
The device supports readback speeds of up to 25MHz
for a microprocessor with 5ns data input setup requirements and allowing 35ns for tDOT at VDDIO > 2.7V.
Variable DOUT phase also supports microprocessors
with longer data input hold time requirements. For
example, if DPHA = 1 is used, the MAX5723/MAX5724/
MAX5725 updates DOUT in response to SCLK rising
edges 9-24 while the microprocessor can strobe in the
DOUT data on SCLK falling edges 9-24. The device
supports readback speeds up to 12.5MHz for a µP with
5ns data input setup requirements and allowing 35ns for
tDOT (assuming 50% duty cycle SCLK).
For improved readback speed while monitoring device
status, the SPI_READ_STATUS command repeats the
device status information for multiple bits, allowing
polling of the device at maximum interface speeds (up
to 50MHz when the readback strobe is placed away
from DOUT transition edges). This transfer speed cannot be achieved for other forms of readback using the
SPI_READ_DATA command, where more DOUT bus
transitions occur.
www.maximintegrated.com
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
+5V
RPU = 5kI
µC
CSB1
CSB
SCLK
SCLK
MOSI
DIN
MISO
DOUT
IRQ
IRQ
CSB2
CSB
MAX5723
MAX5724
MAX5725
SCLK
DIN
DOUT
IRQ
CSB3
CSB
SCLK
DIN
Figure 2. Typical SPI Application Circuit
Figure 1 shows the timing diagram for the complete
4-wire serial interface transmission. The DAC code
settings (D) for the MAX5723/MAX5724/MAX5725 are
accepted in an offset binary format (see Table 1).
Otherwise, the expected data format for each command
is listed in Table 2. See Figure 2 for an example of a
typical SPI circuit application.
SPI User-Command Register Map
This section lists the user-accessible commands and
registers for the MAX5723/MAX5724/MAX5725.
Table 2 provides detailed information about the Command
Registers.
Maxim Integrated │ 19
0
SW_RESET
0
0
SW_CLEAR
CONFIG
0
WD_RESET
1
0
0
0
0
0
0
0
0
0
0
WD_REFRESH
SET
CLR
SW_GATE_
SW_GATE_
0
REF
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
X
X
0
1
1
0
0
0
0
1=ON
10 = 2.0V
DAC
0
0
0
1
1
0
0
0
1
0
1
0
1
0
11 = 4.1V
01 = 2.5V
00 = EXT
REF Mode
X
0=
Power
REF
X
1
1
1
1
1
1
X
0
0
0
0
0
0
X
B11
B10
0
0
0
0
0
0
X
1
1
1
1
1
1
X
0
0
0
0
0
0
X
1
1
1
1
1
1
X
TIMEOUT SELECTION[11:4]
DAC6
0
DAC5
0
DAC4
WDOG
B13 B12
DAC3
CONFIGURATION AND SOFTWARE COMMANDS
DAC7
B14
DAC2
B16 B15
1
1
1
1
1
1
X
B9
DAC1
B23 B22 B21 B20 B19 B18 B17
0
0
0
0
0
0
X
B8
DAC0
COMMAND
B5
TIMEOUT
B6
B4
0
0
0
0
0
0
X
11: HOLD
10: CLR
01: GATE
00: DIS
Config.
WDOG
0
0
0
0
0
0
X
1
1
1
1
1
1
X
1
1
1
1
1
1
X
SELECTION[3:0]
B7
GATE_ENB
B3
0
0
0
0
0
0
X
WD_MASK
Table 2. SPI Commands Summary
LDAC_ENB
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CLEAR_ENB
B1
X
0
0
0
0
0
0
X
X
0
0
0
0
0
0
X
11: Max
10: High
01: Med
00: Low
Level
Safety
B2
X
0
0
0
0
0
0
X
X
B0
are not impacted)
corresponding DACn bit
DACs with a 0 in the
DACn bit are updated,
1 in the corresponding
DACs selected with a
and CLEAR operations.
Watchdog, GATE, LOAD,
Configures selected DAC
values)
to their power-on reset
control registers returned
(all CODE, DAC, and
Executes a software reset
DEFAULT values)
registers cleared to their
clear (all CODE and DAC
Executes a software
timer
refreshes the watchdog
out alarm status and
Reset the watchdog time
timer
Refreshes the watchdog
Initiates a GATE condition
GATE condition
Removes any existing
always powered
1 = Internal reference is
DAC is powered
only powered if at least one
0 = Internal reference is
Power (B18):
operating mode. REF
Sets the reference
settings and safety levels
Updates watchdog
DESCRIPTION
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Maxim Integrated │ 20
www.maximintegrated.com
0
DEFAULT
1
LOADn
CODE_ALL
LOADn
CODEn_
LOAD_ALL
1
1
1
1
CODEn
CODEn_
0
RETURNn
DAC COMMANDS
0
POWER
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
DAC Selection
DAC Selection
DAC Selection
DAC Selection
DAC Selection
0
0
0
0
0
B9
B8
X
X
X
X
X
CODE REGISTER
DATA[3:0]
CODE REGISTER
DATA[11:4]
CODE REGISTER
DATA[3:0]
CODE REGISTER
X
DATA[3:0]
X
DATA[11:4]
CODE REGISTER
DATA[11:4]
CODE REGISTER
X
DATA[3:0]
DATA[11:4]
X
CODE REGISTER
CODE REGISTER
X
DATA[3:0]
DATA[11:4]
101+: No Effect
100: RETURN
011: FULL
010: MID
001: ZERO
000: MZ
Default Values:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
are not impacted)
11 = PD
registers
Writes data to all CODE
register(s)
updating selected DAC
CODE register(s) while
data to the selected
Simultaneously writes
registers
updating all DAC
CODE register(s) while
data to the selected
Simultaneously writes
register(s)
to the selected DAC
selected CODE registers
Transfers data from the
register(s)
selected CODE
Writes data to the
register(s)
selected RETURN
Writes data to the
impacted)
DACn bit are not
a 0 in the corresponding
are updated, DACs with
corresponding DACn bit
selected with a 1 in the
RETURN codes. (DACs
mode programmable
DACs in RETURN
selected DACs. Note,
code settings for
Sets the DEFAULT
corresponding DACn bit
100kI
Hi-Z
DACs with a 0 in the
10 = PD
DACn bit are updated,
1 in the corresponding
PD1kI
(DACs selected with a
DESCRIPTION
01 =
X
B0
of the selected DACs
X
B1
Normal
X
B2
Sets the Power Mode
X
B3
00 =
X
B4
Mode
X
B5
RETURN REGISTER
X
B6
Power
B7
RETURN REGISTER
X
DAC7
DAC7
B10
DAC6
DAC6
B11
DAC5
DAC5
B13 B12
DAC4
DAC4
B14
DAC3
DAC3
B16 B15
DAC2
DAC2
B17
DAC1
DAC1
B23 B22 B21 B20 B19 B18
DAC0
DAC0
COMMAND
Table 2. SPI Commands Summary (continued)
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Maxim Integrated │ 21
www.maximintegrated.com
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
1
0
1
1
0
1
0
X
X
X
X
X
X
X
DAC Selection
0
0
0
B17
X
X
X
X
X
X
X
1
0
1
X
X
X
X
X
X
X
INC
X
B16 B15
X
X
X
X
X
X
X
X
B6
X
B5
X
B4
00 = DAC
X
X
X
X
X
X
X
11 = WDT
10 = RET
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DATA[3:0]
X
RETURN REGISTER
CODE REGISTER
X
B7
DATA[11:4]
X
X
B8
RETURN REGISTER
X
X
B9
DATA[3:0]
X
B10
DATA[11:4]
01 = CODE
X
X
B11
CODE REGISTER
X
B13 B12
DATA SEL [1:0]
X
B14
Reserved Commands: Any commands not specifically listed above are reserved for Maxim internal use only.
No Operation
1
1
0
0
0
0
1
0
0
0
B23 B22 B21 B20 B19 B18
NO OPERATION COMMANDS
DATA
SPI_READ
STATUS
SPI_READ
REQUEST
SPI_DATA_
RETURN_ALL
LOAD_ALL
CODE_ALL
LOAD_ALL
COMMAND
Table 2. SPI Commands Summary (continued)
X
X
X
X
X
X
X
X
X
X
X
B3
X
X
X
X
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
X
X
X
X
B1
X
X
X
X
X
X
X
X
X
X
X
B0
safety level is set to low.
the watchdog timer if
device, but will refresh
have no effect on the
These commands will
requested data
DPHA = 1 Readback
requested data
DPHA = 0 Readback
status
DPHA = 1 Readback
status
DPHA = 0 Readback
read back
the data content to be
DATA SEL[1:0] indicates
operation
each SPI_READ _DATA
to the next DAC after
selection is incremented
INC indicates if the DAC
readback.
Setup data request for
RETURN registers
Writes data to all
all DAC registers
registers while updating
data to the all CODE
Simultaneously writes
register data
with current CODE
Updates all DAC latches
DESCRIPTION
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Maxim Integrated │ 22
MAX5723/MAX5724/
MAX5725
RETURNn Command
The RETURN command (B[23:20] = 0111) sets the programmable default RETURN value. This value is used
for all future watchdog, clear, and gate operations when
RET is selected for the DAC using the DEFAULT command. Issuing this command with DAC_ADDRESS set to
all DACs will program the value for all RETURN registers
and is equivalent to RETURN_ALL. Note: This command is
inaccessible when a watchdog timeout has occurred if the
watchdog timer is configured for safety level = high or max.
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Table 3. DAC Selection
B19
B18
B17
B16
DAC SELECTED
0
0
0
0
DAC0
0
0
0
1
DAC1
0
0
1
0
DAC2
0
0
1
1
DAC3
0
1
0
0
DAC4
0
1
0
1
DAC5
0
1
1
0
DAC6
CODEn Command
0
1
1
1
DAC7
The CODEn command (B[23:20] = 1000) updates
the CODE register contents for the selected DAC(s).
Changes to the CODE register content based on this
command will not affect DAC outputs directly unless the
LDAC input is in a low state or the DAC latch has been
configured as transparent using the CONFIG command.
Issuing this command with DAC_ADDRESS set to all
DACs will program the value for all CODE registers and
is equivalent to CODE_ALL.
1
X
X
X
ALL DACs
LOADn Command
The LOADn command (B[23:20] = 1001) updates the
DAC register content for the selected DAC(s) by uploading the current contents of the selected CODE register(s)
into the selected DAC register(s). Channels for which
CODE content has not been modified since the last LOAD
or LDAC operation will not be updated to reduce digital
crosstalk. Issuing this command with DAC_ADDRESS set
to all DACs will update the contents of all DAC registers
and is equivalent to LOAD_ALL.
CODEn_LOADn Command
The CODEn_LOADn command (B[23:20] = 1011)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of the selected DAC(s). Channels for which CODE content has not
been modified since the last LOAD or LDAC operation
will not be updated to reduce digital crosstalk. Issuing
this command with DAC_ADDRESS set to all DACs is
equivalent to the CODE_ALL_LOAD_ALL (B[23:16] =
1100_0010) command.
CODEn_LOAD_ALL Command
DAC_ADDRESS set to all DACs will update the CODE
and DAC register contents of all DACs and is equivalent
to CODE_ALL_LOAD_ALL. Note this command by definition will modify at least one CODE register; to avoid this
use the LOAD command with DAC_ADDRESS set to all
DACs or the LOAD_ALL command.
CODE_ALL Command
The CODE_ALL command (B[23:16] = 1100_0000)
updates the CODE register contents for all DACs.
LOAD_ALL Command
The LOAD_ALL command (B[23:16] = 1100_0001)
updates the DAC register content for all DACs by uploading the current contents of the CODE registers to the
DAC registers.
CODE_ALL_LOAD_ALL Command
The CODE_ALL_LOAD_ALL command (B[23:16] =
1100_0010) updates the CODE register contents for all
DACs as well as the DAC register content of all DACs.
RETURN_ALL Command
The RETURN_ALL command (B[23:16] = 1100_0011)
updates the RETURN register contents for all DACs.
NO_OP Commands Command
All unused commands in the space (B[23:16] =
1100_01XX or 1100_1XXX) have no effect on the device,
but will refresh the watchdog timer (if active) with the
safety level set to low.
The CODEn_LOAD_ALL command (B[23:20] = 1010)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of all DACs.
Channels for which CODE content has not been modified
since the last LOAD or LDAC operation will not be updated to reduce digital crosstalk. Issuing this command with
www.maximintegrated.com
Maxim Integrated │ 23
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
WDOG Command
any register. LDAC and CLR inputs still function after a
watchdog timeout event.
The WDOG command (B[23:20] = 0001) updates the
watchdog timeout settings and safety levels for the
device. Timeout thresholds are selected in 1ms increments (1ms to 4095ms are available). The WD_MASK bit
can be used to mask the IRQ operation in response to the
watchdog status, if WD_MASK = 1, watchdog alarms will
not assert IRQ . The watchdog alarm status (WD bit) can
be polled using the available SPI status readback commands regardless of WD_MASK settings. A write to this
register will not reset a previously triggered watchdog
alarm (use the WD_RESET command for this purpose).
The watchdog timer refresh and timeout behavior is
defined by the programmable safety level below.
Medium (01): A WD_REFRESH command must be executed in order to refresh the watchdog timer. Other commands
as well as LDAC or CLR activity do not refresh the watchdog timer. A triggered watchdog alarm does not prevent
writes to any register. LDAC and CLR inputs still function
after a watchdog timeout event.
Available safety levels (WL[1:0]):
High (10): A WD_REFRESH command must be executed
to refresh the watchdog timer. Other commands as well
as LDAC or CLR activity do not refresh the watchdog
timer. A triggered watchdog alarm prevents execution
of all POWER, REF, CONFIG, DEFAULT, and RETURN
commands. LDAC and CLR inputs still function after a
watchdog timeout event.
Low (00): Watchdog timer will refresh with the execution
of any valid user mode command or no-op. Any successful slave address acknowledge qualifies to restart the
watchdog timer (run to the ninth SCL edge), regardless
of the command which follows. Issuing hardware CLR or
LDAC falling edge will also refresh the watchdog timer.
A triggered watchdog alarm does not prevent writes to
Max (11): A WD_REFRESH command must be executed
to refresh the watchdog timer. Other commands, as well
as LDAC or CLR activity, do not refresh the watchdog
timer. A triggered watchdog alarm prevents execution of
all POWER, REF, CONFIG, DEFAULT, and RETURN commands. LDAC and CLR are gated and do not function
after a watchdog timeout event.
Table 4. WDOG Command Format
0
0
1
X
WDOG Command
X
X
X
C11 C10 C9
Don’t Care
Default Value →
C8
C7
C6
C5
B7
B6
B5
B4
C4
C3
C2
C1
C0 WDM WL1 WL0
Timeout Selection
0
0
Command Byte
0
0
0
0
Timeout Selection
0
0
0
0
0
Data High Byte
0
B3
B2
B1
WDOG
Safety
Level:
00: Low
01:
Med
10:
High
11: Max
0
0
0
B0
X
Don’t Care
0
B8
WD_MASK
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
X
Data Low Byte
Table 5. Watchdog Safety Level Protection
WATCHDOG ANY COMMAND
SAFETY
REFRESHES
LEVEL
WDT
CLR/LDAC
REFRESHES
WDT
SW_RESET
PLUS WD_RFRS
REFRESHES WDT
ALL REGISTERS
ACCESSIBLE AFTER
WDT TIMEOUT*
CLR/LDAC AFFECT
DAC REGISTERS
AFTER WDT TIMEOUT*
00 (Low)
X
X
X
X
X
01 (Med)
—
—
X
X
X
10 (High)
—
—
X
—
X
11 (Max)
—
—
X
—
—
*Unless otherwise affected by Watchdog HOLD or CLR configurations as set by the CONFIG command. See the CONFIG register
definition for details.
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Maxim Integrated │ 24
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
REF Command
The REF command (B[23:20] = 0010) updates the global
reference setting used for all DAC channels. If an internal
reference mode is selected, bit RF2 (B18) defines the
reference power mode. If RF2 is set to zero (default), the
reference will be powered down any time all DAC channels are powered down (i.e. the device is in STANDBY
mode). If RF2 is set to one, the reference will remain powered even if all DAC channels are powered down, allowing continued operation of external circuitry (note in this
mode the low current shutdown state is not available).
This command is inaccessible when a watchdog timeout
has occurred and the watchdog timer is configured with
a safety level of high or max.
SW_GATE_CLR Command
The SW_GATE_CLR command (B[23:0] = 0011_0000_
1001_0110_0011_0000) will remove any existing GATE
condition initiated by a previous SW_GATE_SET comand.
SW_GATE_SET Command
The SW_GATE_SET command (B[23:0] = 0011_0001_
1001_0110_0011_0000) will initiate a GATE condition.
Any DACs configured with GTB = 0 (see the CONFIG
Command section) will have their outputs held at the
selected DEFAULT value until the GATE condition is later
removed by a subsequent SW_GATE_CLR command.
While in gate mode, the CODE and DAC registers con
tinue to function normally and are not reset (unless reset
by a watchdog timeout).
WD_REFRESH Command
The WD_REFRESH command (B[23:0] = 0011_0010_
1001_0110_0011_0000) will refresh the watchdog timer.
This is the only command which will refresh the watchdog timer if the device is configured with a safety level of
medium, high, or max. Use this command to prevent the
watchdog timer from timing out.
WD_RESET Command
A WD_RESET command (B[23:0] = 0011_0011_
1001_0110_0011_0000) will reset the watchdog interrupt
(timeout) status and refresh the watchdog timer. Use this
command to reset the IRQ timeout condition after the
watchdog timer has timed out. Any DACs impacted by an
existing timeout condition will return to normal operation.
SW_CLEAR Command
A software clear command (B[23:0] = 0011_0100_
001_0110_0011_0000) will clear the contents of the CODE
and DAC registers to the DEFAULT state for all channels
configured with CLB = 0 (see CONFIG command).
SW_RESET Command
A software reset command (B[23:0] = 0011_0101_
1001_0110_0011_0000) will reset all CODE, DAC,
and configuration registers to their defaults (including
POWER, DEFAULT, CONFIG, WDOG, and REF registers), simulating a power-on reset.
0
1
0
REF Command
B17
B16
0
RF2
RF1
RF0
0 = DAC Controlled
1 = Always ON
B23 B22 B21 B20 B19
0
B18
Reserved
Table 6. REF Command Format
Default Value →
0
Command Byte
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B15 B14 B13 B12 B11 B10 B9
X
X
X
REF Mode:
00: EXT
01: 2.5V
10: 2.0V
11: 4.0V
0
0
X
X
X
X
B8
X
B7 B6 B5 B4 B3 B2 B1 B0
X
X
X
Don’t Care
X
X
X
X
X
Data High Byte
X
X
X
X
X
X
X
X
Don’t Care
X
X
X
X
X
X
X
X
Data Low Byte
Maxim Integrated │ 25
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
POWER Command
occurred and the watchdog timer is configured with a
safety level of high or max.
The POWER command (B[23:20] = 0100) updates the
power mode settings of the selected DACs. DACs that
are not selected do not update their power settings in
response to the command. The new power setting is
determined by bits PD[1:0] (B[7:6]) while the affected
DAC(s) are selected using B[15:8]). If all DACs are powered down and the RF2 bit is not set, the device enters
a STANDBY mode (all analog circuitry is disabled). This
command is inaccessible when a watchdog timeout has
Available power modes (PD[1:0]):
Normal (00): DAC channel is active (default).
PD 1kω (01): Power down with 1kω termination to GND.
PD 100kω (10): Power down with 100kω termination to
GND.
PD Hi-Z (11): Power down with high-impedance output.
Table 7. POWER Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
0
0
0
POWER Command
0
0
0
7
6
Reserved
Default Value →
5
3
2
1
B8
0
1
1
1
1
1
Data High Byte
CONFIG Command
The CONFIG command (B[23:16] = 0101) updates the
watchdog, gate, load, and clear mode settings of the
selected DACs. DACs which are not selected do not
update their settings in response to the command. The
new mode settings to be written are determined by bits
B[7:3] while the affected DAC(s) are selected by B[15:8].
This command is inaccessible when a watchdog timeout
has occurred and the watchdog timer is configured with
a safety level of high or max.
Watchdog Configuration:
WDOG Config settings are written by WC[1:0] (B[7:6]):
DISABLE (WC = 00): Watchdog timeout does not affect
the operation of the selected DAC.
GATE (WC = 01): DAC code is gated to DEFAULT value
in response to watchdog timeouts. Unless otherwise
prohibited by the watchdog safety level, LDAC, CLR,
1
B7
B6
PD1 PD0
B5 B4 B3
X
X
Power
Mode:
00 =
Normal
01 = 1kW
10 =
100kW
11 = Hi-Z
Multiple DAC Selection
Command Byte
www.maximintegrated.com
4
1
1
0
0
X
B2 B1 B0
X
X
X
X
X
Don’t Care
X
X
X
X
Data Low Byte
and write operations to the CODE and DAC registers are
accepted but will not be reflected on the DAC output until
the watchdog timeout status is reset.
CLR (WC = 10): CODE and DAC register contents are
cleared to DEFAULT value in response to watchdog timeouts. All writes to CODE and DAC registers are ignored
and LDAC or CLR input activity has no effect until the
watchdog timeout status is reset, regardless of watchdog
safety level.
HOLD (WC = 11): DAC code is held at its previously
programmed value in response to watchdog timeout.
All writes to DAC and CODE registers are ignored and
LDAC or CLR input activity has no effect until the watchdog timeout status is reset, regardless of watchdog
safety level.
Note: For the watchdog to timeout and have an impact,
the function must first be enabled and configured using
the WDOG command.
Maxim Integrated │ 26
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
LDB = 1: DAC latch is transparent, the CODE register
content controls the DAC output directly.
Gate Configuration:
The DAC GATE setting is written by GTB (B5); GATE
operation is as follows:
Clear Configuration:
GTB = 0: Enables software gating function (default), DAC
outputs are gated to their DEFAULT settings as long as
the device remains in GATE mode (set by SW_GATE_
SET and removed by SW_GATE_CLR).
CLEAR_ENB setting is written by CLB (B3); CLEAR_ENB
operation is as follows:
CLB = 0: Clear input and command functions impact the
DAC (default), clearing CODE and DAC registers to their
DEFAULT value.
GTB = 1: Disable software gating function, DAC outputs
are not impacted by GATE mode.
CLB = 1: Clear input and command functions have no
effect on the DAC.
Load Configuration:
The LDAC_ENB setting is written by LDB (B4);
LDAC_ENB operation is as follows:
LDB = 0: DAC latch is operational, enabling LDAC and
LOAD functions (default).
Table 8. CONFIG Command Format
0
1
0
CONFIG Command
0
0
7
6
Reserved
Default Value →
Command Byte
www.maximintegrated.com
0
5
4
3
2
1
0
1
1
1
1
1
Data High Byte
1
1
B5
B4
B3
WC1 WC0 GTB LDB CLB
WDOG
Config:
00:
DISABLE
01: GATE
10: CLR
11: HOLD
Multiple DAC Selection
1
B6
0
0
0
CLEAR_ENB
1
B7
LDAC_ENB
0
B8
GATE_ENB
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
0
B2
B1
B0
X
X
X
Don’t Care
X
X
X
Data Low Byte
Maxim Integrated │ 27
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
DEFAULT Command
DACs to the values determined by the M/Z input and
reset this register to M/Z mode.
The DEFAULT command (B[23:20] = 0110) selects the
default value for selected DACs. DACs which are not
selected do not update their default settings in response
to the command. These default values are used for all
future watchdog, clear, and gate operations. The new
default setting is determined by bits DF[2:0] (B[7:5])
while the affected DAC(s) are selected using B[15:8].
This command is inaccessible when a watchdog timeout
has occurred and the watchdog timer is configured with
a safety level of high or max. Note the selected default
values do not apply to resets initiated by SW_RESET
commands or supply cycling, both of which return all
Available default values (DF[2:0]):
M/Z (000): DAC channel defaults to value as selected by
the M/Z input (default).
ZERO (001): DAC channel defaults to zero scale.
MID (010): DAC channel defaults to midscale.
FULL (011): DAC channel defaults to full scale.
RETURN (100): DAC channel defaults to the value programmed by the RETURN command.
No Effect (101, 110, 111): DAC channel default behavior
is unchanged.
Table 9. DEFAULT Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
1
0
0
DEFAULT Command
0
0
7
6
Reserved
Default Value →
Command Byte
www.maximintegrated.com
0
5
4
3
2
1
B8
0
1
1
1
1
Data High Byte
1
B6
B5
DF2 DF1 DF0
B4
B3
B2
B1
B0
X
X
X
X
X
Default Values:
000: M/Z
001: ZERO
010: MID
011: FULL
100: RETURN
101+: No Effect
Multiple DAC Selection
1
B7
1
1
0
0
0
Don’t Care
X
X
X
X
X
Data Low Byte
Maxim Integrated │ 28
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
SPI_DATA_REQUEST Command
0 = Fix the address pointer (all further readbacks continue at the current address).
The SPI_DATA_REQUEST command (B[23:20] = 1101)
sets up the data request for future SPI_READ_DATA
operations. SPI_READ_DATA is used to fetch the current
settings of the internal CODE, DAC, or RETURN registers
for each channel or the watchdog configuration (WDOG)
settings or the device. The DAC address provided tells
the part which channel location data is to be read back
by the next SPI_READ_DATA command (see Table 3).
Setting the DAC address greater than the number of
available DACS will read back channel 0 content.
1 = Increment the address pointer (further readbacks
continue at the next address, with rollover, default).
The SEL[1:0] bits tells the part what type of data is
requested:
DAC (00): DAC register data (current DAC latch data, not
subject to gating status, default).
CODE (01): CODE register data.
RET (10): RETURN register data.
The INC bit tells the device how the next readback will
update the DAC address pointer:
WDT (11): WDOG register data (DAC selection does not
apply).
Table 10. SPI_DATA_REQUEST Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
1
0
1
DAC SELECTION
SPI_DATA_REQUEST
Default Value →
DAC Selection
0
0
0
INC SEL[1:0]
Increment
1
0
1
X
Data
Selection
00: DAC
01: CODE
10: RET
11: WDT
0
0
Command Byte
X
X
X
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
Don’t Care
X
X
X
X
Don’t Care
X
X
X
X
Data High Byte
SPI_READ_STATUS Command
X
X
Data Low Byte
WD_STAT indicates a watchdog timeout condition. It
reads 0 during normal operation, 1 during a timeout.
WD_STAT is not masked by the WD_MASK bit in the
WDOG_CONFIG command.
The SPI_READ_STATUS command (B[23:18] = 111000
for DPHA = 0, B[23:18] = 111001 for DPHA = 1) reads
back the watchdog timer and CLR pin status (intentionally repeated to allow maximum interface speeds)
through DOUT.
CLR_STAT indicates the line level of the CLR pin. ‘0’ indicates the CLR input is or was asserted (grounded) during
the current SPI operation. ‘1’ indicates the CLR input is
not currently asserted (VDDIO level).
DIN[18] selects the DOUT Phase (DPHA) to be used
(see the SPI Serial Interface Timing Diagram in Figure 1
for details).
Table 11. SPI_READ_STATUS Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
1
1
1
0
0
0
X
X
X
SPI_READ_STATUS (DPHA = 0)
1
1
1
0
0
1
X
X
X
X
X
X
X
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
DOUT = WD_STAT (Repeated)
X
X
X
X
X
X
X
X
DOUT = CLR_STAT (Repeated)
X
X
X
X
X
X
X
X
SPI_READ_STATUS (DPHA = 1)
DOUT = WD_STAT (Repeated)
DOUT = CLR_STAT (Repeated)
Command Byte
Data High Byte
Data Low Byte
www.maximintegrated.com
X
Maxim Integrated │ 29
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
SPI_READ_DATA Command
the Electrical Characteristics for a complete listing of readback speed capabilities based on the DPHA selection).
The SPI_READ_DATA command (B[23:18] = 111010 for
DPHA = 0, B[23:18] = 111011 for DPHA = 1) reads back
the data requested using the SPI_DATA_REQUEST command through DOUT.
DIN[18] selects the DOUT phase (DPHA) to be used (see
Figure 1 for details, and the SPI Timing Characteristics in
The SPI_READ_DATA command provides register and
address data as defined by the SPI_DATA_REQUEST
configuration SEL bits. SPI_READ_DATA also increments
the channel address pointer if configured to do so by the
SPI_DATA_REQUEST INC bit, the address readback is
the address corresponding to the data returned.
Table 12. SPI_READ_DATA Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
1
1
1
0
1
0
X
X
X
X
X
X
X
X
X
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
SPI_READ_DATA (DPHA = 0, SEL = 00)
DOUT = DAC[11:4]
DOUT = DAC[3:0]
ADDRESS[3:0]
SPI_READ_DATA (DPHA = 0, SEL = 01)
DOUT = CODE[11:4]
DOUT = CODE[3:0]
ADDRESS[3:0]
SPI_READ_DATA (DPHA = 0, SEL = 10)
DOUT = RETURN[11:4]
DOUT = RET[3:0]
ADDRESS[3:0]
SPI_READ_DATA (DPHA = 0, SEL = 11)
1
1
1
0
1
1
X
X
DOUT = WDOG[15:8]
X
X
X
X
X
X
DOUT = WDOG[7:1]
X
X
X
X
X
X
X
X
0
X
SPI_READ_DATA (DPHA = 1, SEL = 00)
DOUT = DAC[11:4]
DOUT = DAC[3:0]
ADDRESS[3:0]
SPI_READ_DATA (DPHA = 1, SEL = 01)
DOUT = CODE[11:4]
DOUT = CODE[3:0]
ADDRESS[3:0]
SPI_READ_DATA (DPHA = 1, SEL = 10)
DOUT = RETURN[11:4]
DOUT = RET[3:0]
ADDRESS[3:0]
SPI_READ_DATA (DPHA = 1, SEL = 11)
DOUT = WDOG[15:8]
Command Byte
Data High Byte
www.maximintegrated.com
DOUT = WDOG[7:1]
X
0
Data Low Byte
Maxim Integrated │ 30
MAX5723/MAX5724/
MAX5725
Applications Information
Power-On Reset (POR)
When power is applied to VDD and VDDIO, the DAC output is set to zero scale. To optimize DAC linearity, wait
until the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Power Supplies and
Bypassing Considerations
Bypass VDD and VDDIO with high-quality ceramic capacitors to a low-impedance ground as close as possible to
the device. Minimize lead lengths to reduce lead inductance. Connect the GND to the analog ground plane.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with a
low-inductance ground plane, or star connect all ground
return paths back to the MAX5723/MAX5724/MAX5725
GND. Carefully layout the traces between channels to
reduce AC cross-coupling. Do not use wire-wrapped
boards and sockets. Use shielding to minimize noise immunity. Do not run analog and digital signals parallel to one
another, especially clock signals. Avoid routing digital lines
underneath the MAX5723/MAX5724/MAX5725 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R 1 LSB, the DAC
output may still be monotonic.
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Offset Error
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Zero-Scale Error
Zero-scale error is the difference between the DAC
output voltage when set to code zero and ground. This
includes offset and other die level nonidealities.
Full-Scale Error
Full-scale error is the difference between the DAC output
voltage when set to full scale and the reference voltage. This includes offset, gain error, and other die level
nonidealities.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse. Although all bits change,
larger steps may lead to larger glitch energy.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
www.maximintegrated.com
Maxim Integrated │ 31
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Detailed Functional Diagram
VDD
REF
RIN 100kI
INTERNAL/EXTERNAL
REFERENCE
(USER OPTION)
CODE
REGISTER
0
DAC
LATCH
0
8-/10-/12-BIT
DAC0
OUT0
BUFFER 0
VDDIO
CODE
CLEAR /
RESET
GATE/
CLEAR /
RESET
LOAD
CHANNEL 0
DAC CONTROL LOGIC
CONTROL LOGIC
CSB
100kI
1kI
POWER-DOWN
DAC CHANNEL 0
DAC CHANNEL 1
OUT1
DAC CHANNEL 2
OUT2
DAC CHANNEL 3
OUT3
DAC CHANNEL 4
OUT4
DAC CHANNEL 5
OUT5
DAC CHANNEL 6
OUT6
SCLK
DIN
DOUT
SPI
SERIAL
INTERFACE
CLR
LDAC
IRQ
WATCHDOG
TIMER
M/Z
POR
CODE
REGISTER
7
CODE
MAX5723
MAX5724
MAX5725
CLEAR /
RESET
DAC
LATCH
7
LOAD
CHANNEL 7
DAC CONTROL LOGIC
8-/10-/12-BIT
DAC7
OUT7
BUFFER 7
GATE/
CLEAR /
RESET
100kI
1kI
POWER-DOWN
DAC CHANNEL 7
GND
www.maximintegrated.com
Maxim Integrated │ 32
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Typical Operating Circuits
100nF
100nF
4.7µF
RPU =
5kI
VDDIO
VDD
LDAC
CSB
OUT
DAC
SCLK
DIN
µC
DOUT
MAX5723
MAX5724
MAX5725
R1
REF
R2
CLR
R1 = R2
IRQ
M/Z
GND
NOTE: BIPOLAR OPERATING CIRCUIT, ONE CHANNEL SHOWN
100nF
4.7µF
RPU =
5kI
VDDIO
VDD
LDAC
CSB
100nF
DAC
OUT
SCLK
µC
DIN
DOUT
MAX5723
MAX5724
MAX5725
REF
CLR
IRQ
M/Z
GND
NOTE: UNIPOLAR OPERATING CIRCUIT, ONE CHANNEL SHOWN
www.maximintegrated.com
Maxim Integrated │ 33
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
RESOLUTION (BIT)
MAX5723AUP+
-40°C to +125°C
20 TSSOP
8
MAX5724AUP+
-40°C to +125°C
20 TSSOP
10
MAX5725AAUP+
-40°C to +125°C
20 TSSOP
12
MAX5725AWP+T
-40°C to +125°C
20 WLP
12
MAX5725BAUP+
-40°C to +125°C
20 TSSOP
12
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)–free/RoHS-compliant package.
T = Tape and reel.
Chip Information
PROCESS: BiCMOS
www.maximintegrated.com
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 TSSOP
U20+1
21-0066
90-0116
20 WLP
W202C2+1
21-0059
Refer to
Application
Note 1891
Maxim Integrated │ 34
MAX5723/MAX5724/
MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
Reference and SPI Interface
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
3/12
Initial release
1
11/12
Revised the Ordering Information, Electrical Characteristics, Typical Operating
Characteristics, Pin Configuration, Pin Description, Figure 1, and the DAC Outputs
(OUT_), CODEn_LOADn Command, and Offset Error sections
2
2/13
Released the MAX5723/MAX5724/MAX5725B, and updated the Electrical
Characteristics global and Note 3
DESCRIPTION
—
3, 5, 8, 10–13,
15–18, 23, 31,
34
2–8, 34
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2013 Maxim Integrated Products, Inc. │ 35
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