19-3024; Rev 2; 9/04
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
The MAX5942A/MAX5942B integrate a complete power
IC for powered devices (PD) in a power-over-ethernet
(PoE) system. The MAX5942A/MAX5942B provide a PD
interface and a compact DC-DC PWM controller suitable
for flyback and forward converters in either isolated or
nonisolated designs.
The MAX5942A/MAX5942B PD interface complies with
the IEEE™ 802.3af standard, providing the PD with a
detection signature, a classification signature, and an
integrated isolation switch with programmable inrush current control. These devices also feature power-mode
undervoltage lockout (UVLO) with wide hysteresis and
power-good status outputs.
The MAX5942A/MAX5942B also integrate all the building blocks necessary for implementing DC-DC fixedfrequency isolated power supplies. This device is a
current-mode controller with an integrated high startup
circuit suitable for isolated telecom/industrial voltage
range power supplies. A high-voltage startup circuit
allows the PWM controller to draw power directly from the
18V to 67V input supply during startup. The switching
frequency is internally trimmed to 275kHz ±10%, thus
reducing magnetics and filter components. The
MAX5942A allows an 85% operating duty cycle and can
be used to implement flyback converters. The MAX5942B
limits the operating duty cycle to less than 50% and can
be used in single-ended forward converters. The
MAX5942A/MAX5942B are designed to work with or without an external diode bridge in front of the PD.
The MAX5942A/MAX5942B are available in 16-pin SO
packages.
Applications
Features
♦ Powered Device Interface
Fully Integrated IEEE 802.3af-Compliant PD
Interface
PD Detection and Programmable Classification
Signatures
Less than 10µA Leakage Current Offset During
Detection
Integrated MOSFET for Isolation and Inrush
Current Limiting
Gate Output Allows External Control of the
Internal Isolation FET
Programmable Inrush Current Control/ULVO
PGOOD/PGOOD Outputs Enable PWM
Controller
♦ PWM Controller
Wide Input Range: 18V to 67V
Isolated (Without Optocoupler) or Nonisolated
Power Supply
Current-Mode Control
Leading-Edge Blanking
Internally Trimmed 275kHz ±10% Oscillator
Soft-Start
Ordering Information
PART
TEMP RANGE
PINPACKAGE
MAX DUTY
CYCLE (%)
MAX5942AESE*
-40°C to +85°C
16 SO
85
MAX5942ACSE
0°C to +70°C
16 SO
85
MAX5942BESE*
-40°C to +85°C
16 SO
50
MAX5942BCSE
0°C to +70°C
16 SO
50
*Future product—contact factory for availability.
IP Phones
Wireless Access Nodes
Pin Configuration
Internet Appliances
Computer Telephony
Security Cameras
Power Devices in Power-Over-Ethernet/
Power-Over-MDI
TOP VIEW
V+ 1
VDD 2
15 NDRV
FB 3
SS_SHDN 4
ULVO 5
Typical Operating Circuit appears at end of data sheet.
16 VCC
14 V-
MAX5942A
MAX5942B
12 GND
RCL 6
11 PGOOD
GATE 7
10 PGOOD
VEE 8
IEEE is a trademark of the Institute of Electrical and Electronics
Engineers.
13 CS
9
OUT
SO
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1
MAX5942A/MAX5942B
General Description
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
ABSOLUTE MAXIMUM RATINGS
UVLO, PGOOD, PGOOD to VEE .....................................20mA
GATE to VEE ....................................................................80mA
VDD, VCC .........................................................................20mA
NDRV Continuous ...........................................................25mA
NDRV (pulsed for less than 1µs) .......................................±1A
Continuous Power Dissipation (TA = +70°C)
16-Pin SO (derate 9.1mW/°C above +70°C)................727mW
Operating Temperature Ranges
MAX5942_CSE...................................................0°C to +70°C
MAX5942_ESE ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) ................................+300°C
(All voltages are referenced to VEE, unless otherwise noted.)
GND........................................................................-0.3V to +90V
OUT, PGOOD ...........................................-0.3V to (GND + 0.3V)
RCL, GATE .............................................................-0.3V to +12V
UVLO ........................................................................-0.3V to +8V
PGOOD to OUT.........................................-0.3V to (GND + 0.3V)
V+ to V-...................................................................-0.3V to +80V
VDD to V-.................................................................-0.3V to +40V
VCC to V-..............................................................-0.3V to +12.5V
FB, NDRV, SS_SHDN, CS to V- ..................-0.3V to (VCC + 0.3V)
Maximum Input/Output Current (continuous)
OUT to VEE ...................................................................500mA
GND, RCL to VEE ............................................................70mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OPEN, V- tied to OUT, V+ tied to GND, UVLO = VEE, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
µA
PD INTERFACE
DETECTION MODE
Input Offset Current
Effective Differential Input
Resistance
IOFFSET
dR
VIN = 1.4V to 10.1V (Note 2)
VIN = 1.4V up to 10.1V with 1V step,
OUT = PGOOD = GND (Note 3)
550
VIN rising (Note 4)
20.8
kΩ
CLASSIFICATION MODE
Classification Current Turn-Off
Threshold
Classification Current
VTH,CLSS
ICLASS
Class 0, RCL = 10kΩ
VIN = 12.6V
Class 1, RCL = 732Ω
to 20V, RDISC
Class 2, RCL = 392Ω
= 25.5kΩ
Class 3, RCL = 255Ω
(Notes 5, 6)
Class 4, RCL = 178Ω
21.8
22.5
0
2
9.17
11.83
17.29
19.71
26.45
29.55
36.6
41.4
V
mA
POWER MODE
Operating Supply Voltage
VIN
VIN = (GND - VEE)
Operating Supply Current
IIN
Measure at GND, not including RDISC
Default Power Turn-On Voltage
VUVLO,ON
Default Power Turn-Off Voltage
VUVLO,OFF VIN decreasing, UVLO = VEE
Default Power Turn-On/Off
Hysteresis
External UVLO Programming
Range
UVLO External Reference Voltage
UVLO External Reference
Voltage Hysteresis
2
VIN increasing, UVLO = VEE
VHYST,UVLO
VIN,EX
Set UVLO externally (Note 7)
37.4
67
V
0.4
1
mA
38.6
40.1
V
30
V
7.4
V
12
67
V
VREF,UVLO
VUVLO increasing
2.400
2.460
2.522
V
HYST
Ratio to VREF,UVLO
19.2
20
20.9
%
_______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OPEN, V- tied to OUT, V+ tied to GND, UVLO = VEE, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER
UVLO Bias Current
SYMBOL
IUVLO
UVLO Input Ground Sense
Threshold
Isolation Switch N-Channel
MOSFET On-Resistance
UVLO = 2.460V
VTH,G,UVLO (Note 8)
UVLO Input Ground Sense Glitch
Rejection
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time
CONDITIONS
MIN
MAX
UNITS
-1.5
+1.5
µA
50
440
mV
UVLO = VEE
tOFF_DLY
RON
TYP
7
VIN, VUVLO falling (Note 9)
µs
0.32
TA = +25°C
Output current =
300mA, VGATE = 5.6V, (Note 11)
measured between
TA = +85°C
OUT and VEE
ms
0.6
1.1
0.8
1.5
Ω
VGSTH
OUT = GND, VGATE - VEE, output current
< 1µA
GATE Pulldown Switch Resistance
RG
Power-off mode, VIN = 12V, UVLO = VEE
38
80
Ω
GATE Charging Current
IG
VGATE = 2V
5
10
15
µA
VGATE
IGATE = 1µA
5.58
5.76
5.93
V
VOUT - VEE, |VOUT - VEE| decreasing,
VGATE = 5.75V
1.15
1.23
1.31
V
Isolation Switch N-Channel
MOSFET Off-Threshold Voltage
GATE High Voltage
PGOOD, PGOOD Assertion
VOUT Threshold
VOUTEN
PGOOD, PGOOD Assertion
VGATE Threshold
VGSEN
PGOOD Output Low Voltage
VOLDCDC
0.5
Hysteresis
V
70
(GATE - VEE) increasing, OUT = VEE
4.62
Hysteresis
4.76
mV
4.91
80
V
mV
ISINK = 2mA (Note 10)
0.4
V
PGOOD Output Low Voltage
ISINK = 2mA, OUT ≤ (GND - 5V) (Note 10)
0.2
V
PGOOD Leakage Current
GATE = high, GND - VOUT = 67V (Note 10)
1
µA
PGOOD Leakage Current
GATE = VEE, PGOOD - VEE = 67V (Note 10)
1
µA
ELECTRICAL CHARACTERISTICS (PWM Controller)
(All voltages referenced to V-. VDD = 13V, a 10µF capacitor connects VCC to V-, VCS = V-, V+ = 48V, 0.1µF capacitor connected to
SS_SHDN, NDRV = open circuit, VFB = 3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
VDD = 0V, V+ = 67V, driver not switching
0.8
1.6
V+ = 67V, VDD = 0V, VFB = 4V, driver
switching
1.6
3.2
V+ = 67V, VDD = 13V, VFB = 4V
14
UNITS
SUPPLY CURRENT
IV+(NS)
V+ Supply Current
IV+(S)
V+ Supply Current After Startup
mA
µA
_______________________________________________________________________________________
3
MAX5942A/MAX5942B
ELECTRICAL CHARACTERISTICS (continued)
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
ELECTRICAL CHARACTERISTICS (PWM Controller) (continued)
(All voltages referenced to V-. VDD = 13V, a 10µF capacitor connects VCC to V-, VCS = V-, V+ = 48V, 0.1µF capacitor connected to
SS_SHDN, NDRV = open circuit, VFB = 3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
TYP
MAX
VDD = 36V, driver not switching
0.9
1.6
VDD = 36V, driver switching, VOPTO = 4V
1.9
3.2
V+ Shutdown Current
VSS_SHDN = 0V, V+ = 67V
180
290
µA
VDD Shutdown Current
VSS_SHDN = 0V
4
20
µA
VDD Supply Current
SYMBOL
IVDD(NS)
IVDD(S)
CONDITIONS
MIN
UNITS
mA
PREREGULATORS/STARTUP
V+ Input Voltage
18
67
V
VDD Supply Voltage
13
36
V
INTERNAL REGULATORS
VCC Output Voltage
VCC Undervoltage Lockout
VCC_UVLO
Powered from V+, ICC = 7.5mA, VDD = 0V
7.5
9.8
12
Powered from VDD, ICC = 7.5mA
9.0
10.0
11.0
V
VCC falling
6.6
V
Peak Source Current
VCC = 11V (externally forced)
570
mA
Peak Sink Current
VCC = 11V (externally forced)
1000
mA
OUTPUT DRIVER
NDRV High-Side Driver
Resistance
ROH
VCC = 11V, externally forced, NDRV
sourcing 50mA
NDRV Low-Side Driver
Resistance
ROL
4
12
Ω
VCC = 11V, externally forced, NDRV sinking
50mA
1.6
4
Ω
VFB = VSS_SHDN
±1
µA
-20
V/V
ERROR AMPLIFIER
FB Input Resistance
RIN
FB Input Bias Current
IFB
Error Amplifier Gain (Inverting)
50
AVCL
Closed-Loop 3dB Bandwidth
kΩ
200
FB Input Voltage Range
2
kHz
3
V
SLOPE COMPENSATION
Slope Compensation
VSCOMP
MAX5942A
26
mV/µs
+150
°C
25
°C
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Hysteresis
CURRENT LIMIT
CS Threshold Voltage
VILIM
FB = 4V
419
465
510
mV
+1
µA
CS Input Bias Current
0V ≤ VCS ≤ 2V, FB = 4V
Current-Limit Comparator
Propagation Delay
25mV overdrive on CS, FB = V-
180
ns
CS Blanking Time
FB = GND, only PWM comparator is blanked
70
ns
-1
OSCILLATOR
Clock Frequency Range
Max Duty Cycle
4
FB = V-
235
MAX5942A, FB = V-
75
275
85
MAX5942B, FB = V-
44
50
_______________________________________________________________________________________
314
kHz
%
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
(All voltages referenced to V-. VDD = 13V, a 10µF capacitor connects VCC to V-, VCS = V-, V+ = 48V, 0.1µF capacitor connected to
SS_SHDN, NDRV = open circuit, VFB = 3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
2.0
4.5
6.5
UNITS
SOFT-START
SS Source Current
ISSO
VSS_SHDN = V-
SS Sink Current
1
Peak Soft-Start Voltage Clamp
Shutdown Threshold
µA
mA
No external load
2.331
2.420
2.500
VSS_SHDN falling (Note 11)
0.25
0.37
0.41
VSS_SHDN rising (Note 11)
0.53
0.59
0.65
V
V
Note 1:
All min/max limits for the PD interface are production tested at +85°C (extended grade)/+70°C (commercial grade). Limits
at +25°C and -40°C are guaranteed by design. All PWM controller min/max limits are 100% production tested at +25°C
and +85°C (extended grade)/+70°C (commercial grade). Limits at -40°C are guaranteed by design, unless otherwise
noted.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between GND and VEE without any external
resistance.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the PD Classification Mode section. RDISC and RCL must be 100ppm or better.
Note 6: See Thermal Dissipation section for details.
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turnon threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage.
Note 8: When the VUVLO is below VTH, G, UVLO, the MAX5942_ sets the turn-on voltage threshold internally (VUVLO,ON).
Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY will not cause the
MAX5942A/MAX5942B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V).
Note 10: PGOOD references to OUT while PGOOD references to VEE.
Note 11: Guaranteed by design.
IIN
dRi ≅
1V
(VINi + 1 - VINi)
=
(IINi + 1 - IINi) (IINi + 1 - IINi)
IOFFSET ≅ IINi -
VINi
dRi
IINi +1
dRi
IINi
IOFFSET
VINi
1V
VINi +1
Figure 1. Effective Differential Input Resistance/Offset Current
_______________________________________________________________________________________
5
MAX5942A/MAX5942B
ELECTRICAL CHARACTERISTICS (PWM Controller) (continued)
Typical Operating Characteristics
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX.
Typical values are at TA = +25°C. All voltages are referenced to VEE (for graphs 1–11 in the Typical Operating Characteristics); all
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.
0.30
0.25
0.20
0.15
0.10
CLASS 3
25
20
CLASS 2
15
10
CLASS 1
CLASS 0
0
2
4
6
10
10
8
15
20
2.0
1.5
1.0
0.5
0
0
5
10
OFFSET CURRENT
vs. INPUT VOLTAGE
NORMALIZED UVLO
vs. TEMPERATURE
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
1.008
1.006
-2.5
-3.0
-3.5
5
6
7
8
9
180
160
1.004
140
1.002
1.000
0.998
120
100
80
0.996
60
0.994
40
0.992
20
0.990
4
200
VPGOOD (mV)
NORMALIZED UVLO
-2.0
UVLO = VEE
10 11
MAX5942A/B toc06
1.010
MAX5942A/B toc04
-1.5
0
-40
-15
10
35
60
85
0
4
8
12
TEMPERATURE (°C)
ISINK (mA)
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
OUT LEAKAGE CURRENT
vs. TEMPERATURE
INRUSH CURRENT CONTROL
(VIN = 12V)
250
200
150
100
VOUT = 67V
16
VGATE
5V/div
IINRUSH
100mA/div
12
8
VOUT
10V/div
4
50
0
PGOOD
10V/div
0
4
8
12
ISINK (mA)
16
20
20
MAX5942A/B toc09
MAX5942A/B toc08
300
20
OUT LEAKAGE CURRENT (nA)
MAX5942A/B toc07
350
6
16
INPUT VOLTAGE (V)
400
0
15
INPUT VOLTAGE (V)
-1.0
3
2.5
INPUT VOLTAGE (V)
-0.5
2
3.0
INPUT VOLTAGE (V)
0
1
3.5
30
25
MAX5942A/B toc05
0
EFFECTIVE DIFFERENTIAL INPUT
RESISTANCE vs. INPUT VOLTAGE
MAX5942A/B toc03
30
5
0
OFFSET CURRENT (µA)
CLASS 4
35
0.05
MAX5942A/B toc02
0.35
40
CLASSIFICATION CURRENT (mA)
RDISC = 25.5kΩ
GND = V+ = V- = OUT
0.40
DETECTION CURRENT (mA)
MAX5942A/B toc01
0.45
EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (MΩ)
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
DETECTION CURRENT vs.
INPUT VOLTAGE
VPGOOD (mV)
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
-40
-15
10
35
60
85
1ms/div
INPUT VOLTAGE (V)
_______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX.
Typical values are at TA = +25°C. All voltages are referenced to VEE (for graphs 1–11 in the Typical Operating Characteristics); all
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.
VSS_SHDN vs. TEMPERATURE
(AT THE END OF SOFT-START)
INRUSH CURRENT CONTROL
(VIN = 67V)
VGATE
5V/div
IINRUSH
100mA/div
1.003
VGATE
5V/div
IINRUSH
100mA/div
VOUT
50V/div
VOUT
50V/div
PGOOD
50V/div
PGOOD
50V/div
VFB = V1.002
1.001
1.000
0.999
-40
2ms/div
2ms/div
MAX5942 toc12
MAX5942A/B toc11
MAX5942A/B toc10
VSS_SHDN (V) (NORMALIZED TO VREF = 2.4V)
INRUSH CURRENT CONTROL
(VIN = 48V)
-20
0
20
40
60
80
TEMPERATURE (°C)
MAX5942A
MAXIMUM DUTY CYCLE vs. TEMPERATURE
275
274
MAX5942 toc14
FB = V-
80.7
80.6
80.5
0
20
40
60
47.6
47.4
47.2
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
V+ SUPPLY CURRENT
vs. TEMPERATURE
SOFT-START SOURCE CURRENT
vs. TEMPERATURE
V+ INPUT CURRENT vs.
TEMPERATURE (AFTER STARTUP)
1.63
1.62
FB = VDD = V-
1.60
1.59
1.58
1.57
1.56
4.50
4.49
VDD = FB = SS_SHDN = V-
4.48
4.47
13.80
V+ = 67V
4.46
4.45
4.44
4.43
4.42
MAX5942 toc18
MAX5942 toc16
1.64
1.61
FB = V-
46.8
-40
80
13.75
V+ INPUT CURRENT (µA)
-20
SOFT-START SOURCE CURRENT (µA)
-40
47.8
47.0
80.4
273
V+ SUPPLY CURRENT (mA)
80.8
MAXIMUM DUTY CYCLE (%)
FB = V276
80.9
48.0
MAX5942 toc17
NDRV FREQUENCY (kHz)
277
81.0
MAXIMUM DUTY CYCLE (%)
MAX5942 toc13
278
MAX5942B
MAXIMUM DUTY CYCLE vs. TEMPERATURE
MAX5942 toc15
NDRV FREQUENCY
vs. TEMPERATURE
V+ = 67V, VDD = 13V, FB = V13.70
13.65
13.60
13.55
4.41
1.55
13.50
4.40
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX5942A/MAX5942B
Typical Operating Characteristics (continued)
Typical Operating Characteristics (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX.
Typical values are at TA = +25°C. All voltages are referenced to VEE (for graphs 1–11 in the Typical Operating Characteristics); all
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.
CS THRESHOLD VOLTAGE
vs. TEMPERATURE
V+ SHUTDOWN CURRENT
vs. TEMPERATURE
V+ = 67V, FB = SS_SHDN = V181.5
181.0
180.5
180.0
MAX5942 toc20
182.0
0.488
CS THRESHOLD VOLTAGE (V)
MAX5942 toc19
V+ SHUTDOWN CURRENT (µA)
182.5
0.487
FB = V0.486
0.485
0.484
179.5
179.0
0.483
-40
-20
0
20
40
60
80
-40
-20
0
TEMPERATURE (°C)
60
80
4.0
HIGH-SIDE DRIVER
3.5
3.0
2.5
LOW-SIDE DRIVER
MAX5942 toc22
210
208
CURRENT-LIMIT DELAY (ns)
MAX5942 toc21
4.5
NDRV RESISTANCE (Ω)
40
CURRENT-LIMIT DELAY
vs. TEMPERATURE
5.0
2.0
20
TEMPERATURE (°C)
NDRV RESISTANCE
vs. TEMPERATURE
206
FB = V-, 100mV OVERDRIVE ON CS
204
202
200
198
196
194
192
1.5
190
188
1.0
-40
-20
0
20
60
40
TEMPERATURE (°C)
-40
80
-20
0
20
40
60
80
TEMPERATURE (°C)
VSS_SHDN vs. VDD
NDRV FREQUENCY vs. VDD
270.5
NDRV FREQUENCY (kHz)
2.408
2.406
2.404
MAX5942 toc24
271.0
MAX5942 toc23
2.410
VSS_SHDN (V)
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
270.0
269.5
269.0
268.5
FB = V268.0
2.402
267.5
267.0
2.400
0
5
10
15
20
VDD (V)
8
25
30
35
40
0
5
10
15
20
25
30
35
VDD (V)
_______________________________________________________________________________________
40
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX.
Typical values are at TA = +25°C. All voltages are referenced to VEE (for graphs 1–11 in the Typical Operating Characteristics); all
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.
MAX5942B
MAXIMUM DUTY CYCLE vs. VDD
VCC vs. VDD
10.1
47.7
DEVICE POWERED FROM VDD
10.0
47.6
47.5
DEVICE POWERED
FROM VDD
47.4
47.3
9.9
FB = V9.8
9.7
47.2
DEVICE POWERED
FROM V+
47.1
9.6
47.0
0
5
10
15
20
25
30
35
DEVICE POWERED
FROM V+
9.5
40
0
5
10
VDD (V)
25
30
35
40
VFB = VDD = V-
1.56
1.55
1.54
1.53
MAX5942 toc28
1.58
16
14
V+ LEAKAGE CURRENT (µA)
MAX5942 toc27
1.59
12
VDD = 13V, FB = V-
10
8
6
4
2
1.52
0
1.51
0
20
40
60
80
100
0 10 20 30 40 50 60 70 80 90 100 110
V+ VOLTAGE (V)
V+ VOLTAGE (V)
VCC VOLTAGE vs. VCC CURRENT
VCC VOLTAGE vs. VCC CURRENT
V+ = +67V, VFB = 4V
10.2
VDD = 36V
10.0
MAX5942 toc29
10.4
9.8
VDD = 13V
9.6
VDD = GND, VFB = 4V
9.9
9.8
VCC VOLTAGE (V)
10.0
MAX5942 toc30
V+ SUPPLY CURRENT (mA)
20
V+ SUPPLY CURRENT vs. V+ VOLTAGE
(AFTER STARTUP)
1.60
1.57
15
VDD (V)
V+ SUPPLY CURRENT vs.
V+ VOLTAGE
VCC VOLTAGE (V)
MAX5942 toc26
VFB = 4V, CS = V-
VCC (V)
MAXIMUM DUTY CYCLE (%)
47.9
47.8
10.2
MAX5942 toc25
48.0
V+ = 67V
V+ = 48V
9.7
9.6
9.5
V+ = 36V
9.4
V+ = 24V
9.3
9.4
9.2
9.2
9.1
9.0
9.0
0
5
10
15
VCC CURRENT (mA)
20
0
5
10
15
20
VCC CURRENT (mA)
_______________________________________________________________________________________
9
MAX5942A/MAX5942B
Typical Operating Characteristics (continued)
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
MAX5942A/MAX5942B
Pin Description
PIN
NAME
1
V+
High-Voltage Startup Input. Referenced to V-. Connect directly to an input voltage range between 18V to 67V.
Connects internally to a high-voltage linear regulator that generates VCC during startup.
2
VDD
Line Regulator Input. Referenced to V-. VDD is the input to the linear regulator that generates VCC. For
supply voltages less than 36V, connect VDD and V+ to the supply. For supply voltages greater than 36V,
VDD receives its power from the tertiary winding of the transformer and accepts voltages from 13V to 36V.
Bypass VDD to V- with a 4.7µF capacitor.
3
FB
Fixed-Gain Inverting Amplifier Input. Referenced to V-. Connect a voltage-divider from the regulated output
to FB. The noninverting input of the amplifier is referenced to +2.4V
4
10
FUNCTION
Soft-Start Timing Capacitor Connection. Referenced to V-. Ramp time to full current limit is approximately
SS_SHDN 0.45ms/nF. Bypass with a minimum 10nF capacitor to V-. A 2.4V reference voltage appears across the
capacitor. Disable the PWM controller by pulling SS_SHDN below 0.25V.
Undervoltage Lockout Programming Input for Power Mode. Referenced to VEE. When UVLO is above its
threshold, the device enters the power mode. Connect UVLO to VEE to use the default undervoltage lockout
threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series
resistance value of the external resistors must add to 25.5kΩ (±1%) and replaces the detection resistor. To
keep the device in undervoltage lockout, pull UVLO between VTH,G,UVLO and VREF,UVLO.
5
UVLO
6
RCL
Classification Setting. Referenced to VEE. Add a resistor from RCL to VEE to set a PD class (see Table 1).
7
GATE
Gate of Internal N-Channel Power MOSFET. Referenced to VEE . GATE sources 10µA when the device
enters the power mode. Connect an external 100V ceramic capacitor from GATE to VOUT to program the
inrush current. Pull GATE to VEE to turn off the internal MOSFET. The detection and classification functions
operate normally when GATE is pulled to VEE.
8
VEE
N e ga t ive I n p u t P o w e r . S o u r ce o f th e in te g r a t ed iso la t io n N - c h a nn e l p ow e r MOS F E T . C o n n e ct V EE t o
- 4 8V .
9
OUT
Output Voltage. Referenced to VEE. Drain of the integrated isolation N-channel power MOSFET. Connect
OUT to V-.
10
PGOOD
Power-Good Indicator Output, Active High, Open Drain. PGOOD is referenced to OUT. PGOOD goes high
impedance when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD is pulled
to OUT (given that VOUT is at least 5V below GND).
11
PGOOD
Power-Good Indicator Output, Active Low, Open Drain. PGOOD is referenced to VEE. PGOOD is pulled to
VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD goes high
impedance.
12
GND
13
CS
Current-Sense Input. Referenced to V-. Turns power switch off if VCS rises above 465mV for cycle-by-cycle
current limiting. CS is also the feedback for the current-mode controller. CS connects to the PWM controller
through a leading-edge blanking circuit.
14
V-
Ground. V- is the ground terminal of the PWM controller.
15
NDRV
16
VCC
Ground. Referenced to VEE. GND is the positive input power.
Gate Drive. Referenced to V-. Drives a high-voltage external N-channel power MOSFET.
Regulated IC Supply. Referenced to V-. Provides power for MAX5942_. VCC is regulated from VDD during
normal operation and from V+ during startup. Bypass VCC with a 10µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor to V-.
______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
CLASS
USAGE
RCL (Ω)
MAXIMUM POWER USED BY PD (W)
0
Default
10k
0.44 to 12.95
1
Optional
732
0.44 to 3.84
2
Optional
392
3.84 to 6.49
3
Optional
255
6.49 to 12.95
4
Not allowed
178
Reserved*
*Class 4 reserved for future use.
Detailed Description
The MAX5942A/MAX5942B integrate a complete power
IC for powered devices (PD) in a power-over-ethernet
(PoE) system. The MAX5942A/MAX5942B provide PD
Interface and a compact DC-DC PWM controller suitable
for flyback and forward converters in either isolated or
nonisolated designs.
The MAX5942A/MAX5942B PD interface complies with
the IEEE 802.3af standard, providing the PD with a
detection signature, a classification signature, and an
integrated isolation switch with programmable inrush
current control. These devices also feature power-mode
undervoltage lockout (UVLO) with wide hysteresis, and
power-good status outputs.
An integrated MOSFET provides PD isolation during
detection and classification. The MAX5942A/MAX5942B
guarantee a leakage current offset of less than 10µA during the detection phase. A programmable current limit
prevents high inrush current during power-on. The
devices feature power-mode UVLO with wide hysteresis
and long deglitch time to compensate for twisted-pair
cable resistive drop and to ensure glitch-free transition
between detection, classification, and power-on/off
phases. The MAX5942A/MAX5942B provide both activehigh (PGOOD) and active-low (PGOOD) outputs. Both
devices offer an adjustable UVLO threshold with a
default value compliant to the IEEE 802.3af standard.
The MAX5942A/MAX5942B are designed to work with or
without an external diode bridge in front of the PD.
Use the MAX5942A/MAX5942B PWM current-mode controllers to design flyback- or forward-mode power supplies. Current-mode operation simplifies control-loop
design while enhancing loop stability. An internal highvoltage startup regulator allows the device to connect
directly to the input supply without an external startup
resistor. Current from the internal regulator starts the controller. Once the tertiary winding voltage is established,
the internal regulator is switched off and bias current
for running the PWM controller is derived from the
tertiary winding. The internal oscillator is set to 275kHz
and trimmed to ±10%. This permits the use of small
magnetic components to minimize board space. Both the
MAX5942A and MAX5942B can be used in power supplies providing multiple output voltages. A functional diagram of the PWM controller is shown in Figure 4. Typical
application circuits for forward and flyback topologies are
shown in Figure 5 and Figure 6, respectively.
Powered Device Interface
Operating Modes
The PD front-end section of the MAX5942A/MAX5942B
operates in three different modes: PD detection signature, PD classification, and PD power, depending on its
input voltage (VIN = GND - VEE). All voltage thresholds
are designed to operate with or without the optional
diode bridge while still complying with the IEEE 802.3af
standard (see Application Circuit 1).
Detection Mode (1.4V ≤ VIN ≤ 10.1V)
In detection mode, the power source equipment (PSE)
applies two voltages on V IN in the range of 1.4V to
10.1V (1V step minimum), and then records the current
measurements at the two points. The PSE then computes ∆V/∆I to ensure the presence of the 25.5kΩ signature resistor. In this mode, most of the
MAX5942A/MAX5942B internal circuitry is off and the
offset current is less than 10µA.
If the voltage applied to the PD is reversed, install protection diodes on the input terminal to prevent internal
damage to the MAX5942A/MAX5942B (see Figures 8
and 9). Since the PSE uses a slope technique (∆V/∆I) to
calculate the signature resistance, the DC offset due to
the protection diodes is subtracted and does not affect
the detection process.
Classification Mode (12.6V ≤ VIN ≤ 20V)
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD.
This allows the PSE to efficiently manage power distribution. The IEEE 802.3af standard defines five different
classes as shown in Table 1. An external resistor (RCL)
connected from RCL to VEE sets the classification current.
______________________________________________________________________________________
11
MAX5942A/MAX5942B
Table 1. PD Power Classification/RCL Selection
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Table 2. Setting Classification Current
IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)
CLASS CURRENT SEEN AT VIN (mA)
CLASS
RCL (Ω)
VIN* (V)
MIN
MAX
MIN
0
10k
12.6 to 20
0
4
0
4
1
732
12.6 to 20
9
12
9
12
2
392
12.6 to 20
17
20
17
20
3
255
12.6 to 20
26
30
26
30
4
178
12.6 to 20
36
42
36
44
MAX
*VIN is measured across the MAX5942 input pins (VEE and GND), which does not include the diode bridge voltage drop.
GND
UVLO
REF
2.4V,
REF
EN
GND
CLASSIFICATION
6.8V
RCL
R1
21.8V
PGOOD
2.4V, 0.8
HYST
MAX5942B
Q4
R2
39V
R3
VGATE, 6V
1.2V, REF
EN
UVLO
PGOOD
5V, REF
Q3
VOUT
Q2
200mV
GATE
Q1
VEE
Figure 2. Powered Device Interface Block Diagram
12
______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Power Mode
During power mode, when VIN rises above the undervoltage lockout threshold (V UVLO,ON ), the MAX5942A/
MAX5942B gradually turn on the internal N-channel MOSFET Q1 (see Figure 2). The MAX5942A/MAX5942B
charge the gate of Q1 with a constant current source
(10µA, typ). The drain-to-gate capacitance of Q1 limits
the voltage rise rate at the drain of MOSFET, thereby limiting the inrush current. To reduce the inrush current, add
external drain-to-gate capacitance (see the Inrush
Current section). When the drain of Q1 is within 1.2V of its
source voltage and its gate-to-source voltage is above
5V, the MAX5942A/MAX5942B assert the PGOOD/
PGOOD outputs. The MAX5942A/MAX5942B have a wide
UVLO hysteresis and turn-off deglitch time to compensate
for the high impedance of the twisted-pair cable.
Undervoltage Lockout
The MAX5942A/MAX5942B operate up to a 67V supply
voltage with a default UVLO turn-on set at 39V and a
UVLO turn-off set at 30V. Adjust the UVLO threshold
using a resistor-divider connected to UVLO (see Figure
3). When the input voltage is above the UVLO threshold
(VUVLO,ON), the IC is in power mode and the MOSFET is
on. When the input voltage goes below the UVLO threshold (VUVLO,OFF) for more than tOFF_DLY, the MOSFET
turns off.
To adjust the UVLO threshold, connect an external
resistor-divider from GND to UVLO and from UVLO to
VEE. Use the following equations to calculate R1 and
R2 for a desired UVLO threshold:
R2 = 25.5kΩ x
VREF, UVLO
VINEX
,
R1 = 25.5kΩ - R2
where VIN,EX is the desired UVLO threshold. Since the
resistor-divider replaces the 25.5kΩ PD detection resistor, ensure that the sum of R1 and R2 equals 25.5kΩ
VIN = 24V TO 60V
GND
R1
MAX5942A
MAX5942B
UVLO
R2
VEE
Figure 3. Setting Undervoltage Lockout with an External
Resistor-Divider
±1%. When using the external resistor-divider, the
MAX5942 has an external reference voltage hysteresis of
20% (typ). In other words, when UVLO is programmed
externally, the turn-off threshold will be 80% (typ) of the
new UVLO turn-on threshold.
Inrush Current Limit
The MAX5942A/MAX5942B charge the gate of the internal MOSFET with a constant current source (10µA, typ).
The drain-to-gate capacitance of the MOSFET limits the
voltage rise rate at the drain, thereby limiting the inrush
current. Add an external capacitor from GATE to OUT
to further reduce the inrush current. Use the following
equation to calculate the inrush current:
IINRUSH = IG x
COUT
CGATE
The recommended inrush current for a PoE application
is 100mA.
PGOOD/PGOOD Outputs
PGOOD is an open-drain, active-high logic output.
PGOOD goes high impedance when VOUT is within 1.2V
of VEE and when GATE is 5V above VEE. Otherwise,
PGOOD is pulled to VOUT (given that VOUT is at least 5V
below GND). Connect PGOOD to SS_SHDN to enable
the PWM controller.
PGOOD is an open-drain, active-low logic output.
PGOOD is pulled to VEE when VOUT is within 1.2V of VEE
and when GATE is 5V above VEE. Otherwise, PGOOD
goes high impedance.
______________________________________________________________________________________
13
MAX5942A/MAX5942B
The PSE determines the class of a PD by applying a voltage at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5942A/MAX5942B exhibit a current characteristic with values indicated in Table 2. The
PSE uses the classification current information to classify
the power requirement of the PD. The classification current includes the current drawn by the 25.5kΩ detection
signature resistor and the supply current of the
MAX5942A/MAX5942B so that the total current drawn by
the PD is within the IEEE 802.3af standard figures. The
classification current is turned off whenever the device is
in power mode.
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Thermal Dissipation
Internal Regulators
During classification mode, if the PSE applies the maximum DC voltage, the maximum voltage drop from GND
to VRCL will be 13V. If the maximum classification current of 42mA flows through the MAX5942A/
MAX5942B, then the maximum DC power dissipation
will be close to 546mW, which is slightly higher than the
maximum DC power dissipation the IC can handle.
However, according to the IEEE 802.3af standard, the
duration of the classification mode is limited to 75ms
(max). The MAX5942A/MAX5942B handle the maximum classification power dissipation for the maximum
duration time without sustaining any internal damage. If
the PSE violates the IEEE 802.3af standard by exceeding the 75ms maximum classification duration, it may
cause internal damage to the IC.
The internal regulators of the MAX5942A/MAX5942B
enable initial startup without a lossy startup resistor and
regulate the voltage at the output of a tertiary (bias)
winding to provide power for the IC. At startup, V+ is regulated down to VCC to provide bias for the device. The
VDD regulator then regulates from the output of the tertiary winding to VCC. This architecture allows the tertiary
winding to have only a small filter capacitor at its output,
thus eliminating the additional cost of a filter inductor.
When designing the tertiary winding, calculate the number of turns so the minimum reflected voltage is always
higher than 12.7V. The maximum reflected voltage
must be less than 36V.
PWM Controller
Current-Mode Control
The MAX5942A/MAX5942B offer current-mode control
operation with added features such as leading-edge
blanking with dual internal path that only blanks the
sensed current signal applied to the input of the PWM
comparator. The current-limit comparator monitors the
CS pin at all times and provides cycle-by-cycle current
limit without being blanked. The leading-edge blanking
of the CS signal prevents the PWM comparator from
prematurely terminating the on cycle. The CS signal
contains a leading-edge spike that is the result of the
MOSFET gate charge current, capacitive and diode
reverse recovery current of the power circuit. Since this
leading-edge spike is normally lower than the currentlimit comparator threshold, current limiting is not
blanked and cycle-by-cycle current limiting is provided
under all conditions.
Use the MAX5942A in discontinuous flyback applications where wide line voltage and load current variation
are expected. Use the MAX5942B for single-transistor
forward converters where the maximum duty cycle
must be limited to less than 50%.
Under certain conditions, it may be advantageous to
use a forward converter with greater than 50% duty
cycle. For those cases, use the MAX5942A. The large
duty cycle results in much lower operating primary
RMS currents through the MOSFET switch and in most
cases a smaller output filter inductor. The major disadvantage to this is that the MOSFET voltage rating must
be higher and that slope compensation must be provided to stabilize the inner current loop. The MAX5942A
provides internal slope compensation.
14
To reduce power dissipation, the high-voltage regulator
is disabled when the VDD voltage reaches 12.7V. This
greatly reduces power dissipation and improves efficiency. If VCC falls below the undervoltage lockout
threshold (VCC = 6.6V), the low-voltage regulator is disabled, and soft-start is reinitiated. In undervoltage lockout, the MOSFET driver output (NDRV) is held low.
If the input voltage range is between 13V and 36V, V+
and VDD may be connected to the line voltage, provided that the maximum power dissipation is not exceeded. This eliminates the need for a tertiary winding.
PWM Controller Undervoltage Lockout,
Soft-Start, and Shutdown
The soft-start feature of the MAX5942A/MAX5942B
allows the load voltage to ramp up in a controlled manner, thus eliminating output voltage overshoot.
While the part is in undervoltage lockout, the capacitor
connected to the SS_SHDN pin is discharged. Upon
coming out of undervoltage lockout, an internal current
source starts charging the capacitor to initiate the softstart cycle. Use the following equation to calculate total
soft-start time:
tstartup = 0.45
ms
× Css
nF
where CSS is the soft-start capacitor as shown in Figure 5.
Operation begins when VSS_SHDN ramps above 0.6V.
When soft-start has completed, VSS_SHDN is regulated
to 2.4V, the internal voltage reference. Pull VSS_SHDN
below 0.25V to disable the controller.
Undervoltage lockout shuts down the controller when
VCC is less than 6.6V. The regulators for V+ and the reference remain on during shutdown.
______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
MAX5942A/MAX5942B
VDD
VDD-OK
V+
IN
IN
HIGHVOLTAGE
REGULATOR
VEN
BIAS
WINDING
REGULATOR
OUT
EN
OUT
0.7V
VCC
MAX5942A ONLY
UVLO
SLOPE
COMPENSATION
26mV/µs
6.6V
275kHz
OSCILLATOR
VCC
R
NDRV
Q
26mV/µs
80%/50%
DUTY CYCLE
CLAMP
1MΩ
FB
S
∑
50kΩ
ILIM
PWM
125mV
CS
ERROR
AMP
5kΩ
VCC
SS_SHDN
70ns
BLANKING
4µA
3R
2.4V
BUF
R
0.25V
Figure 4. MAX5942A/MAX5942B PWM Controller Functional Diagram
______________________________________________________________________________________
15
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
1N4148
6
VIN
(36V TO 72V)
VDD
NT
GND
N
14 R
CMHD2003
V+
CDD
4.7µF
NDRV
RCL
VCC
25.5kΩ
MAX5942
NS
5
L1
4.7µH
COUT
3✕
560µF
0.1µF
1nF
M1
IRF640N
100Ω
VOUT
5V/10A
20Ω
R1
2kΩ
CS
CCC
10µF
RCL
CIN
3✕
0.47µF NP
14
SBL204OCT
RSENSE
100mΩ
VUVLO
SS_SHDN
CSS
0.1µF
PGOOD
OUT
GATE
VEE
GATE
FB
R2
2kΩ
CFB
(OPTIONAL)
Figure 5. Forward Converter
Current-Sense Comparator
The current-sense (CS) comparator and its associated
logic limit the peak current through the MOSFET.
Current is sensed at CS as a voltage across a sense
resistor between the source of the MOSFET and GND.
To reduce switching noise, connect CS to the external
MOSFET source through a 100Ω resistor or an RC lowpass filter (Figures 5, 6). Select the current-sense resistor, RSENSE according to the following equation:
RSENSE = 0.465V / ILIMPrimary
where ILIMPrimary is the maximum peak primary-side
current.
When VCS > 465mV, the power MOSFET switches off.
The propagation delay from the time the switch current
reaches the trip level to the driver turn-off time is 180ns.
Internal Error Amplifier
The MAX5942A/MAX5942B include an internal error
amplifier that can be used to regulate the output voltage in the case of a nonisolated power supply (see
16
Figure 5). Calculate the output voltage using the following equation:
⎛ R ⎞
VOUT = ⎜1 + 1 ⎟ × VREF
⎝ R2 ⎠
where VREF = 2.4V.
Choose R1//R2 VEA - VREF - VSCOMP
where IPRIMARY is the current through the N-channel
MOSFET, VREF is the 2.4V internal reference, VEA is the
output voltage of the internal amplifier, and VSCOMP is a
ramp function starting at zero and slewing at 26mV/µs
(MAX5942A only). When using the MAX5942A in a forward-converter configuration, the following condition
must be met to avoid control-loop subharmonic oscillations:
NS k × RSENSE × VOUT
×
= 26mV/µs
L
NP
where k = 0.75 to 1, and NS and NP are the number of
turns on the secondary and primary side of the transformer, respectively. L is the output filter inductor. This
makes the output inductor current downslope as referenced across RSENSE equal to the slope compensation. The controller responds to transients within one
cycle when this condition is met.
N-Channel MOSFET Gate Driver
NDRV drives an N-channel MOSFET. NDRV sources
and sinks large transient currents to charge and discharge the MOSFET gate. To support such switching
transients, bypass VCC with a ceramic capacitor. The
average current as a result of switching the MOSFET is
the product of the total gate charge and the operating
frequency. It is this current plus the DC quiescent current that determines the total operating current.
Applications Information
Design Example
The following is a general procedure for designing a
forward converter using the MAX5942B:
1) Determine the requirements.
2) Set the output voltage.
3) Calculate the transformer primary to secondary
winding turns ratio.
4) Calculate the reset to primary winding turns ratio.
5) Calculate the tertiary to primary winding turns
ratio.
6) Calculate the current-sense resistor value.
7) Calculate the output inductor value.
8) Select the output capacitor.
The circuit in Figure 5 was designed as follows:
1) 30V ≤ VIN ≤ 67V, VOUT = 5V, IOUT = 10A, VRIPPLE ≤
50mV. Turn-on threshold is set at 38.6V.
2) To set the output voltage, calculate the values of
resistors R1 and R2 according to the following
equation:
⎡
R1 ⎤
VOUT = VREF ⎢
1 +
⎥
⎣
R2 ⎦
R1// R2
工商网监
湘ICP备2023018690号
