EVALUATION KIT AVAILABLE
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MAX5974A/MAX5974B/
MAX5974C/MAX5974D
General Description
The MAX5974_ provide control for wide-input-voltage,
active-clamped, current-mode PWM, forward converters
in Power-over-Ethernet (PoE) powered device (PD) applications. The MAX5974A/MAX5974C are well-suited for
universal or telecom input range, while the MAX5974B/
MAX5974D also accommodate low input voltage down
to 10.5V.
The devices include several features to enhance supply
efficiency. The AUX driver recycles magnetizing current instead of wasting it in a dissipative clamp circuit.
Programmable dead time between the AUX and main
driver allows for zero-voltage switching (ZVS). Under
light-load conditions, the devices reduce the switching frequency (frequency foldback) to reduce switching losses.
The MAX5974A/MAX5974B feature unique circuitry to
achieve output regulation without using an optocoupler,
while the MAX5974C/MAX5974D utilize the traditional
optocoupler feedback method. An internal error amplifier
with a 1% reference is very useful in nonisolated design,
eliminating the need for an external shunt regulator.
The devices feature a unique feed-forward maximum
duty-cycle clamp that makes the maximum clamp voltage during transient conditions independent of the line
voltage, allowing the use of a power MOSFET with lower
breakdown voltage. The programmable frequency dithering feature provides low-EMI, spread-spectrum operation.
The MAX5974_ are available in 16-pin TQFN-EP packages and are rated for operation over the -40°C to +85°C
and -40°C to +125°C temperature ranges.
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
Ordering Information/Selector Guide appears at end of data
sheet.
19-5331; Rev 8; 11/20
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Features
●● Peak Current-Mode Control, Active-Clamped Forward
PWM Controller
●● Regulation Without Optocoupler (MAX5974A/
MAX5974B)
●● Internal 1% Error Amplifier
●● 100kHz to 600kHz Programmable ±8% Switching
Frequency, Synchronization Up to 1.2MHz
●● Programmable Frequency Dithering for Low-EMI,
Spread-Spectrum Operation
●● Programmable Dead Time, PWM Soft-Start, Current
Slope Compensation
●● Programmable Feed-Forward Maximum Duty-Cycle
Clamp, 80% Maximum Limit
●● Frequency Foldback for High-Efficiency Light-Load
Operation
●● Internal Bootstrap UVLO with Large Hysteresis
●● 100μA (typ) Startup Supply Current
●● Fast Cycle-by-Cycle Peak Current-Limit, 35ns Typical
Propagation Delay
●● 115ns Current-Sense Internal Leading-Edge Blanking
●● Output Short-Circuit Protection with Hiccup Mode
●● Reverse Current Limit to Prevent Transformer
Saturation Due to Reverse Current
●● Internal 18V Zener Clamp on Supply Input
●● 3mm x 3mm, Lead-Free, 16-Pin TQFN-EP
Applications
●●
●●
●●
●●
●●
●●
PoE IEEE® 802.3af/at Powered Devices
High-Power PD (Beyond the 802.3af/at Standard)
Active-Clamped Forward DC-DC Converters
IP Phones
Wireless Access Nodes
Security Cameras
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Absolute Maximum Ratings
IN to GND (VEN = 0V)............................................-0.3V to +26V
NDRV, AUXDRV to GND.............................-0.3V to (VIN + 0.3V)
RT, DT, FFB, COMP, SS, DCLMP, DITHER/SYNC
to GND..................................................................-0.3V to +6V
FB to GND (MAX5974A/MAX5974B only)..................-6V to +6V
FB to GND (MAX5974C/MAX5974D only)...............-0.3V to +6V
CS, CSSC to GND...................................................-0.8V to +6V
PGND to GND.......................................................-0.3V to +0.3V
Maximum Input/Output Current (continuous)
EN......................................................................................1mA
NDRV, AUXDRV (pulsed for less than 100ns)...................±1A
Continuous Power Dissipation (TA = +70°C)
16-Pin TQFN (derate 20.8mW/°C above +70°C).......1666mW
Operating Temperature Range.......................... -40°C to +125°C
Maximum Junction Temperature......................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................ +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 16 TQFN
Package Code
T1633+4
Outline Number
21-0136
Land Pattern Number
90-0031
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
48°C/W
Junction to Case (θJC)
7°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated │ 2
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Electrical Characteristics
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND,
VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, CIN = 1µF, TA = -40°C to +85°C (MAX5974BETE+,
MAX5974CETE+, MAX5974DETE+), TA = -40°C to +105°C (MAX5974AETE+), TA = -40°C to +125°C (MAX5974AATE+, MAX5974BATE+,
MAX5974CATE+, MAX5974DATE+), unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UNDERVOLTAGE LOCKOUT/STARTUP (IN)
MAX5974A/C
Bootstrap UVLO Wakeup Level
Bootstrap UVLO Shutdown
Level
IN Clamp Voltage
IN Supply Current in
Undervoltage Lockout
IN Supply Current After Startup
VINUVR
VINUVF
VIN_CLAMP
ISTART
VIN rising
MAX5974B/D
VIN falling
15.4
16
16.5
-40°C to
+85°C
8
8.4
8.85
-40°C to
+125°C
7.95
8.4
8.85
-40°C to +85°C
6.65
7
7.35
-40°C to +125°C
6.6
7
7.35
17
18.5
20
100
150
IIN = 2mA (sinking)
VIN = +15V (for
MAX5974A/C);
VIN = +7.5V (for
MAX5974B/D), when
in bootstrap UVLO
IC
VIN = +12V
VENR
VEN rising
VENF
VEN falling
-40°C to +85°C
V
V
V
µA
-40°C to +125°C
100
250
-40°C to +85°C
1.8
3
-40°C to +125°C
1.8
4
mA
ENABLE (EN)
Enable Threshold
Input Current
IEN
-40°C to +85°C
1.17
1.215
1.26
-40°C to +125°C
1.17
1.2155
1.2655
-40°C to +85°C
1.09
1.14
1.19
-40°C to +125°C
1.085
1.14
1.19
-40°C to +85°C
1
-40°C to +105°C
1.5
V
µA
OSCILLATOR (RT)
RT Bias Voltage
VRT
NDRV Switching Frequency
Range
fSW
NDRV Switching Frequency
Accuracy
Maximum Duty Cycle
DMAX
1.23
100
V
600
-40°C to +85°C
-8
+8
-40°C to +105°C
-11
+11
-40°C to +125°C
-13
+13
fSW = 250kHz
-40°C to +85°C
79
80
82
-40°C to +125°C
79
80
83
kHz
%
%
SYNCHRONIZATION (SYNC)
Synchronization Logic-High
Input
VIH-SYNC
2.91
Synchronization Pulse Width
Synchronization Frequency
Range
www.maximintegrated.com
V
50
fSYNCIN
1.1 x
fSW
ns
2x
fSW
kHz
Maxim Integrated │ 3
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Electrical Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND,
VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, CIN = 1µF, TA = -40°C to +85°C (MAX5974BETE+,
MAX5974CETE+, MAX5974DETE+), TA = -40°C to +105°C (MAX5974AETE+), TA = -40°C to +125°C (MAX5974AATE+, MAX5974BATE+,
MAX5974CATE+, MAX5974DATE+), unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
Maximum Duty Cycle During
Synchronization
TYP
MAX
DMAX x fSYNC/
fSW
UNITS
%
DITHERING RAMP GENERATOR (DITHER)
Charging Current
VDITHER = 0V
Discharging Current
VDITHER = 2.2V
-40°C to +85°C
45
50
55
-40°C to +125°C
44.5
50
55.5
-40°C to +85°C
43
50
57
-40°C to +125°C
42
50
58
µA
µA
Ramp’s High Trip Point
2
V
Ramp’s Low Trip Point
0.4
V
SOFT-START AND RESTART (SS)
Charging Current
ISS-CH
ISS-D
Discharging Current
Discharge Threshold to Disable
Hiccup and Restart
Minimum Restart Time During
Hiccup Mode
Normal Operating High Voltage
Duty-Cycle Control Range
DUTY-CYCLE CLAMP (DCLMP)
DCLMP Input Current
Duty-Cycle Control Range
ISS-DH
-40°C to +85°C
9.5
10
10.5
-40°C to +125°C
9
10
11
VSS = 2V, normal shutdown
0.65
1.34
2
mA
(VEN < VENF or VIN < VINUVF),
VSS = 2V, hiccup mode discharge for
tRSTRT (Note 2)
1.6
2
2.4
µA
µA
VSS-DTH
0.15
V
tRSTRT-MIN
1024
Clock
Cycles
VSS-HI
VSS-DMAX
IDCLMP
VDCLMP-R
5
DMAX (typ) = (VSS-DMAX/2.43V)
VDCLMP = 0 to 5V
VDCLMP = 0.5V
VDCLMP = 1V
0
V
2
V
nA
-100
0
+100
73
75.4
77.5
54
56
58
14.7
16.5
18.3
DMAX (typ) =
1 - (VDCLMP/2.43V)
VDCLMP = 2V
-40°C to +85°C
1.9
3.4
-40°C to +125°C
1.9
3.5
4.7
8.3
%
NDRV DRIVER
Pulldown Impedance
RNDRV-N
INDRV (sinking) =
100mA
Pullup Impedance
RNDRV-P
INDRV (sourcing) = 50mA
tNDRV-F
CNDRV = 1nF
Pulldown Impedance
RAUX-N
IAUXDRV (sinking) =
50mA
Pullup Impedance
RAUX-P
IAUXDRV (sourcing) = 25mA
Peak Sink Current
Peak Source Current
Fall Time
Rise Time
AUXDRV DRIVER
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tNDRV-R
CNDRV = 1nF
1
Ω
Ω
A
0.65
A
14
ns
27
ns
-40°C to +85°C
4.3
7.7
-40°C to +125°C
4.3
7.95
10.6
18.9
Ω
Ω
Maxim Integrated │ 4
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Electrical Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND,
VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, CIN = 1µF, TA = -40°C to +85°C (MAX5974BETE+,
MAX5974CETE+, MAX5974DETE+), TA = -40°C to +105°C (MAX5974AETE+), TA = -40°C to +125°C (MAX5974AATE+, MAX5974BATE+,
MAX5974CATE+, MAX5974DATE+), unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
Peak Sink Current
Rise Time
DEAD-TIME PROGRAMMING (DT)
tAUX-F
tAUX-R
DT Bias Voltage
CAUXDRV = 1nF
CAUXDRV = 1nF
VDT
NDRV to AUXDRV Delay
(Dead Time)
tDT
From NDRV falling
to AUXDRV falling
From AUXDRV rising
to NDRV rising
CURRENT-LIMIT COMPARATOR (CS)
Cycle-by-Cycle Peak
Current-Limit Threshold
Cycle-by-Cycle Reverse
Current-Limit Threshold
Current-Sense Blanking Time for
Reverse Current Limit
VCS-REV
tCS-BLANKREV
NHICCUP
Current-Sense Leading-Edge
Blanking Time
tCS-BLANK
Minimum On-Time
SLOPE COMPENSATION (CSSC)
RDT = 10kΩ
tPDCS
Turns AUXDRV off
for the remaining
cycle if reverse
current limit is
exceeded
A
24
ns
45
ns
1.215
V
40
RDT = 100kΩ
310
360
420
375
393
410
-118
-100
-88
-40°C to +85°C
350
410
40
ns
ns
mV
mV
-40°C to +105°C
-124
From AUXDRV falling edge
-100
-88
115
ns
8
Events
From NDRV rising edge
115
ns
From CS rising (10mV overdrive) to
NDRV falling (excluding leading-edge
blanking)
35
ns
tON-MIN
Current ramp’s peak
added to CSSC
input per switching
cycle
Slope Compensation Current
Ramp Height
0.3
300
RDT = 10kΩ
UNITS
A
RDT = 100kΩ
VCS-PEAK
Number of Consecutive Peak
Current-Limit Events to Hiccup
Propagation Delay from
Comparator Input to NDRV
MAX
0.5
Peak Source Current
Fall Time
TYP
100
150
200
-40°C to +85°C
47
52
58
-40°C to +125°C
46.5
52
59.5
ns
µA
PWM COMPARATOR
-40°C to +85°C
1.35
1.7
2
-40°C to +125°C
1.34
1.7
2
3.1
3.33
3.6
Comparator Offset Voltage
VPWM-OS
VCOMP - VCSSC
Current-Sense Gain
ACS-PWM
ΔVCOMP/ΔVCSSC (Note 3)
Current-Sense Leading-Edge
Blanking Time
www.maximintegrated.com
tCSSC-BLANK
From NDRV rising edge
115
V
V/V
ns
Maxim Integrated │ 5
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Electrical Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND,
VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, CIN = 1µF, TA = -40°C to +85°C (MAX5974BETE+,
MAX5974CETE+, MAX5974DETE+), TA = -40°C to +105°C (MAX5974AETE+), TA = -40°C to +125°C (MAX5974AATE+, MAX5974BATE+,
MAX5974CATE+, MAX5974DATE+), unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Comparator Propagation Delay
SYMBOL
tPWM
CONDITIONS
MIN
Change in VCSSC = 10mV (including
internal leading-edge blanking)
TYP
MAX
150
UNITS
ns
ERROR AMPLIFIER
MAX5974A/B
FB Reference Voltage
FB Input Bias Current
Voltage Gain
VREF
IFB
VFB when ICOMP =
0, VCOMP = 2.5V
VFB = 0 to 1.75V
AEAMP
Transconductance
gM
Transconductance Bandwidth
BW
1.54
1.202
1.215
1.227
MAX5974CATE/
DATE (Note 4)
1.202
1.215
1.230
MAX5974A/B
-250
+250
MAX5974CETE/
DETE
-500
+100
MAX5974CATE/
DATE (Note 4)
-1000
+100
80
Open loop (typical
gain = 1) -3dB
frequency
1.8
2.55
3.2
MAX5974C/D
1.8
2.66
3.5
MAX5974A/B
2
MAX5974C/D
30
FREQUENCY FOLDBACK (FFB)
VCSAVG-to-FFB Comparator Gain
IFFB
fSW-FB
nA
mS
MHz
300
375
455
µA
300
375
455
µA
-40°C to +85°C
26
30
33
-40°C to +125°C
26
30
33.5
10
VFFB = 0V, VCS = 0V
(not in FFB mode)
V
dB
MAX5974A/B
VFB = 1.75V, VCOMP = 1V
Sink Current
NDRV Switching Frequency
During Foldback
1.52
VFB = 1V, VCOMP = 2.5V
Source Current
FFB Bias Current
1.5
MAX5974CETE/
DETE
V/V
µA
fSW/2
kHz
Temperature rising
165
°C
Temperature falling
10
°C
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
TSD
Note 1: All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
Note 2: See the Output Short-Circuit Protection with Hiccup Mode section.
Note 3: The parameter is measured at the trip point of latch with VFB = 0V. Gain is defined as ∆VCOMP/∆VCSSC for 0.15V <
∆VCSSC < 0.25V.
Note 4: Operates over the -40°C to +125°C operating temperature range.
www.maximintegrated.com
Maxim Integrated │ 6
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
16.0
15.9
15.8
-15
10
35
60
8.3
8.2
8.1
8.0
85
-15
-40
10
35
60
MAX5974A/B/C/D toc03
7.0
6.9
6.8
85
-40
-15
35
60
EN FALLING THRESHOLD
vs. TEMEPRATURE
UVLO SHUTDOWN CURRENT
vs. TEMPERATURE
1.148
1.214
1.145
1.144
1.212
120
MAX5974A/MAX5974C
100
80
MAX5974B/MAX5974D
1.143
-15
10
35
60
1.142
85
-40
-15
10
35
60
60
85
-40
-15
10
35
60
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5974A/MAX5974C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5974B/MAX5974D)
SUPPLY CURRENT
vs. SWITCHING FREQUENCY
100
1000
100
TA = -40°C
0
2
4
6
8
10 12 14 16 18 20
TEMPERATURE (°C)
www.maximintegrated.com
TA = -40°C
10
0
2
4
6
8
10 12 14 16 18 20
TEMPERATURE (°C)
85
MAX5974A/B/C/D toc09
1000
TA = +85°C
2.4
2.0
SUPPLY CURRENT (mA)
TA = +85°C
MAX5974A/B/C/D toc08
TEMPERATURE (°C)
MAX5974A/B/C/D toc07
TEMPERATURE (°C)
10,000
85
MAX5974A/B/C/D toc06
1.149
140
UVLO CURRENT (µA)
MAX5974A/B/C/D toc04
EN RISING THRESHOLD (V)
1.150
1.147
-40
10
EN RISING THRESHOLD
vs. TEMPERATURE
1.146
10
7.1
TEMPERATURE (°C)
1.216
10,000
7.2
TEMPERATURE (°C)
1.218
1.210
7.3
TEMPERATURE (°C)
1.220
SUPPLY CURRENT (µA)
8.4
MAX5974A/B/C/D toc05
-40
8.5
EN FALLING THRESHOLD (V)
15.7
MAX5974B/MAX5974D
IN UVLO SHUTDOWN LEVEL
16.1
MAX5974A/B/C/D toc02
16.2
IN UVLO SHUTDOWN LEVEL
vs. TEMPERATURE
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
8.6
IN UVLO WAKE-UP LEVEL (V)
MAX5974A/MAX5974C
SUPPLY CURRENT (µA)
IN UVLO WAKE-UP LEVEL (V)
16.3
MAX5974A/B/C/D toc01
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
1.6
1.2
0.8
0.4
0
0
100 200 300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
Maxim Integrated │ 7
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
SWITCHING FREQUENCY
vs. RRT VALUE
10.03
10.02
10.01
10.00
9.99
-40
-15
10
35
60
10
85
248
247
246
10
244
100
10
35
60
MAXIMUM DUTY CYCLE
vs. SWITCHING FREQUENCY
MAXIMUM DUTY CYCLE
vs. TEMPERATURE
2
81
80
79
78
77
81.0
80.9
76
400
500
600
700
75
900 1000
800
80.8
80.7
80.6
80.5
80.4
80.3
0
80.2
100 200 300 400 500 600 700 800
-40
-15
10
35
60
SWITCHING FREQUENCY (kHz)
TEMPERATURE (°C)
MAXIMUM DUTY CYCLE
vs. SYNC FREQUENCY
MAXIMUM DUTY CYCLE
vs. VSS
MAXIMUM DUTY CYCLE
vs. VDCLMP
25
20
15
10
80
70
60
50
40
30
20
5
10
0
0
300
350
400
450
SYNC FREQUENCY (kHz)
www.maximintegrated.com
500
100
85
MAX5974A/B/C/D toc18
90
90
MAXIMUM DUTY CYCLE (%)
30
MAX5974A/B/C/D toc17
35
100
MAXIMUM DUTY CYCLE (%)
MAX5974A/B/C/D toc16
RDITHER (kΩ)
VSS = 0.5V
85
MAX5974A/B/C/D toc15
MAX5974A/B/C/D toc14
82
MAXIMUM DUTY CYCLE (%)
4
83
MAXIMUM DUTY CYCLE (%)
6
250
-15
FREQUENCY DITHERING
vs. RDITHER
8
300
-40
TEMPERATURE (°C)
10
40
249
RRT VALUE (kΩ)
12
45
250
TEMPERATURE (°C)
MAX5974A/B/C/D toc13
FREQUENCY DITHERING (%)
14
0
251
245
9.98
9.97
MAXIMUM DUTY CYCLE (%)
100
252
MAX5974A/B/C/D toc12
10.04
1000
MAX5974A/B/C/D toc11
10.05
SWITCHING FREQUENCY (kHz)
MAX5974A/B/C/D toc10
SOFT-START CHARGING CURRENT (µA)
10.06
SWITCHING FREQUENCY
vs. TEMPERATURE
SWITCHING FREQUENCY (kHz)
SOFT-START CHARGING CURRENT
vs. TEMPERATURE
80
70
60
50
40
30
20
10
0
0.5
1.0
1.5
VSS (V)
2.0
2.5
0
0
0.5
1.0
1.5
2.0
2.5
VDCLMP (V)
Maxim Integrated │ 8
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
200
150
50
90
0
88
30
40
50
60
70
80
90 100
10
35
60
85
REVERSE CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
SLOPE COMPENSATION CURRENT
vs. TEMPERATURE
-101
-102
-103
-104
-105
-106
10
35
60
MAX5974A/B/C/D toc23
53.5
53.0
52.5
52.0
51.5
51.0
-40
-15
10
MAX5974A/B/C/D toc21
391
390
389
-40
-15
10
35
60
35
60
165
160
150
145
140
85
-40
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
CURRENT-SENSE GAIN
vs. TEMPERATURE
FEEDBACK VOLTAGE
vs. TEMPERATURE
FEEDBACK VOLTAGE
vs. TEMPERATURE
3.37
3.36
1.219
MAX5974C/MAX5974D
1.218
1.217
1.216
3.35
1.215
3.34
1.212
3.31
1.211
-15
10
35
TEMPERATURE (°C)
www.maximintegrated.com
60
85
1.210
1.520
1.518
1.213
3.32
1.521
1.519
1.214
3.33
1.522
85
MAX5974A/B/C/D toc27
3.38
1.220
85
155
TEMPERATURE (°C)
3.39
-40
392
170
50.5
50.0
85
MAX5974A/B/C/D toc25
3.40
-15
393
NDRV MINIMUM ON-TIME
vs. TEMPERATURE
MAX5974A/B/C/D toc26
-40
394
TEMPERATURE (°C)
54.0
SLOPE COMPENSATION CURRENT (mA)
-100
395
388
110
TEMPERATURE (°C)
-99
3.30
-15
RDT VALUE (kΩ)
-98
-107
-40
396
FEEDBACK VOLTAGE (V)
20
FEEDBACK VOLTAGE (V)
-97
10
MAX5974A/B/C/D toc22
REVERSE CURRENT-LIMIT THRESHOLD (mV)
94
92
100
CURRENT-SENSE GAIN (V/V)
96
397
MAX5974A/B/C/D toc24
250
98
398
PEAK CURRENT-LIMIT THRESHOLD (mV)
100
DEAD TIME (ns)
300
MAX5974A/B/C/D toc20
350
DEAD TIME (ns)
102
MAX5974A/B/C/D toc19
400
PEAK CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
DEAD TIME vs. TEMPERATURE
NDRV MINIMUM ON-TIME (ns)
DEAD TIME vs. RDT VALUE
1.517
-40
-15
10
35
TEMPERATURE (°C)
60
85
1.516
-40
-15
10
35
60
85
TEMPERATURE (°C)
Maxim Integrated │ 9
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
TRANSCONDUCTANCE HISTOGRAM
(MAX5974A/MAX5974B)
2.6
20
2.5
2.4
MAX5974A/MAX5974B
15
20
N (%)
2.7
25
MAX5974A/B/C/D toc29
MAX5974C/MAX5974D
N (%)
TRANSCONDUCTANCE (mS)
2.9
2.8
25
MAX5974A/B/C/D toc28
3.0
TRANSCONDUCTANCE HISTOGRAM
(MAX5974C/MAX5974D)
MAX5974A/B/C/D toc30
TRANSCONDUCTANCE
vs. TEMPERATURE
15
10
10
5
5
2.3
2.2
2.1
2.0
-40
-15
10
35
85
60
0
2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 2.62 2.64
TEMPERATURE (°C)
0
2.56 2.58 2.60 2.62 2.64 2.66 2.68 2.70 2.72 2.74 2.76
TRANSCONDUCTANCE (mS)
ENABLE RESPONSE
MAX5974A/B/C/D toc31
TRANSCONDUCTANCE (mS)
SHUTDOWN RESPONSE
MAX5974A/B/C/D toc32
VEN
5V/div
VNDRV
10V/div
VNDRV
10V/div
VAUXDRV
10V/div
VAUXDRV
10V/div
VOUT
5V/div
VSS RAMP RESPONSE
VDCLMP RAMP RESPONSE
MAX5974A/B/C/D toc33
www.maximintegrated.com
VOUT
5V/div
100µs/div
200µs/div
10µs/div
VEN
5V/div
MAX5974A/B/C/D toc34
VSS
2V/div
VDCLMP
2V/div
VNDRV
10V/div
VNDRV
10V/div
VAUXDRV
10V/div
VAUXDRV
10V/div
10µs/div
Maxim Integrated │ 10
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 17V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP =
VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kΩ, RDT = 25kΩ, unless otherwise noted.)
NDRV 10% TO 90% RISE TIME
NDRV 90% TO 10% FALL TIME
MAX5974A/B/C/D toc35
AUXDRV 10% TO 90% RISE TIME
MAX5974A/B/C/D toc36
MAX5974A/B/C/D toc37
0ns
27.6ns
45.6ns
VNDRV
2V/div
VNDRV
2V/div
13.8ns
0ns
10ns/div
VAUXDRV
2V/div
0ns
10ns/div
10ns/div
PEAK NDRV CURRENT
AUXDRV 90% TO 10% FALL TIME
MAX5974A/B/C/D toc39
MAX5974A/B/C/D toc38
PEAK SOURCE CURRENT
0ns
INDRV
0.5A/div
VAUXDRV
2V/div
21ns
PEAK SINK CURRENT
200ns/div
10ns/div
SHORT-CURRENT BEHAVIOR
PEAK AUXDRV CURRENT
MAX5974A/B/C/D toc40
MAX5974A/B/C/D toc41
15V
PEAK SOURCE
CURRENT
VIN
5V/div
5V
IAUXDRV
0.2A/div
VNDRV
10V/div
VCS
500mV/div
PEAK SINK CURRENT
400ns/div
www.maximintegrated.com
40ms/div
Maxim Integrated │ 11
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
2
RT
3
FFB
4
DCLMP
EN
IN
13
12 AUXDRV
MAX5974A
MAX5974B
MAX5974C
MAX5974D
11 NDRV
10 PGND
EP
COMP
5
9
6
7
CS
8
CSSC
DITHER/
SYNC
14
GND
1
15
+
DT
16
FB
TOP VIEW
SS
Pin Configuration
16 TQFN
(3mm x 3mm)
Pin Description
PIN
NAME
1
DT
Dead-Time Programming Resistor Connection. Connect resistor RDT from DT to GND to set the
desired dead time between the NDRV and AUXDRV signals. See the Dead Time section to calculate
the resistor value for a particular dead time.
2
DITHER/
SYNC
Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency
operation, connect a capacitor from DITHER to GND and a resistor from DITHER to RT. To
synchronize the internal oscillator to the externally applied frequency, connect DITHER/SYNC to the
synchronization pulse.
3
RT
Switching Frequency Programming Resistor Connection. Connect resistor RRT from RT to GND to set
the PWM switching frequency. See the Oscillator/Switching Frequency section to calculate the resistor
value for the desired oscillator frequency.
4
FFB
Frequency Foldback Threshold Programming Input. Connect a resistor from FFB to GND to set the
output average current threshold below which the converter folds back the switching frequency to 1/2
of its original value. Connect to GND to disable frequency foldback.
5
COMP
Transconductance Amplifier Output and PWM Comparator Input. COMP is level shifted down and
connected to the inverting input of the PWM comparator. COMP is actively pulled low by the controller
after shutdown.
www.maximintegrated.com
FUNCTION
Maxim Integrated │ 12
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Pin Description (continued)
PIN
NAME
6
FB
FUNCTION
7
GND
Signal Ground
8
CSSC
Current Sense with Slope Compensation Input. A resistor connected from CSSC to CS programs the
amount of slope compensation. See the Programmable Slope Compensation section.
9
CS
Current-Sense Input. Current-sense connection for average current sense and cycle-by-cycle current
limit. Peak current-limit trip voltage is 400mV and reverse current-limit trip voltage is -100mV.
10
PGND
Power Ground. PGND is the return path for gate-driver switching currents.
11
NDRV
Main Switch Gate-Driver Output
12
AUXDRV
13
IN
Converter Supply Input. IN has wide UVLO hysteresis, enabling the design of efficient power supplies.
See the Enable Input section to determine if an external zener diode is required at IN.
14
EN
Enable Input. The gate drivers are disabled and the device is in a low-power UVLO mode when the
voltage on EN is below VENF. When the voltage on EN is above VENR, the device checks for other
enable conditions. See the Enable Input section for more information about interfacing to EN.
Transconductance Amplifier Inverting Input
pMOS Active Clamp Switch Gate-Driver Output. AUXDRV can also be used to drive a pulse
transformer for synchronous flyback application.
15
DCLMP
Feed-Forward Maximum Duty-Cycle Clamp Programming Input. Connect a resistive divider between
the input supply voltage DCLMP and GND. The voltage at DCLMP sets the maximum duty cycle
(DMAX) of the converter inversely proportional to the input supply voltage, so that the MOSFET
remains protected during line transients.
16
SS
Soft-Start Programming Capacitor Connection. Connect a capacitor from SS to GND to program the
soft-start period. This capacitor also determines hiccup mode current-limit restart time. A resistor from
SS to GND can also be used to set the DMAX below 75%.
—
EP
Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance. Not intended as an electrical connection point.
www.maximintegrated.com
Maxim Integrated │ 13
www.maximintegrated.com
1
3
DT
RT
2
7
DITHER/
SYNC
GND
10
4
FFB
PGND
SYNC
PGND
DRIVER
0.5A/-0.3A
VC
PGND
DRIVER
1A/-0.65A
VB
VB
AUXDRV
NDRV
-50µA
50µA/
90µA
30µA/
FFB COMP
SS
DEAD TIME
DEAD-TIME
CONTROL
OSCILLATOR
15 20% < DMAX < 80%
12
AUXDRV
DCLMP
11
NDRV
VC
2V/400mV
VCSAVG
10X
POK
NDRV
BLANKING
PULSE
REVERSE ILIM LIMIT TURNS
OFF AUX IMMEDIATELY
DRIVER LOGIC
VSS < 150mV
R
S
VB
POK
5V
REGULATOR
MAX5974A
MAX5974B
QCLR
QSET
ENABLE
COUNT 8
EVENTS
REVERSE ILIM COMP
HICCUP
LATCH
THERMAL
SHUTDOWN
PWM
COMP
PEAK ILIM
COMP
1.215V
R1
18V
VB
115ns
BLANKING
115ns
BLANKING
2 x R1
400mV
-100mV
gM
VB
VB
1.52V
SLOPE
COMPENSATION
LOW-POWER UVLO
UVLO VINUVR = 16V (MAX5974A)
VINUVR = 8.4V (MAX5974B)
VINUVF = 7V
2µA
POK
2mA
10µA
S/H
VB
14 EN
13 IN
6 FB
5 COMP
8 CSSC
9 CS
16 SS
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Block Diagrams
Maxim Integrated │ 14
www.maximintegrated.com
1
3
DT
RT
2
7
DITHER/
SYNC
GND
10
4
FFB
PGND
SYNC
PGND
DRIVER
0.5A/-0.3A
VC
PGND
DRIVER
1A/-0.65A
VB
VB
AUXDRV
NDRV
OSCILLATOR
-50µA
50µA/
90µA
30µA/
15 20% < DMAX < 80%
12
AUXDRV
DCLMP
11
NDRV
VC
FFB COMP
SS
DEAD TIME
DEAD-TIME
CONTROL
2V/400mV
VCSAVG
10X
POK
NDRV
BLANKING
PULSE
REVERSE ILIM LIMIT TURNS
OFF AUX IMMEDIATELY
DRIVER LOGIC
VB
POK
VSS < 150mV
R
S
5V
REGULATOR
MAX5974C
MAX5974D
QCLR
QSET
ENABLE
COUNT 8
EVENTS
REVERSE ILIM COMP
HICCUP
LATCH
THERMAL
SHUTDOWN
PWM
COMP
PEAK ILIM
COMP
1.215V
R1
18V
VB
115ns
BLANKING
115ns
BLANKING
2 x R1
400mV
-100mV
gM
VB
VB
1.215V
SLOPE
COMPENSATION
LOW-POWER UVLO
UVLO VINUVR = 16V (MAX5974C)
VINUVR = 8.4V (MAX5974D)
VINUVF = 7V
2µA
POK
VB
2mA
10µA
14 EN
13 IN
6 FB
5 COMP
8 CSSC
9 CS
16 SS
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Block Diagrams (continued)
Maxim Integrated │ 15
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Detailed Description
The MAX5974A/MAX5974B/MAX5974C/MAX5974D are
optimized for controlling a 25W to 50W active-clamped,
self-driven synchronous rectification forward converter in
continuous-conduction mode. The main switch gate driver
(NDRV) and the active-clamped switch driver (AUXDRV)
are sized to optimize efficiency for 25W design. The
features-rich devices are ideal for PoE IEEE 802.3af/atpowered devices.
The MAX5974A/MAX5974C offer a 16V bootstrap UVLO
wake-up level with a 9V wide hysteresis. The low startup
and operating currents allow the use of a smaller storage
capacitor at the input without compromising startup and
hold times. The MAX5974A/MAX5974C are well-suited
for universal input (rectified 85V AC to 265V AC) or telecom (-36V DC to -72V DC) power supplies.
The MAX5974B/MAX5974D have a UVLO rising threshold
of 8.4V and can accommodate for low-input voltage (12V
DC to 24V DC) power sources such as wall adapters.
Power supplies designed with the MAX5974A/MAX5974C
use a high-value startup resistor, RIN, that charges a reservoir capacitor, CIN (see the Typical Application Circuits).
During this initial period, while the voltage is less than
the internal bootstrap UVLO threshold, the device typically consumes only 100µA of quiescent current. This low
startup current and the large bootstrap UVLO hysteresis
help to minimize the power dissipation across RIN even at
the high end of the universal AC input voltage (265V AC).
Feed-forward maximum duty-cycle clamping detects
changes in line conditions and adjusts the maximum duty
cycle accordingly to eliminate the clamp voltage’s (i.e.,
the main power FET’s drain voltage) dependence on the
input voltage.
For EMI-sensitive applications, the programmable frequency dithering feature allows up to ±10% variation in
the switching frequency. This spread-spectrum modulation technique spreads the energy of switching harmonics
over a wider band while reducing their peaks, helping to
meet stringent EMI goals.
www.maximintegrated.com
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
The devices include a cycle-by-cycle current limit that
turns off the main and AUX drivers whenever the internally set threshold of 400mV is exceeded. Eight consecutive
occurrences of current-limit events trigger hiccup mode,
which protects external components by halting switching
for a period of time (tRSTRT) and allowing the overload
current to dissipate in the load and body diode of the synchronous rectifier before soft-start is reattempted.
The reverse current-limit feature of the devices turns the
AUX driver off for the remaining off period when VCS
exceeds the -100mV threshold. This protects the transformer core from saturation due to excess reverse current
under some extreme transient conditions.
Current-Mode Control Loop
The advantages of current-mode control over voltagemode control are twofold. First, there is the feed-forward
characteristic brought on by the controller’s ability to
adjust for variations in the input voltage on a cycle-bycycle basis. Second, the stability requirements of the current-mode controller are reduced to that of a single-pole
system, unlike the double pole in voltage-mode control.
The devices use a current-mode control loop where the
scaled output of the error amplifier (COMP) is compared
to a slope-compensated current-sense signal at CSSC.
Input Clamp
When the device is enabled, an internal 18V input clamp
is active. During an overvoltage condition, the clamp prevents the voltage at the supply input IN from rising above
18.5V (typ).
When the device is disabled, the input clamp circuitry is
also disabled.
Enable Input
The enable input is used to enable or disable the device.
Driving EN low disables the device. Note that the internal 18V input clamp is also disabled when EN is low.
Therefore, an external 18V zener diode is needed for
certain operating conditions as described below.
Maxim Integrated │ 16
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
UVLO on Power Source
The enable input has an accurate threshold of 1.26V
(max). For applications that require a UVLO on the
power source, connect a resistive divider from the power
source to EN to GND as shown in Figure 1. A zener diode
between IN and GND is required to prevent the NDRV
and AUXDRV gate-drive voltages from exceeding 20V,
the maximum allowed gate voltage of power FETs.
The external zener diode should clamp in the following
range:
20V > V Z > VUVLO(MAX)
where VZ is the zener voltage and VUVLO(MAX) is the
maximum wakeup level (16.5V or 8.85V depending on the
device version). An 18V zener diode is the best choice.
Design the resistive divider by first selecting the value of
REN1 to be on the order of 100kΩ. Then calculate REN2
as follows:
V=
EN2 R EN1 ×
VEN(MAX)
VS(UVLO)
_
VEN(MAX)
where VEN(MAX) is the maximum enable threshold voltage and is equal to 1.26V and VS(UVLO) is the desired
UVLO threshold for the power source, below which the
device is disabled.
The digital output connected to EN should be capable of
withstanding more than the maximum supply voltage.
MCU Control of Enable Input
When using a microcontroller GPIO to control the enable
input, an 18V zener diode is required on IN as shown in
Figure 2.
High-Voltage Logic Control of Enable Input
In the case where EN is externally controlled by a highvoltage open-drain/collector output (e.g., PGOOD indicator of a powered device controller), connect IN to EN
through a resistor REN and connect EN to an open-drain
or open-collector output as shown in Figure 3. Select REN
such that the voltage at IN, when EN is low, is less than
20V (i.e., the maximum gate voltage of the main and AUX
FETs):
VS(MAX) ×
R EN
< 20V
R EN + R IN
where VS(MAX) is the maximum supply voltage. Obeying
this relationship eliminates the need for an external zener
diode.
The digital output connected to EN should be capable of
withstanding more than 20V.
VS
VS
RIN
RIN
IN
18V
CIN
IN
MAX5974
REN1
CIN
18V
MAX5974_
MCU
DIGITAL
CONTROL
EN
N
I/O
EN
REN2
Figure 1. Programmable UVLO for the Power Source
www.maximintegrated.com
Figure 2. MCU Control of the Enable Input
Maxim Integrated │ 17
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
VS
Because the MAX5974B/MAX5974D are designed for
use with low-voltage power sources such as wall adapters
outputting 12V to 24V, they have a lower UVLO wake-up
threshold of 8.4V.
RIN
Startup Operation
The device starts up when the voltage at IN exceeds 16V
(MAX5974A/MAX5974C) or 8.4V (MAX5974B/MAX5974D)
and the enable input voltage is greater than 1.26V.
IN
CIN
MAX5974
REN
DIGITAL
CONTROL
EN
N
Figure 3. High-Voltage Logic Control of the Enable Input
VS
RIN
IN
CIN
MAX5974_
EN
Figure 4. Always-On Operation
Always-On Operation
For always-on operation, connect EN to IN as shown
in Figure 4. No external zener diode is needed for this
configuration.
Bootstrap Undervoltage Lockout
The devices have an internal bootstrap UVLO that is very
useful when designing high-voltage power supplies (see
the Block Diagrams). This allows the device to bootstrap
itself during initial power-up. The MAX5974A/MAX5974C
soft-start when VIN exceeds the bootstrap UVLO threshold of VINUVR (16V typ).
www.maximintegrated.com
During normal operation, the voltage at IN is normally derived from a tertiary winding of the transformer
(MAX5974C/MAX5974D). However, at startup there is no
energy being delivered through the transformer; hence,
a special bootstrap sequence is required. In the Typical
Application Circuits, CIN charges through the startup
resistor, RIN, to an intermediate voltage. Only 100µA of
the current supplied through RIN is used by the ICs, the
remaining input current charges CIN until VIN reaches the
bootstrap UVLO wake-up level. Once VIN exceeds this
level, NDRV begins switching the n-channel MOSFET
and transfers energy to the secondary and tertiary outputs. If the voltage on the tertiary output builds to higher
than 7V (the bootstrap UVLO shutdown level), then startup has been accomplished and sustained operation commences. If VIN drops below 7V before startup is complete,
the device goes back to low-current UVLO. In this case,
increase the value of CIN in order to store enough energy
to allow for the voltage at the tertiary winding to build up.
While the MAX5974A/MAX5974B derive their input voltage from the coupled inductor output during normal
operation, the startup behavior is similar to that of the
MAX5974C/MAX5974D.
Soft-Start
A capacitor from SS to GND, CSS, programs the soft-start
time. VSS controls the oscillator duty cycle during startup
to provide a slow and smooth increase of the duty cycle
to its steady-state value. Calculate the value of CSS as
follows:
I
×t
C SS = SS-CH SS
2V
where ISS-CH (10µA typ) is the current charging CSS during soft-start and tSS is the programmed soft-start time.
A resistor can also be added from the SS pin to GND to
clamp VSS < 2V and, hence, program the maximum duty
cycle to be less than 80% (see the Duty-Cycle Clamping
section)
Maxim Integrated │ 18
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
n-Channel MOSFET Gate Driver
The NDRV output drives an external n-channel MOSFET.
NDRV can source/sink in excess of 650mA/1000mA
peak current; therefore, select a MOSFET that yields
acceptable conduction and switching losses. The external
MOSFET used must be able to withstand the maximum
clamp voltage.
p-Channel MOSFET Gate Driver
The AUXDRV output drives an external p-channel
MOSFET with the aid of a level shifter. The level shifter
consists of CAUX, RAUX, and D5 as shown in the Typical
Application Circuits. When AUXDRV is high, CAUX is
recharged through D5. When AUXDRV is low, the gate of
the p-channel MOSFET is pulled below the source by the
voltage stored on CAUX, turning on the pFET.
Add a zener diode between gate to source of the external
n-channel and p-channel MOSFETs after the gate resistors to protect VGS from rising above its absolute maximum rating during transient condition (see the Typical
Application Circuits).
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Dead Time
Dead time between the main and AUX output edges allow
ZVS to occur, minimizing conduction losses and improving efficiency. The dead time (tDT) is applied to both leading and trailing edges of the main and AUX outputs as
shown in Figure 5. Connect a resistor between DT and
GND to set tDT to any value between 40ns and 400ns:
R
=
DT
10kΩ
× t DT
40ns
Oscillator/Switching Frequency
The ICs’ switching frequency is programmable between
100kHz and 600kHz with a resistor RRT connected
between RT and GND. Use the following formula to determine the appropriate value of RRT needed to generate the
desired output-switching frequency (fSW):
R RT =
8.7 × 10 9
f SW
where fSW is the desired switching frequency.
BLANKING, tBLK
NDRV
AUXDRV
DEAD TIME, tDT
Figure 5. Dead Time Between AUXDRV and NDRV
www.maximintegrated.com
Maxim Integrated │ 19
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Peak Current Limit
The current-sense resistor (RCS in the Typical Application
Circuits), connected between the source of the n-channel
MOSFET and PGND, sets the current limit. The currentlimit comparator has a voltage trip level (VCS-PEAK) of
400mV. Use the following equation to calculate the value
of RCS:
R CS =
400mV
IPRI
where IPRI is the peak current in the primary side of the
transformer, which also flows through the MOSFET. When
the voltage produced by this current (through the currentsense resistor) exceeds the current-limit comparator
threshold, the MOSFET driver (NDRV) terminates the
current on-cycle, within 35ns (typ).
The devices implement 115ns of leading-edge blanking
to ignore leading-edge current spikes. These spikes are
caused by reflected secondary currents, current-discharging capacitance at the FET’s drain, and gate-charging current. Use a small RC network for additional filtering of the
leading-edge spike on the sense waveform when needed.
Set the corner frequency between 10MHz and 20MHz.
After the leading-edge blanking time, the device monitors
VCS for any breaches of the peak current limit of 400mV.
The duty cycle is terminated immediately when VCS
exceeds 400mV.
VCSBL
(BLANKED CS
VOLTAGE)
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Reverse Current Limit
The devices protect the transformer against saturation
due to reverse current by monitoring the voltage across
RCS while the AUX output is low and the p-channel FET
is on.
Output Short-Circuit Protection
with Hiccup Mode
When the device detects eight consecutive peak currentlimit events, both NDRV and AUXDRV driver outputs are
turned off for a restart period, tRSTRT. After tRSTRT, the
device undergoes soft-start. The duration of the restart
period depends on the value of the capacitor at SS (CSS).
During this period, CSS is discharged with a pulldown current of ISS-DH (2µA typ). Once its voltage reaches 0.15V,
the restart period ends and the device initiates a soft-start
sequence. An internal counter ensures that the minimum
restart period (tRSTRT-MIN) is 1024 clock cycles when the
time required for CSS to discharge to 0.15V is less than
1024 clock cycles. Figure 6 shows the behavior of the
device prior and during hiccup mode.
Frequency Foldback for High-Efficiency
Light-Load Operation
The frequency foldback threshold can be programmed
from 0 to 20% of the full load current using a resistor from
FFB to GND.
VCS-PEAK
(400mV)
HICCUP
DISCHARGE WITH ISS-DH
VSS-HI
SOFT-START
VOLTAGE,
VSS
VSS-DTH
tSS
tRSTRT
Figure 6. Hiccup Mode Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 20
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
When VCSAVG falls below VFFB, the device folds back
the switching frequency to 1/2 the original value to reduce
switching losses and increase the converter efficiency.
Calculate the value of RFFB as follows:
R FFB =
10 × ILOAD(LIGHT) × R CS
IFFB
where RFFB is the resistor between FFB and GND,
ILOAD(LIGHT) is the current at light-load conditions that
triggers frequency foldback, RCS is the value of the sense
resistor connected between CS and PGND, and IFFB is
the current sourced from FFB to RFFB (30µA typ).
Duty-Cycle Clamping
The maximum duty cycle is determined by the lowest
of three voltages: 2V, the voltage at SS (VSS), and the
voltage (2.43V - VDCLMP). The maximum duty cycle is
calculated as:
D MAX =
VMIN
2.43V
where VMIN = minimum (2V, VSS, 2.43V - VDCLMP).
SS
By connecting a resistor between SS and ground, the
voltage at SS can be made to be lower than 2V. VSS is
calculated as follows:
V=
SS R SS × I SS-CH
where RSS is the resistor connected between SS and
GND, and ISS-CH is the current sourced from SS to RSS
(10µA typ).
DCLMP
To set DMAX using supply voltage feed-forward, connect
a resistive divider between the supply voltage, DCLMP,
and GND as shown in the Typical Application Circuits.
This feed-forward duty-cycle clamp ensures that the
external n-channel MOSFET is not stressed during supply
transients. VDCLMP is calculated as follows:
R DCLMP2
=
× VS
VDCLMP
R DCLMP1 + R DCLMP2
where RDCLMP1 and RDCLMP2 are the resistive divider
values shown in the Typical Application Circuits and VS is
the input supply voltage.
www.maximintegrated.com
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Oscillator Synchronization
The internal oscillator can be synchronized to an external
clock by applying the clock to DITHER/SYNC directly. The
external clock frequency can be set anywhere between
1.1x to 2x the internal clock frequency.
Using an external clock increases the maximum duty
cycle by a factor equal to fSYNC/fSW. This factor should
be accounted for in setting the maximum duty cycle using
any of the methods described in the Duty-Cycle Clamping
section. The formula below shows how the maximum duty
cycle is affected by the external clock frequency:
D=
MAX
VMIN f SYNC
×
2.43V
f SW
where VMIN is described in the Duty-Cycle Clamping section, fSW is the switching frequency as set by the resistor
connected between RT and GND, and fSYNC is the external clock frequency.
Frequency Dithering for SpreadSpectrum Applications (Low EMI)
The switching frequency of the converter can be dithered in a range of ±10% by connecting a capacitor from
DITHER/SYNC to GND, and a resistor from DITHER/
SYNC to RT as shown in the Typical Application Circuits.
This results in lower EMI.
A current source at DITHER/SYNC charges the capacitor
CDITHER to 2V at 50µA. Upon reaching this trip point, it
discharges CDITHER to 0.4V at 50µA. The charging and
discharging of the capacitor generates a triangular waveform on DITHER/SYNC with peak levels at 0.4V and 2V
and a frequency that is equal to:
f TRI =
50µA
C DITHER × 3.2V
Typically, fTRI should be set close to 1kHz. The resistor
RDITHER connected from DITHER/SYNC to RT determines the amount of dither as follows:
%DITHER=
R RT
4
×
3 R DITHER
where %DITHER is the amount of dither expressed as a
percentage of the switching frequency. Setting RDITHER
to 10 x RRT generates ±10% dither.
Maxim Integrated │ 21
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Programmable Slope Compensation
The device generates a current ramp at CSSC such that
its peak is 50µA at 80% duty cycle of the oscillator. An
external resistor connected from CSSC to the CS then
converts this current ramp into programmable slopecompensation amplitude, which is added to the currentsense signal for stability of the peak current-mode control
loop. The ramp rate of the slope compensation signal is
given by:
m=
R CSSC × 50µA × f SW
80%
where m is the ramp rate of the slope-compensation signal, RCSSC is the value of the resistor connected between
CSSC and CS used to program the ramp rate, and fSW is
the switching frequency.
Error Amplifier
The MAX5974A/MAX5974B include an internal error
amplifier with a sample-and-hold input. The feedback
input of the MAX5974C/MAX5974D is continuously connected. The noninverting input of the error amplifier is
connected to the internal reference and feedback is
provided at the inverting input. High open-loop gain and
unity-gain bandwidth allow good closed-loop bandwidth
and transient response. Calculate the power-supply output voltage using the following equation:
V=
OUT VREF ×
R FB1 + R FB2
R FB2
where VREF = 1.52V for the MAX5974A/MAX5974B and
VREF = 1.215V for the MAX5974C/MAX5974D. The
amplifier’s noninverting input is internally connected to a
soft-start circuit that gradually increases the reference
voltage during startup. This forces the output voltage to
come up in an orderly and well-defined manner under all
load conditions.
Applications Information
Startup Time Considerations
The bypass capacitor at IN, CIN, supplies current immediately after the devices wake up (see the Typical
www.maximintegrated.com
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Application Circuits). Large values of CIN increase the
startup time, but also supply gate charge for more cycles
during initial startup. If the value of CIN is too small, VIN
drops below 7V because NDRV does not have enough
time to switch and build up sufficient voltage across the
tertiary output (MAX5974C/MAX5974D) or coupled inductor output (MAX5974A/MAX5974B), which powers the
device. The device goes back into UVLO and does not
start. Use a low-leakage capacitor for CIN.
Typically, offline power supplies keep startup times to less
than 500ms even in low-line conditions (85V AC input
for universal offline or 36V DC for telecom applications).
Size the startup resistor, RIN, to supply both the maximum startup bias of the device (150µA) and the charging current for CIN. CIN must be charged to 16V within
the desired 500ms time period. CIN must store enough
charge to deliver current to the device for at least the
soft-start time (tSS) set by CSS. To calculate the approximate amount of capacitance required, use the following
formula:
I G = Q GTOT f SW
(I + I )(t )
C IN = IN G SS
VHYST
where IIN is the ICs’ internal supply current (1.8mA) after
startup, QGTOT is the total gate charge for the n-channel
and p-channel FETs, fSW is the ICs’ switching frequency,
VHYST is the bootstrap UVLO hysteresis (9V typ), and tSS
is the soft-start time. RIN is then calculated as follows:
R IN ≅
VS(MIN) − VINUVR
I START
where VS(MIN) is the minimum input supply voltage for the
application (36V for telecom), VINUVR is the bootstrap
UVLO wake-up level (16V), and ISTART is the IN supply
current at startup (150µA max).
RIN needs to be reduced when operating at +125°C ambient temperature since the IN supply current is increased.
Choose a higher value for RIN than the one calculated
above if a longer startup time can be tolerated in order to
minimize power loss on this resistor.
Maxim Integrated │ 22
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Active Clamp Circuit
Traditional clamp circuits prevent transformer saturation by channeling the magnetizing current (IM) of the
transformer onto a dissipative RC network. To improve
efficiency, the active clamp circuit recycles IM between the
magnetizing inductance and clamp capacitor. VCLAMP is
given by:
VCLAMP =
VS
1− D
where VS is the voltage of the power source and D is
the duty cycle. To select n-channel and p-channel FETs
with adequate breakdown voltages, use the maximum
value of VCLAMP. VCLAMP(MAX) occurs when the input
voltage is at its minimum and the duty cycle is at its
maximum. VCLAMP(MAX-NORMAL) during normal operation is therefore:
VCLAMP(MAX-NORMAL) =
VS(MIN)
N P × VO
1−
N S × VS(MIN)
where VS(MIN) is the minimum voltage of the power
source, NP/NS is the primary to secondary turns ratio, and
VO is the output voltage. The clamp capacitor, n-channel,
and p-channel FETs must have breakdown voltages
exceeding this level.
If feed-forward maximum duty-cycle clamp is used then:
VMIN VDCLMP
= 1−
D MAX-FF=
2.43
2.43
VS
R DCLMP2
=−
×
1
2.43 R DCLMP1 + R DCLMP2
Therefore, VCLAMP(MAX-FF) during feed-forward maximum duty clamp is:
VCLAMP(MAX-FF) =
=
VS
1 − D MAX−FF
2.43 × (R DCLMP1 + R DCLMP2 )
www.maximintegrated.com
R DCLMP2
The AUX driver controls the p-channel FET through a
level shifter. The level shifter consists of an RC network
(formed by CAUX and RAUX) and diode D5, as shown in
the Typical Application Circuits. Choose RAUX and CAUX
so that the time constant exceeds 100/fSW. Diode D5 is
a small-signal diode with a voltage rating exceeding 25V.
Additionally, CCLAMP should be chosen such that the
complex poles formed with magnetizing inductance
(LMAG) and CCLAMP are 2x to 4x away from the loop
bandwidth:
1-D
2π L MAG × C CLAMP
> 3 × f BW
Bias Circuit
Optocoupler Feedback (MAX5974C/MAX5974D)
An in-phase tertiary winding is needed to power the bias
circuit when using optocoupler feedback. The voltage
across the tertiary VT during the on-time is:
N
=
V T VOUT × T
N
S
where VOUT is the output voltage and NT/NS is the turns
ratio from the tertiary to the secondary winding. Select the
turns ratio so that VT is above the UVLO shutdown level
(7.35V max) by a margin determined by the holdup time
needed to “ride through” a brownout.
Coupled-Inductor Feedback (MAX5974A/MAX5974B)
When using coupled-inductor feedback, the power for
the devices can be taken from the coupled inductor during the off-time. The voltage across the coupled inductor,
VCOUPLED, during the off-time is:
N
VCOUPLED
= VOUT × C
N
O
where VOUT is the output voltage and NC/NO is the turns
ratio from the coupled output to the main output winding.
Select the turns ratio so that VCOUPLED is above the
UVLO shutdown level (7.5V max) by a margin determined
by the holdup time needed to “ride through” a brownout.
This voltage appears at the input of the devices, less
a diode drop. An RC network consisting of RSNUB and
CSNUB is for damping the reverse recovery transients of
diode D6.
Maxim Integrated │ 23
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Layout Recommendations
During on-time, the coupled output is:
N
VCOUPLED-ON =
−(VS × S
N
P
−
N
VOUT ) C
NO
where VS is the input supply voltage.
Care must be taken to ensure that the voltage at FB
(equal to VCOUPLED-ON attenuated by the feedback
resistive divider) is not more than 5V:
VFB-ON = VCOUPLED-ON ×
R FB2
< 5V
(R FB1 + R FB2 )
If this condition is not met, a signal diode should be
placed from GND (anode) to FB (cathode).
www.maximintegrated.com
Typically, there are two sources of noise emission in a
switching power supply: high di/dt loops and high dV/dt
surfaces. For example, traces that carry the drain current
often form high di/dt loops. Similarly, the heatsink of the
main MOSFET presents a dV/dt source; therefore, minimize the surface area of the MOSFET heatsink as much
as possible. Keep all PCB traces carrying switching currents as short as possible to minimize current loops. Use
a ground plane for best results.
For universal AC input design, follow all applicable safety
regulations. Offline power supplies can require UL, VDE,
and other similar agency approvals.
Refer to the MAX5974A and MAX5974C Evaluation Kit
data sheets for recommended layout and component
values.
Maxim Integrated │ 24
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Application Circuits
VS
36V TO 57V
L1
3.3mH
CBULK
33µF
D1
NT
RIN
100kΩ
D2
L2
6.8µH
CIN
1µF
25V
D3
RDCLMP1
30.1kΩ
1%
PGOOD
NP
IN
T1
NS
RGATE2
10Ω
RGATE1
10Ω
N
SS
CDITHER
10nF
RRT
14.7kΩ 1%
RFFB
10.0kΩ 1%
RG2
200kΩ 1%
www.maximintegrated.com
N1
5i412DP
MAX5974C
MAX5974D
IN
(OPTOCOUPLER
FEEDBACK)
DT
DITHER/
SYNC
RGATE3
10Ω
NDRV
N3
FDS3692
N
CCLAMP
47nF
RGATE4
10Ω
AUXDRV
RT
CAUX
47nF
RF
499Ω 1%
FFB
CS
FB
COMP
GND
ROPTO2
1kΩ
1%
RFB2
2.49kΩ
1%
N
DCLMP
RDT
16.9kΩ 1%
N2
5i412DP
D4
EN
CSS
0.1µF
RG1
121kΩ 1%
COUT5
COUT1 COUT2 COUT3 COUT4 0.1µF
REN
100kΩ
RDCLMP2
750Ω 1%
5V, 5A
RFB1
7.5kΩ
1%
CF
330pF
D5
CSSC
PGND
RCSSC
4.02kΩ 1%
RAUX
10kΩ
ROPTO3
4.99kΩ
1%
U1
FOD817CSD
P
N4
IRF6217
ROPTO1
825Ω
1%
CCOMP1
2.2nF
RBIAS
4.02kΩ
1%
RCOMP2
499Ω
1%
CCOMP2
6.8pF
CINT
0.1µF
RCOMP2
2.00kΩ
1%
U2
TLV4314AIDBVT-1.24V
RCS
0.2Ω
Maxim Integrated │ 25
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Application Circuits (continued)
D6
CBULK
33µF
63V
TO FB
RFB2
10kΩ 1%
RIN
100kΩ
CIN
1µF
25V
RDCLMP1
30.1kΩ
1%
T1
NS
REN
100kΩ
SS
CDITHER
10nF
RRT
14.7kΩ 1%
RFFB
10kΩ 1%
N
(COUPLED INDUCTOR
FEEDBACK)
DT
DITHER/
SYNC
RGATE3
10Ω
NDRV
www.maximintegrated.com
N3
FDS3692
N
CCLAMP
47nF
RGATE4
10Ω
AUXDRV
RT
CAUX
47nF
P
N4
IRF6217
RF
499Ω 1%
FFB
CF
330pF
D5
COMP
GND
CINT
47nF
COUT5
0.1µF
N1
5i412DP
MAX5974A
MAX5974B
FB
RZ
2kΩ 1%
COUT1 COUT2 COUT3 COUT4
N2
5i412DP
N
CS
CCOMP
4.7nF
RGATE1
10Ω
DCLMP
RDT
16.9kΩ 1%
5V, 5A
D4
EN
CSS
0.1µF
4 x 47µF
6.3V
NO
NP
RDCLMP2
750Ω 1%
LCOUPLED
NC
RGATE2
10Ω
D3
IN
PGOOD
RFB1
54.9kΩ 1%
CSNUB RSNUB
10pF 69.8Ω 1%
VS
36V TO 57V
CSSC
PGND
RAUX
10kΩ
RCSSC
4.02kΩ 1%
RCS
0.2Ω
Maxim Integrated │ 26
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Application Circuits (continued)
D1
L1
VS
NT
CBULK
D2
RIN
L2
CIN
T1
D3
NP
IN
RDCLMP1
REN
100kΩ
NS
RGATE2
COUT1 COUT2 COUT3 COUT4
RGATE1
N
N2
RFB1
RFB2
D4
PGOOD
N
EN
RDCLMP2
N1
DCLMP
MAX5974C
MAX5974D
CSS
SS
RDT
DT
CDITHER
RDITHER
DITHER/
SYNC
RRT
NDRV
RGATE3
P
N4
CAUX
FFB
CS
CSSC
FB
RCSSC
COMP
CCOMP
N3
RGATE4
AUXDRV
RT
RFFB
Rz
CCLAMP
N
GND
D5
RAUX
PGND
RCS
CHF
Ordering Information/Selector Guide
TOP MARK
PIN-PACKAGE
TEMP RANGE
UVLO
THRESHOLD (V)
FEEDBACK MODE
MAX5974AETE+
+AHY
16 TQFN-EP*
-40°C to +105°C
16
Sample/Hold
MAX5974AATE+**
+AHY
16 TQFN-EP*
-40°C to +125°C
16
Sample/Hold
MAX5974BETE+
+AHZ
16 TQFN-EP*
-40°C to +85°C
8.4
Sample/Hold
MAX5974BATE+
+AHZ
16 TQFN-EP*
-40°C to +125°C
8.4
Sample/Hold
MAX5974CETE+
+AIA
16 TQFN-EP*
-40°C to +85°C
16
Continuously Connected
MAX5974CATE+
+AIA
16 TQFN-EP*
-40°C to +125°C
16
Continuously Connected
MAX5974DETE+
+AIB
16 TQFN-EP*
-40°C to +85°C
8.4
Continuously Connected
MAX5974DATE+
+AIB
16 TQFN-EP*
-40°C to +125°C
8.4
Continuously Connected
PART
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
Chip Information
PROCESS: BiCMOS
www.maximintegrated.com
Maxim Integrated │ 27
MAX5974A/MAX5974B/
MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Revision History
REVISION
NUMBER
REVISION
DATE
0
6/10
Initial release
1
9/10
Introduced the MAX5974B/MAX5974D. Updated the Absolute Maximum
Ratings, Electrical Characteristics, Pin Description, the p-Channel MOSFET
Gate Driver, Frequency Foldback for High-Efficiency Light-Load Operation
sections, and Typical Application Circuits.
2
6/11
Added internal zener diode information
3
10/13
Updated COMP function in Pin Description, corrected pin name in UVLO
on Power Source section, corrected Figures 1 and 2, corrected Typical
Application Circuits
11, 16, 24–26
4
10/14
Added MAX5974DATE+ option to Ordering Information, Electrical
Characteristics, and updated Typical Application Circuits
1, 2–5, 25–27
5
7/15
Removed EN from 2nd line in Absolute Maximum Ratings and changed the
1st line under Maximum Input/Output Current (continuous) from IN, NDRV,
AUXDRV to EN
6
7/17
Updated Absolute Maximum Ratings section, Electrical Characteristics table,
and Ordering Information table.
2–6, 27
7
12/17
Updated Absolute Maximum Ratings section, Electrical Characteristics table
global characteristics, Startup Time Considerations section, and Ordering
Information table.
2–6, 22, 27
—
11/20
1, 2, 3, 12, 15, 17,
19, 21, 23, 24, 25
1–10, 12–17, 19–25
Added future product designation to MAX5974AATE+in the Ordering
Information table.
7.1
8
PAGES
CHANGED
DESCRIPTION
Updated General Description, Electrical Characteristics table, and Ordering
Information/Selector Guide table.
2
27
1, 3–6, 27
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2020 Maxim Integrated Products, Inc. │ 28
