19-5545; Rev 0; 9/10
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
The MAX5975_ current-mode PWM controllers contain
all the control circuitry required for the design of wideinput-voltage forward and flyback power supplies in
Power-over-Ethernet (PoE) IEEE® 802.3af/at powered
devices. The MAX5975A is well-suited for universal input
(rectified 85V AC to 265V AC) or telecom (-36V DC to
-72V DC) power supplies. The MAX5975B is available for
low-voltage supplies (12V to 24V) such as wall adapters.
The devices are suitable for both isolated and nonisolated designs. Because the devices have an internal error
amplifier with a 1% accurate reference, they can be used
in nonisolated power supplies without the need for an
external shunt regulator.
An enable input (EN) is used to shut down the devices.
Programmable soft-start eliminates output voltage overshoot. The MAX5975A has an internal bootstrap UVLO
with large hysteresis that requires 20V for startup, while
the MAX5975B requires 10V for startup.
The switching frequency for the ICs is programmable
from 100kHz to 600kHz with an external resistor. For
EMI-sensitive design, use the programmable frequency
dithering feature for low-EMI spread-spectrum operation. The duty cycle is also programmable up to the 80%
maximum duty-cycle limit. These devices are available in
16-lead TQFN packages and are rated for operation over
the -40°C to +85°C temperature range.
Features
S Peak Current-Mode Control, Forward/Flyback
PWM Controllers
S Internal 1% Error Amplifier
S 100kHz to 600kHz Programmable ±8% Switching
Frequency
S Switching Frequency Synchronization Up to
1.2MHz
S Programmable Frequency Dithering for Low-EMI
Spread-Spectrum Operation
S PWM Soft-Start, Current Slope Compensation
S Programmable Feed-Forward Maximum DutyCycle Clamp, 80% Maximum Limit
S Frequency Foldback for High-Efficiency LightLoad Operation
S Internal Bootstrap UVLO with Large Hysteresis
S 100µA (typ) Startup Supply Current
S Fast Cycle-by-Cycle Peak Current-Limit, 35ns
Typical Propagation Delay
S 115ns Current-Sense Internal Leading-Edge
Blanking
S Output Short-Circuit Protection with Hiccup Mode
S 3mm x 3mm, Lead-Free, 16-Pin TQFN
Applications
PoE IEEE 802.3af/at Powered Devices
Flyback/Forward DC-DC Converters
IP Phones
Wireless Access Nodes
Security Cameras
Power Devices in PoE/Power-over-MDI
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK
UVLO THRESHOLD (V)
MAX5975AETE+
-40°C to +85°C
16 TQFN-EP*
+AIC
20
MAX5975BETE+
-40°C to +85°C
16 TQFN-EP*
+AID
10
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX5975A/MAX5975B
General Description
MAX5975A/MAX5975B
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70NC) (Note 1)
16-Pin TQFN (derate 20.8mW/NC above +70NC)........1666mW
Junction-to-Case Thermal Resistance (BJC) (Note 1)
16-Pin TQFN................................................................. +7NC/W
Junction-to-Ambient Thermal Resistance (BJA) (Note 1)
16-Pin TQFN............................................................... +48NC/W
Operating Temperature Range........................... -40NC to +85NC
Maximum Junction Temperature......................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
IN to GND...............................................................-0.3V to +26V
EN, NDRV to GND.......................................-0.3V to (VIN + 0.3V)
RT, FFB, COMP, SS, DCLMP, DITHER/SYNC
to GND..................................................................-0.3V to +6V
FB to GND................................................................-0.3V to +6V
CS, CSSC to GND....................................................-0.8V to +6V
PGND to GND.......................................................-0.3V to +0.3V
Maximum Input/Output Current (continuous)
NDRV.............................................................................100mA
NDRV (pulsed for less than 100ns)................................... Q1A
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 12V (for MAX5975A, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN =
+2V, NDRV = SS = COMP = unconnected, RRT = 34.8kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values
are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX5975A
19.1
19.8
20.4
MAX5975B
9.4
9.8
10.25
6.65
7
7.35
V
UNDERVOLTAGE LOCKOUT/STARTUP (IN)
Bootstrap UVLO Wakeup Level
VINUVR
VIN rising
Bootstrap UVLO Shutdown
Level
VINUVF
VIN falling
IN Supply Current in
Undervoltage Lockout
ISTART
VIN = +18V (for MAX5975A);
VIN = +9V (for MAX597BA),
when in bootstrap UVLO
100
150
FA
IC
VIN = +12V
1.8
3
mA
VENR
VEN rising
1.17
1.215
1.26
VENF
VEN falling
1.09
1.14
1.19
IN Supply Current After Startup
V
ENABLE (EN)
Enable Threshold
Input Current
IEN
1
V
FA
OSCILLATOR (RT)
RT Bias Voltage
VRT
NDRV Switching Frequency
Range
fSW
1.23
NDRV Switching Frequency
Accuracy
Maximum Duty Cycle
2
DMAX
fSW = 250kHz
V
100
600
kHz
-8
+8
%
84
%
81
82.5
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
(VIN = 12V (for MAX5975A, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN =
+2V, NDRV = SS = COMP = unconnected, RRT = 34.8kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values
are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYNCHRONIZATION (SYNC)
Synchronization Logic-High
Input
VIH-SYNC
2.91
fSYNCIN
1.1 x
fSW
Synchronization Pulse Width
Synchronization Frequency
Range
V
50
Maximum Duty Cycle During
Synchronization
ns
2x
fSW
DMAX x fSYNC/
fSW
kHz
%
DITHERING RAMP GENERATOR (DITHER)
Charging Current
VDITHER = 0V
45
50
55
FA
Discharging Current
VDITHER = 2.2V
43
50
57
FA
Ramp’s High Trip Point
2
V
Ramp’s Low Trip Point
0.4
V
SOFT-START AND RESTART (SS)
Charging Current
ISS-D
Discharging Current
Discharge Threshold to Disable
Hiccup and Restart
Minimum Restart Time During
Hiccup Mode
Normal Operating High Voltage
Duty-Cycle Control Range
9.5
10
10.5
FA
VSS = 2V, normal shutdown
0.65
1.34
2
mA
(VEN < VENF or VIN < VINUVF),
VSS = 2V, hiccup mode discharge for
tRESTART (Note 3)
1.6
2
2.4
FA
ISS-CH
ISS-DH
VSS-DTH
0.15
V
tRSTRT-MIN
1024
Clock
Cycles
VSS-HI
VSS-DMAX
5
DMAX (typ) = (VSS-DMAX/2.43V)
0
V
2
V
nA
DUTY-CYCLE CLAMP (DCLMP)
DCLMP Input Current
Duty-Cycle Control Range
IDCLMP
VDCLMP = 0 to 5V
VDCLMP-R
DMAX (typ) =
1 - (VDCLMP/2.43V)
-100
0
+100
VDCLMP = 0.5V
75
77.3
79.5
VDCLMP = 1V
56
58
60
VDCLMP = 2V
17
18.6
20.5
%
NDRV DRIVER
Pulldown Impedance
RNDRV-N
INDRV (sinking) = 100mA
1.9
3.4
I
Pullup Impedance
RNDRV-P
INDRV (sourcing) = 50mA
4.7
8.3
I
Peak Sink Current
1
Peak Source Current
A
0.65
A
Fall Time
tNDRV-F
CNDRV = 1nF
14
ns
Rise Time
tNDRV-R
CNDRV = 1nF
27
ns
3
MAX5975A/MAX5975B
ELECTRICAL CHARACTERISTICS (continued)
MAX5975A/MAX5975B
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V (for MAX5975A, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN =
+2V, NDRV = SS = COMP = unconnected, RRT = 34.8kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values
are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
375
393
410
mV
CURRENT-LIMIT COMPARATORS (CS)
Cycle-by-Cycle Peak
Current-Limit Threshold
VCS-PEAK
Number of Consecutive Peak
Current-Limit Events to Hiccup
NHICCUP
Current-Sense Leading-Edge
Blanking Time
tCS-BLANK
Propagation Delay from
Comparator Input to NDRV
Minimum On-Time
tPDCS
8
Events
From NDRV rising edge
115
ns
From CS rising (10mV overdrive) to
NDRV falling (excluding leading-edge
blanking)
35
ns
tON-MIN
100
150
200
ns
47
52
58
FA
SLOPE COMPENSATION (CSSC)
Slope Compensation Current
Ramp Height
Current ramp’s peak added to CSSC
input per switching cycle
PWM COMPARATOR
Comparator Offset Voltage
VPWM-OS
VCOMP - VCSSC
1.35
1.7
2
V
Current-Sense Gain
ACS-PWM
DVCOMP/DVCSSC (Note 4)
3.1
3.33
3.6
V/V
Current-Sense Leading-Edge
Blanking Time
tCSSC-BLANK
From NDRV rising edge
115
ns
tPWM
Change in VCSSC = 10mV (including
internal leading-edge blanking)
150
ns
FB Reference Voltage
VREF
VFB when ICOMP = 0, VCOMP = 2.5V
1.202
FB Input Bias Current
IFB
VFB = 0 to 1.75V
-500
Comparator Propagation Delay
ERROR AMPLIFIER
Voltage Gain
gM
Transconductance Bandwidth
BW
1.227
V
+100
nA
3.5
mS
80
AEAMP
Transconductance
1.215
1.8
Open loop (typical gain = 1) -3dB
frequency
2.66
dB
30
MHz
Source Current
VFB = 1V, VCOMP = 2.5V
300
375
455
FA
Sink Current
VFB = 1.75V, VCOMP = 1V
300
375
455
FA
FREQUENCY FOLDBACK (FFB)
VCSAVG-to-FFB Comparator
Gain
FFB Bias Current
NDRV Switching Frequency
During Foldback
IFFB
fSW-FB
10
VFFB = 0V, VCS = 0V (not in FFB mode)
26
30
V/V
33
fSW/2
Note 2: The devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design.
Note 3: See the Output Short-Circuit Protection with Hiccup Mode section.
Note 4: The parameter is measured at the trip point of latch with VFB = 0V. Gain is defined as DVCOMP/DVCSSC for 0.15V <
DVCSSC < 0.25V.
4
FA
kHz
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
19.9
19.8
19.7
19.6
9.9
9.8
9.7
9.5
-15
10
35
60
85
7.2
7.1
7.0
6.9
6.8
-15
-40
10
35
60
85
-40
-15
10
TEMPERATURE (°C)
EN RISING THRESHOLD
vs. TEMPERATURE
EN FALLING THRESHOLD
vs. TEMPERATURE
UVLO SHUTDOWN CURRENT
vs. TEMPERATURE
1.214
1.148
1.147
1.146
1.145
1.144
120
MAX5975A
100
80
MAX5975B
1.143
1.142
1.210
-15
10
35
60
60
-15
-40
85
10
35
60
85
-40
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5975A)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5975B)
SUPPLY CURRENT
vs. SWITCHING FREQUENCY
100
1000
TA = -40°C
100
2
4
6
8 10 12 14 16 18 20 22
SUPPLY VOLTAGE (V)
1.6
1.2
0.8
0
10
0
2.0
0.4
TA = -40°C
10
2.4
85
MAX5975A/B toc09
MAX5975A/B toc08
TA = +85°C
SUPPLY CURRENT (mA)
1000
10,000
SUPPLY CURRENT (µA)
TA = +85°C
MAX5975A/B toc07
TEMPERATURE (°C)
10,000
85
MAX5974A/B/C/D toc06
1.149
140
UVLO SHUTDOWN CURRENT (µA)
1.216
1.150
MAX5975A/B toc05
MAX5975A/B toc04
1.218
1.212
SUPPLY CURRENT (µA)
60
TEMPERATURE (°C)
1.220
-40
35
TEMPERATURE (°C)
EN FALLING THRESHOLD (V)
-40
MAX5975A/B toc03
10.0
7.3
9.6
19.5
EN RISING THRESHOLD (V)
MAX5975B
IN UVLO SHUTDOWN LEVEL
20.0
10.1
IN UVLO SHUTDOWN LEVEL
vs. TEMPERATURE
MAX5975A/B toc02
MAX5975A
IN UVLO WAKE-UP LEVEL (V)
IN UVLO WAKE-UP LEVEL (V)
20.1
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
MAX5975A/B toc01
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
0
2
4
6
8 10 12 14 16 18 20 22
SUPPLY VOLTAGE (V)
0
100 200 300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
5
MAX5975A/MAX5975B
Typical Operating Characteristics
(VIN = 12V (for MAX5975A, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN =
+2V, NDRV = SS = COMP = unconnected, RRT = 34.8kI, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5975A, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN =
+2V, NDRV = SS = COMP = unconnected, RRT = 34.8kI, unless otherwise noted.)
SWITCHING FREQUENCY
vs. RRT VALUE
10.03
10.02
10.01
10.00
9.99
100
251
250
249
248
247
246
245
9.98
10
9.97
-15
10
35
60
10
85
35
60
FREQUENCY DITHERING
vs. RDITHER
MAXIMUM DUTY CYCLE
vs. SWITCHING FREQUENCY
MAXIMUM DUTY CYCLE
vs. TEMPERATURE
6
4
2
83.6
83.4
83.2
83.0
82.8
82.6
82.4
500
600
700
800
900
0
RDITHER (kΩ)
82.6
82.5
82.4
82.3
82.2
-40
-15
SWITCHING FREQUENCY (kHz)
35
60
30
25
20
15
10
5
MAX5975A/B toc17
35
100
90
MAXIMUM DUTY CYCLE (%)
VSS = 0.5V
10
TEMPERATURE (°C)
MAXIMUM DUTY CYCLE
vs. VSS
MAX5975A/B toc16
40
82.7
100 200 300 400 500 600 700 800
MAXIMUM DUTY CYCLE
vs. SYNC FREQUENCY
45
82.8
82.0
82.0
1000
82.9
82.1
82.2
0
83.0
80
70
60
50
40
30
20
10
0
0
250
300
350
400
SYNC FREQUENCY (kHz)
450
85
MAX5975A/B toc15
83.8
MAXIMUM DUTY CYCLE (%)
8
84.0
MAX5975A/B toc14
MAX5975A/B toc13
10
MAXIMUM DUTY CYCLE (%)
10
TEMPERATURE (°C)
12
400
-15
-40
RRT VALUE (kΩ)
14
300
244
100
TEMPERATURE (°C)
MAXIMUM DUTY CYCLE (%)
-40
6
252
MAX5975A/B toc12
10.04
MAX5975A/B toc11
10.05
1000
SWITCHING FREQUENCY (kHz)
MAX5975A/B toc10
SOFT-START CHARGING CURRENT (µA)
10.06
SWITCHING FREQUENCY
vs. TEMPERATURE
SWITCHING FREQUENCY (kHz)
SOFT-START CHARGING CURRENT
vs. TEMPERATURE
FREQUENCY DITHERING (%)
MAX5975A/MAX5975B
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
500
0
0.5
1.0
1.5
VSS (V)
2.0
2.5
85
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
MAXIMUM DUTY CYCLE
vs. VDCLMP
60
50
40
30
20
10
0
0.5
1.0
1.5
2.0
395
394
393
392
391
390
389
53.5
53.0
52.5
52.0
51.5
51.0
50.5
50.0
-40
-15
10
35
60
85
-40
-15
10
35
60
VDCLMP (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
NDRV MINIMUM ON-TIME
vs. TEMPERATURE
CURRENT-SENSE GAIN
vs. TEMPERATURE
FEEDBACK VOLTAGE
vs. TEMPERATURE
155
150
145
3.38
3.37
3.36
3.35
3.34
3.33
10
35
60
10
35
60
1.213
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TRANSCONDUCTANCE HISTOGRAM
25
MAX5975A/B toc24
20
2.7
2.6
N (%)
TRANSCONDUCTANCE (mS)
1.214
1.210
-15
TRANSCONDUCTANCE
vs. TEMPERATURE
2.8
1.215
1.211
TEMPERATURE (°C)
2.9
1.216
1.212
TEMPERATURE (°C)
3.0
1.217
3.31
-40
85
1.218
MAX5975A/B toc25
-15
1.219
3.32
3.30
140
1.220
85
MAX5975A/B toc23
3.39
FEEDBACK VOLTAGE (V)
160
3.40
CURRENT-SENSE GAIN (V/V)
MAX5975A/B toc21
165
-40
MAX5975A/B toc20
396
54.0
388
2.5
170
NDRV MINIMUM ON-TIME (ns)
397
SLOPE COMPENSATION CURRENT (mA)
70
MAX5975A/B toc19
80
398
MAX5975A/B toc22
MAXIMUM DUTY CYCLE (%)
90
PEAK CURRENT-LIMIT THRESHOLD (mV)
MAX5975A/B toc18
100
0
SLOPE COMPENSATION CURRENT
vs. TEMPERATURE
PEAK CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
2.5
2.4
15
10
2.3
2.2
5
2.1
2.0
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
2.56 2.58 2.60 2.62 2.64 2.66 2.68 2.70 2.72 2.74 2.76
TRANSCONDUCTANCE (mS)
7
MAX5975A/MAX5975B
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5975A, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN =
+2V, NDRV = SS = COMP = unconnected, RRT = 34.8kI, unless otherwise noted.)
MAX5975A/MAX5975B
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5975A, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN =
+2V, NDRV = SS = COMP = unconnected, RRT = 34.8kI, unless otherwise noted.)
ENABLE RESPONSE
SHUTDOWN RESPONSE
MAX5975A/B toc26
SHUTDOWN RESPONSE
MAX5975A/B toc27
VEN
2V/V
MAX5975A/B toc28
VEN
2V/V
VEN
2V/ V
VNDRV
10V/div
VNDRV
10V/div
VNDRV
10V/div
VSS
5V/div
10ms/div
10µs/div
VSS RAMP RESPONSE
1ms/div
VDCLMP RAMP RESPONSE
MAX5975A/B toc29
VSS
5V/div
NDRV 10% TO 90% RISE TIME
MAX5975A/B toc30
VSS
2V/div
MAX5975A/B toc31
VDCLMP
2V/div
27.6ns
VNDRV
2V/div
VNDRV
10V/div
VNDRV
10V/div
0ns
10µs/div
10µs/div
NDRV 90% TO 10% FALL TIME
10ns/div
PEAK NDRV CURRENT
MAX5975A/B toc32
SHORT-CIRCUIT BEHAVIOR
MAX5975A/B toc33
MAX5975A/B toc34
PEAK SOURCE CURRENT
VIN
0ns
VNDRV
2V/div
INDRV
0.5A/div
VNDRV
ILX
13.8ns
PEAK SINK CURRENT
10ns/div
8
200ns/div
40ms/div
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
N.C.
NDRV
PGND
CS
TOP VIEW
12
11
10
9
IN 13
EN 14
MAX5975A
MAX5975B
DCLMP 15
EP
1
2
3
4
DITHER/
SYNC
RT
FFB
+
N.C.
SS 16
8
CSSC
7
GND
6
FB
5
COMP
TQFN
Pin Description
PIN
NAME
1, 12
N.C.
FUNCTION
2
DITHER/
SYNC
Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency
operation, connect a capacitor from DITHER to GND, and a resistor from DITHER to RT. To
synchronize the internal oscillator to the externally applied frequency, connect DITHER/SYNC to
the synchronization pulse.
3
RT
Switching Frequency Programming Resistor Connection. Connect resistor RRT from RT to GND to
set the PWM switching frequency. See the Oscillator/Switching Frequency section to calculate the
resistor value for the desired oscillator frequency.
4
FFB
Frequency Foldback Threshold Programming Input. Connect a resistor from FFB to GND to set the
output average current threshold below which the converter folds back the switching frequency to
1/2 of its original value. Connect to GND to disable frequency foldback.
5
COMP
Transconductance Amplifier Output and PWM Comparator Input. COMP is level shifted down and
connected to the inverting input of the PWM comparator.
No Connection. Not internally connected.
9
MAX5975A/MAX5975B
Pin Configuration
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
MAX5975A/MAX5975B
Pin Description (continued)
PIN
10
NAME
FUNCTION
6
FB
7
GND
Transconductance Amplifier Inverting Input
Signal Ground
8
CSSC
Current Sense with Slope Compensation Input. A resistor connected from CSSC to CS programs
the amount of slope compensation. See the Programmable Slope Compensation section.
9
CS
10
PGND
Power Ground. PGND is the return path for gate-driver switching currents.
11
NDRV
External Switching nMOS Gate-Driver Output
Current-Sense Input. Current-sense connection for average current sense and cycle-by-cycle
current limit. Peak current-limit trip voltage is 400mV.
13
IN
Converter Supply Input. IN has wide UVLO hysteresis, enabling the design of efficient power
supplies. When the enable input EN is used to program a UVLO level for the power source,
connect a zener diode between IN and PGND to ensure that VIN is always clamped below its
absolute maximum rating of 26V.
14
EN
Enable Input. The gate drivers are disabled and the device is in a low-power UVLO mode, when
the voltage on EN is below VENF. When the voltage on EN is above VENR, the device checks for
other enable conditions. See the Enable Input section for more information about interfacing to EN.
15
DCLMP
Feed-Forward Maximum Duty-Cycle Clamp Programming Input. Connect a resistor-divider
between the input supply voltage DCLMP and GND. The voltage at DCLMP sets the maximum
duty cycle (DMAX) of the converter inversely proportional to the input supply voltage, so that the
MOSFET remains protected during line transients.
16
SS
Soft-Start Programming Capacitor Connection. Connect a capacitor from SS to GND to program
the soft-start period. This capacitor also determines hiccup mode current-limit restart time. A
resistor from SS to GND can also be used to set the DMAX below 75%.
—
EP
Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance. Not intended as an electrical connection point.
1
3
N.C.
RT
SYNC
PGND
DRIVER
1A/-0.65A
OSCILLATOR
4
2
7
10
FFB
DITHER/
SYNC
GND
PGND
VB
VB
-50µA
50µA/
90µA
30µA/
15 20% < DMAX < 80%
12
N.C.
DCLMP
11
NDRV
VC
FFB COMP
SS
2V/400mV
CSAVG
10x
POK
DRIVER LOGIC
NDRV
BLANKING
PULSE
VB
POK
SS < 150mV
R
S
5V
REGULATOR
MAX5975A
MAX5975B
QCLR
QSET
ENABLE
COUNT 8
EVENTS
R1
THERMAL
SHUTDOWN
PWM
COMP
PEAK ILIM
COMP
1.23V
2 x R1
UVLO
VB
115ns
BLANKING
400mV
115ns
BLANKING
2µA
gm
VB
1.215V
SLOPE
COMPENSATION
2mA
10µA
LOW-POWER UVLO
VINUVR = 20V (MAX5975A)
VINUVR = 10V (MAX5975B)
VINUVF = 7V
VB
POK
VB
14 EN
13 IN
6 FB
5 COMP
8 CSSC
9 CS
16 SS
Block Diagram
11
MAX5975A/MAX5975B
HICCUP
LATCH
REVERSE ILIM COMP
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
MAX5975A/MAX5975B
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Detailed Description
The MAX5975_ is optimized for controlling a 25W to
50W forward/flyback converter in continuous-conduction
mode. The power MOSFET gate driver (NDRV) is sized
to optimize efficiency for 25W design. The feature-rich
devices are ideal for PoE IEEE 802.3af/at-powered
devices.
The MAX5975A offers a bootstrap UVLO wakeup level of
20V with a wide hysteresis of 13V. The low startup and
operating currents allow the use of a smaller storage
capacitor at the input without compromising startup and
hold times. The device is well-suited for universal input
(rectified 85V AC to 265V AC) or telecom (-36V DC to
-72V DC) power supplies.
The MAX5975B has a UVLO rising threshold of 10V and
is well-suited for low-input voltage (12V DC to 24V DC)
power sources such as wall adapters.
Power supplies designed with the MAX5975A use a
high-value startup resistor, RIN, that charges a reservoir
capacitor, CIN (see the Typical Applications Circuits).
During this initial period, while the voltage is less than
the internal bootstrap UVLO threshold, the device typically consumes only 100FA of quiescent current. This
low startup current and the large bootstrap UVLO hysteresis help to minimize the power dissipation across RIN
even at the high end of the universal AC input voltage
(265V AC).
Feed-forward maximum duty-cycle clamping detects
changes in line conditions and adjusts the maximum
duty cycle accordingly to eliminate the clamp voltage's
(i.e., the main power FET's drain voltage) dependence
on the input voltage.
For EMI-sensitive applications, the programmable frequency dithering feature allows up to Q10% variation in
the switching frequency. This spread-spectrum modulation technique spreads the energy of switching harmonics over a wider band while reducing their peaks, helping to meet stringent EMI goals.
The devices include a cycle-by-cycle current limit that
turns off the driver whenever the internally set threshold
of 400mV is exceeded. Eight consecutive occurrences
of current-limit event trigger hiccup mode, which protects external components by halting switching for a
period of time (tRSTRT) and allowing the overload current
to dissipate in the load and body diode of the synchronous rectifier before soft-start is reattempted.
12
Current-Mode Control Loop
The advantages of current-mode control over voltagemode control are twofold. First, there is the feed-forward
characteristic brought on by the controller’s ability to adjust
for variations in the input voltage on a cycle-by-cycle basis.
Secondly, the stability requirements of the current-mode
controller are reduced to that of a single-pole system,
unlike the double pole in voltage-mode control.
The devices use a current-mode control loop where the
scaled output of the error amplifier (COMP) is compared
to a slope-compensated current-sense signal at CSSC.
Enable Input
The enable input EN is used to enable or disable the
device. Connect EN to IN for always enabled applications. Connecting EN to ground disables the device and
reduces current consumption to 100FA.
The enable input has an accurate threshold of 1.26V
(max). For applications that require a UVLO on the
power source, connect a resistive divider from the power
source to EN to GND as shown in Figure 1. A zener
diode between IN and PGND is required to prevent
IN from exceeding its absolute maximum rating of 26V
when the device is disabled. The zener diode should
be inactive below the maximum UVLO rising threshold
voltage VINUVR(MAX) (21V for the MAX5975A and 10.5V
for the MAX5975B). Design the resistive divider by first
selecting the value of REN1 to be on the order of 100kI.
Then calculate REN2 as follows:
R EN2 = REN1
VEN(MAX)
VS(UVLO) − VEN(MAX)
where VEN(MAX) is the maximum enable threshold voltage and is equal to 1.26V and VS(UVLO) is the desired
UVLO threshold for the power source, below which the
devices are disabled.
In the case where EN is externally controlled and UVLO for
the power source is unnecessary, connect EN to IN and an
open-drain or open-collector output as shown in Figure 2.
The digital output connected to EN should be capable of
withstanding IN’s absolute maximum voltage of 26V.
Bootstrap Undervoltage Lockout
The device has an internal bootstrap UVLO that is very
useful when designing high-voltage power supplies (see
the Block Diagram). This allows the device to bootstrap
itself during initial power-up. The MAX5975A soft-starts
when VIN exceeds the bootstrap UVLO threshold of
VINUVR (20V typ).
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
VS
Startup Operation
The device starts up when the voltage at IN exceeds 20V
(MAX5975A) or 10V (MAX5975B) and the enable input
voltage is greater than 1.26V.
RIN
IN
CIN
MAX5975
REN1
DIGITAL
CONTROL
EN
REN2
N
Figure 1. Programmable UVLO for the Power Source
During normal operation, the voltage at IN is normally
derived from a tertiary winding of the transformer.
However, at startup there is no energy being delivered through the transformer; hence, a special bootstrap sequence is required. In the Typical Applications
Circuits, CIN charges through the startup resistor, RIN, to
an intermediate voltage. Only 100FA of the current supplied through RIN is used by the ICs, the remaining input
current charges CIN until VIN reaches the bootstrap
UVLO wakeup level. Once VIN exceeds this level, NDRV
begins switching the n-channel MOSFET and transfers
energy to the secondary and tertiary outputs. If the voltage on the tertiary output builds to higher than 7V (the
bootstrap UVLO shutdown level), then startup has been
accomplished and sustained operation commences.
If VIN drops below 7V before startup is complete, the
device goes back to low-current UVLO. In this case,
increase the value of CIN to store enough energy to allow
the voltage at the tertiary winding to build up.
VS
Soft-Start
A capacitor from SS to GND, CSS, programs the softstart time. VSS controls the oscillator duty cycle during
startup to provide a slow and smooth increase of the
duty cycle to its steady-state value. Calculate the value
of CSS as follows:
RIN
IN
CIN
MAX5975
DIGITAL
CONTROL
EN
N
I
×t
C SS = SS-CH SS
2V
where ISS-CH (10FA typ) is the current charging CSS during soft-start and tSS is the programmed soft-start time.
A resistor can also be added from the SS pin to GND to clamp
VSS < 2V and, hence, program the maximum duty cycle to be
less than 80% (see the Duty-Cycle Clamping section).
n-Channel MOSFET Gate Driver
Figure 2. External Control of the Enable Input
The NDRV output drives an external n-channel MOSFET.
NDRV can source/sink in excess of 650mA/1000mA peak
current; therefore, select a MOSFET that yields acceptable
conduction and switching losses. The external MOSFET
used must be able to withstand the maximum clamp voltage.
13
MAX5975A/MAX5975B
Because the MAX5975B is designed for use with lowvoltage power sources such as wall adapters outputting
12V to 24V, it has a lower UVLO wakeup threshold of 10V.
MAX5975A/MAX5975B
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Oscillator/Switching Frequency
The ICs’ switching frequency is programmable between
100kHz and 600kHz with a resistor RRT connected
between RT and GND. Use the following formula to
determine the appropriate value of RRT needed to generate the desired output-switching frequency (fSW):
R RT =
8.7 × 10 9
fSW
where fSW is the desired switching frequency.
Peak Current Limit
The current-sense resistor (RCS in the Typical
Application Circuits), connected between the source
of the n-channel MOSFET and PGND, sets the current
limit. The current-limit comparator has a voltage trip level
(VCS-PEAK) of 400mV. Use the following equation to calculate the value of RCS:
R CS =
400mV
IPRI
where IPRI is the peak current in the primary side of
the transformer, which also flows through the MOSFET.
When the voltage produced by this current (through the
current-sense resistor) exceeds the current-limit comparator threshold, the MOSFET driver (NDRV) terminates
the current on-cycle, within 35ns (typ).
VCSBL
(BLANKED CS
VOLTAGE)
The devices implement 115ns of leading-edge blanking
to ignore leading-edge current spikes. These spikes
are caused by reflected secondary currents, currentdischarging capacitance at the FET’s drain, and gatecharging current. Use a small RC network for additional
filtering of the leading-edge spike on the sense waveform when needed. Set the corner frequency between
10MHz and 20MHz.
After the leading-edge blanking time, the device monitors VCS for any breaches of the peak current limit of
400mV. The duty cycle is terminated immediately when
VCS exceeds 400mV.
Output Short-Circuit Protection
with Hiccup Mode
When the device detects eight consecutive peak currentlimit events, the driver output is turned off for a restart
period, tRSTRT. After tRSTRT, the device undergoes
soft-start. The duration of the restart period depends
on the value of the capacitor at SS (CSS). During this
period, CSS is discharged with a pulldown current of
ISS-DH (2FA typ). Once its voltage reaches 0.15V, the
restart period ends and the device initiates a soft-start
sequence. An internal counter ensures that the minimum
restart period (tRSTRT-MIN) is 1024 clock cycles when
the time required for CSS to discharge to 0.15V is less
than 1024 clock cycles. Figure 3 shows the behavior of
the device prior and during hiccup mode.
VCS-PEAK
(400mV)
HICCUP
DISCHARGE WITH ISS_DS
VSS_H
SOFT-START
VOLTAGE,
VSS
VSS_SD
tSS
Figure 3. Hiccup Mode Timing Diagram
14
tRSTRT
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
The frequency foldback threshold can be programmed
from 0 to 20% of the full load current using a resistor from
FFB to GND.
Figure 4 shows device operation in frequency foldback
mode. Calculate the value of RFFB as follows:
R FFB =
10 × ILOAD(LIGHT) × R CS
IFFB
where RFFB is the resistor connected to FFB, ILOAD(LIGHT)
is the current at light-load conditions that triggers frequency foldback, RCS is the value of the sense resistor
connected between CS and PGND, and IFFB is the current sourced from FFB to RFFB (30FA typ).
Duty-Cycle Clamping
The maximum duty cycle is determined by the lowest
of three voltages: 2V, the voltage at SS (VSS), and the
voltage (2.43V - VDCLMP). The maximum duty cycle is
calculated as:
V
D MAX = MIN
2.43V
where VMIN = minimum (2V, VSS, 2.43V - VDCLMP).
SS
By connecting a resistor between SS and ground, the
voltage at SS can be made to be lower than 2V. VSS is
calculated as follows:
VSS = R SS × I SS − CH
where RSS is the resistor connected between SS and
GND, and ISS-CH is the current sourced from SS to RSS
(10FA typ).
DCLMP
To set DMAX using supply voltage feed forward, connect
a resistive divider between the supply voltage, DCLMP,
and GND as shown in the Typical Applications Circuits.
This feed-forward duty-cycle clamp ensures that the
external n-channel MOSFET is not stressed during supply transients. VDCLMP is calculated as follows:
VDCLMP =
R DCLMP2
× VS
R DCLMP1 + R DCLMP2
where RDCLMP1 and RDCLMP2 are the resistive divider
values shown in the Typical Applications Circuits and VS
is the input supply voltage.
Oscillator Synchronization
The internal oscillator can be synchronized to an external clock by applying the clock to SYNC/DITHER directly. The external clock frequency can be set anywhere
between 1.1x to 2x the internal clock frequency.
Using an external clock increases the maximum duty
cycle by a factor equal to fSYNC/fSW. This factor should
be accounted for in setting the maximum duty cycle
using any of the methods described in the Duty-Cycle
Clamping section. The formula below shows how the
maximum duty cycle is affected by the external clock
frequency:
D MAX =
VMIN fSYNC
×
2.43V
fSW
VCSAVG
FFB
NDRV
tSW
tSW X 2
tSW X 2
COMP
Figure 4. Entering Frequency Foldback
15
MAX5975A/MAX5975B
Frequency Foldback for High-Efficiency
Light-Load Operation
MAX5975A/MAX5975B
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
where VMIN is described in the Duty-Cycle Clamping
section, fSW is the switching frequency as set by the
resistor connected between RT and GND, and fSYNC is
the external clock frequency.
Frequency Dithering for
Spread-Spectrum Applications (Low EMI)
The switching frequency of the converter can be dithered in a range of Q10% by connecting a capacitor from
SYNC/DITHER to GND, and a resistor from DITHER to
RT as shown in the Typical Applications Circuits. This
results in lower EMI.
A current source at SYNC/DITHER charges the capacitor CDITHER to 2V at 50FA. Upon reaching this trip point,
it discharges CDITHER to 0.4V at 50FA. The charging
and discharging of the capacitor generates a triangular
waveform on SYNC/DITHER with peak levels at 0.4V and
2V and a frequency that is equal to:
fTRI =
50µA
C DITHER × 3.2V
Typically, fTRI should be set close to 1kHz. The resistor
RDITHER connected from SYNC/DITHER to RT determines the amount of dither as follows:
R RT
4
%DITHER = ×
3 R DITHER
where %DITHER is the amount of dither expressed as a
percentage of the switching frequency. Setting RDITHER
to 10 x RRT generates Q10% dither.
Programmable Slope Compensation
The devices generate a current ramp at CSSC such
that its peak is 50FA at 80% duty cycle of the oscillator.
An external resistor connected from CSSC to CS then
converts this current ramp into programmable slopecompensation amplitude, which is added to the current-
16
sense signal for stability of the peak current-mode
control loop. The ramp rate of the slope compensation
signal is given by:
R
× 50µA × fSW
m = CSSC
80%
where m is the ramp rate of the slope-compensation
signal, RCSSC is the value of the resistor connected
between CSSC and CS used to program the ramp rate,
and fSW is the switching frequency.
Error Amplifier
The MAX5975A/MAX5975B include an internal error
amplifier. The noninverting input of the error amplifier is connected to the internal 1.215V reference and
feedback is provided at the inverting input. High 80dB
open-loop gain and 30MHz unity-gain bandwidth allow
good closed-loop bandwidth and transient response.
Calculate the power-supply output voltage using the following equation:
R
+ R FB2
VOUT = VREF × FB1
R FB2
where VREF = 1.215V.
Applications Information
Startup Time Considerations
The bypass capacitor at IN, CIN, supplies current
immediately after the devices wake up (see the Typical
Application Circuits). Large values of CIN increase
the startup time, but also supply gate charge for more
cycles during initial startup. If the value of CIN is too
small, VIN drops below 7V because NDRV does not have
enough time to switch and build up sufficient voltage
across the tertiary output, which powers the device. The
device goes back into UVLO and does not start. Use a
low-leakage capacitor for CIN.
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
I G = Q GTOT fSW
(I + I )(t )
CIN = IN G SS
VHYST
where IIN is the internal supply current (1.7mA) after
startup, QGTOT is the total gate charge for the n-channel
FET, fSW is the switching frequency, VHYST is the bootstrap UVLO hysteresis (13V typ), and tSS is the soft-start
time. RIN is then calculated as follows:
RIN ≅
VS(MIN) − VINUVR
I START
where VS(MIN) is the minimum input supply voltage for
the application (36V for telecom), VINUVR is the bootstrap UVLO wake-up level (20V), and ISTART is the IN
supply current at startup (150FA max).
Choose a higher value for RIN than the one calculated
above if longer startup time can be tolerated in order to
minimize power loss on this resistor.
MAX5975B
The parameters governing the design of the bootstrap
circuit are different for the MAX5975B. While the above
design equations remain valid, the following values must
be used when designing for RIN and CIN: VHYST = 3V and
VS(MIN) is the minimum output voltage of the wall adapter.
Bias Circuit
An in-phase tertiary winding is needed to power the bias
circuit. The voltage across the tertiary VT during the ontime is:
N
VT = VOUT × T
N
S
where VOUT is the output voltage and NT/NS is the turns
ratio from the tertiary to the secondary winding. Select the
turns ratio so that VT is above the UVLO shutdown level
(7.5V max).
Layout Recommendations
Typically, there are two sources of noise emission in a
switching power supply: high di/dt loops and high dV/dt
surfaces. For example, traces that carry the drain current
often form high di/dt loops. Similarly, the heatsink of the
main MOSFET presents a dV/dt source; therefore, minimize the surface area of the MOSFET heatsink as much
as possible. Keep all PCB traces carrying switching currents as short as possible to minimize current loops. Use
a ground plane for best results.
For universal AC input design, follow all applicable
safety regulations. Offline power supplies may require
UL, VDE, and other similar agency approvals.
17
MAX5975A/MAX5975B
MAX5975A
Typically, offline power supplies keep startup times to
less than 500ms even in low-line conditions (85V AC
input for universal offline or 36V DC for telecom applications). Size the startup resistor, RIN, to supply both the
maximum startup bias of the device (150FA) and the
charging current for CIN. CIN must be charged to 20V
within the desired 500ms time period. CIN must store
enough charge to deliver current to the device for at
least the soft-start time (tSS) set by CSS. To calculate the
approximate amount of capacitance required, use the
following formula:
MAX5975A/MAX5975B
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Typical Application Circuits
RIN
VS
D1
L1
NT
CIN
CBULK
D2
CCLAMP
RCLAMP
D3
T1
IN
NP
D5
COUT1
COUT2
COUT3
COUT4
RFB2
DT
RDITHER
RRT
DITHER/
SYNC
MAX5975
(FORWARD
CONFIGURATION)
NDRV
ROPTO1
RGATE3
N
RT
RFFB
U1
FFB
RQ2
CZ
N3
IN
CS
FB
RQ1
RFB1
SS
RDT
CDITHER
L2
NS
EN
CSS
D4
CSSC
COMP
RBIAS
RCSSC
RCS
CINT
CHF
ROPTO2
SGND
PGND
U2
18
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
RIN
VS
D1
L1
NT
CIN
CBULK
D2
CCLAMP
RCLAMP
D3
T1
IN
RFB1
NP
COUT1
EN
CSS
SS
RDT
CDITHER
COUT2
COUT3
COUT4
RFB2
NS
DT
RDITHER
RRT
DITHER/
SYNC
MAX5975
(FLYBACK
CONFIGURATION)
R
NDRV GATE3
RT
RFFB
ROPTO1
N
U1
FFB
RQ2
CZ
N3
IN
CS
FB
RQ1
D4
CSSC
COMP
RBIAS
RCSSC
RCS
CINT
CHF
ROPTO2
SGND
PGND
U2
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
No.
LAND
PATTERN No.
16 TQFN-EP
T1655+4
21-0136
90-0031
19
MAX5975A/MAX5975B
Typical Application Circuits (continued)
MAX5975A/MAX5975B
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/10
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
© 2010
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
工商网监
湘ICP备2023018690号
