EVALUATION KIT AVAILABLE
MAX5991A /MAX5991B
IEEE 02. af-Compliant High-Efficiency
Class 1 Class 2 Powered Devices
with Integrated DC-DC Converter
General Description
Benefits and Features
The MAX5991A/MAX5991B provide a complete powersupply solution as IEEE® 802.3af-compliant Class 1/
Class 2 Powered Devices (PDs) in a Power-over-Ethernet
(PoE) system. The devices integrate the PD interface with
an efficient DC-DC converter, offering a low external part
count PD solution. The devices also include a low-dropout regulator, MPS, sleep, and ultra-low power modes.
● High Integration Saves Space and BOM Cost
• Efficient, Integrated DC-DC Converter (with
Integrated Switches)
• Built-In Output-Voltage Monitoring
• Protects Against Overload, Output Short Circuit,
Output Overvoltage, and Overtemperature
• Integrated TVS Diode Withstands Cable Discharge
Event (CDE)
• Internal LDO Regulator with Up to 100mA Load
The PD interface provides a detection signature and
a Class 1/Class 2 classification signature with a single
external resistor. The PD interface also provides an isolation power MOSFET, a 60mA (max) inrush current limit,
and a 321mA (typ) operating current limit.
The integrated step-down DC-DC converter uses a peak
current-mode control scheme and provides an easy-toimplement architecture with a fast transient response.
The step-down converter operates in a wide input voltage range from 8.7V to 60V and supports up to 6.49W of
input power at 1.3A load. The DC-DC converter operates
at a fixed 430kHz switching frequency, with an efficiencyboosting frequency foldback that reduces the switching
frequency by half at light loads.
The devices feature an input undervoltage-lockout
(UVLO) with wide hysteresis and long deglitch time
to compensate for twisted-pair cable resistive drop
and to assure glitch-free transition during power-on/-off
conditions. The devices also feature overtemperature
shutdown, short-circuit protection, output overvoltage protection, and hiccup current limit for enhanced
performance and reliability.
All devices are available in a 20-pin, 4mm x 4mm, TQFN
power package and operate over the -40°C to +85°C
temperature range.
Applications
●
●
●
●
●
IEEE 802.3af-Powered Devices
IP Phones
Wireless Access Nodes
IP Security Cameras
WiMAX® Base Stations
● IEEE 802.3af-Compliant Features Reduce Design Time
• PoE Class 1/Class 2 Classification Set with Single
Resistor
• Intelligent Maintain Power Signature (MPS)
Complies with IEEE 802.3af Specification
• Simplified Wall Adapter Interface
• Pass 2kV, 200m CAT-6 Cable Discharge Event
● High Efficiency During Light Loads Reduces Power
Consumption
• Sleep and Ultra-Low-Power Mode
• Frequency Foldback for High-Efficiency LightLoad Operation
• Back-Bias Capability to Optimize the Efficiency
● Robust Performance
• 8.7V to 60V Wide Input Voltage Range
• Hiccup-Mode Runaway Current Limit
• 49mA (typ) Inrush Current Limit
• Open-Drain RESET Output
● Easy to Design With
• 3.2V to 14V Programmable Output Voltage Range
• Internal Compensation
• Fixed 430kHz Switching Frequency
Ordering Information appears at end of data sheet.
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
WiMAX is a registered certification mark and registered service
mark of WiMAX Forum.
19-6529; Rev 2; 1/15
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Absolute Maximum Ratings
(All voltages referenced to GND, unless otherwise noted.)
VDD to GND...........................................................-0.3V to +70V
(100V, 100ms, RTEST = 3.3kω) (Note 1)
VCC, WAD, RREF to GND ........................ -0.3V to (VDD + 0.3V)
AUX, LDO_IN, LED to GND .................................... -0.3V to 16V
LDO_OUT to GND .............................. -0.3V to (LDO_IN + 0.3V)
LDO_FB to GND ......................................................-0.3V to +6V
LX to GND ................................................ -0.3V to (VCC + 0.3V)
LDO_OUT, VDRV, FB, RESET, WK,
SL, ULP, MPS, CLASS2 to GND .........................-0.3V to +6V
VDRV to VDD ............................................ -0.3V to (VDD + 0.3V)
PGND to GND ......................................................-0.3V to +0.3V
LX Total RMS Current ...........................................................1.6A
Continuous Power Dissipation (TA = + 70NC)
TQFN (derate 28.6mW/NC above +70NC)...............2285.7mW
Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Note 1: See Figure 1, Test Circuit.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 2)
Junction-to-Ambient Thermal Resistance (qJA) ..............35°C/W
Junction-to-Case Thermal Resistance (qJC) ..................2.7°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
8
FA
25.5
kI
V
POWER DEVICE (PD) INTERFACE
DETECTION MODE
Input Offset Current
Effective Differential Input
Resistance
IOFFSET
dR
VVDD = 1.4V to 10.1V (Note 4)
VVDD = 1.4V to 10.1V with 1V step,
(Note 5)
23.95
CLASSIFICATION MODE
Classification Enable Threshold
VTH,CLS,EN
VDD rising
10.2
11.42
12.5
Classification Disable Threshold
VTH,CLS,DIS
VDD rising
22
23
23.8
Classification Stability Time
Classification Current
2
ICLASS
VDD = 12.6V to
20V
V
ms
CLASS2 = GND
9.12
10.5
11.88
CLASS2 = VDRV
16.1
18
20.9
60
V
4.8
6.6
mA
40
V
mA
POWER MODE
VDD Supply Voltage Range
VDD
VDD Supply Current
IDD
VDD = 60V
VDD Turn-On Voltage
VON
VDD rising
37.2
38.7
VDD Turn-Off Voltage
VOFF
VDD falling
30
31.4
www.maximintegrated.com
V
Maxim Integrated │ 2
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Electrical Characteristics (continued)
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
VDD Turn-On/Off Hysteresis
VDD Deglitch Time
Inrush to Operating Mode Delay
Isolation Power MOSFET
On-Resistance
SYMBOL
VHYST_UVLO
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 6)
7.3
V
tOFF_DLY
VDD falling from 40V to 20V (Note 5)
150
Fs
tDELAY
tDELAY = time after (VDD - VCC) from
1.5V to 0V
115
ms
RON_ISO
IVCC = 100mA
TJ = +25NC
1.2
TJ = +85NC
1.5
I
MAINTAIN POWER SIGNATURE (MPS = VDRV)
PoE MPS Current Rising
Threshold
IMPS_RISE
18
28.7
40
mA
PoE MPS Current Falling
Threshold
IMPS_FALL
14
24
35
mA
PoE MPS Current Threshold
Hysteresis
IMPS_HYS
4.3
mA
PoE MPS Output Average
Current
IMPS_AVE
4.8
mA
PoE MPS Peak Output Current
IMPS_PEAK
12.6
mA
PoE MPS Time High
IMPS_HIGH
95
ms
PoE MPS Time Low
IMPS_LOW
190
ms
10
CURRENT LIMIT
Inrush Current Limit
Current Limit During Normal
Operation
IINRUSH
ILIM
During initial turn-on period,
VDD - VCC = 4V, measured at VCC
39
49
60
mA
After inrush completed,
VCC = VDD - 1.5V, measured at VCC
290
321
360
mA
8.8
V
LOGIC
WAD Detection Rising Threshold
VWAD_RISE
WAD Detection Falling
Threshold
VWAD_FALL
5.8
WAD Detection Hysteresis
WAD Input Current
IWAD
VWAD = 24V
CLASS2, MPS Voltage Rising
Threshold
RESET, CLASS2, MPS Leakage
www.maximintegrated.com
0.6
V
125
FA
2.9
CLASS2, MPS Voltage Falling
Threshold
RESET Output Voltage Low
V
0.4
ISINK = 1mA
-1
V
V
0.2
V
+1
FA
Maxim Integrated │ 3
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Electrical Characteristics (continued)
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL REGULATOR WITH BACK BIAS
VAUX Input Voltage Range
VAUX
VAUX Input Current
Inferred from VAUX input current
4.75
14
V
VAUX from 4.75V to 14V
0.65
3.1
mA
4.2
5.5
V
1.6
2.9
V
VDRV Output Voltage
SLEEP MODE
WK and ULP Logic Threshold
SL Logic Threshold
VWK falling and VULP rising and falling
Falling
SL Current
V SL = 0V
LED Current Amplitude
VTH
ILED
0.55
9.2
10.6
12
R SL = 30.2kI, VLED = 6.5V
19.2
21.2
23.5
mA
20
mA
31.4
mA
IRANGE
LED Current with Grounded SL
V SL = 0V
fILED
Sleep and ultra-low power modes
LED Current Duty Cycle
DILED
Sleep and ultra-low power modes
VDD Current Amplitude
IVDD
Sleep mode, VLED = 6.5V
Sleep and ultra-low power modes
DIVDD
21.2
10
LED Current Frequency
Internal Current Duty Cycle
V
FA
R SL = 60.4kI, VLED = 6.5V
R SL = 30.2kI, VLED = 3.5V
LED Current Programmable
Range
0.8
62
20.6
26
250
Hz
25
10
%
12
14.5
75
mA
%
Internal Current Enable Time
tMPS
Ultra-low power mode
76
88
98
ms
Internal Current Disable Time
tMPDO
Ultra-low power mode
205
237
265
ms
THERMAL SHUTDOWN
Thermal Shutdown Threshold
TSD
Thermal Shutdown Hysteresis
TSD,HYS
TJ rising
151
NC
16
NC
LDO
Input Voltage Range
Inferred from line regulation
Output Voltage
LDO_FB = VDRV
Max Output Voltage Setting
With external divider to LDO_FB
LDO Quiescent Current
VLDO_IN = 4.5V
LDO FB Regulation Voltage
4.5
3.3
4
V
FA
1.227
-1
V
V
5.5
1.20
LDO FB Leakage Current
14
1.25
V
+1
FA
Dropout
VLDO_IN = 5V, VLDO_FB = VDRV,
ILOAD = 80mA
265
mV
Load Regulation
ILOAD from 1mA to 80mA
0.5
mV/mA
Line Regulation
VLDO_IN from 4.5V to 14V
1.4
mV/V
Overcurrent Limit
www.maximintegrated.com
85
mA
Maxim Integrated │ 4
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Electrical Characteristics (continued)
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
TYP
MAX
UNITS
LDO_FB Rising Threshold
PARAMETER
SYMBOL
CONDITIONS
MIN
3.3
3.7
V
LDO_FB Hysteresis
2.4
V
DC-DC CONVERTER INPUT SUPPLY
VDD Voltage Range
WAD Detection Rising Threshold
WAD Detection Falling
Threshold
WAD Detection Hysteresis
VDD,RISING
VCC = VDD = VWAD - 0.3V, rising
8
60
VDD,FALLING
VCC = VDD = VWAD - 0.3V, falling
7.7
60
VWAD,RISE
(Note 7)
VWAD,FALL
(Note 7)
8.8
5.8
V
V
V
0.6
V
POWER MOSFETs
High-Side pMOS On-Resistance
RDSON-H
ILX = 0.5A (sourcing)
0.54
I
Low-Side nMOS On-Resistance
RDSON-L
ILX = 0.5A (sinking)
0.14
I
LX Leakage Current
ILX-LKG
VDD = VCC = 28V,
VLX = (VPGND + 1V) to (VCC - 1V)
-5
+5
FA
SOFT-START (SS)
Soft-Start Time
tSS-TH
10
ms
FEEDBACK (FB)
FB Regulation Voltage
VFB-RG
FB Input Bias Current
IFB
1.203
VFB = 1.224V
1.226
1.252
V
10
200
nA
OUTPUT VOLTAGE
Output Voltage Range
Cycle by Cycle Overvoltage
Protection
VOUT
VOUT-OV
MAX5991A
3.0
5.6
MAX5991B
5.4
14
Rising (Note 8)
101
108
Falling (Note 8)
98.5
104
V
%
INTERNAL COMPENSATION NETWORK
Compensation Network ZeroResistance
RZERO
200
kI
Compensation Network ZeroCapacitance
CZERO
150
pF
CURRENT LIMIT
MAX5991A
Peak Current-Limit Threshold
IPEAK-LIMIT
MAX5991B
www.maximintegrated.com
CLASS2 = GND
1.45
1.64
CLASS2 = VDRV
1.66
1.79
CLASS2 = GND
0.75
0.81
CLASS2 = VDRV
0.85
0.94
A
Maxim Integrated │ 5
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Electrical Characteristics (continued)
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
Runaway Current-Limit
Threshold
Valley Current-Limit Threshold
ZX Threshold
SYMBOL
IRUNAWAYLIMIT
CONDITIONS
MAX5991A
MAX5991B
MIN
CLASS2 = GND
TYP
MAX
UNITS
1.9
CLASS2 = VDRV
2.1
CLASS2 = GND
0.93
CLASS2 = VDRV
1.07
IVALLEY-
MAX5991A
1.45
LIMIT
MAX5991B
0.75
IZX
A
A
25
mA
TIMINGS
Switching Frequency
fSW
380
430
475
kHz
Frequency Foldback
fSW-FOLD
195
215
238
kHz
Consecutive ZX Events for
Entering Foldback
8
Events
Consecutive ZX Events for
Exiting Foldback
8
Events
VOUT Undervoltage Trip Level to
Cause HICCUP
VOUT-HICF
After soft-start completed (Note 8)
55
HICCUP Timeout
Minimum On-Time
60
65
77
tON-MIN
113
LX Dead Time
%
ms
140
14
ns
ns
RESET
VFB Threshold for RESET
Assertion
VFB-OKF
VFB falling (Note 8)
87
90
93
%
VFB Threshold for RESET
Deassertion
VFB-OKR
VFB rising (Note 8)
91.5
95
98
%
VLDO_FB Threshold for RESET
Assertion
VFB Threshold for RESET
Deassertion
RESET Deassertion Delay
VLDO_FB-OKF
VLDO_FB falling, LDO_FB = VDRV
(Note 9)
90
%
VFB rising
95
%
2.4
ms
All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
The input offset current is illustrated in Figure 2.
Effective differential input resistance is defined as the differential resistance between VDD and GND, see Figure 2.
A 20V glitch on input voltage, which takes VDD below VON shorter than or equal to tOFF_DLY does not cause the device to
exit power-on mode.
Note 7: The WAD detection rising and falling thresholds control the isolation power MOS transistor. To turn the DC-DC on in WAD
mode, the WAD must be detected and the VDD must be within the VDD voltage range.
Note 8: Referred to feedback regulation voltage.
Note 9: Referred to LDO feedback regulation voltage.
Note
Note
Note
Note
3:
4:
5:
6:
www.maximintegrated.com
Maxim Integrated │ 6
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
IIN
RTEST
dRi =
1V
(VINi + 1 - VINi)
=
(IINi + 1 - IINi) (IINi + 1 - IINi)
IOFFSET = IINi 1ms/10ms/100ms
100V
EVALUATION
BOARD*
VINi
dRi
IINi + 1
dRi
IINi
IOFFSET
*EVALUATION PERFORMED WITH THE MAX5988A EV KIT.
Figure 1. MAX5991A/MAX5991B Internal TVS Test Setup
www.maximintegrated.com
VINi
1V
VINi + 1
VIN
Figure 2. Effective Differential Resistance and Offset Current
Maxim Integrated │ 7
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
QUIESCENT CURRENT vs. SUPPLY
VOLTAGE (ULTRA-LOW POWER MODE)
DETECTION CURRENT vs. INPUT VOLTAGE
0.40
0.35
0.30
0.25
0.20
0.15
MAX5991A toc02
DETECTION CURRENT (mA)
0.45
4.00
3.75
QUIESCENT CURRENT (mA)
MAX5991A toc01
0.50
0.10
3.50
3.25
3.00
2.75
0.05
2.50
0
2.9
4.4
5.9
7.4
8.9
45
50
55
SUPPLY VOLTAGE (V)
SIGNATURE RESISTANCE
vs. SUPPLY VOLTAGE
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
2
OFFSET CURRENT (µA)
27
26
25
24
23
60
3
MAX5991A toc03
DIFFERENTIAL RESISTANCE (kI)
40
INPUT VOLTAGE (V)
28
1
0
-1
-2
22
-3
1.4
2.9
4.4
5.9
7.4
8.9
10.1
1.4
2.9
4.4
5.9
7.4
8.9
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
CLASSIFICATION SETTLING TIME
10.1
MAX5991A toc06
MAX5991A toc05
25
23
CLASSIFICATION CURRENT (mA)
35
10.1
MAX5991A toc04
1.4
CLASS 2
21
VDD
10V/div
GND
19
17
15
CLASS 1
13
11
IDD
10mA/div
0mA
9
7
5
10
12
14
16
18
20
22
24
400µs/div
INPUT VOLTAGE (V)
www.maximintegrated.com
Maxim Integrated │ 8
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
INRUSH CURRENT LIMIT vs. VCC VOLTAGE
52
48
44
20
18
12
40
8
6
12
18
24
30
36
42
48
10
20
30
40
50
60
70
VCC (V)
RSL (kI)
LED CURRENT vs. LED VOLTAGE
EFFICIENCY vs. LOAD CURRENT
(MAX5991A, VOUT = 5V)
100
MAX5991A toc09
25
RSL = 30.2kI
20
80
MAX5991A toc10
0
VIN = 12V
95
90
EFFICIENCY (%)
LED CURRENT (mA)
MAX5991A toc08
24
LED CURRENT (mA)
56
INRUSH CURRENT (mA)
LED CURRENT vs. R SL
28
MAX5991A toc07
60
15
RSL = 60.4kI
10
85
80
VIN = 48V
75
VIN = 36V
VIN = 57V
70
65
5
1.75
0
5.25
7.00
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT
(MAX5991B, VOUT = 12V)
LED VOLTAGE
vs. PORT CURRENT (MPS ENABLED)
90
EFFICIENCY (%)
0
LED VOLTAGE (V)
VIN = 36V
95
60
MAX5991A toc12
MAX5991A toc11
100
3.50
LED VOLTAGE
(2 IN SERIES)
5V/div
VIN = 48V
85
VIN = 57V
80
75
IDD CURRENT
5mA/div
70
65
60
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
40ms/div
LOAD CURRENT (A)
www.maximintegrated.com
Maxim Integrated │ 9
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
5V LOAD TRANSIENT
(0% TO 50%)
5V LOAD TRANSIENT
(50% TO 100%)
MAX5991A toc13
MAX5991A toc14
VOUT
AC-COUPLED
50mV/div
VOUT
AC-COUPLED
50mV/div
IOUT
500mA /div
0A
IOUT
500mA/div
0A
100µs/div
100µs/div
DC-DC CONVERTER STARTUP
(IOUT = 0A)
DC-DC CONVERTER STARTUP
(IOUT = 1A)
MAX5991A toc15
MAX5991A toc16
VOUT
2V/div
2ms/div
www.maximintegrated.com
VOUT
2V/div
2ms/div
Maxim Integrated │ 10
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
LDO_FB
RESET
MPS
CLASS2
TOP VIEW
WK
Pin Configurations
15
14
13
12
11
WAD 16
VDD 17
MAX5991A
MAX5991B
VCC 18
PGND 19
2
3
4
5
LDO_IN
LDO_OUT
AUX
1
LED
+
LX
RREF 20
*EP
TQFN
4mm × 4mm
10
ULP
9
SL
8
VDRV
7
GND
6
FB
*EP = EXPOSED PAD. CONNECT EP TO GND.
Pin Description
PIN
NAME
FUNCTION
1
AUX
Auxiliary Voltage Input. Auxiliary input to the internal regulator, VDRV. Connect AUX to the output of
the buck converter if the output voltage is greater than 4.75V to back bias the internal circuitry and
increase efficiency. Connect to a clean ground when not used.
2
LX
3
LED
LED Driver Output. In sleep mode, LED sources a periodic current (ILED) at 250Hz with 25% duty
cycle.
4
LDO_IN
LDO Input Voltage. Connect LDO_IN to the output of the DC-DC converter when used; otherwise,
connect to GND. Connect a minimum 1µF bypass capacitor between LDO_IN and GND.
5
LDO_OUT
6
FB
7
GND
Ground. Reference rail for the device. It is also the “quiet” ground for all voltage reference (e.g., FB
is referenced to this GND).
8
VDRV
Internal 5V Regulator Voltage Output. The internal voltage regulator provides 5V to the MOSFET
driver and other internal circuits. VDRV is referenced to GND. Do not use VDRV to drive external
circuits. Connect a 1µF bypass capacitor between VDRV and GND.
www.maximintegrated.com
Inductor Connection. Inductor connection for the internal DC-DC converter.
LDO Output Voltage. Connect a minimum 1µF output capacitor between LDO_OUT and GND.
Feedback. Feedback input for the DC-DC buck converter. Connect FB to a resistive divider from
the output to GND to adjust the output voltage.
Maxim Integrated │ 11
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Pin Description (continued)
PIN
NAME
9
SL
FUNCTION
Sleep Mode Enable Input. A falling edge on SL brings the device into sleep mode. An external
resistor (RSL) connected between SL and GND sets the LED current (ILED).
Ultra-Low Power-Mode Enable Input. ULP has an internal 50kI pullup resistor to the internal 5V
bias rail. A falling edge on SL while ULP is asserted low enables ultra-low power mode. When
ultra-low power mode is enabled, the power consumption of the device is reduced even lower than
sleep mode to comply with ultra-low power sleep power requirements while still supporting MPS.
10
ULP
11
CLASS2
12
MPS
13
RESET
Open-Drain Reset Output. The RESET output is driven low if either LDO_OUT or FB drops below
90% of its set value. RESET goes high 100µs after both LDO_OUT and FB rise above 95% of their
set values. Leave unconnected when not used.
14
LDO_FB
LDO Regulator Feedback Input. Connect to VDRV to get the preset LDO output voltage of 3.3V, or
connect to a resistive divider from the LDO_OUT to GND for an adjustable LDO output voltage.
15
WK
Class 2 Selection Pin. Connect to VDRV for Class 2 operation. Connect to GND for Class 1
operation.
MPS Enable Pin. Connect to VDRV to turn the MPS function on. Connect to GND to turn the MPS
function off.
Wake Mode Enable Input. WK has an internal 50kI pullup resistor to the internal 5V bias rail.
A falling edge on WK brings the device out of sleep mode and into the normal operating mode
(wake mode).
16
WAD
Wall Power Adapter Detector Input. Wall adapter detection is enabled when the voltage from WAD
to GND is greater than 8.8V. When a wall power adapter is present, the isolation p-channel power
MOSFET turns off. Connect WAD directly to GND when the wall power adapter or other auxiliary
power source is not used.
17
VDD
Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and PGND.
18
VCC
DC-DC Converter Power Input. VDD is connected to VCC by an isolation p-channel MOSFET.
Connect a 10FF capacitor in parallel with a 1µF ceramic capacitor between VCC and PGND.
19
PGND
Power Ground. Power ground of the DC-DC converter power stage. Connect PGND to GND with a
star connection. Do not use PGND as reference for sensitive feedback circuit.
20
RREF
Signature Resistor Connection. Connect a 24.9kI resistor (RSIG) to GND.
—
EP
www.maximintegrated.com
Exposed Pad. Connect the exposed pad to ground.
Maxim Integrated │ 12
MAX5991A/MAX5991B
Detailed Description
PD Interface
The MAX5991A/MAX5991B include complete interface
functions for a PD to comply with the IEEE 802.3af
standard as a Class 1/Class 2 PD. The devices provide
the detection and classification signatures using a single
external signature resistor. An integrated MOSFET provides isolation from the buck converter when the PSE
has not applied power. The devices guarantee a leakage
current offset of less than 8µA during the detection
phase. The devices feature power-mode undervoltagelockout (UVLO) with wide hysteresis and long deglitch
time to compensate for twisted-pair-cable resistive drop
and to ensure glitch-free transitions between detection,
classification, and power-on/-off modes.
Operating Modes
The devices operate in three different modes depending
on VDD. The three modes are detection mode, classification mode, and power mode. The device is in detection
mode when VDD is between 1.4V and 10.1V, classification mode when VDD is between 12.6V and 20V, and
power mode when the input voltage exceeds VON.
Detection Mode (1.4V < VDD < 10.1V)
In detection mode, the devices provide a signature
differential resistance to VDD. During detection, the
power-sourcing equipment (PSE) applies two voltages to
VDD, both between 1.4V and 10.1V with a minimum 1V
increment. The PSE computes the differential resistance
to ensure the presence of the 24.9kω signature resistor. Connect the 24.9kω signature resistor (RSIG) from
RREF to GND for proper signature detection. The device
applies VDD to RREF when in detection mode, and the
VDD offset current due to the device is less than 8µA. The
DC offset due to protection diodes does not significantly
affect the signature resistance measurement.
Classification Mode (12.6V < VDD < 20V)
In classification mode, the devices sink a Class 1/Class
2 classification currents. The PSE applies a classification voltage between 12.6V and 20V, and measures the
classification currents. The devices use the external
24.9kω resistor (RSIG) and the CLASS2 pin to set the
classification current at 10.5mA (Class 1, CLASS1 =
www.maximintegrated.com
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
GND) or 18mA (Class 2, CLASS2 = VDRV). The PSE
uses this to determine the maximum power to deliver.
The classification current includes current drawn by the
supply current of the device so the total current drawn
by the PD is within the IEEE 802.3af standard. The
classification current is turned off when the device leaves
classification mode.
Power Mode (VDD > VON)
In power mode, the devices have the isolation MOSFET
between VDD and VCC fully on. The devices have the
buck regulator enabled and the LDO enabled. The
devices can be in either wake mode, sleep mode, or
ultra-low power mode. The buck regulator and LDO are
only enabled in wake mode.
The devices enter power mode when VDD rises above
the undervoltage lockout threshold (VON). When VDD
rises above VON, the device turns on the internal p-channel isolation MOSFET to connect VCC to VDD with inrush
current limit internally set to 49mA (typ). The isolation
MOSFET is fully turned on when VCC is near VDD and the
inrush current is below the inrush limit. Once the isolation MOSFET is fully turned on, the device changes the
current limit to 321mA. The buck converter turns on
115ms after the isolation MOSFET turns on fully.
Undervoltage Lockout
The devices operate with up to a 60V supply voltage
with a turn-on UVLO threshold (VON) at 38.7V (typ), and
a turn-off UVLO threshold (VOFF) at 31.4V (typ). When
the input voltage is above VON, the device enters power
mode and the internal isolation MOSFET is turned on.
When the input voltage is below VOFF for more than
tOFF_DLY, the MOSFET and the buck converter are off.
LED Driver
The devices drive an LED, or multiple LEDs in series, with
a maximum LED voltage of 6.5V. In sleep mode and ultralow power mode, the LED current is pulse width modulated with a duty cycle of 25% and the amplitude is set by
R SL. The LED driver current amplitude is programmable
from 10mA to 20mA using R SL according to the formula:
ILED = 646/R SL (mA)
where R SL is in kω.
Maxim Integrated │ 13
MAX5991A/MAX5991B
Sleep and Ultra-Low Power Modes
The devices feature a sleep mode and an ultra-low power
mode in which the internal p-channel isolation MOSFET
is kept on and the buck regulator is off. In sleep mode,
the LED driver output (LED) pulse width modulates the
LED current with a 25% duty cycle. The peak LED current
(ILED) is set by an external resistor R SL. To enable sleep
mode, apply a falling edge to SL with ULP disconnected
or high impedance. Sleep mode can only be entered
from wake mode.
Ultra-low power mode allows the devices to reduce
power consumption lower than sleep mode, while maintaining the power signature of the IEEE standard. The
ultra-low power-mode enable input ULP is internally held
high with a 50kω pullup resistor to the internal 5V bias of
the device. To enable ultra-low power mode, apply a falling edge to SL with ULP = LOW. Ultra-low power mode
can only be entered from wake mode.
To exit from sleep mode or ultra-low power mode and
resume normal operation, apply a falling edge on the
wake-mode enable input (WK).
Thermal-Shutdown Protection
If the devices’ die temperature reaches 151°C, an overtemperature fault is generated and the device shuts down.
The die temperature must cool down below +127°C to
remove the overtemperature fault condition. After a thermal shutdown condition clears, the device is reset.
WAD Description
For applications where an auxiliary power source such
as a wall power adapter is used to power the PD, the
devices feature wall power adapter detection.
The wall power adapter is connected from WAD to PGND.
The devices detect the wall power adapter when the voltage from WAD to PGND is greater than 8.8V. When a wall
power adapter is detected, the internal isolation MOSFET
is turned off, classification current is disabled.
Connect the auxiliary power source to WAD, connect a
diode from WAD to VDD, and connect a diode from WAD
to VCC. See the typical application circuit in Figures 3
and 4.
The application circuit must ensure that the auxiliary
power source can provide power to VDD and VCC by
means of external diodes. The voltage on VDD must be
within the VDD voltage range to allow the DC-DC to operate. To allow operation of the DC-DC converter, the VDD
and VCC voltage must be greater than 8V, on the rising
www.maximintegrated.com
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
edge, while on the falling edge the VDD and VCC may fall
down to 7.7V keeping the DC-DC converter on.
Note: When operating solely with a wall power adapter,
the WAD voltage must be able to meet the condition VDD
> 8V, that likely results in WAD > 8.8V.
Internal Linear
Regulator and Back Bias
An internal voltage regulator provides VDRV to internal
circuitry. The VDRV output is filtered by a 1µF capacitor connected from VDRV to GND. The regulator is for
internal use only and cannot be used to provide power to
external circuits. VDRV can be powered by either VDD or
VAUX, depending on VAUX. The internal regulator is used
for both PD and buck converter operations.
VOUT can be used to back bias the VDRV voltage regulator if VOUT is greater than 4.75V. Back biasing VDRV
increases device efficiency by drawing current from
VOUT instead of VDD. If VOUT is used as back bias,
connect AUX directly to VOUT. In this configuration, the
VDRV source switches from VDD to VAUX after the buck
converter’s output has reached its regulation voltage.
Cable Discharge Event Protection (CDE)
A 70V voltage clamp is integrated to protect the internal
circuits from a cable discharge event.
DC-DC Buck Converter
The DC-DC buck converter uses a PWM, peak currentmode, fixed-frequency control scheme providing an
easy-to-implement architecture without sacrificing a fast
transient response. The buck converter operates in a
wide input voltage range from 8V to 60V and supports up
to 6.49W of output power at 1.3A load. The devices provide a wide array of protection features including UVLO,
overtemperature shutdown, short-circuit protection with
hiccup runaway current limit, cycle-by-cycle peak current protection, and cycle-by-cycle output overvoltage
protection, for enhanced performance and reliability. A
frequency foldback scheme is implemented to reduce
the switching frequency to half at light loads to increase
the efficiency.
Frequency Foldback Protection for
High-Efficiency Light-Load Operation
The devices enter frequency foldback mode when eight
consecutive inductor current zero-crossings occur. The
switching frequency is 430kHz under loads large enough
that the inductor current does not cross zero. In frequency foldback mode, the switching frequency is reduced
Maxim Integrated │ 14
MAX5991A/MAX5991B
to 215kHz to increase power conversion efficiency. The
device returns to normal mode when the inductor current
does not cross zero for eight consecutive switching periods. Frequency foldback mode is forced during startup
until 50% of the soft-start is completed.
Hiccup Mode
The devices include a hiccup protection feature. When
hiccup protection is triggered, the devices turn off the
high-side and turn on the low-side MOSFET until the
inductor current reaches the valley current limit. The
control logic waits 77ms until attempting a new soft-start
sequence. Hiccup mode is triggered if the current in
the high-side MOSFET exceeds the runaway currentlimit threshold, both during soft-start and during normal
operating mode. Hiccup mode can also be triggered in
normal operating mode in the case of an output undervoltage event. This happens if the regulated feedback
voltage drops below 60% (typ).
RESET Output
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
power source through VCC. Connect the auxiliary power
source to WAD, connect a diode from WAD to VCC. See
the typical application circuit in Figures 3 and 4.
Adjusting LDO Output Voltage
An uncommitted LDO regulator is available to provide
a supply voltage to external circuits. A preset voltage
of 3.3V is set by connecting LDO_FB directly to VDRV.
For different output voltages connect a resistor divider
from LDO_OUT and LDO_FB to GND. The total feedback
resistance should be in the range of 100kω. The maximum output current is 85mA and thermal considerations
must be taken to prevent triggering thermal shutdown.
The LDO regulator can be powered by VOUT, a different power supply, or grounded when not used. The LDO
is enabled once the buck converter has reached the
regulation voltage. The LDO is disabled when the buck
converter is turned off or not regulating.
Adjusting Buck Converter Output Voltage
The devices feature an open-drain RESET output that
indicates if either the LDO or the switching regulator drop
out of regulation. The RESET output goes low if either
regulator drops below 92% of its regulated feedback
value. RESET goes high impedance 100µs after both
regulators are above 95% of their value.
The buck converter output voltage is set by changing
the feedback resistor-divider ratio. The output voltage
can be set from 3.0V to 5.6V (MAX5991A) or 5.4V to
14V (MAX5991B). The FB voltage is regulated to 1.226V.
Keep the trace from the FB pin to the center of the resistive divider short, and keep the total feedback resistance
around 100kω.
Maintain Power Signature (MPS)
Inductor Selection
The devices feature the MPS to comply with the IEEE
802.3af standard. It is able to maintain a minimum current
(10mA) of the port to avoid the power disconnection from
the PSE. The devices enter MPS mode when the port
current is lower than 14mA and also exit the MPS mode
when the port current is greater than 40mA. The feature is
enabled by connecting the MPS pin to VDRV, or disabled
by connecting the MPS pin to GND.
Choose an inductor with the following equation:
Applications Information
Operation with Wall Adapter
For applications where an auxiliary power source such
as a wall power adapter is used to power the PD, the
devices feature wall power adapter detection. The device
gives priority to the WAD supply over VDD supply, and
smoothly switches the power supply to WAD when it is
detected. The wall power adapter is connected from
WAD to PGND. The devices detect the wall power adapter when the voltage from WAD to PGND is greater than
8.8V. When a wall power adapter is detected, the internal
isolation MOSFET is turned off, classification current is
disabled and the device draws power from the auxiliary
www.maximintegrated.com
where LIR is the ratio of the inductor ripple current to
full load current at the minimum duty cycle. Choose LIR
between 20% to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the devices.
VCC Input Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching noise
in the IC. The total input capacitance must be equal or
greater than the value given by the following equation
to keep the input-ripple voltage within specification and
minimize the high-frequency ripple current being fed
back to the input source:
Maxim Integrated │ 15
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
where VIN-RIPPLE is the maximum allowed input ripple
voltage across the input capacitors and is recommended
to be less than 2% of the minimum input voltage. D is
the duty cycle (VOUT/VIN) and TS is the switching period
(1/fS).
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
where IRIPPLE is the input RMS ripple current.
Output Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage,
and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in
the output capacitor, the voltage drop due to the capacitor’s ESR, and the voltage drop due to the capacitor’s
ESL. Estimate the output-voltage ripple due to the output
capacitance, ESR, and ESL:
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) +VRIPPLE(ESL)
where the output ripple due to output capacitance, ESR,
and ESL is:
or whichever is larger. The peak-to-peak inductor current
(IP-P)
Use these equations for initial output capacitor selection. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current is
a factor of the inductor value, the output-voltage ripple
decreases with larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency
of the converter. The ripple voltage due to ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected output
capacitance. During a load transient, the output instantly
changes by ESR x ILOAD. Before the controller can
respond, the output deviates further, depending on the
inductor and output capacitor values. After a short time,
the controller responds by regulating the output voltage
back to its predetermined value. The controller response
time depends on the closed-loop bandwidth. A higher
bandwidth yields a faster response time, preventing the
output from deviating further from its regulating value.
Table 1. Design Selection Table
CIN
COUT
OUTPUT
(V)
CERAMIC
ELECTROLYTIC
CERAMIC
3.3
2.2FF/100V
10FF/63V
2 x 22FF/6.3V
15FH/1.7A
1
5
2.2FF/100V
10FF/63V
2 x 22FF/6.3V
22FH/1.7A
1 or 2
12
2.2FF/100V
10FF/63V
2 x 10FF/16V
100FH/0.8A
1 or 2
www.maximintegrated.com
L
CLASS
Maxim Integrated │ 16
MAX5991A/MAX5991B
PCB Layout
Careful PCB layout is critical to achieve clean and stable
operation. It is highly recommended to duplicate the
MAX5991A EV kit layout for optimum performance. If
deviation is necessary, follow these guidelines for good
PCB layout:
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the signal ground plane.
2) Place capacitors on VDD, VCC, AUX, VDRV as close
as possible to the IC and its corresponding pin using
direct traces. Keep power ground plane (connected
to PGND) and signal ground plane (connected to
GND) separate.
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
4) Connect VDD, VCC, and PGND separately to a large
copper area to help cool the IC to further improve
efficiency and long-term reliability.
5) Ensure all feedback connections are short and direct.
Place the feedback resistors and compensation components as close as possible to the IC.
6) Route high-speed switching nodes, such as LX, away
from sensitive analog areas (FB).
7) Place enough vias in the pad for the EP of the devices
so that heat generated inside can be effectively dissipated by the PCB copper. The recommended spacing for the vias is 1mm to 1.2mm pitch. The thermal
vias should be plated (1oz copper) and have a small
barrel diameter (0.3mm to 0.33mm).
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output
capacitors, and the input capacitors.
www.maximintegrated.com
Maxim Integrated │ 17
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Typical Application Circuits
C1
68nF
RJ45 AND
BRIDGE
RECTIFIER
1µF
VDRV
CLASS2
MPS
LDO_FB
C3
1µF
C2
10µF
VDD VCC
WAD
AUX
L0
22µH
LX
5V
OUTPUT
WK
TO µP OPEN-DRAIN OUTPUTS
OR PULLDOWN SWITCHES
ULP
R1
75kI
MAX5991A
MAX5991B
SL
FB
RSL
60.4kI
TO 5V OUTPUTS
C5
1µF
C4
47µF
R2
24.9kI
LDO_IN
LDO_OUT
3.3V
OUTPUT
C6
1µF
LED
RREF
RSIG
24.9kI
GND
PGND
0I
Figure 3. MAX5991A/MAX5991B 5V Buck Regulator and Fixed LDO Output
www.maximintegrated.com
Maxim Integrated │ 18
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Typical Application Circuits (continued)
C1
68nF
RJ45 AND
BRIDGE
RECTIFIER
1µF
VDRV
C3
1µF
C2
10µF
VDD VCC
WAD
AUX
CLASS2
L0
22µH
MPS
LX
MAX5991A
MAX5991B
WK
TO µP OPEN-DRAIN OUTPUTS
OR PULLDOWN SWITCHES
R1
75kI
5V
OUTPUT
C4
47µF
FB
ULP
R2
24.9kI
SL
RSL
60.4kI
ADJ_LDO_OUT
LDO_OUT
R3
C6
1µF
LDO_FB
TO 5V OUTPUTS
C5
1µF
LDO_IN
R4
LED
RREF
RSIG
24.9kI
GND
PGND
0I
Figure 4. MAX5991A/MAX5991B 5V Buck Regulator and Adjustable LDO Output
www.maximintegrated.com
Maxim Integrated │ 19
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Functional Diagram
VCC
VDD
MAX5991A
MAX5991B
5V
TVS
HOT-SWAP
CONTROLLER
DETECTION
CLASSIFICATION
GND
5V
RREF
WAD
PD VOLTAGE
MONITOR
AUX
5V
5V
1.5V
VDRV
1
5V
REGULATOR
5V
0
CLK
LX
BANDGAP
CONTROL
DRIVER
VREF
LDO_IN
VREF
LDO_OUT
LDO
PGND
FB
LDO_FB
OPEN DRAIN
VDD
CLASS2
CLASS
RESET
5V
50kI
VDD
50kI
WK
MPS
MPS
LOGIC
SL
ULP
LED
www.maximintegrated.com
Maxim Integrated │ 20
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Chip Information
Package Information
PROCESS: BiCMOS
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 TQFN-EP
T2044+4
21-0139
90-0409
Ordering Information
PART
PIN-PACKAGE
SLEEP/ULP
MODE
LDO
UVLO (V)
RESET
MPS/CLASS2
OUTPUTADJ
MAX5991AETP+
20 TQFN-EP*
Yes
Yes
38.7
Yes
Yes
Yes
MAX5991BETP+
20 TQFN-EP*
Yes
Yes
38.7
Yes
Yes
Yes
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
www.maximintegrated.com
Maxim Integrated │ 21
MAX5991A/MAX5991B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Revision History
REVISION
NUMBER
REVISION
DATE
0
11/12
Initial release
—
1
1/13
Changed land pattern number
21
2
1/15
Updated Benefits and Features section
1
DESCRIPTION
PAGES
CHANGED
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2015 Maxim Integrated Products, Inc. │ 22
工商网监
湘ICP备2023018690号
