MAX6876ETX+

19-3479; Rev 0; 10/04 KIT ATION EVALU E L B AVAILA EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit Applications Multivoltage Systems Networking Systems Telecom Storage Equipment Servers/Workstations ♦ EEPROM-Configurable Tracking/Sequencing Control ♦ Bus Voltage Independent Operation (MAX6876 Is Powered from the Tracked Supply Voltages or Always-On Supply) ♦ EEPROM-Selectable Undervoltage/OvervoltageLockout Thresholds for Each Input Supply ♦ EEPROM-Selectable Power-Up/Down Slew Rate ♦ Programmable Power-Good Output Thresholds and Timing ♦ Global Adjustable Undervoltage Lockout or Logic ENABLE Input ♦ Independent Internal Charge Pumps to Enhance External n-Channel FETs (VGATE_SOURCE = 5V) ♦ Post Power-Up Selectable Overcurrent Detection ♦ 0.5V to 5.5V IN_ Threshold Range ♦ ±1.5% Threshold Accuracy ♦ I2C/SMBus™-Compatible Serial Interface ♦ Small 6mm x 6mm, 36-Pin Thin QFN Package Ordering Information PART TEMP RANGE PINPACKAGE MAX6876ETX -40°C to +85°C 36 Thin QFN PKG CODE T3666-3 TOP VIEW IN2 GATE2 OUT2 IN3 GATE3 OUT3 Pin Configuration GATE1 OUT1 The MAX6876 is available in a small 6mm x 6mm, 36pin thin QFN package and is fully specified over the extended -40°C to +85°C temperature range. ♦ Tracking/Sequencing for Up to Four Supply Voltages (With One MAX6876 Device) and Tracking for Up to 16 Supply Voltages (Using Four MAX6876 Devices) IN1 The MAX6876 EEPROM-configurable, multivoltage power tracker/supervisor monitors four system voltages and ensures proper power-up and power-down conditions for systems requiring voltage tracking and/or sequencing. The MAX6876 provides a highly configurable solution as key thresholds and timing parameters are programmed through an I 2C interface and these values are stored in internal EEPROM. The MAX6876 also provides supervisory functions and an overcurrent detection circuit. The MAX6876 features programmable undervoltage and overvoltage thresholds for each input supply. When all voltages are within specifications, the device turns on the external n-channel MOSFETs to either sequence or track the voltages to the system. All of the voltages can be sequenced or tracked or powered up with a combination of the two options. During tracking, the voltage at the GATE of each MOSFET is increased to slowly turn on each supply. The voltages at the source of each MOSFET are compared to each other to ensure that the voltage differential between each monitored supply does not exceed 250mV (typ). Tracking is dynamically adjusted to force all outputs to track within a ±125mV window from a reference ramp; if, for any reason, any supply fails to track within ±250mV from the reference ramp, a FAULT output is asserted, the power-up mode is terminated, and all outputs are powered off. Power-up mode is also terminated if the controlled voltages fail to complete the rampup within a programmable FAULT timeout. The MAX6876 features latch-off and autoretry modes to power on again after a fault condition has been detected. Other features of the MAX6876 include a reset circuit, a manual reset input (MR), and a margin disable input (MARGIN). The device also features outputs for indicating a power-good condition (PG_) and an overcurrent condition (OC), and a bus-removal (REM) output. Features 36 35 34 33 32 31 30 29 28 VCC GND 1 27 IN4 2 26 ABP TRKEN SYNCH HOLD 3 25 GATE4 OUT4 OC REM FAULT 7 21 8 20 PG4 PG3 PG2 19 PG1 4 24 5 23 MAX6876 6 22 EP* 9 REFIN N.C. *EXPOSED PADDLE A0 A1 RESET SMBus is a trademark of Intel Corp. ENABLE MARGIN N.C. MR SDA SCL 10 11 12 13 14 15 16 17 18 6mm x 6mm THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX6876 General Description MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit ABSOLUTE MAXIMUM RATINGS (All voltages are referenced to GND, unless otherwise noted.) GATE_.............................................................-0.3V to (IN_ + 6V) IN1–IN4, VCC ............................................................-0.3V to +6V OUT1–OUT4, SYNCH, ABP, REFIN...............................-0.3V to Max (IN1–IN4, VCC ) + 0.3V ENABLE, TRKEN, HOLD, FAULT, MR, MARGIN......-0.3V to +6V RESET, PG1–PG4, OC, REM....................................-0.3V to +6V SDA, SCL, A0, A1.....................................................-0.3V to +6V Input/Output Current (all pins except OUT_ and GND) ...±20mA OUT_, GND Current..........................................................±50mA Continuous Power Dissipation (TA = +70°C) 36-Pin, 6mm x 6mm Thin QFN (derate 26.3mW/°C above +70°C) ..............................2105mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC, IN1–IN4 = +2.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1) PARAMETER Operating Voltage Range (Note 2) Undervoltage Lockout SYMBOL VCC VUVLO Supply Current ICC IN_ Threshold Range VTH CONDITIONS 1.4 Voltage on ABP (from VCC or IN1–IN4) to ensure the device is fully operational 2.7 2 MAX 5.5 2.5 VCC = 5.5V, IN1–IN4 = 3.3V, no load 1.8 3 Configuration registers or memory access, no load 2.5 4 UNITS V V mA IN1–IN4 (in 20mV increments) 1.00 5.50 IN1–IN4 (in 10mV increments) 0.50 3.05 0.5V < IN_ < 5.5V, IN_ TA = 0°C to +85°C falling for UV, rising for OV -1.5 +1.5 % 2V < IN_ < 5.5V, IN_ falling for UV, rising for OV (20mV increments) -2.5 +2.5 % 1V < IN_ < 2V, IN_ falling for UV, rising for OV (20mV increments) -50 +50 mV 1V < IN_ < 3.05V, IN_ falling for UV, rising for OV (10mV increments) -2.5 +2.5 % 0.5V < IN_ < 1V, IN_ falling for UV, rising for OV (10mV increments) -25 +25 mV TA = -40°C to +85°C RESET Threshold Tempco TYP Minimum voltage on ABP (from VCC or IN1–IN4) to ensure the device is EEPROM configured Threshold Accuracy Threshold Hysteresis MIN GATE_ = PG_ = RESET = 0 V VTH_HYS 0.5 %VTH ∆VTH/C 50 ppm/°C _______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit (VCC, IN1–IN4 = +2.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Tracking-Differential-Voltage Hold Ramp (Note 3) VTRK CONDITIONS VOUT_ > VTH_PL VOUT_ < VTH_PG MIN TYP MAX UNITS 95 125 155 mV Tracking-Differential-Voltage Hysteresis Tracking-Differential FAULT Voltage (Note 3) FAULT Timeout Period (Note 4) FAULT to GATE Delay IN1–IN4 Input Impedance OUT1–OUT4 Input Impedance Power-On Delay 25 VTRK_F Register tFAULTUP, contents tFAULTDOWN (Table 16) RIN1-4 ROUT1-4 tD-GATE OUT_ to PG_ Delay 200 250 300 00 20 25 30 01 40 50 60 10 80 100 120 11 160 200 240 tFG tPO IN_ to GATE_ Delay VOUT_ > VTH_PL VOUT_ < VTH_PG tPOK 2 OC Timeout Period tRESET, tAUTO, tGATE tOC TRKSLEW VTH_OC µs 55 90 145 70 100 130 kΩ 3 ms VABP ≥ VUVLO kΩ IN_ falling/rising, 100mV overdrive 6 µs OUT_ rising, 100mV overdrive 3 ms OUT_ falling, 100mV overdrive 25 µs Register contents (Table 16) Register contents (Table 16) Register contents (Table 16) Register contents (Table 16), OUT_ falling 25 µs 001 10 12.5 15 010 011 20 40 25 50 30 60 100 80 100 120 101 160 200 240 110 111 320 1280 400 1600 480 1920 00 10 12.5 15 01 40 50 60 10 11 80 160 100 200 120 240 TA = 0°C to +85°C 560 800 1040 TA = -40°C to 0°C 480 800 1120 TA = 0°C to +85°C TA = -40°C to 0°C 280 240 400 400 520 560 TA = 0°C to +85°C 140 200 260 TA = -40°C to 0°C 120 200 280 TA = 0°C to +85°C TA = -40°C to 0°C 70 60 100 100 130 140 00 96.25 97.5 98.75 01 93.75 95 96.25 10 11 91.25 88.75 92.5 90 93.75 91.25 01 10 11 IN_ to OUT_ Overcurrent Threshold ms OUT_ pulldown disabled 00 Track/Sequence Slew Rate Rising or Falling mV For IN_ voltages < the highest IN_ supply 000 GATE, RESET, Autoretry Timeout Period (Notes 5, 6) mV ms ms V/s % _______________________________________________________________________________________ 3 MAX6876 ELECTRICAL CHARACTERISTICS (continued) MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit ELECTRICAL CHARACTERISTICS (continued) (VCC, IN1–IN4 = +2.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1) PARAMETER IN_ to OUT_ Power-Good Threshold VTH_PG and VTH_OC Hysteresis SYMBOL VTH_PG VTH_PL Power Low Hysteresis VTH_PL_HYS OUT_ to GND Pulldown Impedance (When Enabled) Output Low PG1–PG4, HOLD, FAULT, OC, RESET (Note 2) GATE1–GATE4 Output Low Register contents (Table 16), OUT_ rising MIN TYP MAX 00 01 93.75 91.25 95 92.5 96.25 93.75 10 88.75 90 91.25 11 86.25 87.5 88.75 VOUT_HYS Power Low Threshold REM Output Low CONDITIONS 0.5 OUT_ falling ABP ≥ 2.5V VOL_REM VOL VGOL ABP ≥ 2.5V, ISINK = 1mA 0.3 ABP ≥ 4.0V, ISINK = 4mA 0.4 ABP ≥ 1.4V, ISINK = 50µA 0.3 ABP ≥ 2.5V, ISINK = 1mA 0.3 ABP ≥ 4.0V, ISINK = 4mA 0.8 -1 V V V +1 µA IN_ + 5.8 V IN_ + 4.4 IN_ + 5 During power-up/down, VGATE_ = 1V 2.5 4.5 µA IGATEDOWN During power-up/down, VGATE_ = 4V 2.5 4.5 µA IGATEUP 0.3 x ABP VIL V VIH 0.6 x ABP tMR 2 FAULT, HOLD, MARGIN, MR, ENABLE Glitch Rejection Digital Input to Logic Delay, FAULT, HOLD, MARGIN, MR, ENABLE tD MARGIN, MR Digital Input to ABP Pullup Resistance RP 4 Ω 0.3 IGATE_ = 0.5µA MR Input Pulse Width 100 ABP ≥ 1.4V, ISINK = 50µA (PG_, RESET only) VGOH MARGIN, FAULT, HOLD, MR, ENABLE Input Voltage mV 0.4 GATE_ Output-Voltage High mV 10 0.3 Output deasserted % % 165 ABP ≥ 4.0V, ISINK = 15mA ILKG GATE_ Pulldown Current 142 ABP ≥ 2.5V, ISINK = 4mA PG1–PG4, HOLD, FAULT, OC , RESET, REM Output Open-Drain Leakage Current GATE_ Pullup Current 125 UNITS 70 µs 100 ns 1 µs 100 _______________________________________________________________________________________ 130 kΩ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit (VCC, IN1–IN4 = +2.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1) PARAMETER TRKEN Input Delay SYMBOL tEN TRKEN Reference Voltage Range VTRKEN TRKEN Input Current ITRKEN Reference Input Voltage Range VREFIN Reference Input Resistance RREFIN CONDITIONS MIN TRKEN falling, 100mV overdrive TYP MAX 2 UNITS µs Input rising 1.245 1.285 1.320 Input falling 1.225 1.25 1.275 +100 nA 1.25 1.275 V VTRKEN = 1.25V -100 1.225 VREFIN = 1.25V 500 V kΩ SERIAL INTERFACE LOGIC (SDA, SCL, A0, A1) Logic-Input Low Voltage VIL Logic-Input High Voltage VIH Input Leakage Current IILKG Output-Voltage Low VOL Output Leakage Current Input/Output Capacitance 0.3 x ABP V 0.6 x ABP V 1 ISINK = 3mA IOLKG CI/O µA 0.4 V 1 µA 10 pF SERIAL INTERFACE TIMING (SDA, SCL) Serial Clock Frequency fSCL 400 kHz Clock Low Period tLOW 1.3 µs Clock High Period tHIGH 0.6 µs Bus Free Time tBUF 1.3 µs START Setup Time tSU:STA 0.6 µs START Hold Time tHD:STA 0.6 µs STOP Setup Time tSU:STO 0.6 Clock Low to Valid Output tAA 0.1 µs Data Out Hold Time tDH 50 ns Data In Setup Time tSU:DAT 100 ns Data In Hold Time tHD:DAT 0 0.9 µs ns SCL/SDA Rise Time tR 300 ns SCL/SDA Fall Time tF 300 ns Transmit SDA Fall Time tF SCL/SDA Noise Suppression Time Byte Write Cycle Time tI tWR CBUS = 400pF 20 + 0.1 x CBUS 300 50 ns ns 11 ms Note 1: Specifications guaranteed for the stated global conditions. 100% production tested at TA = +25°C and TA = +85°C. Specifications at TA = -40°C are guaranteed by design. Note 2: The internal supply voltage, measurable on ABP, is equal to the maximum of IN1–IN4 and VCC supplies. Note 3: Differential between each of the OUT_ and the SYNCH ramp voltage during power-up/down measured as VOUT_ - 2 x VSYNCH. Note 4: FAULT timeout starts to count at the beginning of each sequence of power-up/down and clears when the programmed OUT_ voltages track successfully. _______________________________________________________________________________________ 5 MAX6876 ELECTRICAL CHARACTERISTICS (continued) MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit ELECTRICAL CHARACTERISTICS (continued) (VCC, IN1–IN4 = +2.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1) Note 5: The MAX6876 programmed as a single device; GATE timeout has counted prior to beginning each sequence of power-up. GATE timeout is not enabled during power-down or when the device is programmed as a master/slave. Note 6: The MAX6876 programmed as a single device, the autoretry time begins to count at the assertion of the FAULT signal. The MAX6876 programmed as a master/slave device; the autoretry time begins to count at the deassertion of the common FAULT signal. Timing Diagrams VTRKEN VTRKEN BUS VOLTAGE MONITORED THROUGH TRKEN INPUT GND IN1 = 3.3V IN2 = 2.5V IN3 = 1.8V IN4 = 1.5V MONITORED THROUGH SET THRESHOLDS ON IN_ INPUTS (EEPROM-SELECTABLE) GND OUT1 = 3.3V EEPROMADJUSTED SLEW RATE OUT2 = 2.5V OUT3 = 1.8V OUT4 = 1.5V tGATE GND >tFAULTDOWN VTH_PL threshold) (see the Typical Application Circuit and the Bus Removal Output (REM) section). 9 FAULT Active-Low, Open-Drain Tracking Fault Alert Output or Input. FAULT asserts low if a tracking failure is present for longer than the specified fault period or if tracking voltages fails by more than ±250mV (see the FAULT section). 10 RESET Active-Low, Open-Drain Reset or Power-Good Output. RESET is low during power-up and powerdown tracking. RESET goes high after all selected OUT_ outputs exceed their selected thresholds and the reset timeout period tRESET has expired. The reset timeout period is internally selectable. RESET requires an external pullup resistor. 11 ENABLE Logic ENABLE Input. ENABLE must be high to enable voltage tracking/sequencing power-up operation. OUT_ begins tracking down when ENABLE is low. Connect to ABP if not used. 12 MARGIN Active-Low Margin Input. The MARGIN function allows systems to be tested with supply voltages outside their normal ranges without affecting supply tracking/sequencing or reset states. MARGIN functionality is usually enabled after systems have powered up in normal mode. The MARGIN functionality is disabled (returns to normal monitoring mode) after MARGIN returns high. MARGIN is internally pulled up to ABP through a 100kΩ resistor. 13, 23 N.C. No Connection. Not internally connected. 14 MR Active-Low Manual Reset Input. When MR is low, RESET goes low and remains asserted for the selected timeout period after MR is pulled high. MR is internally pulled up to ABP through a 100kΩ resistor. 15 SDA Serial-Interface Data Input/Output (Open-Drain). SDA requires an external pullup resistor. 16 SCL 17 A0 18 19 A1 PG1 20 PG2 21 PG3 22 PG4 7 Serial-Interface Clock Input. SCL requires an external pullup resistor. Serial-Interface Address Inputs. The inputs allow up to four MAX6876 devices to be addressed when sharing a common data bus. A1 and A0 should be connected to GND or ABP. Power-Good Output, Open-Drain. Each PG_ output signals when its monitored OUT_ voltage is within the selected percentage of the IN_ voltage range (VTH_PG). PG_ is low until OUT_ exceeds the programmable threshold (VTH_PG) for more than tPOK. PG_ outputs are open-drain and require external pullups if used. ______________________________________________________________________________________ 11 MAX6876 Pin Description (continued) EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit MAX6876 Pin Description (continued) PIN 24 REFIN 25 OUT4 26 GATE4 27 28 29 30 31 12 NAME IN4 FUNCTION Reference Voltage Input. The MAX6876 can be configured to use the internal 1.25V reference or an external voltage reference. REFIN is tri-stated when using the internal reference. REFIN provides the threshold voltage for the voltage detectors when using an external voltage reference. Use an external voltage reference when tighter voltage-detector accuracy is desired. When configured to an internal reference, leave REFIN unconnected. When configured for an external reference, connect a 1.225V to 1.275V reference to REFIN. Monitored Output Voltage. The OUT4 output is monitored to control the supply slew rate and tracking performance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the minimum voltage requirements, VTRKEN > 1.285V threshold, ENABLE is logic high, and IN1–IN4 are all within their selected thresholds. The OUT4 output falls out of the tracking equation as OUT4 approaches IN4; other OUT_ supplies continue tracking up without signaling a system fault. OUT_ outputs are tracked down during power-off conditions. Gate Drive for External n-Channel FETs. GATE4 begins enhancing the external n-channel FETs when all monitored inputs are within their selected thresholds (0.5V to 5.5V), at least one IN_ input or VCC is above the minimum operating voltage, VTRKEN > 1.285V threshold, and the ENABLE input is logic high. During power-up mode, GATE_ voltages are enhanced with internal control loops forcing all OUT_ voltages to track the reference ramp (SYNCH) at a programmed slew rate. An internal charge pump boosts GATE4 to VIN4 + 5V to fully enhance the external n-channel FET when power-up is complete. Supply Voltage and Tracked Input Voltage. Nominal supply range is 0.5V to 5V. IN1, IN2, IN3, IN4, or VCC must be greater than the internal UVLO (VABP = 2.7V) to enable the tracking functionality. The IN4 input is monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or sequencing) is enabled. OUT3 Monitored Output Voltage. OUT3 is monitored to control the supply slew rate and tracking performance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the minimum voltage requirements, VTRKEN > 1.285V threshold, ENABLE is logic high, and IN1–IN4 are all within their selected thresholds. The OUT3 output falls out of the tracking equation as OUT3 approaches IN3; other OUT_ supplies continue tracking up without signaling a system fault. OUT_ outputs are tracked down during power-off conditions. GATE3 Gate Drive for External n-Channel FETs. GATE3 begins enhancing the external n-channel FETs when all monitored inputs are within their selected thresholds (0.5V to 5.5V), at least one IN_ input or VCC is above the minimum operating voltage, VTRKEN > 1.285V threshold, and the ENABLE input is logic high. During power-up mode, GATE_ voltages are enhanced with internal control loops forcing all OUT_ voltages to track the reference ramp (SYNCH) at a programmed slew rate. An internal charge pump boosts GATE3 to VIN3 + 5V to fully enhance the external n-channel FET when power-up is complete. IN3 Supply Voltage and Tracked Input Voltage. Nominal supply range is 0.5V to 5V. IN1, IN2, IN3, IN4, or VCC must be greater than the internal UVLO (VABP = 2.7V) to enable the tracking functionality. IN3 is monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or sequencing) is enabled. OUT2 Monitored Output Voltage. OUT2 is monitored to control the supply slew rate and tracking performance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the minimum voltage requirements, VTRKEN > 1.285V threshold, ENABLE is logic high, and IN1–IN4 are all within their selected thresholds. OUT2 output falls out of the tracking equation as OUT2 approaches IN2; other OUT_ supplies continue tracking up without signaling a system fault. OUT_ outputs are tracked down during power-off conditions. ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit PIN 32 33 NAME FUNCTION GATE2 Gate Drive for External n-Channel FETs. GATE2 begins enhancing the external n-channel FETs when all monitored inputs are within their selected thresholds (0.5V to 5.5V), at least one IN_ input or VCC is above the minimum operating voltage, VTRKEN > 1.285V threshold, and the ENABLE input is logic high. During power-up mode, GATE_ voltages are enhanced with internal control loops forcing all OUT_ voltages to track the reference ramp (SYNCH) at a programmed slew rate. An internal charge pump boosts GATE2 to VIN2 + 5V to fully enhance the external n-channel FET when power-up is complete. IN2 Supply Voltage and Tracked Input Voltage. Nominal supply range is 0.5V to 5V. IN1, IN2, IN3, IN4, or VCC must be greater than the internal UVLO (VABP = 2.7V) to enable the tracking functionality. IN2 is monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or sequencing) is enabled. OUT1 Monitored Output Voltage. Each OUT1 is monitored to control the supply slew rate and tracking performance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the minimum voltage requirements, VTRKEN > 1.285V threshold, ENABLE is logic high, and IN1–IN4 are all within their selected thresholds. The OUT1 output falls out of the tracking equation as OUT1 approaches IN1; other OUT_ supplies continue tracking up without signaling a system fault. OUT_ outputs are tracked down during power-off conditions. GATE1 Gate Drive for External n-Channel FETs. GATE1 begins enhancing the external n-channel FETs when all monitored inputs are within their selected thresholds (0.5V to 5.5V), at least one IN_ input or VCC is above the minimum operating voltage, VTRKEN > 1.285V threshold, and the ENABLE input is logic high. During power-up mode, GATE_ voltages are enhanced with internal control loops forcing all OUT_ voltages to track the reference ramp (SYNCH) at a programmed slew rate. An internal charge pump boosts GATE1 to VIN1 + 5V to fully enhance the external n-channel FET when power-up is complete. 36 IN1 Supply Voltage and Tracked Input Voltage. Nominal supply range is 0.5V to 5V. IN1, IN2, IN3, IN4, or VCC must be greater than the internal UVLO (VABP = 2.7V) to enable the tracking functionality. IN1 is monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or sequencing) is enabled. — EP Exposed Paddle. Exposed paddle is internally connected to GND. 34 35 Detailed Description The MAX6876 EEPROM-configurable, multivoltage power tracker/supervisor monitors four system voltages and ensures proper power-up and power-down conditions for systems requiring voltage tracking and/or sequencing. The MAX6876 provides a highly configurable solution as key thresholds and timing parameters are programmed through an I 2C interface and these values are stored in internal EEPROM. In addition to tracking and sequencing voltages, the MAX6876 also provides supervisory functions as well as an overcurrent detection circuit. The MAX6876 features programmable undervoltage and overvoltage thresholds for each input supply. The thresholds are EEPROM configured in 10mV (0.5V to 3.05V) or 20mV (1.0V to 5.5V) increments. When all of the voltages are within their specifications, the device turns on the external n-channel MOSFETs to either sequence or track the voltages to the system. All of the voltages can be sequenced or tracked or powered up with a combination of the two options. During voltage tracking, the voltage at the GATE of each MOSFET is increased to slowly turn on each OUT_. The GATE delay is EEPROM-selectable from 25µs to 1.6s. The ______________________________________________________________________________________ 13 MAX6876 Pin Description (continued) Functional Diagram IN1 IN2 ABP IN3 VCC IN4 ABP GATE1 OUT1 VCP1 = VIN1 + 5V INTERNAL SUPPLY/UVLO MAX6876 CHARGE PUMP IN1 UV/OV IN1 COMP RAMP GENERATOR IN2 UV/OV PG1 OVERCURRENT DETECT COMP IN1 VTHPG COMP ABP CONTROL LOGIC IN3 UV/OV GND COMP RAMP IN4 UV/OV TRACKING MONITORS 1.25V IN2 TO OUT2 CONTROL BLOCK GATE2 PG2 OUT2 IN3 TO OUT3 CONTROL BLOCK GATE3 PG3 OUT3 IN4 TO OUT4 CONTROL BLOCK GATE4 PG4 OUT4 HOLD RESET SYNCH OC FAULT REM MR MARGIN TRKEN ENABLE GND REFIN REF voltages at the sources of the MOSFETs are compared to each other to ensure that the voltage differential between each monitored supply does not exceed 250mV (typ). Tracking is dynamically adjusted to force all outputs to track within a ±125mV window from a reference ramp; if, for any reason, any supply fails to track within ±250mV from the reference ramp, the FAULT output is asserted, the power-up mode is terminated, and all outputs are powered off. Power-up mode is in the same way terminated if the controlled voltages fail to complete the ramp up within a programmable FAULT timeout. The MAX6876 generates all required voltages (with internal charge pumps) and timing to control up to four external n-channel MOSFETs for the OUT1–OUT4 supply voltages. 14 OUT1 OUT2 OUT3 OUT4 IN1 IN2 IN3 IN4 COMP A1 A0 SCL EEPROM/ CONFIGURATION REGISTERS SDA MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit A synchronization feature allows up to 16 voltages to be tracked simultaneously. In addition, HOLD and SYNCH communicate synchronization status between master/slave devices in multiple MAX6876 applications. Other features of the MAX6876 include a reset circuit with an I2C-programmable timeout feature. A manual reset input (MR) and a margin disable input (MARGIN) allow for more control during the manufacturing process. The device also features four power-good outputs (PG_), an overcurrent output (OC), and a bus-removal safe (REM) output. The device has an accurate internal 1.25V reference; for greater accuracy, connect an external +1.25V reference to REFIN. ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit MAX6876 Table 1. Master/Slave Settings REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION If “00,” the device configuration is a single device. 09h 29h [7:6] If “01,” the device configuration is multiple devices, slave. If “10,” the device configuration is multiple devices, slave. If “11,” the device configuration is multiple devices, master. Modes of Operation The MAX6876 provides three different modes of operation: tracking, sequencing, and mixed modes. The mixed mode is a combination of both tracking and sequencing modes (see the Mixed Mode (Tracking/ Sequencing) section). Tracking When all selected inputs exceed their selected thresholds, VTRKEN > 1.285V, and ENABLE is logic high, the tracking process is initialized. The MAX6876 generates an internal ramp voltage that drives the control loops for the desired tracked voltage. The tracking functionality is monitored with a comparator control block (see the Functional Diagram and Figure 5). The comparators monitor and control each output voltage with respect to the common tracking ramp voltage to stay within a ±125mV differential window, monitor each tracked output voltage with respect to its input voltage, and monitor each output voltage with respect to GND during power-up/retry cycles. Under normal conditions each OUT_ voltage will track the ramp voltage until the OUT_ voltage approximates the IN_ voltage (the external n-channel FET is saturated). The slew rate for the ramp voltage is selected through EEPROM. Master/Slave Operation (Tracking Only) To support voltage tracking for more than four supplies, combine multiple MAX6876 devices. Two MAX6876 devices (one master/one slave) track up to eight supply voltages and four MAX6876 devices (one master and three slaves) track up to 16 supply voltages. Each device must be programmed to act in master or slave mode (only one master is allowed); the default state is single device (see Table 1). The MAX6876 outputs the ramp control voltage with the SYNCH output when configured as a master device. This ramp allows multiple devices to synchronize with the master when slave SYNCHs are configured as inputs. For proper functionality control, connect all ENABLE pins together. In master/slave mode, all controlled supplies are tracked up/down (no mixed sequencing/tracking modes are supported). In master-slave application, the part is RAMP 1 RAMP 2 RAMP 3 RAMP 4 BIT 0 BIT 4 BIT 0 BIT 4 OUT2 BIT 1 BIT 5 BIT 1 BIT 5 OUT3 BIT 2 BIT 6 BIT 2 BIT 6 OUT4 BIT 3 BIT 7 (MSB) BIT 3 BIT 7 (MSB) OUT1 R0Bh[7:0] R0Ch[7:0] Figure 6. Mapping Tracking and Sequencing Modes intended to provide only tracking for the four supplies (only one ramp is generated). To control one particular channel, insert a “1” in any of the four possible positions (one row for each channel contains 4 bits) and the circuit will generate the proper signals (see Figure 6). For multiple MAX6876 operations, the ramp control voltage is brought out of the master’s SYNCH (programmed as an output) and into the slave’s SYNCH (programmed as an input). The highest tracked supply must be connected to one of the master’s IN_ inputs. When all IN_ threshold conditions are met (on master and slaves), the master ramp begins rising at the selected ramp slew rate. During normal operation all OUT_ voltages (for master and slave) track the ramp voltage. If the slave’s OUT_ voltages do not properly follow the ramp voltage (exceed 125mV differential), the slave device asserts HOLD low. The master recognizes the HOLD and holds the ramp voltage, allowing the slave’s slower OUT_ voltages to ______________________________________________________________________________________ 15 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit catch up. When the slave’s voltages approach the ramp voltage, the slave releases HOLD and the master allows the ramp voltage to begin rising again. All tracking must be completed by the selected tracking fault timeout period or the supplies are powered down. The slave HOLD output is asserted low until the selected tracking IN_ voltages are within their selected thresholds. This ensures that the master does not begin the tracking operation until the slave’s input voltages (IN_) have properly stabilized. Sequencing The sequencing operation can be initialized by properly setting the bit of registers 0Bh and 0Ch. During a sequencing power-up phase, each OUT_ is independently powered on with a controlled slew rate. No more than one supply is powered on for each generated ramp. The bits of registers 0Bh and 0Ch establish the turn-on order. During each phase, the ramp is enabled to start only after the tGATE timeout has been counted. The sequencing phase will be considered complete when all the channels programmed to power on reach the independently set PG_ thresholds (see Figure 5). Mixed Mode (Tracking/Sequencing) The MAX6876 is fully programmable to generate up to four ramps during power-up or power-down modes. Each OUT_ voltage independently is programmed to follow any of the control ramps generated by the MAX6876. To do the latter, set the bits on register 0Bh and 0Ch to “1” for each channel. The following are programming examples of different power-up modes (➞ = sequence, / = track): 0Bh = 0000 1111 0Ch = 0000 0000 tracking mode: OUT1/OUT2/OUT3/OUT4 on Ramp1 0Bh = 1000 0100 0Ch = 0010 0001 sequencing mode: OUT3 ➞ OUT4 ➞ OUT1 ➞ OUT2 on Ramp1, Ramp2, Ramp3, Ramp4 0Bh = 1100 0001 0Ch = 0010 0000 mix mode*: OUT1 ➞ OUT4/OUT3 ➞ OUT2 on Ramp1, Ramp2, Ramp4 *(Ramp3 is not considered because no OUT_ outputs are selected by bit [0:3] of 0Ch.) Drive ENABLE or TRKEN low or use a software command to initiate a controlled power-down. The MAX6876 powers down the OUT_ voltages in a reverse sequence from the one at power-up when this option is selected. For example, with the following power-up sequence: OUT1 ➞ OUT4/OUT3 ➞ OUT2 then the power-down sequence will be: OUT2 ➞ OUT4/OUT3 ➞ OUT1 16 Configuring Tracking and Sequencing Modes To configure tracking and sequencing modes, insert “1” and “0” into the 0Bh and 0Ch registers (see Table 2). Figure 6 shows how to map for tracking and sequencing modes. Each OUT_ output can follow one of the four possible ramps in tracking or sequencing mode (16 bits are available) and one bit set to “1,” means that the channel of the interested row is powered up/down by the corresponding ramp (see Figure 6). 1) If the depicted table (in Figure 6) is made by all “1s,” the part simply generates a single ramp (all channels in tracking mode since the first column is full of “1s,”) and it ignores the remaining values of the other 12 bits. 2) If one row contains more than one symbol “1,” only the first encountered (columns starting with R0Bh [3:0]) is taken into account and the channel is powered up/down with the corresponding ramp. 3) If there is one (or more) row in which all 4 bits are set to “0,” it means that the device will not control that particular channel. 4) If there is one (or more) column where all 4 bits are set to “0,” the device skips that ramp and its associate tD-GATE. In master-slave applications, the device is intended to provide only tracking for the four supplies (only one ramp can be generated). To control one particular channel, only insert a “1” in any of the four possible positions (one row for each channel contains 4 bits) and the device generates the proper signals. When three or less ramps are needed, use consecutive ramps starting with ramp 1. Power-Down and Power-Up When all the IN_ inputs are within the selected threshold range and the internal enable is logic high (Figure 7), the device initiates a power-up phase. During power-up, the OUT_ outputs are forced by an internal loop that controls the GATE_ of the external MOSFET to follow the reference ramp voltage. This phase for each individual ramp must be completed within the programmable fault timeout time; otherwise, the part will force a shutdown on the GATE_. Once the power-up is completed, a power-down phase can be initiated by forcing the internal enable low. Two power-down options are available: a fast-shutdown option where all GATE_ gates are quickly turned off or a reverseorder option. This reverse-order option allows the OUT_ voltage to be powered down with a controlled slew rate and in the reverse order they have been powered up (see Figure 2). ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit MAX6876 Table 2. Configuring Tracking and Sequencing Modes REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION Bit 7—If 1, OUT4 on ramp 2 Bit 6—If 1, OUT3 on ramp 2 Bit 5—If 1, OUT2 on ramp 2 0Bh 2Bh [7:0] Bit 4—If 1, OUT1 on ramp 2 Bit 3—If 1, OUT4 on ramp 1 Bit 2—If 1, OUT3 on ramp 1 Bit 1—If 1, OUT2 on ramp 1 Bit 0—If 1, OUT1 on ramp 1 Bit 7—If 1, OUT4 on ramp 4 Bit 6—If 1, OUT3 on ramp 4 Bit 5—If 1, OUT2 on ramp 4 0Ch 2Ch [7:0] Bit 4—If 1, OUT1 on ramp 4 Bit 3—If 1, OUT4 on ramp 3 Bit 2—If 1, OUT3 on ramp 3 Bit 1—If 1, OUT2 on ramp 3 Bit 0—If 1, OUT1 on ramp 3 To speed up the discharge of the OUT_ voltage, an optional 100Ω pulldown resistor can be selected (see Table 3). Slew-Rate Control The reference ramp voltage slew rate during any controlled power-up/down phase can be programmed in the 100V/s to 800V/s range. Before any power-up or retry cycle, the MAX6876 must first ensure that all OUT_ voltages are near ground (below the V TH_PL power low threshold). An internal programmable tracking timeout period can be selected to signal a fault and shut down the output voltages if tracking takes too long (see Table 4). Power-supply tracking operation should be completed within the selected fault timeout period. For selected control ramps of 100V/s the normal tracking time should be approximately 50ms (5V supply, SR = 100V/s). The total tracking time is extended when the MAX6876 must vary the control slew rate to allow slow supplies to catch up. If the external FET is too small (RDS is too high for the selected load current and IN_ source current), the OUT_ voltage may never reach the control ramp voltage. Autoretry and Latch-Off Functions The MAX6876 features latch-off or autoretry mode to power on again after a fault condition has been detect- ed. Toggle ENABLE, I2C command bit, and TRKEN or cycle device power to clear the latch. Set bit 5 of register 09h to “1” to program the MAX6876 in latch-off mode, or “0” to program for autoretry mode. The autoretry time can be programmed with bits 2, 3, and 4 of register 09h (see Table 5). During autoretry, the gate drive remains off and FAULT remains asserted. In a master-slave application, FAULT is asserted low until all the OUT_ outputs of each device are discharged to GND, and only the master counts the autoretry time while HOLD remains low (see Table 5). Stability Comment No external compensation is required for tracking or slew-rate control. Powering the MAX6876 The MAX6876 derives power from VCC or the voltagedetector inputs: IN1–IN4 (see the Functional Diagram). VCC (if being used) or one of the IN_ inputs must be at least +2.7V to ensure full device operation. The highest input voltage on IN1–IN4 or VCC supplies power to the device. Internal hysteresis ensures that the supply input that initially powers the device continues to power the device when multiple input voltages are within 50mV (typ) of each other. ______________________________________________________________________________________ 17 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit Table 3. Program Power-Down and Power-Up REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION Bit 7—If 1, reverse order of track/sequence power-down If 0, GATE_ fast pulldown Bit 6—If 1, OUT1 charges with internal pulldown If 0, no pulldown is allowed 13h 33h Bit 5—If 1, OUT2 charges with internal pulldown If 0, no pulldown is allowed [7:3] Bit 4—If 1, OUT3 charges with internal pulldown If 0, no pulldown is allowed Bit 3—If 1, OUT4 charges with internal pulldown If 0, no pulldown is allowed “00” fault power-up timer value = 25ms “01” fault power-up timer value = 50ms [7:6] 0Ah “10” fault power-up timer value = 100ms “11” fault power-up timer value = 200ms 2Ah “00” fault power-down timer value = 25ms “01” fault power-down timer value = 50ms [5:4] “10” fault power-down timer value = 100ms “11” fault power-down timer value = 200ms Table 4. Setting the Slew Rate REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION “00” track/sequence slew rate (rise or fall) = 800V/s 12h 32h Bit [7:6] “01” track/sequence slew rate (rise or fall) = 400V/s “10” track/sequence slew rate (rise or fall) = 200V/s “11” track/sequence slew rate (rise or fall) = 100V/s Inputs IN1–IN4 The IN1–IN4 voltage detectors monitor voltages from 1V to 5.5V in 20mV increments, or +0.5V to +3.05V in 10mV increments. Use the following equations to set the threshold voltages for IN_: x= VTH - 1V 0.02V for +1V to +5.5V range. 18 x= VTH - 0.5V 0.01V for +0.5V to +3.05V range. where VTH is the desired threshold voltage and x is the decimal code for the desired threshold (Table 6). For the +1V to +5.5V range, x must equal 225 or less; otherwise, the threshold exceeds the maximum operating voltage of IN1–IN4 (Table 6). An overvoltage or undervoltage failure on an IN_ input immediately shuts down all the OUT_ outputs and generates a FAULT in the master/slave condition. ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit MAX6876 Table 5. Program Autoretry/Latch off REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE 5 DESCRIPTION If 1, latch-on fault If 0, autoretry “000” autoretry timer value = 25µs “001” autoretry timer value = 12.5ms 09h “010” autoretry timer value = 25.0ms 29h [4:2] “011” autoretry timer value = 50.0ms “100” autoretry timer value = 100.0ms “101” autoretry timer value = 200.0ms “110” autoretry timer value = 400.0ms “111” autoretry timer value = 1600.0ms Table 6. IN1–IN4 Threshold Settings REGISTER ADDRESS 00h 01h 02h 03h 04h EEPROM MEMORY ADDRESS 20h 21h 22h 23h 24h BIT RANGE DESCRIPTION [7:0] IN1 Undervoltage Threshold VTH = 1.0 + n x 20mV (if R08[7] = 0) VTH = 0.5 + n x 10mV (if R08[7] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. [7:0] IN2 Undervoltage Threshold VTH = 1.0 + n x 20mV (if R08[6] = 0) VTH = 0.5 + n x 10mV (if R08[6] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. [7:0] IN3 Undervoltage Threshold VTH = 1.0 + n x 20mV (if R08[5] = 0) VTH = 0.5 + n x 10mV (if R08[5] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. [7:0] IN4 Undervoltage Threshold VTH = 1.0 + n x 20mV (if R08[4] = 0) VTH = 0.5 + n x 10mV (if R08[4] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. [7:0] IN1 Overvoltage Threshold VTH = 1.0 + n x 20mV (if R08[7] = 0) VTH = 0.5 + n x 10mV (if R08[7] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. ______________________________________________________________________________________ 19 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit Table 6. IN1–IN4 Threshold Settings (continued) REGISTER ADDRESS 05h 06h 07h EEPROM MEMORY ADDRESS 25h 26h 27h BIT RANGE DESCRIPTION [7:0] IN2 Overvoltage Threshold VTH = 1.0 + n x 20mV (if R08[6] = 0) VTH = 0.5 + n x 10mV (if R08[6] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. [7:0] IN3 Overvoltage Threshold VTH = 1.0 + n x 20mV (if R08[5] = 0) VTH = 0.5 + n x 10mV (if R08[5] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. [7:0] IN4 Overvoltage Threshold VTH = 1.0 + n x 20mV (if R08[4] = 0) VTH = 0.5 + n x 10mV (if R08[4] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. Bit 7—If 0, 20mV steps in VTH setting for IN1 If 1, 10mV steps in VTH setting for IN1 Bit 6—If 0, 20mV steps in VTH setting for IN2 If 1, 10mV steps in VTH setting for IN2 08h 28h [7:4] Bit 5—If 0, 20mV steps in VTH setting for IN3 If 1, 10mV steps in VTH setting for IN3 Bit 4—If 0, 20mV steps in VTH setting for IN4 If 1, 10mV steps in VTH setting for IN4 Manual Reset Input (MR) The manual reset (MR) input initiates a reset condition. MR is internally pulled up to ABP through a 100kΩ resistor. When MR is low, RESET remains low for the selected reset timeout period after MR transitions from low to high (see the Reset Output (RESET) section). Margin Input (MARGIN) MARGIN allows system-level testing while power supplies exceed the normal ranges. Drive MARGIN low before varying system voltages below/above the selected threshold without signaling an error. MARGIN makes it possible to vary the supplies without a need to reprogram the IN_ or PG_ thresholds and prevents tracker/sequencer alerts or faults. Drive MARGIN high or leave it floating for normal operating mode. ENABLE Drive logic ENABLE input high to initiate voltage tracking/sequencing during power-up operation. Drive logic 20 ENABLE low to initiate tracking/sequencing power-down operation. When ENABLE is not used, connect to ABP. When the MAX6876 is configured to use the I2C on/off command, a valid I2C signal must be received before the device begins the power-up tracking/sequencing routine. The internal enable logic is an AND function of the ENABLE logic, the TRKEN logic, and the I2C control/command logic (Figure 7). When all three AND gate input variables are true (and the monitored IN/OUT voltages meet their required thresholds), turn-on is allowed. When any AND input variable becomes false, the turnoff cycle (track/sequence down) begins immediately. Drive ENABLE and TRKEN high if only the I 2C command is to be used to turn on/off the device. The detectors monitoring IN_ and OUT_ voltages, and overcurrent conditions have a higher priority after a power-on routine has been initiated by the internal enable logic. If a fault occurs during the power-up cycle, the device is powered down immediately, independent of ENABLE, TRKEN, and the I 2C shutdown ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit MAX6876 Table 7. Program ENABLE REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION Bit 1—If 1, check ENABLE with I2C enable control bit If 0, ignore ENABLE with I2C 09h 29h [1:0] Bit 0—If 0, enable with I2C = 0, I2C enable command bit If 1, enable with I2C = 1 Table 8. Select External Reference REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE 11h 31h 0 DESCRIPTION Bit 0—If 1, selects external reference; 0 selects internal reference command (Table 7). If a latch-on fault mode is chosen, a toggle on the internal enable clears the latch condition and restarts the device after a fault condition (Figure 7). ENABLE TRKEN INTERNAL ENABLE Reference Voltage Input (REFIN) The MAX6876 features an internal +1.25V voltage reference. The voltage reference sets the threshold of the voltage detectors. Leave REFIN unconnected when using the internal reference. REFIN accepts an external reference in the +1.225V to +1.275V range. Use Table 8 commands to select the external reference. Track Enable Input (TRKEN) The track enable (TRKEN) monitor input is another feature of the MAX6876. To enable voltage-tracking power-up operation, drive TRKEN higher than 1.285V. When TRKEN goes below 1.25V, OUT_ outputs start tracking down. Connect TRKEN to an external resistordivider network to set the desired monitor threshold. Connect TRKEN to ABP if not used. SYNCH The MAX6876 provides selectable tracking synchronization output or input (SYNCH). SYNCH allows tracking of up to 16 power supplies on the same I2C bus. One device is programmed as the SYNCH master and the other devices are programmed as slaves. SYNCH of the master device outputs the common ramp voltage to which all OUT_ voltages are tracked. The SYNCH pins of the slave devices are inputs for the ramp control voltage (no internal ramp is generated in the slave devices) (see Table 1). VTRKEN I2C ENABLE CONTROL BIT (RAM REGISTER) 1 = YES 09h[1] 0 = NO I2C ENABLE COMMAND BIT (RAM REGISTER) 0 = OFF 09h[0] 1 = ON Figure 7. Logic ENABLE Monitored Outputs OUT1–OUT4 The MAX6876 monitors four OUT_ outputs to control the tracking/sequencing performance. After the internal supply (ABP) exceeds the minimum voltage (2.7V) requirements, TRKEN > 1.25V, the internal ENABLE input is logic high, and IN1–IN4 are all within their selected thresholds, OUT1–OUT4 will begin to track or sequence. During power-up mode, the MAX6876 drives the gates of the external n-channel FETs to force the OUT_ voltages to track the internally set ramp voltage. If OUT_ voltages vary from the ramp voltage by more than ±125mV, an internal comparator signals an alert that dynamically adjusts the ramp voltage (stops the ramp until the slow OUT_ catches up). During power-down mode, an internal pulldown resistor (100Ω) on OUT_ can be enabled to help discharge load capacitance. ______________________________________________________________________________________ 21 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit Table 9. GATE-Delay Time Settings REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION “000” gate-delay timer value = 25µs “001” gate-delay timer value = 12.5ms “010” gate-delay timer value = 25.0ms 0Fh 2Fh “011” gate-delay timer value = 50.0ms [7:5] “100” gate-delay timer value = 100.0ms “101” gate-delay timer value = 200.0ms “110” gate-delay timer value = 400.0ms “111” gate-delay timer value = 1600.0ms Table 10. FAULT Power-Up and Power-Down Time Settings REGISTER ADDRESS 0Ah EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION [7:6] Bit [7:6] “00” fault power-up timer value = 25ms “01” fault power-up timer value = 50ms “10” fault power-up timer value = 100ms “11” fault power-up timer value = 200ms [5:4] Bit [5:4] “00” fault power-down timer value = 25ms “01” fault power-down timer value = 50ms “10” fault power-down timer value = 100ms “11” fault power-down timer value = 200ms 2Ah FAULT Outputs GATE_ The MAX6876 features four GATE_ outputs to drive four external n-channel FET gates. The following conditions must be met before GATE_ begins enhancing the external n-channel FET_: 1) All monitored inputs (IN1–IN4) are above their selected thresholds (0.5V to 5.5V) 2) At least one IN_ input or VCC is above 2.7V 3) Drive ENABLE high 4) TRKEN > 1.25V At power-up mode, GATE_ voltages are enhanced control loops so all OUT_ voltages track together at a userselected slew rate. Each GATE_ is internally pulled up to 5V above its relative IN_ voltage to fully enhance the external n-channel FET when power-up is complete. In sequencing/tracking mode, a gate delay timeout is internally counted prior to the start of each control ramp (see Figures 1 and 2 and Table 9). 22 The MAX6876 offers an open-drain, active-low tracking fault alarm (FAULT). FAULT asserts low when a powerup phase is not completed within the specified fault period or if tracking voltages fail by more than ±250mV. For multiple MAX6876 applications, FAULT is an input/output pin and communicates fault information between master/slave devices. Connect all FAULT pins in an ORed configuration to force simultaneous shutdown on all MAX6876s (Table 10.) See the Typical Application Circuit. Power-Good Outputs (PG_) The MAX6876 features four power-good (PG_) outputs. PG_ outputs are open-drain and require external pullups. When the OUT_ output is within the selected percentage of the IN_ voltage range (VTH_PG), the corresponding PG_ output goes high impedance. PG_ stays low until the OUT_ voltage exceeds the programmable VTH_PG threshold for more than tPOK (Table 11). ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit MAX6876 Table 11. PG Threshold Settings REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION “00” IN4 to OUT4 power-good threshold = 95% [7:6] “01” IN4 to OUT4 power-good threshold = 92.5% “10” IN4 to OUT4 power-good threshold = 90% “11” IN4 to OUT4 power-good threshold = 87.5% “00” IN3 to OUT3 power-good threshold = 95% "01" IN3 to OUT3 power-good threshold = 92.5% “10” IN3 to OUT3 power-good threshold = 90% 10h “11” IN3 to OUT3 power-good threshold = 87.5% 30h “00” IN2 to OUT2 power-good threshold = 95% [5:0] “01” IN2 to OUT2 power-good threshold = 92.5% “10” IN2 to OUT2 power-good threshold = 90% “11” IN2 to OUT2 power-good threshold = 87.5% “00” IN1 to OUT1 power-good threshold = 95% “01” IN1 to OUT1 power-good threshold = 92.5% “10” IN1 to OUT1 power-good threshold = 90% “11” IN1 to OUT1 power-good threshold = 87.5% Bus Removal Output (REM) The MAX6876 features an open-drain bus removal (REM) output. REM signals when it is safe to remove the card after a controlled track/sequence power-down operation. To initiate a power-down, drive ENABLE low or send an I2C power-down command. REM monitors OUT_ and when any of the OUT_ voltages are above the VTH_PL threshold, REM stays low. When all OUT_ outputs are below VTH_PL, REM goes high impedance. Connect REM to an external pullup resistor/LED chain to visually signal when it is safe to remove a powered board from the bus. In tracking mode when REM is used in master/slave operations, connect all REM pins together. The common REM connection remains low if any OUT_ supply is above the VTH_PL threshold. Overcurrent Output (OC) The open-drain, active-low OC output asserts low if an overcurrent condition is detected in any selected channel for longer than tOC. Overcurrent conditions are determined as a differential voltage between IN_ and OUT_. OC monitoring begins only after supply tracking or sequencing has been completed and is disabled during power-down operation (Table 12). Reset Output (RESET) The reset output, RESET, is an open-drain output that monitors the selected OUT_ voltages. The selected OUT_ voltages must exceed their selected PG_ thresholds for the selected reset timeout period (tRP) before RESET is deasserted. A manual reset input (MR) can assert RESET. RESET remains low while MR is low. RESET remains low for the selected reset timeout period (tRP) after MR transitions from low to high (Table 13). Synchronization Hold Output (HOLD) The MAX6876 features an open-drain, active-low synchronization alert output/input. HOLD communicates synchronization status between master/slave devices in multiple MAX6876 applications. When a slave device detects a tracking problem with respect to the master SYNCH signal, the slave asserts HOLD low. When tracking is back under control, the slave’s HOLD is deasserted and goes high again. The HOLD output remains asserted while selected tracking IN_ inputs are below their selected thresholds (the slave device can delay a tracking start until its inputs are at their required stable voltage levels) or held low by the master when it is counting the autoretry time after a detected fault condition. Connect HOLD pins only to other MAX6876 HOLD pins. ______________________________________________________________________________________ 23 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit Table 12. OC Threshold Settings REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [7:6] DESCRIPTION Bit [7:6] “00” IN4 to OUT4 overcurrent threshold = 97.5% “01” IN4 to OUT4 overcurrent threshold = 95% “10” IN4 to OUT4 overcurrent threshold = 92.5% “11” IN4 to OUT4 overcurrent threshold = 90% Bit [5:4] “00” IN3 to OUT3 overcurrent threshold = 97.5% “01” IN3 to OUT3 overcurrent threshold = 95% “10” IN3 to OUT3 overcurrent threshold = 92.5% “11” IN3 to OUT3 overcurrent threshold = 90% 0Dh 2Dh [5:0] Bit [3:2] “00” IN2 to OUT2 overcurrent threshold = 97.5% “01” IN2 to OUT2 overcurrent threshold = 95% “10” IN2 to OUT2 overcurrent threshold = 92.5% “11” IN2 to OUT2 overcurrent threshold = 90% Bit [1:0] “00” IN1 to OUT1 overcurrent threshold = 97.5% “01” IN1 to OUT1 overcurrent threshold = 95% “10” IN1 to OUT1 overcurrent threshold = 92.5% “11” IN1 to OUT1 overcurrent threshold = 90% Bit [7:6] “00” overcurrent timer value = 12.5ms “01” overcurrent timer value = 50ms “10” overcurrent timer value = 100ms “11” overcurrent timer value = 200ms Bit 5—If 1, overcurrent monitoring on OUT1 is enabled If 0, no overcurrent monitoring on OUT1 0Eh 2Eh [7:1] Bit 4—If 1, overcurrent monitoring on OUT2 is enabled If 0, no overcurrent monitoring on channel 1 Bit 3—If 1, overcurrent monitoring on OUT3 is enabled If 0, no overcurrent monitoring on OUT3 Bit 2—If 1, overcurrent monitoring on OUT4 is enabled If 0, no overcurrent monitoring on OUT4 ABP ABP powers the analog circuitry. Bypass ABP to GND with a 1µF ceramic capacitor installed as close to the device as possible. Do not use ABP to provide power to external circuitry. Configuring the MAX6876 The MAX6876 factory-default configuration sets all registers to 00h. This device requires configuration before full power is applied to the system. To configure the MAX6876, first apply an input voltage greater than 2.7V to one of IN1–IN4 or V CC (see the Powering the MAX6876 section). Next, transmit data with the serial interface. Use the block write protocol to quickly configure the device. Write to the configuration registers first, 24 to ensure the device is configured properly. After completing the setup procedure, use the read word protocol to read back the data from the configuration registers. Lastly, use the write word protocol to write this data to the EEPROM registers. After completing the EEPROM register configuration, apply full power to the system to begin normal operation. The nonvolatile EEPROM stores the latest configuration upon removal of power (Table 14). Software Reboot A command code of C4h initiates a software reboot. A software reboot allows the user to restore the EEPROM configuration to the volatile registers without cycling the power supplies. ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE MAX6876 Table 13. Program RESET DESCRIPTION Bit 7—If 1, OUT1 also controls RESET If 0, OUT1 does not control RESET Bit 6—If 1, OUT2 also controls RESET If 0, OUT2 does not control RESET Bit 5—If 1, OUT3 also controls RESET If 0, OUT3 does not control RESET 11h 31h [7:1] Bit 4—If 1, OUT4 also controls RESET If 0, OUT4 does not control RESET Bit [3:1] “000” reset timer value = 25µs “001” reset timer value = 12.5ms “010” reset timer value = 25.0ms “011” reset timer value = 50.0ms “100” reset timer value = 100.0ms “101” reset timer value = 200.0ms “110” reset timer value = 400.0ms “111” reset timer value = 1600.0ms SMBus/I2C-Compatible Serial Interface The MAX6876 features an I2C/SMBus-compatible 2wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX6876 and the master device at clock rates up to 400kHz. Figure 10 shows the 2-wire interface timing diagram. The MAX6876 is transmit/receive slave-only, relying upon a master device to generate a clock signal. The master device (typically a microcontroller) initiates a data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX6876 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (SR) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is an open-drain input/output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7kΩ for most applications. Bit Transfer Each clock pulse transfers one data bit. The data on SDA must remain stable while SCL is high (Figure 11); otherwise, the MAX6876 registers a START or STOP condition (Figure 12) from the master. SDA and SCL idle high when the bus is not busy. Start and Stop Conditions Both SCL and SDA idle high when the bus is not busy. A master device signals the beginning of a transmission with a START (S) condition (Figure 8) by transitioning SDA from high to low while SCL is high. The master device issues a STOP (P) condition (Figure 8) by transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a REPEATED START condition is generated, such as in the block read protocol (see Figure 11). Early STOP Conditions The MAX6876 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition. This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP condition. ______________________________________________________________________________________ 25 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit Table 14. Registers Summary REGISTERS DESCRIPTIONS Input Undervoltage Thresholds (Registers 00h to 03h) Input undervoltage thresholds (0.5V to 3.04V in 10mV increments or 1.0V to 5.5V in 20mV increments). Each channel’s range is selected with register 08h. Input Overvoltage Thresholds (Registers 04h to 07h) Input overvoltage thresholds (0.5V to 3.04V in 10mV increments or 1.0V to 5.5V in 20mV increments). Each channel’s range is selected with register 08h. Tracking/Sequencing Modes Selects if outputs are to be sequenced or tracked. Sequencing/tracking modes are defined by 4 bits for each OUT voltage of register 0Bh and 0Ch (see the Track/Sequence section). Tracking/Sequencing Power-Up/Down Slew Rate Selectable output slew rate for power-up/down mode. Selected slew is overwritten during tracking faults. Power-up/down slew rate is selected by bit [6:7] of register 12h. Power-Up Delay Period Power-up sequencing delay. Selects delay time for sequencing each supply. Programmable delays are selected with bit [5:7] of register 0Fh. Power-Down Sequence/Track Behavior Selectable power-down operation. Chooses if output voltages should be brought down in the reverse sequence from power-up mode selections or if power supplies should be simultaneously fast powered down (selected with bit 7 register 13h). OUT Pulldown Enable Selects if OUT_ should be internally pulled to GND when in fast shutdown or tracking fault mode (selected with bit [6:3] register 13h). Single/Multiple Device Application Selects if the device will be used alone or in a master/slave application. If a single application, the device can be operated in mixed sequencing/tracking modes. If multidevice application, the device can be operated in tracking mode only (selected with bit [7:6] register 09h). 00: single device 11: master device 01 or 10: slave device Overcurrent Threshold Selects IN_-to-OUT_ threshold voltage for overcurrent monitoring for each channel (register 0Dh). Power-Good Threshold Selects IN_-to-OUT_ threshold voltage for power-good monitoring for each channel (register 10h). Overcurrent Assert Select Selects which overcurrent monitors will assert the OC output (selected by bit [5:2] of reg. 0Eh). Overcurrent Filter Period Selects the filter time for the overcurrent monitors. OC will not assert until the overcurrent condition has existed longer than the selected filter period (selected by bit [7:6] of reg. 0Eh). Fault Timeout Period Selects the timeout period for sequencing/tracking completion. If sequencing/tracking operation is not complete before the fault timeout period, a FAULT alert will be signaled and all supplies will be powered down (selected by bit [7:4] of reg. 0Ah). Fault Behavior Selects how the device should operate during faults. Options include latch-off after fault or autoretry after fault. Autoretry delay is selectable (selected by bit 5 of reg. 09h). Reset Assert Select Selects which OUT detectors will assert the RESET output (selected by bit [7:4] of reg. 11h). Reset Timeout Period Select Selects the reset timeout period (selected by bit [3:1] of reg. 11h). Enable the Part with I2C Interface Bit 0 and bit 1 of register 09h allows a micro to turn the MAX6876 on/off with the I2C interface. While 09h[1] is 0, the part will ignore any enable command from I2C. If 09h[1] is set to 1, then 09h[0] has to be 1 to enable the part to power on. 26 ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit MAX6876 SDA tBUF tSU:DAT tSU:STA tHD:DAT tLOW tHD:STA tSU:STO SCL tHIGH tHD:STA tR tF START CONDITION STOP CONDITION REPEATED START CONDITION START CONDITION Figure 10. Serial-Interface Timing Details SDA SDA SCL SCL DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID S P START CONDITION STOP CONDITION Figure 11. Bit Transfer Figure 12. Start and Stop Conditions Repeated START Conditions A REPEATED START (SR) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation (see Figure 12). SR may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX6876 serial interface supports continuous write operations with or without an SR condition separating them. Continuous read operations require SR conditions because of the change in direction of data flow. erates an ACK. The MAX6876 generates an ACK when receiving an address or data by pulling SDA low during the 9th clock period (Figure 13). When transmitting data, such as when the master device reads data back from the MAX6876, the device waits for the master device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. The MAX6876 generates a NACK after the slave address during a software reboot, while writing to the EEPROM, or when receiving an illegal memory address. Acknowledge The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. The receiving device always gen- ______________________________________________________________________________________ 27 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit START CONDITION CLOCK PULSE FOR ACKNOWLEDGE 2 1 SCL 8 9 SDA BY TRANSMITTER S SDA BY RECEIVER Figure 13. Acknowledge Slave Address The MAX6876 slave address conforms to the following table: SA7 (MSB) SA6 SA5 SA4 SA3 SA2 SA1 SA0 (LSB) 1 0 1 0 A1 A0 X R/W X = Don’t care. SA7–SA4 represent the standard 2-wire interface address (1010) for devices with EEPROM. SA3 and SA2 correspond to the A1 and A0 address inputs of the MAX6876 (hardwired as logic low or logic high). SA0 is a read/write flag bit (0 = write, 1 = read). The A0 and A1 address inputs allow up to four MAX6876s to connect to one bus. Connect A0 and A1 to GND or to HBP (see Figure 14). Send Byte The send byte protocol allows the master device to send one byte of data to the slave device (see Figure 15). The send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of an ACK if the master tries to send an address that is not allowed. If the master sends C0h or C1h, the data is ACK, because this could be the start of the write block or read block. If the master sends a stop condition, the internal address pointer does not change. If the master 28 sends C4h, this signifies a software reboot. The send byte procedure follows: 1) The master sends a start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit data byte. 5) The addressed slave asserts an ACK on SDA. 6) The master sends a stop condition. Write Byte/Word The write byte/word protocol allows the master device to write a single byte in the register bank, preset an EEPROM (configuration or user) address for a subsequent read, or to write a single byte to the configuration EEPROM (see Figure 15). The write byte/word procedure follows: 1) The master sends a start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit command code. 5) The addressed slave asserts an ACK on SDA. 6) The master sends an 8-bit data byte. 7) The addressed slave asserts an ACK on SDA. ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit START 1 0 1 0 MSB A1 A0 X R/W MAX6876 SDA ACK LSB SCL Figure 14. Slave Address 8) The master sends a stop condition or sends another 8-bit data byte. 9) The addressed slave asserts an ACK on SDA. 10) The master sends a stop condition. To write a single byte to the register bank, only the 8-bit command code and a single 8-bit data byte are sent. The command code must be in the range of 00h to 13h to write on RAM or 20h to 33h to write on EEPROM. The data byte is written to the register bank if the command code is valid. The slave generates a NACK at step 5 if the command code is invalid. Block Write The block write protocol allows the master device to write a block of data (1 to 16 bytes) to the EEPROM or to the register bank (see Figure 15). The destination address must already be set by the send byte or write byte protocol. If the number of bytes to be written causes the address pointer to exceed 13h for the configuration register (or 33h for the configuration EEPROM), the address pointer stays at 13h (or 33h), overwriting this memory address with the remaining bytes of data. The last data byte sent is stored at register address 13h (or 33h). The block write procedure follows: 1) The master sends a start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends the 8-bit command code for block write (83h). 5) The addressed slave asserts an ACK on SDA. 6) The master sends the 8-bit byte count (1 to 16 bytes), N. 7) The addressed slave asserts an ACK on SDA. 8) The master sends 8 bits of data. 9) The addressed slave asserts an ACK on SDA. 10) Repeat steps 8 and 9 N - 1 times. 11) The master generates a stop condition. Block Read The block read protocol allows the master device to read a block of 16 bytes from the EEPROM or register bank (see Figure 15). Read fewer than 16 bytes of data by issuing an early STOP condition from the master, or by generating a NACK with the master. The send byte or write byte protocol predetermines the destination address with a command code of C1h. The block read procedure follows: 1) The master sends a start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends 8 bits of the block read command (C1h). 5) The slave asserts an ACK on SDA, unless busy. ______________________________________________________________________________________ 29 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit SEND BYTE FORMAT S WRITE WORD FORMAT ADDRESS WR 7 bits 0 ACK DATA ACK P S 8 bits Slave Address– equivalent to chipselect line of a 3wire interface. Data Byte–presets the internal address pointer. ADDRESS WR 7 bits 0 ACK COMMAND ACK DATA 8 bits Slave Address– equivalent to chipselect line of a 3wire interface. ACK DATA 8 bits Write Address of the register you are writing to. ACK P 8 bits Data Byte– Data goes into the register set by the command. Data Byte– Data goes into the next register set by the command. WRITE BYTE FORMAT S ADDRESS WR 7 bits 0 ACK COMMAND ACK 8 bits Slave Address– equivalent to chipselect line of a 3wire interface. DATA ACK P 8 bits Command Byte– selects register you are writing to. Data Byte–data goes into the register set by the command. BLOCK WRITE FORMAT S ADDRESS ACK WR 0 7 bits BYTE COUNT= N COMMAND ACK DATA BYTE 1 8 bits 8 bits Slave Address– equivalent to chipselect line of a 3wire interface. ACK ACK DATA BYTE ... 8 bits Command Byte– prepares device for block operation. ACK 8 bits DATA BYTE N ACK P 8 bits Data Byte–data goes into the register set by the command byte. BLOCK READ FORMAT S ADDRESS WR 7 bits 0 Slave Address– equivalent to chipselect line of a 3wire interface. S = Start condition. P = Stop condition. ACK COMMAND ACK SR 8 bits Command Byte– prepares device for block operation. ADDRESS WR 7 bits 0 Slave Address– equivalent to chipselect line of a 3wire interface. ACK BYTE COUNT= 16 10h ACK DATA BYTE ACK 1 8 bits DATA BYTE ACK ... 8 bits Data Byte–data goes into the register set by the command byte. Shaded = Slave transmission. SR = Repeated start condition. Figure 15. SMBus/I2C Protocols 30 ______________________________________________________________________________________ DATA BYTE ACK N 8 bits P EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE 13h 33h 2 DESCRIPTION If 1, configuration registers are locked If 0, configuration registers unlocked 6) The master generates a repeated start condition. 7) The master sends the 7-bit slave address and a read bit (high). 8) The slave asserts an ACK on SDA. 9) The slave sends the 8-bit byte count (16). 10) The master asserts an ACK on SDA. 11) The slave sends 8 bits of data. 12) The master asserts an ACK on SDA. 13) Repeat steps 8 and 9 fifteen times. 14) The master generates a stop condition. Address Pointers Use the send byte protocol to set the register address pointers before read and write operations. For the configuration registers, valid address pointers range from 00h to 13h. Register addresses outside of this range result in a NACK being issued from the MAX6876. When using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 13h. If the address pointer is already 13h, and more data bytes are being sent, these subsequent bytes overwrite address 13h repeatedly, leaving only the last data byte sent stored at this register address. For the configuration EEPROM, valid address pointers range from 20h to 33h. When using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 33h. If the address pointer is already 33h, and more data bytes are being sent, these subsequent bytes overwrite address 33h repeatedly, leaving only the last data byte sent stored at this register address. Configuration EEPROM The configuration EEPROM addresses range from 20h to 33h. Write data to the configuration EEPROM to automatically set up the MAX6876 upon power-up. Data transfers from the configuration EEPROM to the configuration registers when ABP exceeds UVLO during power-up. After ABP exceeds UVLO, an internal 1MHz clock starts after a 5µs delay, and data transfer begins. Data transfer disables access to the configuration registers and EEPROM. The data transfer from EEPROM to the configuration registers takes 2ms (max). Read configuration EEPROM data at any time after power-up or software reboot. Write commands to the configuration EEPROM are allowed at any time, unless the configuration lock bit is set (see Table 15). The maximum cycle time to write a single byte is 11ms (max). Configuration Register Bank and EEPROM The configuration registers can be directly modified with the serial interface without modifying the EEPROM, after the power-up procedure terminates and the configuration EEPROM data has been loaded into the configuration register bank. Use the write byte or block write protocols to write directly to the configuration registers. Changes to the configuration registers are lost upon power removal. At device power-up, the register bank loads configuration data from the EEPROM. Configuration data can be directly altered in the register bank during application development, allowing maximum flexibility. Transfer the new configuration data byte-by-byte to the configuration EEPROM with the write byte protocol. The next device power-up or software reboot automatically loads the new configuration (Table 16). ______________________________________________________________________________________ 31 MAX6876 Table 15. Configuration of Lock Bit MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit Table 16. Register Map REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 32 EEPROM MEMORY ADDRESS 20h 21h 22h 23h 24h 25h 26h READ/WRITE DESCRIPTION R/W IN1 Undervoltage Threshold Value (VTH): VTH = 1.0 + n x 20mV (if R08[7] = 0) VTH = 0.5 + n x 10mV (if R08[7] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. R/W IN2 Undervoltage Threshold Value (VTH): VTH = 1.0 + n x 20mV (if R08[6] = 0) VTH = 0.5 + n x 10mV (if R08[6] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. R/W IN3 Undervoltage Threshold Value (VTH): VTH = 1.0 + n x 20mV (if R08[5] = 0) VTH = 0.5 + n x 10mV (if R08[5] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. R/W IN4 Undervoltage Threshold Value (VTH): VTH = 1.0 + n x 20mV (if R08[4] = 0) VTH = 0.5 + n x 10mV (if R08[4] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. R/W IN1 Overvoltage Threshold Value (VTH): VTH = 1.0 + n x 20mV (if R08[7] = 0) VTH = 0.5 + n x 10mV (if R08[7] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. R/W IN2 Overvoltage Threshold Value (VTH): VTH = 1.0 + n x 20mV (if R08[6] = 0) VTH = 0.5 + n x 10mV (if R08[6] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. R/W IN3 Overvoltage Threshold Value (VTH): VTH = 1.0 + n x 20mV (if R08[5] = 0) VTH = 0.5 + n x 10mV (if R08[5] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit REGISTER ADDRESS 07h EEPROM MEMORY ADDRESS 27h READ/WRITE R/W MAX6876 Table 16. Register Map (continued) DESCRIPTION IN4 Overvoltage Threshold Value (VTH): VTH = 1.0 + n x 20mV (if R08[4] = 0) VTH = 0.5 + n x 10mV (if R08[4] = 1) where n is the register content decimal representation. Note that VTH ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively. Bit 7—If 0, 20mV steps in VTH setting for IN1 If 1, 10mV steps in VTH setting for IN1 Bit 6—If 0, 20mV steps in VTH setting for IN2 If 1, 10mV steps in VTH setting for IN2 Bit 5—If 0, 20mV steps in VTH setting for IN3 If 1, 10mV steps in VTH setting for IN3 Bit 4—If 0, 20mV steps in VTH setting for IN4 If 1, 10mV steps in VTH setting for IN4 08h 28h R/W Bit 3—UV1 or OV1 Fault (read only for register address). If 1, IN1 is under undervoltage threshold or over overvoltage threshold. If 0, IN1 is over undervoltage threshold and under overvoltage threshold. Bit 2—UV2 or OV2 Fault (read only for register address). If 1, IN2 is under undervoltage threshold or over overvoltage threshold. If 0, IN2 is over undervoltage threshold and under overvoltage threshold. Bit 1—UV3 or OV3 Fault (read only for register address). If 1, IN3 is under undervoltage threshold or over overvoltage threshold. If 0, IN3 is over undervoltage threshold and under overvoltage threshold. Bit 0—UV4 or OV4 Fault (read only for register address). If 1, IN4 is under undervoltage threshold or over overvoltage threshold. If 0, IN4 is over undervoltage threshold and under overvoltage threshold. Bit [7:6] If “00” the device configuration is a single device If “01” the device configuration is multiple devices, slave If “10” the device configuration is multiple devices, slave If “11” the device configuration is multiple devices, master Bit 5—If 1, latch-on fault If 0, autoretry 09h 29h R/W Bit [4:2] “000” autoretry timer value = 25µs “001” autoretry timer value = 12.5ms “010” autoretry timer value = 25.0ms “011” autoretry timer value = 50.0ms “100” autoretry timer value = 100.0ms “101” autoretry timer value = 200.0ms “110” autoretry timer value = 400.0ms “111” autoretry timer value = 1600.0ms Bit 1—If 1, check I2C enable bit If 0, ignore I2C enable bit Bit 0—If 1 and 09h[1] = 1, I2C enabled If 0 and 09h[1] = 1, I2C disabled ______________________________________________________________________________________ 33 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit Table 16. Register Map (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS READ/WRITE DESCRIPTION Bit [7:6] “00” fault power-up timer value = 25ms “01” fault power-up timer value = 50ms “10” fault power-up timer value = 100ms “11” fault power-up timer value = 200ms 0Ah 2Ah R/W 0Bh 2Bh R/W 0Ch 2Ch R/W Bit [5:4] “00” fault power-down timer value = 25ms “01” fault power-down timer value = 50ms “10” fault power-down timer value = 100ms “11” fault power-down timer value = 200ms Bit 3—Reserved (write 0’s for EEPROM writes) Bit 2—Reserved (write 0’s for EEPROM writes) Bit 1—Reserved (write 0’s for EEPROM writes) Bit 0—Reserved (write 0’s for EEPROM writes) Bit 7—If 1, OUT4 on ramp 2 Bit 6—If 1, OUT3 on ramp 2 Bit 5—If 1, OUT2 on ramp 2 Bit 4—If 1, OUT1 on ramp 2 Bit 3—If 1, OUT4 on ramp 1 Bit 2—If 1, OUT3 on ramp 1 Bit 1—If 1, OUT2 on ramp 1 Bit 0—If 1, OUT1 on ramp 1 Bit 7—If 1, OUT4 on ramp 4 Bit 6—If 1, OUT3 on ramp 4 Bit 5—If 1, OUT2 on ramp 4 Bit 4—If 1, OUT1 on ramp 4 Bit 3—If 1, OUT4 on ramp 3 Bit 2—If 1, OUT3 on ramp 3 Bit 1—If 1, OUT2 on ramp 3 Bit 0—If 1, OUT1 on ramp 3 Bit [7:6] “00” IN4 to OUT4 overcurrent threshold = 97.5% “01” IN4 to OUT4 overcurrent threshold = 95% “10” IN4 to OUT4 overcurrent threshold = 92.5% “11” IN4 to OUT4 overcurrent threshold = 90% Bit [5:4] “00” IN3 to OUT3 overcurrent threshold = 97.5% “01” IN3 to OUT3 overcurrent threshold = 95% “10” IN3 to OUT3 overcurrent threshold = 92.5% “11” IN3 to OUT3 overcurrent threshold = 90% 0Dh 2Dh R/W Bit [3:2] “00” IN2 to OUT2 overcurrent threshold = 97.5% “01” IN2 to OUT2 overcurrent threshold = 95% “10” IN2 to OUT2 overcurrent threshold = 92.5% “11” IN2 to OUT2 overcurrent threshold = 90% Bit [1:0] “00” IN1 to OUT1 overcurrent threshold = 97.5% “01” IN1 to OUT1 overcurrent threshold = 95% “10” IN1 to OUT1 overcurrent threshold = 92.5% “11” IN1 to OUT1 overcurrent threshold = 90% 34 ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit REGISTER ADDRESS EEPROM MEMORY ADDRESS READ/WRITE MAX6876 Table 16. Register Map (continued) DESCRIPTION Bit [7:6] “00” overcurrent timer value = 12.5ms “01” overcurrent timer value = 50ms “10” overcurrent timer value = 100ms “11” overcurrent timer value = 200ms Bit 5—If 1, overcurrent monitoring on OUT1 is enabled If 0, no overcurrent monitoring on OUT1 0Eh 2Eh R/W Bit 4—If 1, overcurrent monitoring on OUT2 is enabled If 0, no overcurrent monitoring on OUT2 Bit 3—If 1, overcurrent monitoring on OUT3 is enabled If 0, no overcurrent monitoring on OUT3 Bit 2—If 1, overcurrent monitoring on OUT4 is enabled If 0, no overcurrent monitoring on OUT4 Bit [1:0] Not used Bit [7:5] “000” gate1-delay timer value = 25µs “001” gate1-delay timer value = 12.5ms “010” gate1-delay timer value = 25.0ms “011” gate1-delay timer value = 50.0ms “100” gate1-delay timer value = 100.0ms “101” gate1-delay timer value = 200.0ms “110” gate1-delay timer value = 400.0ms “111” gate1-delay timer value = 1600.0ms 0Fh 2Fh R/W Bit 4—Not used Bit 3—OC1 overcurrent fault (read only for register address). If 1, OC1 is overcurrent. If 0, OC1 is not overcurrent. Bit 2—OC2 overcurrent fault (read only for register address). If 1, OC2 is overcurrent. If 0, OC2 is not overcurrent. Bit 1—OC3 overcurrent fault (read only for register address). If 1, OC3 is overcurrent. If 0, OC3 is not overcurrent. Bit 0—OC4 overcurrent fault (read only for register address). If 1, OC4 is overcurrent. If 0, OC4 is not overcurrent. Bit [7:6] “00” IN4 to OUT4 power-good threshold = 95% “01” IN4 to OUT4 power-good threshold = 92.5% “10” IN4 to OUT4 power-good threshold = 90% “11” IN4 to OUT4 power-good threshold = 87.5% 10h 30h R/W Bit [5:4] “00” IN3 to OUT3 power-good threshold = 95% “01” IN3 to OUT3 power-good threshold = 92.5% “10” IN3 to OUT3 power-good threshold = 90% “11” IN3 to OUT3 power-good threshold = 87.5% Bit [3:2] “00” IN2 to OUT2 power-good threshold = 95% “01” IN2 to OUT2 power-good threshold = 92.5% “10” IN2 to OUT2 power-good threshold = 90% “11” IN2 to OUT2 power-good threshold = 87.5% Bit [1:0] “00” IN1 to OUT1 power-good threshold = 95% “01” IN1 to OUT1 power-good threshold = 92.5% “10” IN1 to OUT1 power-good threshold = 90% “11” IN1 to OUT1 power-good threshold = 87.5% ______________________________________________________________________________________ 35 MAX6876 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit Table 16. Register Map (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS READ/WRITE DESCRIPTION Bit 7—If 1, OUT1 also controls RESET If 0, OUT1 does not control RESET Bit 6—If 1, OUT2 also controls RESET If 0, OUT2 does not control RESET Bit 5—If 1, OUT3 also controls RESET If 0, OUT3 does not control RESET 11h 31h R/W Bit 4—If 1, OUT4 also controls RESET If 0, OUT4 does not control RESET Bit [3:1] “000” reset timer value = 25µs “001” reset timer value = 12.5ms “010” reset timer value = 25.0ms “011” reset timer value = 50.0ms “100” reset timer value = 100.0ms “101” reset timer value = 200.0ms “110” reset timer value = 400.0ms “111” reset timer value = 1600.0ms Bit 0. If 1, selects external reference, if 0 internal reference selected Bit [7:6] “00” track/sequence slew rate (rise or fall) = 800V/s “01” track/sequence slew rate (rise or fall) = 400V/s “10” track/sequence slew rate (rise or fall) = 200V/s “11” track/sequence slew rate (rise or fall) = 100V/s 12h 32h R/W Bit [5:3] Not used Bit 2—Reserved (write 0’s for EEPROM writes) Bit 1—Reserved (write 0’s for EEPROM writes) Bit 0—Reserved (write 0’s for EEPROM writes) Bit 7—If 1, reverse order of track/sequence power-down If 0, GATE_ fast pulldown Bit 6—If 1, OUT1 pulldown with 100Ω If 0, OUT1 100Ω pulldown disabled Bit 5—If 1, it is possible to discharge OUT2 with a pulldown If 0, no pulldown is allowed 13h 33h R/W Bit 4—If 1, it is possible to discharge OUT3 with a pulldown If 0, no pulldown is allowed Bit 3—If 1, it is possible to discharge OUT4 with a pulldown If 0, no pulldown is allowed Bit 2—If 1, configuration registers are locked If 0, configuration registers unlocked Bit [1:0] not used 36 14h 34h — Reserved. Should not be overwritten. 15h 35h — Reserved. Should not be overwritten. 16h 36h — Reserved. Should not be overwritten. ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit MAX6876 Table 16. Register Map (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS READ/WRITE 17h 37h — 18h 38h — 19h 39h — 1Ah 3Ah — 1Bh 3Bh — 1Ch 3Ch — DESCRIPTION Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. 1Dh 3Dh — Reserved. Should not be overwritten. Reserved. Should not be overwritten. 1Eh 3Eh — Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. 1Fh 3Fh — Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Reserved. Should not be overwritten. Applications Information Layout and Bypassing For better noise immunity, bypass each of the voltagedetector inputs to GND with 0.1µF capacitors installed as close to the device as possible. Bypass ABP to GND with 1µF capacitors installed as close to the device as possible. ABP is an internally generated voltage and should not be used to supply power to external circuitry. Configuration Latency Period A delay of less than 5µs occurs between writing to the configuration registers and the time when these changes actually take place, unless when changing one of the voltage detector’s thresholds. Changing a voltage-detector threshold typically takes 150µs. When changing EEPROM contents, software reboot or cycling of power is required for these changes to transfer to volatile memory. Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 37 EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit MAX6876 Typical Application Circuits IN1 OUT1 IN2 OUT2 IN3 OUT3 IN4 OUT4 IN1 IN2 IN3 VCC IN4 GATE1 GATE2 GATE3 GATE4 OUT1 OUT2 FAULT OUT3 HOLD MAX6876 SYNCH OUT4 ENABLE ABP IN1 REM GND SDA 5V IN2 3.0V 1.8V IN3 IN4 1V IN1 IN2 IN3 VPULLUP RESET TRKEN SCL A0 A1 OUT1 IN5 OUT2 IN6 OUT3 IN7 OUT4 IN8 IN4 GATE1 GATE2 GATE3 GATE4 OUT1 OUT2 OUT3 OUT4 SYNCH (OUT) PG_ OUT5 3.3V OUT6 2.5V 1.5V OUT7 OUT8 0.75V IN1 IN2 SYNCH (IN) HOLD HOLD FAULT FAULT IN3 IN4 GATE1 GATE2 GATE3 GATE4 OUT1 OUT2 OUT3 OUT4 SLAVE MASTER VCC VCC TRKEN ABP ENABLE ABP ENABLE TRKEN ALWAYS ON 3.3V NOTE: CONFIGURING THE MAX6876 FOR MASTER/SLAVE OPERATION. 38 ______________________________________________________________________________________ EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit QFN THIN 6x6x0.8.EPS D2 D CL D/2 b D2/2 k E/2 E2/2 (NE-1) X e E CL E2 k e L (ND-1) X e e L CL CL L1 L L e A1 A2 e A PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 39 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX6876 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)