MAX6902ETA+T

19-2134; Rev 3; 1/08 SPI-Compatible RTC in a TDFN Features The MAX6902 SPI™-compatible real-time clock contains a real-time clock/calendar and 31 x 8 bits of static random-access memory (SRAM). The real-time clock/calendar provides seconds, minutes, hours, day, date, month, year, and century information. A time/date programmable polled ALARM is included in the MAX6902. The end-of-the-month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year up to the year 2100. The clock operates in either the 24hr or 12hr format with an AM/PM indicator. The MAX6902 operates with a supply voltage of +2V to +5.5V, is available in the ultra-small 8-pin TDFN package, and works over the -40°C to +85°C industrial temperature range. ♦ Real-Time Clock Counts Seconds, Minutes, Hours, Day of Week, Date of Month, Month, Year, and Century ♦ Leap-Year Compensation Valid up to Year 2100 ♦ +2V to +5.5V Wide Operating Voltage Range ♦ SPI Interface: 4MHz at 5V; 1MHz at 2V ♦ 31 x 8-Bit SRAM for Scratchpad Data Storage ♦ Uses Standard 32.768kHz, 12.5pF Watch Crystal ♦ Low Timekeeping Current (400nA at 2V) ♦ Single-Byte or Multiple-Byte (Burst Mode) Data Transfer for Read or Write of Clock Registers or SRAM ♦ Ultra-Small 8-Pin 3mm x 3mm x 0.8mm TDFN Package ♦ Programmable Time/Date Polled ALARM Function ♦ No External Crystal Bias Resistors or Capacitors Required Applications Point-of-Sale Equipment Ordering Information Intelligent Instruments Fax Machines PART Battery-Powered Products MAX6902ETA+T Portable Instruments TEMP RANGE PINPACKAGE TOP MARK -40°C to +85°C 8 TDFN +AGT +Denotes lead-free package. Related Real-Time Clock Products ALARM FUNCTION OUTPUT FREQUENCY PINPACKAGE — — 6 TDFN Polled 32kHz 8 TDFN — 8 TDFN PART SERIAL INTERFACE SRAM MAX6900 I2C compatible 31 ✕ 8 MAX6901 3 Wire 31 ✕ 8 Polled MAX6902 SPI compatible 31 ✕ 8 Pin Configuration Typical Operating Circuit +3.3V 0.1μF TOP VIEW 6 VCC +3.3V + X1 8 MAX6902 1 μc 5 2 3 SCLK X2 CS DOUT DIN 7 32.768kHz CRYSTAL SCLK 1 DOUT 2 4 X1 7 X2 6 VCC 5 CS MAX6902 DIN 3 GND 4 GND 8 EXPOSED PADDLE TDFN SPI is a trademark of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX6902 General Description MAX6902 SPI-Compatible RTC in a TDFN ABSOLUTE MAXIMUM RATINGS VCC to GND ..............................................................-0.3V to +6V All Other Pins to GND ................................-0.3V to (VCC + 0.3V) Current into Any Pin..........................................................±20mA Rate of Rise, VCC ............................................................100V/µs Continuous Power Dissipation (TA = +70°C) 8-Pin TDFN (derate 24.4mW/°C above +70°C) ..........1951.0mW Junction Temperature .....................................................+150°C Storage Temperature Range…………………… -65°C to +150°C ESD Protection (all pins, Human Body Model) ..................2000V Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +2.0V to +5.5V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Operating Voltage Range VCC Active Supply Current (Note 2) ICC Timekeeping Supply Current (Note 3) ITK CONDITIONS MIN TYP 2 MAX UNITS 5.5 V VCC = +2V 0.3 VCC = +5V 1.1 VCC = +2V 0.4 1.05 VCC = +3.6V 0.8 2.1 VCC = +5V 1.3 4.2 mA µA SPI DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIL VCC = +2V 1.4 VCC = +5V 2.2 V VCC = +2V 0.6 VCC = +5V 0.8 VIN = 0 to VCC -10 Input Capacitance 10 10 V nA pF SPI DIGITAL OUTPUTS (DOUT) Output Capacitance 2 15 Output Low Voltage VOL Output High Voltage VOH pF VCC = +2.0V, ISINK = 1.5mA 0.4 VCC = +5.0V, ISINK = 4mA 0.4 VCC = +2.0V, ISOURCE = -0.4mA 1.8 VCC = +5.0V, ISOURCE = -1mA 4.5 _______________________________________________________________________________________ V V SPI-Compatible RTC in a TDFN (VCC = +2.0V to +5.5V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Figure 5, Notes 1, 4) PARAMETER OSCILLATOR SYMBOL CONDITIONS MIN TYP MAX UNITS X1 to Ground Capacitance 25 pF X2 to Ground Capacitance 25 pF SPI SERIAL TIMING Maximum Input Rise Time trIN DIN, SCLK, CS 2 μs Maximum Input Fall Time tfIN DIN, SCLK, CS 2 μs 10 ns 10 ns Output Rise Time trOUT DOUT, CLOAD = 100pF Output Fall Time tfOUT DOUT, CLOAD = 100pF VCC = +2V 1000 VCC = +5V 238 ns SCLK Period tCP SCLK High Time tCH 100 ns SCLK Low Time tCL 100 ns SCLK Fall to DOUT Valid tDO DIN to SCLK Setup Time tDS 100 ns DIN to SCLK Hold Time tDH 2 ns SCLK Rise to CS Rise Hold Time tCSH 2 ns CS High Pulse Width tCSW 200 ns CS High to DOUT High Impedance tCSZ CS to SCLK Setup Time tCSS CLOAD = 100pF 100 100 100 ns ns ns Note 1: All parameters are 100% tested at TA = +25°C. Limits over temperature are guaranteed by design and characterization and not production tested. Note 2: ICC is specified with DOUT open, CS = DIN = GND, SCLK = 4MHz at VCC = +5V; SCLK = 1MHz at VCC = +2.0V. Note 3: Timekeeping current is specified with CS = VCC, SCLK = DIN = GND, DOUT = 100kΩ to GND. Note 4: All values referred to VIH min and VIL max levels. _______________________________________________________________________________________ 3 MAX6902 AC ELECTRICAL CHARACTERISTICS Detailed Description Typical Operating Characteristic (TA = +25°C, unless otherwise noted.) TIMEKEEPING CURRENT vs. SUPPLY VOLTAGE MAX6902 toc01 10.0 SUPPLY CURRENT (μA) MAX6902 SPI-Compatible RTC in a TDFN 1.0 The MAX6902 is a real-time clock/calendar with an SPIcompatible interface and 31 x 8 bits of SRAM. It provides seconds, minutes, hours, day of the week, date of the month, month, and year information, held in seven 8bit timekeeping registers (Functional Diagram). An onchip 32.768kHz oscillator circuit requires only a single external crystal to operate. Table 1 specifies the parameters for the external crystal, and Figure 1 shows a functional schematic of the oscillator circuit. The MAX6902’s register addresses and definitions are described in Figure 2 and in Table 2. Time and calendar data are stored in the registers in binary-coded decimal (BCD) format. A polled alarm function is included for scheduled timing of user-defined times or intervals. 0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) Table 1. Acceptable Quartz Crystal Parameters PARAMETER Pin Description PIN NAME FUNCTION 1 SCLK Serial Clock Input. SPI clock for DIN and DOUT data transfers. 2 DOUT SPI Data Output 3 DIN SPI Data Input 4 GND Ground 5 CS Chip Select Input. Active low for valid data transfers. 6 VCC Power-Supply Pin. Bypass VCC to GND with a 0.1µF capacitor. 7 X2 External 32.768kHz Crystal 8 X1 — EP External 32.768kHz Crystal Exposed Paddle. Internally connected to GND. Connect to GND, but do not use as the sole ground connection point or leave unconnected. SYMBOL MIN Frequency f Equivalent Series Resistance (ESR) RS 40 Parallel Load Capacitance CL 11.2 Q Factor Q 40,000 TYP 12.5 60 kΩ 13.7 pF MAX6902 25pF X1 X2 EXTERNAL CRYSTAL Figure 1. Crystal Oscillator Circuit Schematic _______________________________________________________________________________________ UNITS kHz 60,000 25pF 4 MAX 32.768 SPI-Compatible RTC in a TDFN FUNCTION MAX6902 REGISTER ADDRESS REGISTER DEFINITION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 D6 D5 D4 00-59 0 10 SEC *POR STATE 0 D3 D2 D1 D0 CLOCK SECONDS RD 0 0 0 0 0 0 1 /W MINUTES RD 0 0 0 0 0 1 1 /W HOURS RD 0 00-59 *POR STATE 0 0 0 1 0 1 0 ALM OUT DATE RD 0 0 0 0 1 1 1 /W MONTH RD 0 0 0 1 0 0 1 /W DAY RD 0 0 0 1 0 1 1 /W YEAR RD 0 0 0 1 1 0 1 /W CONTROL RD 0 0 0 00-23 12/24 01-12 1/0 0 1 1 1 CENTURY RD 0 0 1 0 0 1 1 0 0 10 HR 10 A/P HR 0/1 0 01-28/29 01-30 0-31 0 0 10 DATE *POR STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 HR 0 0 0 0 1 DATE 0 0 0 1 01-12 0 0 0 10M *POR STATE 0 0 0 0 0 01-07 0 0 0 0 0 WEEK DAY *POR STATE 0 0 0 0 0 0 00-99 *POR STATE /W 0 0 1 /W 0 1 MIN *POR STATE *POR STATE 0 0 10 MIN 0 /W 0 1 SEC 10 YEAR 0 0 0 1 1 1 YEAR 0 1 1 1 0 0 0 0 WP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 00-99 *POR STATE 1 MONTH 1000 YEAR 0 0 0 100 YEAR 0 0 1 Note: *POR STATE defines power-on reset state of register contents. Figure 2. Register Address Definition (Sheet 1 of 3) _______________________________________________________________________________________ 5 0 1 0 /W RESERVED Do not write to this location. RD 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 *POR STATE 0 0 0 0 0 1 1 1 00-59 0 *POR STATE 0 00-59 0 *POR STATE 0 1 *POR STATE 0 1 0 1 1 1 /W D5 D4 D3 D2 D1 D0 SECOND 1 VALUE MINUTE 0 D6 DATE RD 0 D7 MONTH ALARM CONFIG A7 A6 A5 A4 A3 A2 A1 A0 DAY FUNCTION REGISTER DEFINITION YEAR REGISTER ADDRESS HOUR MAX6902 SPI-Compatible RTC in a TDFN 0 0 0 ALARM THRESHOLDS SECONDS RD 0 0 1 1 0 0 1 /W MINUTES RD 0 0 1 1 0 1 1 /W HOURS RD 0 0 1 1 1 0 1 00-23 12/24 01-12 1/0 10 SEC 1 DATE RD 0 0 1 1 1 1 1 /W MONTH RD 0 1 0 0 0 0 1 /W DAY RD 0 1 0 0 0 1 1 /W YEAR RD 0 1 0 0 1 0 1 /W CLOCK BURST RD 0 1 1 1 1 1 1 1 1 1 1 1 1 HR 1 0 01-28/29 01-30 01-31 0 0 *POR STATE 0 0 1 01-12 0 0 0 10M *POR STATE 0 0 0 1 1 1 01-07 0 0 0 0 0 WEEK DAY *POR STATE 0 0 0 0 0 1 00-99 1 1 1 10 DATE 1 1 1 1 1 1 DATE 1 1 1 1 1 MONTH 10 YEAR 1 1 1 1 1 1 1 YEAR 1 1 1 1 /W Figure 2. Register Address Definition (Sheet 2 of 3) 6 1 1 MIN 10 10 HR HR A/P 0/1 1 1 *POR STATE *POR STATE 1 1 10 MIN 1 0 /W 1 1 SEC _______________________________________________________________________________________ 1 1 SPI-Compatible RTC in a TDFN FUNCTION MAX6902 REGISTER ADDRESS REGISTER DEFINITION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 D6 D5 D4 D3 D2 D1 D0 RAM RAM 0 RD 1 0 0 0 0 0 1 RAM DATA 0 x x x x x x x x x x x x /W • • • • • • • • • • RAM 30 RD 1 • 1 1 1 1 0 1 1 1 1 1 1 1 RAM DATA 30 • x x x x /W RAM BURST RD 1 /W Note: *POR STATE defines power-on reset state of register contents. Figure 2. Register Address Definition (Sheet 3 of 3) Table 2. Register Address and Description WRITE (HEX) READ (HEX) DESCRIPTION POR CONTENTS (HEX) 01 81 Seconds 00 03 83 Minutes 00 05 85 Hours 00 07 87 Date 01 09 89 Month 01 0B 8B Day 01 0D 8D Year 70 0F 8F Control 00 13 93 Century 19 15 95 Alarm Configuration 00 17 97 Reserved 07 7F 19 99 Seconds Alarm Threshold 1B 9B Minutes Alarm Threshold 7F 1D 9D Hours Alarm Threshold BF 3F 1F 9F Date Alarm Threshold 21 A1 Month Alarm Threshold 1F 23 A3 Day Alarm Threshold 07 25 A5 Year Alarm Threshold FF 3F BF Clock Burst Not applicable _______________________________________________________________________________________ 7 MAX6902 SPI-Compatible RTC in a TDFN Table 2. Register Address and Description (continued) 8 WRITE (HEX) READ (HEX) DESCRIPTION POR CONTENTS (HEX) 41 C1 RAM 0 Indeterminate 43 C3 RAM 1 Indeterminate 45 C5 RAM 2 Indeterminate 47 C7 RAM 3 Indeterminate 49 C9 RAM 4 Indeterminate 4B CB RAM 5 Indeterminate 4D CD RAM 6 Indeterminate 4F CF RAM 7 Indeterminate 51 D1 RAM 8 Indeterminate 53 D3 RAM 9 Indeterminate 55 D5 RAM 10 Indeterminate 57 D7 RAM 11 Indeterminate 59 D9 RAM 12 Indeterminate 5B DB RAM 13 Indeterminate 5D DD RAM 14 Indeterminate 5F DF RAM 15 Indeterminate 61 E1 RAM 16 Indeterminate 63 E3 RAM 17 Indeterminate 65 E5 RAM 18 Indeterminate 67 E7 RAM 19 Indeterminate 69 E9 RAM 20 Indeterminate 6B EB RAM 21 Indeterminate 6D ED RAM 22 Indeterminate 6F EF RAM 23 Indeterminate 71 F1 RAM 24 Indeterminate 73 F3 RAM 25 Indeterminate 75 F5 RAM 26 Indeterminate 77 F7 RAM 27 Indeterminate 79 F9 RAM 28 Indeterminate 7B FB RAM 29 Indeterminate 7D FD RAM 30 Indeterminate 7F FF RAM Burst Not applicable _______________________________________________________________________________________ SPI-Compatible RTC in a TDFN Address/Command Byte Each data transfer into or out of the MAX6902 is initiated by an Address/Command byte. The Address/Command byte specifies which registers are to be accessed, and if the access is a read or a write. Figure 2 shows the Address/Command bytes and their associated registers, and Table 2 lists the hex codes for all read and write operations. The Address/Command bytes are input MSB (bit 7) first. Bit 7 specifies a write (logic 0) or read (logic 1). Bit 6 specifies register data (logic 0) or RAM data (logic 1). Bits 5–1 specify the designated register to be written or read. The LSB (bit 0) must be logic 1. If the LSB is a zero, writes to the MAX6902 are disabled. Clock Burst Mode Sending the Clock Burst Address/Command (3Fh for Write and BFh for Read), specifies burst-mode operation. In this mode, multiple bytes are read or written after a single Address/Command. The first seven clock/calendar registers (Seconds, Minutes, Hours, Date, Month, Day, and Year) and the Control register are consecutively read or written, starting with the MSB of the Seconds register. When writing to the clock registers in burst mode, all seven clock/calendar registers and the Control register must be written in order for the data to be transferred. See Example: Setting the Clock with a Burst Write. RAM Burst Mode Sending the RAM Burst Address/Command (F7h for Write, FFh for Read) specifies burst-mode operation. In this mode, the 31 RAM locations can be consecutively read or written, starting at 41h for Writes, and C1h for Reads. A Burst Read outputs all 31 bytes of RAM. When writing to RAM in burst mode, it is not necessary to write all 31 bytes for the data to transfer; each complete byte written is transferred to RAM. When reading from RAM, data are output until all 31 bytes have been read, or until CS is driven high. with a Seconds register increment. The updated time data are loaded into the timekeeping registers after the rising edge of CS, at the end of the SPI write operation. An incomplete write operation aborts the update procedure, and the contents of the input buffer are discarded. The timekeeping registers reflect the new time beginning with the first Seconds register increment after the rising edge of CS. Although both Single Writes and Burst Writes are possible, the best way to write to the timekeeping registers is with a Burst Write. With a Burst Write, the main timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year) and the Control register are written sequentially following the Address/Command byte. They must be written as a group of eight registers, with 8 bits each, for proper execution of the Burst Write function. All seven timekeeping registers are simultaneously loaded into the clock counters by the rising edge of CS, at the end of the SPI write operation. For a normal burst data transfer, the worst-case error that can occur between the actual time and the written time update is 1s. If single write operations are used to enter data into the timekeeping registers, error checking is required. If not writing to the Seconds register, begin by reading the Seconds register and save it as initial-seconds. Then write to the required timekeeping registers, and finally read the Seconds register again (final-seconds). Check to see that final-seconds is equal to initial-seconds. If not, repeat the write process. If writing to the Seconds register, update the Seconds register first, and then read it back and store its value (initial-seconds). Update the remaining timekeeping registers and then read the Seconds register again (final-seconds). Check to see that final-seconds is equal to initial-seconds. If not, repeat the write process. Note: After writing to any time or date register, no read or write operations are allowed for 45µs. AM/PM and 12Hr/24Hr Mode Writing to the Timekeeping Registers Bit 7 of the Hours register selects 12hr or 24hr mode. When high, 12hr mode is selected. In 12hr mode, bit 5 is the AM/PM bit, logic high for PM. In 24hr mode, bit 5 is the second 10hr bit, logic high for hours 20 through 23. The time and date are set by writing to the timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year, and Century). During a write operation, an input buffer accepts the new time data while the timekeeping registers continue to increment normally, based on the crystal counter. The buffer also keeps the timekeeping registers from changing as the result of an incomplete write operation, and collision-detection circuitry ensures that a Time Write does not occur coincident Bit 7 of the Control register is the Write-Protect bit. When high, the Write-Protect bit prevents write operations to all registers except itself. After initial settings are written to the timekeeping registers, set the WriteProtect bit to logic 1 to prevent erroneous data from entering the registers during power glitches or interrupted serial transfers. The lower 7 bits (bits 0–6) are Setting the Clock Write-Protect Bit _______________________________________________________________________________________ 9 MAX6902 Command and Control MAX6902 SPI-Compatible RTC in a TDFN unusable, and always read zero. Any data written to bits 0–6 are ignored. Bit 7 must be set to zero before a single write to the clock, before a write to RAM, or during a Burst Write to the clock. Example: Setting the Clock with a Burst Write To set the clock to 10:11:31PM, Thursday July 4th, 2002 with a burst write operation, write 3Fh as the Address/Command byte, followed by 8 bytes, 31h, 11h, B0h, 04h, 07h, 05h, 02h, and 00h (Figure 2). 3Fh is the Clock Burst Write Address/Command. The first byte, 31h, sets the Seconds register to 31. The second byte, 11h, sets the Minutes register to 11. The third byte, B0h, sets the Hours register to 12hr mode, and 10PM. The fourth byte, 04h, sets the Date register (day of the month) to the 4th. The fifth byte, 07h, sets the Month register to July. The sixth byte, 05h, sets the Day register (day of the week) to Thursday. The seventh byte, 02h, sets the Year register to 02. The eighth byte, 00h, clears the Write-Protect bit of the Control register to allow writing to the MAX6902. The Century register is not accessed with a Burst Write and therefore must be written to separately to set the century to 20. Note the Century register corresponds to the thousand and hundred digits of the current year and defaults to 19. Reading the Clock Reading the Timekeeping Registers The main timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year) can be read with either Single Reads or a Burst Read. In the MAX6902, a latch buffers each clock counter’s data. Clock counter data are latched by the SPI Read Command (on the falling edge of SCLK, after the Address/Command byte has been sent by the master to read a timekeeping register). Collision-detection circuitry ensures that this does not happen coincident with a Seconds counter increment to ensure accurate time data are being read. The clock counters continue to count and keep accurate time during the read operation. The simplest way to read the timekeeping registers is to use a Burst Read. In a Burst Read, the main timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year), and the Control register are read sequentially, in the order listed with the Seconds register first. They are read out as a group of eight registers, with 8 bits each. All timekeeping registers (except Century) are latched upon the receipt of the Burst Read command. The worst-case error between the “actual” time and the “read” time is 1s for a normal data transfer. 10 The timekeeping registers may also be read using Single Reads. If Single Reads are used, it is necessary to do some error checking on the receiving end, because it is possible that the clock counters could change during the Read operations, and report inaccurate time data. The potential for error is when the Seconds register increments before all the registers are read. For example, suppose a carry of 13:59:59 to 14:00:00 occurs during single read operations. The net data read could be 14:59:59, which is erroneous. To prevent errors from occurring with single read operations, read the Seconds register first (initial-seconds) and store this value for future comparison. After the remaining timekeeping registers have been read, reread the Seconds register (final-seconds). Check that the final-seconds value equals the initial-seconds value. If not, repeat the entire Single Read process. Using Single Reads at a 100kHz serial speed, it takes under 2.5ms to read all seven of the timekeeping registers, including two reads of the Seconds register. Example: Reading the Clock with a Burst Read To read the time with a Burst Read, send BFh as the Address/Command byte. Then clock out 8 bytes, Seconds, Minutes, Hours, Date of the month, Month, Day of the week, Year, and finally the Control byte. All data are output MSB first. Decode the required information based on the register definitions listed in Figure 2. Using the Alarm A polled alarm function is available by reading the ALM OUT bit. The ALM OUT bit is D7 of the Minutes timekeeping register. A logic 1 in ALM OUT indicates the Alarm function is triggered. There are eight registers associated with the alarm function—seven programmable Alarm Threshold registers and one programmable Alarm Configuration register. The Alarm Configuration register determines which Alarm Threshold registers are compared to the timekeeping registers, and the ALM OUT bit sets if the compared registers are equal. Figure 2 shows the function of each bit of the Alarm Configuration register. Placing a logic 1 in any given bit of the Alarm Configuration register enables the respective alarm function. For example, if the Alarm Configuration register is set to 0000 0011, ALM OUT is set when both the minutes and seconds indicated in the Alarm Threshold registers match the respective timekeeping registers. Once set, ALM OUT stays high until it is cleared by reading or writing to the Alarm Configuration register, or by reading or writing to any of the Alarm Threshold registers. The Alarm Configuration register is written with address 15h, and read with address 95h. ______________________________________________________________________________________ SPI-Compatible RTC in a TDFN The static RAM is 31 x 8 bits addressed consecutively in the RAM Address/Command space. Table 2 details the specific hex Address/Commands for Reads and Writes to each of the 31 locations of RAM. The contents of the RAM are static and remain valid for VCC down to 2V. All RAM data are lost if power is cycled. The WriteProtect Bit (bit 7 of the Control register), when high, disallows any writes to RAM. SPI-Compatible Serial Interface Interface the MAX6902 with a microcontroller using a serial, 4-wire, SPI interface. SPI is a synchronous bus for address and data transfer, and is used with Motorola or other microcontrollers that have an SPI port. Four connections are required for the interface: DOUT (Serial Data Out); DIN (Serial Data In); SCLK (Serial Clock); and CS (Chip Select). In an SPI application, the MAX6902 acts as a slave device and the microcontroller acts as the master. CS is asserted low by the microcontroller to initiate a transfer, and deasserted high to terminate a transfer. DIN transfers input data from the microcontroller to the MAX6902. DOUT transfers output data from the MAX6902 to the microcontroller. A shift clock, SCLK, is used to synchronize data movement between the microcontroller and the MAX6902. SCLK, which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus. The inactive clock polarity is usually programmable on the microcontroller side of the SPI interface. In the MAX6902, input data are latched on the positive edge, and output data are shifted out on the negative edge. There is one clock cycle for each bit transferred. Address and data bits are transferred in groups of eight. The SPI protocol allows for one of four combinations of serial clock phase and polarity from the microcontroller, through a 2-bit selection in its SPI Control register. The clock polarity is specified by the CPOL Control bit, which selects active-high or active-low clock, and has no significant effect on the transfer format. The Clock Phase Control bit, CPHA, selects one of two different transfer formats. The clock phase and polarity must be identical for the master and the slave. For the MAX6902, set the control bits to CPHA = 1 and CPOL = 1. This configures the system for data to be launched on the negative edge of SCLK and sampled on the positive edge. With CPHA equal to 1, CS can remain low between successive data byte transfers, allowing burst-mode data transfers to occur. Address and data bytes are shifted MSB first into DIN of the MAX6902, and out of DOUT. Data are shifted out at the negative edge of SCLK, and shifted in or sampled at the positive edge of SCLK. Any transfer requires an Address/Command byte followed by one or more bytes of data. Data are transferred out of DOUT for a read operation, and into DIN for a write operation. DOUT transmits data only after an Address/Command byte specifies a read operation; otherwise, it is high impedance. Data Transfer Write timing is shown in Figure 3. Data Transfer Read timing is shown in Figure 4. Detailed Read and Write Timing is shown in Figure 5. CS SCLK DIN 0 R* A5 A4 A3 A2 A1 1 D7 D6 D5 ADDRESS/COMMAND BYTE DOUT D4 D3 D2 D1 D0 DATA BYTE HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES. * R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0. Figure 3a. Single Write ______________________________________________________________________________________ 11 MAX6902 Using the On-Board RAM MAX6902 SPI-Compatible RTC in a TDFN CS SCLK DIN 0 R* 1 1 1 1 1 1 D7 D6 D5 ADDRESS/COMMAND BYTE** D4 D3 D2 D1 D0 D7 D6 D5 DATA BYTE 1 D4 D3 D2 D1 D2 D1 D0 DATA BYTE N HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES. DOUT * R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0. ** ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION. Figure 3b. Burst Write CS SCLK DIN 1 R* A5 A4 A3 A2 A1 1 ADDRESS/COMMAND BYTE HIGH IMPEDANCE DOUT D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE * R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0. Figure 4a. Single Read CS SCLK DIN 1 R* 1 1 1 1 1 1 ADDRESS/COMMAND BYTE** DOUT HIGH IMPEDANCE * R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0. ** ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION. D7 D6 D5 D4 D3 DATA BYTE 1 D2 D1 D0 D7 D6 D5 D4 D3 DATA BYTE N Figure 4b. Burst Read 12 ______________________________________________________________________________________ D0 SPI-Compatible RTC in a TDFN MAX6902 tCSH CS tCSS tCH tCL tCP tCSW SCLK tDH tDS D7 D6 D5 D0 DIN tCSZ D7 DOUT D0 tDO Figure 5. SPI Bus Timing Diagrams Chip Select CS serves two functions. First, CS turns on the control logic that allows access to the Shift register for Address/Command and data transfer. Second, CS provides a method of terminating either single-byte or multiple-byte data transfers. All data transfers are initiated by driving CS low. If CS is high, then DOUT is high impedance. Serial Clock A clock cycle on SCLK is a rising edge followed by a falling edge. For data input, data must be valid at DIN before the rising edge of the clock. For data outputs, bits are valid on DOUT after the falling edge of the clock. Data Output (Single-Byte Read and Burst Read) A read from the MAX6902 is initiated by an Address/Command Write from the microcontroller (master) to the MAX6902 (slave). The Address/Command Write portion of the data transfer is clocked into the MAX6902 on rising clock edges. Following the eighth falling clock edge of SCLK, after tDO (Figure 4) data begins to be output on DOUT of the MAX6902. Data bytes are output MSB first. Additional SCLK cycles transmit additional data bits, as long as CS remains low. This permits continuous burst-mode read capability. Applications Information Data Input (Single-Byte Write) Crystal Selection Following the eight SCLK cycles that input a Single-Byte Write Address/Command, data bits are input on the rising edges of the next eight SCLK cycles. Additional SCLK cycles are ignored. Input data MSB first. The MAX6902 is designed to use a standard 32.768kHz watch crystal. Table 1 details the recommended crystal requirements. Some suggested crystals are listed in Table 3. In addition to the specified SMT devices, some of the listed manufacturers also offer other package options. Data Input (Burst Write) Following the eight SCLK cycles that input a Burst-Write Address/Command, data bits are input on the rising edges of the following SCLK cycles. The number of clock cycles depends on whether the timekeeping registers or RAM are being written. A Clock Burst Write requires 1 Address/Command byte, 7 timekeeping data bytes, and 1 Control register byte. A Burst Write to RAM may be terminated after any complete data byte by driving CS high. Input data MSB first (Figure 3). Frequency Stability and Temperature Timekeeping accuracy of the MAX6902 is dependent on the frequency stability, of the external crystal. To determine frequency stability, use the parabolic curve in Figure 6 and the following equations: Δf = fk(T0 - T)2 where: Δf = change in frequency from +25°C (Hz) f = nominal crystal frequency (Hz) ______________________________________________________________________________________ 13 Table 3. 32.768kHz Surface-Mount Watch Crystals MANUFACTURER PART NO. MANUFACTURER TEMP. RANGE CL (pF) +25°C FREQUENCY TOLERANCE (ppm) Abracon Corporation ABS25-32.768-12.5-B-2-T -40°C to +85°C 12.5 ±20 Caliber Electronics AWS2A-32.768KHz, AWS2B-32.768KHz -20°C to +70°C 12.5 ±20 ECS INC International ECS-.327-12.5-17 -10°C to +60°C 12.5 ±20 Fox Electronics FSM327 -40°C to +85°C 12.5 ±20 M-tron SX2010/ SX2020 -20°C to +75°C 12.5 ±20 Raltron RSE-32.768-12.5-C-T -10°C to +60°C 12.5 ±20 SaRonix 32S12A -40°C to +85°C 12.5 ±20 k = parabolic curvature constant (-0.035 ±0.005ppm/°C2 for 32.768kHz watch crystals) T0 = turnover temperature (+25°C ±5°C for 32.768kHz watch crystals) T = temperature of interest (°C) For example: What is the worst-case change in oscillator frequency from +25°C ambient to +45°C ambient? Δfdrift = 32.768Hz × (-0.04ppm/ oC2 × (1× 10-6 )) × (20o C - 45o C)2 = -0.8192Hz ]] } {[ [ = {[1/[(32,768Hz - 0.8192Hz) / 32,768]] - 1s} / 1s Δt drift = 1/ (f + Δfdrift ) / 32,768 - 1s / 1s = 0.000025s / s Error due to 25°C initial crystal tolerance of ±20ppm: {[ [ ]] } Δtinitial = 1/ (f + Δfinitial ) / 32,768 - 1s / 1s ( ) Total timekeeping error per second: [ ]] } Δtinitial = 1/ (32,768 - 0.65536) / 32,768 - 1 / 1s = 0.000020s / s Δt total = Δt drift + Δtinitial Δt total = 0.000025s / s + 0.000020s / s = 0.000045s / s 14 -20 TEMPERATURE (°C) 0 20 40 60 80 100 -50 -100 -150 -250 TYPICAL TEMPERATURE CHARACTERISTICS (k = -0.035 ppm/°C2; TO = +25°C) Figure 6. Typical Temperature Curve for 32.768kHz Watch Crystal After 1 month that translates to: ⎛ hr ⎞ ⎛ min ⎞ ⎛ s ⎞ Δt = (31day)⎜ 24 ⎟ ⎜ 60 ⎟ (0.000045s/s) ⎟ ⎜ 60 hr ⎠ ⎝ min ⎠ ⎝ day ⎠ ⎝ =120.528s Δfinitial = 32,768Hz × -20ppm × (1 × 10-6 ) = 0.65536Hz {[ -40 -200 What is the worst-case timekeeping error per second? Error due to temperature drift: Δt drift 0 f (ppm) MAX6902 SPI-Compatible RTC in a TDFN Total worst-case timekeeping error at the end of 1 month at 45°C is about 120s or 2min (assumes negligible parasitic layout capacitance). Oscillator Start Time The MAX6902 oscillator typically takes 5s to 10s to begin oscillating. To ensure the oscillator is operating correctly, the software should validate proper timekeeping. This is accomplished by reading the Seconds register. Any reading of 1s or more from the POR value of zero seconds is a validation of proper startup. ______________________________________________________________________________________ SPI-Compatible RTC in a TDFN PCB Considerations The MAX6902 uses a very-low-current oscillator to minimize supply current. This causes the oscillator pins, X1 and X2, to be relatively high impedance. Exercise care to prevent unwanted noise pickup. Connect the 32.768kHz crystal directly across X1 and X2 of the MAX6902. To eliminate unwanted noise pickup, design the PCB using these guidelines (Figure 7): 1) Place the crystal as close to X1 and X2 as possible and keep the trace lengths short. 2) Place a guard ring around the crystal, X1 and X2 traces (where applicable), and connect the guard ring to GND; keep all signal traces away from beneath the crystal, X1, and X2. 3) Finally, an additional local ground plane can be added under the crystal on an adjacent PCB layer. The plane should be isolated from the regular PCB ground plane, and tied to ground at the MAX6902 ground pin. 4) Restrict the plane to be no larger than the perimeter of the guard ring. Do not allow this ground plane to contribute significant capacitance between X1 and X2. Power-On Reset The MAX6902 contains an integral POR circuit that ensures all registers are reset to a known state on power-up. Once VCC rises above 1.6V (typ), the POR circuit releases the registers for normal operation. When VCC drops to less than 1.6V (typ), the MAX6902 resets all register contents to the POR defaults (Figure 2). RESERVED Register Address/Command 17h is reserved for factory testing ONLY. Do not write to this register. If inadvertent writes are done to this register, cycle power to the MAX6902. Power-Supply Considerations For most applications, a 0.1µF capacitor from VCC to GND provides adequate bypassing for the MAX6902. A series resistor can be added to the supply line for operation in extremely harsh or noisy environments. Chip Information TRANSISTOR COUNT: 26,418 PROCESS: CMOS ______________________________________________________________________________________ 15 MAX6902 Timekeeping Current When DOUT is high impedance (CS = high or during a DIN transfer segment), there is a potential for increased timekeeping current (up to 100x) if DOUT is allowed to float. If minimum timekeeping current is desired, then ensure DOUT is not allowed to float. The microcontroller port pin attached to DOUT could be configured as an input with a weak pullup. An alternate solution is to use a 100kΩ, or less, pulldown or pullup resistor (for microcontroller port pins with ≤1µA input leakage). MAX6902 SPI-Compatible RTC in a TDFN GROUND PLANE VIA CONNECTION * VCC PLANE VIA CONNECTION GUARD RING GROUND PLANE VIA CONNECTION * 0.1μF SM CAP * ** ** * MAX6902 * * * * * ** 2 LOCAL GROUND PLANE ** LAYER CONNECT ONLY TO PIN 4 SM WATCH CRYSTAL GROUND PLANE VIA * ** * GROUND PLANE VIA CONNECTION *LAYER 1 TRACE Figure 7. MAX6902 Crystal PCB Layout 16 ______________________________________________________________________________________ SPI-Compatible RTC in a TDFN X1 X2 OSCILLATOR 32.768kHz 1Hz DIVIDER SECONDS MINUTES HOURS DATE VCC GND CONTROL LOGIC MONTH DAY SCLK DIN DOUT CS YEAR INPUT SHIFT REGISTERS CONTROL ADDRESS REGISTER CENTURY ALARM CONFIG 31x 8 RAM RESERVED ALARM THRESHOLDS CLOCK BURST RAM BURST ALARM OUT ALARM CONTROL LOGIC ______________________________________________________________________________________ 17 MAX6902 Functional Diagram Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 6, 8, &10L, DFN THIN.EPS MAX6902 SPI-Compatible RTC in a TDFN 18 ______________________________________________________________________________________ SPI-Compatible RTC in a TDFN COMMON DIMENSIONS PACKAGE VARIATIONS SYMBOL MIN. MAX. PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e A 0.70 0.80 T633-2 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF D 2.90 3.10 T833-2 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF E 2.90 3.10 T833-3 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF A1 0.00 0.05 T1033-1 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF 0.40 T1033-2 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF L 0.20 k 0.25 MIN. T1433-1 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF A2 0.20 REF. T1433-2 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF ______________________________________________________________________________________ 19 MAX6902 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Revision History REVISION NUMBER REVISION DATE 0 — Initial release 1 — — — 2 12/06 — 1, 4, 15, 18, 19 3 1/08 Updated Timekeeping Supply Current in DC Electrical Characteristics and Package Information outline; various style edits. 2, 15, 16, 18, 19 DESCRIPTION PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX6902 MAX6902 SPI-Compatible RTC in a TDFN