MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
General Description
The MAX7034 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitude-shiftkeyed (ASK) data in the 300MHz to 450MHz frequency
range (including the popular 315MHz and 433.92MHz frequencies). The receiver has an RF sensitivity of -114dBm.
With few external components and a low-current powerdown mode, it is ideal for cost-sensitive and power-sensitive applications typical in the automotive and consumer
markets. The MAX7034 consists of a low-noise amplifier
(LNA), a fully differential image-rejection mixer, an onchip phase-locked loop (PLL) with integrated voltagecontrolled oscillator (VCO), a 10.7MHz IF limiting amplifier
stage with received-signal-strength indicator (RSSI), and
analog baseband data-recovery circuitry.
The MAX7034 is available in a 28-pin (9.7mm x 4.4mm)
TSSOP package and is specified over the automotive
(-40°C to +125°C) temperature range.
Applications
●● Automotive Remote
Keyless Entry
●● Security Systems
●● Garage Door Openers
●●
●●
●●
●●
Home Automation
Remote Controls
Local Telemetry
Wireless Sensors
Features
●● Optimized for 315MHz or 433.92MHz Band
●● Operates from Single +3.3V/+5.0V Supply
●● Selectable Image-Rejection Center Frequency
●● Selectable x64 or x32 fLO/fXTAL Ratio
●● Low (< 6.7mA) Operating Supply Current
●● < 3.0μA Low-Current Power-Down Mode for Efficient
Power Cycling
●● 250μs Startup Time
●● Built-In 44dB RF Image Rejection
●● Excellent Receive Sensitivity Over Temperature
●● -40°C to +125°C Operation
●● -40°C to +105°C Operation (3.0V to 3.6V Supply)
Ordering Information and Typical Application Circuit
appear at end of data sheet.
Pin Configuration
TOP VIEW
XTAL1 1
+
28 XTAL2
AVDD 2
27 SHDN
LNAIN 3
26 PDOUT
25 DATAOUT
LNASRC 4
AGND 5
LNAOUT 6
MAX7034
23 DSP
AVDD 7
22 DFFB
MIXIN1 8
21 OPP
MIXIN2 9
20 DSN
AGND 10
19 DFO
IRSEL 11
18 IFIN2
MIXOUT 12
17 IFIN1
DGND 13
16 XTALSEL
DVDD 14
15 EN_REG
TSSOP
19-3109; Rev 4; 11/16
24 VDD5
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Absolute Maximum Ratings
VDD5 to AGND......................................................-0.3V to +6.0V
AVDD to AGND.....................................................-0.3V to +4.0V
DVDD to DGND.....................................................-0.3V to +4.0V
AGND to DGND....................................................-0.1V to +0.1V
IRSEL, DATAOUT, XTALSEL,
SHDN, EN_REG to AGND.................. -0.3V to (VDD5 + 0.3V)
All Other Pins to AGND.........................-0.3V to (VDVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C)...1025.6mW
Operating Temperature Range.......................... -40°C to +125°C
Storage Temperature Range............................. -65°C to +150°C
Junction Temperature.......................................................+150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
(Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied. TA = -40°C to +125°C, unless otherwise noted. Typical values
are at VDD5 = +5.0V and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Supply Voltage
VDD5
Supply Current
IDD
Shutdown Supply Current
Input-Voltage Low
Input-Voltage High
Input Logic Current High
ISHDN
CONDITIONS
MIN
TYP
MAX
UNITS
+5.0V nominal supply voltage
4.5
5.0
5.5
V
fRF = 315MHz
6.7
8.2
fRF = 433MHz
7.2
8.7
VSHDN = VDD5
VSHDN = 0V
3
VIL
VIH
EN_REG, SHDN
VDD5 0.4
XTALSEL
VDVDD
- 0.4
IIH
Image-Reject Select Voltage
(Note 2)
8
µA
0.4
V
V
15
fRF = 433MHz, VIRSEL = VDVDD
fRF = 375MHz, VIRSEL = VDVDD/2
mA
µA
VDVDD
- 0.4
VDVDD
- 1.5
1.1
fRF = 315MHz, VIRSEL = 0V
V
0.4
DATAOUT Voltage-Output Low
VOL
ISINK = 10µA
0.125
V
DATAOUT Voltage-Output High
VOH
ISOURCE = 10µA
VDD5 0.125
V
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Maxim Integrated │ 2
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
AC Electrical Characteristics
(Typical Application Circuit, VDD5 = +4.5V to +5.5V, all RF inputs are referenced to 50Ω, fRF = 433.92MHz, TA = -40°C to +125°C,
unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Startup Time
tON
Receiver Input Frequency Range
fRF
Time for valid signal detection after VSHDN
= VDD5. Does not include baseband filter
settling.
250
300
Maximum Receiver Input Level
450
0
Sensitivity at TA = +25°C (Note 3)
Sensitivity at TA = +125°C
(Note 3)
Maximum Data Rate
µs
315MHz
-114
434MHz
-113
315MHz
-113
434MHz
-110
MHz
dBm
dBm
dBm
Manchester coded
33
NRZ coded
66
330Ω IF filter load
45
dB
-50
dBm
330
Ω
kbps
LNA/MIXER
LNA/Mixer Voltage Gain (Note 4)
LNA/Mixer Input-Referred 1dB
Compression Point
Mixer Output Impedance
ZOUT_MIX
Mixer Image Rejection
fRF = 434MHz, VIRSEL = VDVDD
42
fRF = 375MHz, VIRSEL = VDVDD/2
44
fRF = 315MHz, VIRSEL = 0V
44
dB
INTERMEDIATE FREQUENCY (IF)
Input Impedance
Operating Frequency
ZIN_IF
fIF
Bandpass response
330
Ω
10.7
MHz
3dB Bandwidth
10
MHz
RSSI Linearity
±0.5
dB
80
dB
RSSI Dynamic Range
RSSI Level
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PRFIN < -120dBm
1.15
PRFIN > -40dBm
2.2
V
Maxim Integrated │ 3
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
AC Electrical Characteristics (continued)
(Typical Application Circuit, VDD5 = +4.5V to +5.5V, all RF inputs are referenced to 50Ω, fRF = 433.92MHz, TA = -40°C to +125°C,
unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DATA FILTER
Maximum Bandwidth
50
kHz
100
kHz
Output High Voltage
VDD5
V
Output Low Voltage
0
V
DATA SLICER
Comparator Bandwidth
CRYSTAL OSCILLATOR
fRF = 433.92MHz
Crystal Frequency (Note 5)
fXTAL
fRF = 315MHz
VXTALSEL = 0V
6.6128
VXTALSEL = VDVDD
13.2256
VXTALSEL = 0V
4.7547
VXTALSEL = VDVDD
9.5094
Crystal Tolerance
Input Capacitance
Maximum Load Capacitance
From each pin to ground
CLOAD
MHz
50
ppm
6.2
pF
10
pF
Note 1: 100% tested at TA = +125°C. Guaranteed by design and characterization over entire temperature range.
Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass
to AGND with a 1nF capacitor in a noisy environment.
Note 3: Peak power level. BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz.
Note 4: The voltage conversion gain is measured with the LNA input matching inductor and the LNA/Mixer resonator in place, and
does not include the IF filter insertion loss.
Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for
XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = VDVDD.
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Maxim Integrated │ 4
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Typical Operating Characteristics
(Typical Application Circuit, VDD5 = +5.0V, fRF = 433.92MHz, TA = +25°C, unless otherwise noted.)
6.5
5.5
4.7
4.9
5.1
5.3
SUPPLY VOLTAGE (V)
SENSITIVITY vs. TEMPERATURE
433.92MHz
-108
315MHz
-110
-112
-114
-116
-118
-40
10
35
60
85
TEMPERATURE (°C)
49.7dB
IMAGE
REJECTION
35
25
15
LOWER SIDEBAND
5
-5
0
5
10
15
20
IF FREQUENCY (MHz)
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25
IF BANDWIDTH = 280kHz
1.60
2.40
1.20
1.20
60
-20
IMAGE REJECTION vs. RF FREQUENCY
fRF = 315MHz
50
40
30
20
0
1.00
0
52
fRF = 433.92MHz
MAX7034 toc03
-110
RSSI AND DELTA vs. IF INPUT POWER
MAX7034 toc06
RSSI
15
10
5
0
-5
DELTA
1.60
1.40
-140 -120 -100 -80 -60 -40
RF INPUT POWER (dBm)
-125
-120
-115
PEAK RF INPUT POWER (dBm)
2.20
1.40
10
30
-130
1.80
IMAGE REJECTION (dB)
45
0.01
1.80
MAX7034 toc07
UPPER SIDEBAND
55
500
2.00
1.00
110
350
400
450
RF FREQUENCY (MHz)
2.00
LNA/MIXER VOLTAGE GAIN
vs. IF FREQUENCY
65
LNA/MIXER VOLTAGE GAIN (dB)
-15
300
RSSI vs. RF INPUT POWER
2.20
RSSI (V)
SENSITIVITY (dBm)
-106
250
2.40
MAX7034 toc04
-104
315MHz
0.10
-40°C
5.0
5.5
1.00
RSSI (V)
4.5
-102
-120
+25°C
6.0
6.8
6.6
MAX7034 toc02
7.0
-10
-15
-20
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
IF INPUT POWER (dBm)
10
-25
IMAGE REJECTION vs. TEMPERATURE
50
48
315MHz
46
433.92MHz
44
42
280 300 320 340 360 380 400 420 440 460 480
RF FREQUENCY (MHz)
40
DELTA
-40°C
7.5
MAX7034 toc09
+25°C
10.00
BIT-ERROR RATE (%)
7.0
+125°C
433.92MHz
IMAGE REJECTION (dB)
7.2
+105°C
+125°C
8.0
100.00
MAX7034 toc05
+85°C
+85°C
+105°C
MAX7034 toc08
7.4
8.5
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
7.6
BIT-ERROR RATE
vs. PEAK RF INPUT POWER
SUPPLY CURRENT vs. RF FREQUENCY
9.0
MAX7034 toc01
7.8
SUPPLY CURRENT vs. SUPPLY VOLTAGE
-40
-15
10
35
60
85
TEMPERATURE (°C)
110
Maxim Integrated │ 5
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Typical Operating Characteristics (continued)
(Typical Application Circuit, VDD5 = +5.0V, fRF = 433.92MHz, TA = +25°C, unless otherwise noted.)
NORMALIZED IF GAIN
vs. IF FREQUENCY
40
30
S11 MAGNITUDE (dB)
-5
-10
-15
-20
WITH INPUT
MATCHING
10
0
-10
315MHz
315MHz
-24.1dB
-20
200MHz
-40
10
1
-50
100
200 230 260 290 320 350 380 410 440 470 500
IF FREQUENCY (MHz)
FREQUENCY (MHz)
PHASE NOISE
vs. OFFSET FREQUENCY
fRF = 315MHz
-40
-60
-80
-100
-120
-140
fRF = 433.92MHz
-20
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
-20
0
MAX7033 toc13
0
PHASE NOISE
vs. OFFSET FREQUENCY
MAX7033 toc14
-30
MAX7034 toc12
500MHz
20
-30
-25
S11 SMITH CHART PLOT OF RFIN
MAX7034 toc11
0
NORMALIZED IF GAIN (dB)
50
MAX7034 toc10
5
S11 MAGNITUDE PLOT OF RFIN
vs. FREQUENCY
-40
-60
-80
-100
-120
10
100
1k
10k
100k
1M
10M
-140
10
OFFSET FREQUENCY (Hz)
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
Pin Description
PIN
NAME
1
XTAL1
Crystal Input 1
2, 7
AVDD
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.4V lowdropout regulator, and should be bypassed to AGND with a 0.1µF capacitor as close as possible to
the pin. Pin 7 must be externally connected to the supply from pin 2, and bypassed to AGND with a
0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section and the Typical
Application Circuit).
3
LNAIN
Low-Noise Amplifier Input. See the Low-Noise Amplifier section.
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FUNCTION
Maxim Integrated │ 6
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Pin Description (continued)
PIN
NAME
4
LNASRC
5, 10
AGND
6
LNAOUT
8
MIXIN1
1st Differential Mixer Input. Connect to LC tank filter from LNAOUT through a 100pF capacitor. See
the Typical Application Circuit.
9
MIXIN2
2nd Differential Mixer Input. Connect to VDD3 side of the LC tank filter through a 100pF capacitor. See
the Typical Application Circuit.
11
IRSEL
Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set VIRSEL = DVDD to center image rejection at
434MHz. See the Mixer section.
12
MIXOUT
13
DGND
Digital Ground
14
DVDD
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01µF
capacitor as close as possible to the pin (see the Typical Application Circuit).
15
EN_REG
Regulator Enable. Connect to VDD5 to enable internal regulator. Pull this pin low to allow device
operation between +3.0V and +3.6V. See the Voltage Regulator section.
16
XTALSEL
Crystal Divider Ratio Select. Drive XTALSEL low to select fLO/fXTAL ratio of 64, or drive XTALSEL high
to select fLO/fXTAL ratio of 32.
17
IFIN1
1st Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
18
IFIN2
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF
capacitor as close as possible to the pin.
19
DFO
Data Filter Output
20
DSN
Negative Data Slicer Input
21
OPP
Noninverting Op-Amp Input for the Sallen-Key Data Filter
22
DFFB
Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23
DSP
Positive Data Slicer Input
24
VDD5
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For +5V
operation, VDD5 is the input to an on-chip voltage regulator whose +3.4V output appears at AVDD pin
2. (see the Voltage Regulator section and the Typical Application Circuit).
25
DATAOUT
26
PDOUT
27
SHDN
Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a
100kΩ resistor.
28
XTAL2
Crystal Input 2. Can also be driven with an external reference oscillator. See the Crystal Oscillator section.
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FUNCTION
Low-Noise Amplifier Source for external Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. See the Low-Noise Amplifier section.
Analog Ground
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter. See the Low-Noise
Amplifier section.
330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
Digital Baseband Data Output
Peak-Detector Output
Maxim Integrated │ 7
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Functional Diagram
LNASRC
4
LNAIN
AVDD
VDD5
AVDD
DVDD
DGND
AGND
3
IRSEL
11
EN_REG LNAOUT MIXIN1 MIXIN2
15
6
8
9
LNA
Q
3.4V REG
7
VCO
13
PHASE
DETECTOR
LOOP
FILTER
5, 10
1
2
CRYSTAL
DRIVER
XTALSEL
XTAL1 XTAL2
16
1
28
IFIN2
18
IF LIMITING
AMPS
IMAGE
REJECTION
I
DIVIDE
BY 64
14
IFIN1
17
0˚
2
24
MIXOUT
12
90˚
MAX7034
RSSI
DATA
FILTER
RDF2
100kΩ
DATA
SLICER
POWERDOWN
27
SHDN
RDF1
100kΩ
25
DATAOUT
20
23
19
DSN DSP DFO
26
21
22
PDOUT
OPP
DFFB
Detailed Description
Low-Noise Amplifier
The MAX7034 CMOS superheterodyne receiver and a few
external components provide the complete receive chain
from the antenna to the digital output data. Depending on
signal power and component selection, data rates can be
as high as 33kbps Manchester (66kbps NRZ).
The LNA is an nMOS cascode amplifier with off-chip
inductive degeneration. The gain and noise figures are
dependent on both the antenna matching network at the
LNA input and the LC tank network between the LNA output and the mixer inputs.
The MAX7034 is designed to receive binary ASK data
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data.
The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor
sets the real part of the input impedance at LNAIN, allowing for a more flexible input impedance match, such as a
typical printed-circuit board (PCB) trace antenna. A nominal value for this inductor with a 50Ω input impedance is
15nH, but is affected by the PCB trace.
Voltage Regulator
For operation with a single +4.5V to +5.5V supply voltage,
connect VDD5 and the EN_REG pin to the supply voltage.
An on-chip voltage regulator drives one of the AVDD pins
(pin 2) to approximately +3.4V. For proper operation,
DVDD and both AVDD pins must be connected together.
For operation with a single +3.0V to +3.6V supply voltage,
connect both the AVDD pins, DVDD, and VDD5 to the supply voltage and connect the EN_REG pin to ground (which
disables the internal voltage regulator). If the MAX7034 is
powered from +3.0V to +3.6V, the performance is limited
to the -40°C to +105°C range.
In either supply voltage mode, bypass VDD5, DVDD, and
the pin 7 AVDD pin to AGND with 0.01μF capacitors, and
the pin 2 AVDD to AGND with a 0.1μF capacitor, all placed
as close as possible to the pins.
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The LC tank filter connected to LNAOUT comprises L1
and C9 (see the Typical Application Circuit). Select L1
and C9 to resonate at the desired RF input frequency. The
resonant frequency is given by:
f RF =
1
2π L TOTAL × C TOTAL
where:
LTOTAL = L1 + LPARASITICS.
CTOTAL = C9 + CPARASITICS.
Maxim Integrated │ 8
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
LPARASITICS and CPARASITICS include inductance and
capacitance of the PCB traces, package pins, mixer input
impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank
filter center frequency. The total parasitic capacitance is
generally between 4pF and 6pF.
Mixer
A unique feature of the MAX7034 is the integrated image
rejection of the mixer. This device eliminates the need
for a costly front-end SAW filter for most applications.
Advantages of not using a SAW filter are increased sensitivity, simplified antenna matching, less board space,
and lower cost.
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz IF from a low-side injected LO (i.e., fLO = fRF
- fIF). The image-rejection circuit then combines these
signals to achieve 44dB of image rejection. Low-side
injection is required due to the on-chip image-rejection
architecture. The IF output is driven by a source follower
biased to create a driving-point impedance of 330Ω; this
provides a good match to the off-chip 330Ω ceramic
IF filter.
The IRSEL pin is a logic input that selects one of the
three possible image-rejection frequencies. When VIRSEL
= 0V, the image rejection is tuned to 315MHz. VIRSEL
= VDVDD/2 tunes the image rejection to 375MHz, and
VIRSEL = VDVDD tunes the image rejection to 434MHz.
The IRSEL pin is internally set to VDVDD/2 (image rejection at 375MHz) when it is left unconnected, thereby eliminating the need for an external VDVDD/2 voltage.
Phase-Locked Loop
Intermediate Frequency and RSSI
The IF section presents a differential 330Ω load to provide
matching for the off-chip ceramic filter. The six internal
AC-coupled limiting amplifiers produce an overall gain of
approximately 65dB, with a bandpass-filter-type response
centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. The RSSI circuit demodulates the IF by producing a DC output proportional to the
log of the IF signal level, with a slope of approximately
14.2mV/dB.
Applications Information
Crystal Oscillator
The crystal oscillator in the MAX7034 is designed to
present a capacitance of approximately 3pF between the
XTAL1 and XTAL2. If a crystal designed to oscillate with
a different load capacitance is used, the crystal is pulled
away from its intended operating frequency, introducing
an error in the reference frequency. Crystals designed to
operate with higher differential load capacitance always
pull the reference frequency higher. For example, a
4.7547MHz crystal designed to operate with a 10pF load
capacitance oscillates at 4.7563MHz with the MAX7034,
causing the receiver to be tuned to 315.1MHz rather than
315.0MHz, an error of about 100kHz, or 320ppm. It is
very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7034
crystal oscillator plus PCB parasitics.
In actuality, the oscillator pulls every crystal. The crystal’s
natural frequency is really below its specified frequency,
but when loaded with the specified load capacitance, the
crystal is pulled and oscillates at its specified frequency.
This pulling is already accounted for in the specification of
the load capacitance. Additional pulling can be calculated
if the electrical parameters of the crystal are known. The
frequency pulling is given by:
The PLL block contains a phase detector, charge pump,
integrated loop filter, VCO, asynchronous 64x clock
divider, and crystal oscillator driver. Besides the crystal,
this PLL does not require any external components. The
CM
1
1
6
VCO generates a low-side=
LO. The relationship between
fP
× 10
2 C CASE + C LOAD C CASE + C SPEC
the RF, IF, and crystal frequencies is given by:
f -f
f XTAL = RF IF
32 × M
where:
M = 1 (VXTALSEL = VDVDD) or 2 (VXTALSEL = 0V)
To allow the smallest possible IF bandwidth (for best sensitivity), minimize the tolerance of the reference crystal.
where:
fP is the amount the crystal frequency pulled in ppm.
CM is the motional capacitance of the crystal.
CCASE is the case capacitance.
CSPEC is the specified load capacitance.
CLOAD is the actual load capacitance.
When the crystal is loaded as specified (i.e., CLOAD =
CSPEC), the frequency pulling equals zero.
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Maxim Integrated │ 9
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
It is possible to use an external reference oscillator in
place of a crystal to drive the VCO. AC-couple the external oscillator to XTAL2 with a 1000pF capacitor. Drive
XTAL2 with a signal level of approximately 500mVP-P.
AC-couple XTAL1 to ground with a 1000pF capacitor.
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the
combination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capacitors
changes the corner frequency to optimize for different
data rates. The corner frequency should be set to approximately 1.5 times the fastest expected data rate from the
transmitter. Keeping the corner frequency near the data
rate rejects any noise at higher frequencies, resulting in
an increase in receiver sensitivity.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband and
a rolloff rate of 40dB/decade for the two-pole filter. The
Bessel filter has a linear phase response, which works
well for filtering digital data. To calculate the value of C7
and C6, use the following equations, along with the coefficients in Table 1:
C7 =
C6 =
b
a(100k )(π)(f C )
a
4(100k )(π)(f C )
voltage. One input is supplied by the data filter output. Both
comparator inputs are accessible off-chip to allow for different methods of generating the slicing threshold, which is
applied to the second comparator input.
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capacitor
(C8) from DSN to DGND (Figure 2). This configuration
averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts as
the analog signal varies, minimizing the possibility for
errors in the digital data. The values of R1 and C8 affect
how fast the threshold tracks to the analog amplitude. Be
sure to keep the corner frequency of the RC circuit much
lower than the lowest expected data rate.
Note that a long string of zeros or ones can cause the
threshold to drift. This configuration works best if a coding
scheme, such as Manchester coding, which has an equal
number of zeros and ones, is used.
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, add hysteresis to
the data slicer as shown in Figure 3.
Table 1. Coefficents to Calculate C7 and C6
FILTER TYPE
a
b
Butterworth (Q = 0.707)
1.414
1.000
Bessel (Q = 0.577)
1.3617
0.618
where fC is the desired 3dB corner frequency.
For example, to choose a Butterworth filter response with
a corner frequency of 5kHz:
C7
=
C6
MAX7034
1.000
≈ 450pF
(1.414)(100kΩ)(3.14)(5kHz)
RSSI
Choosing standard capacitor values changes C7 to 470pF
and C6 to 220pF, as shown in the Typical Application Circuit.
RDF1
100kΩ
RDF2
100kΩ
1.414
≈ 225pF
(4)(100kΩ)(3.14)(5kHz)
22
DFFB
21
OPP
19
DFO
C6
C7
Data Slicer
The data slicer takes the analog output of the data filter and
converts it to a digital signal. This is achieved by using a
comparator and comparing the analog input to a threshold
Figure 1. Sallen-Key Lowpass Data Filter
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Maxim Integrated │ 10
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Peak Detector
The peak-detector output (PDOUT), in conjunction with an
external RC filter, creates a DC output voltage equal to the
peak value of the data signal. The resistor provides a path
for the capacitor to discharge, allowing the peak detector
to dynamically follow peak changes of the data-filter output
voltage. For faster data slicer response, use the circuit
shown in Figure 4. For more details on hysteresis and
peak-detector applications, refer to Maxim Application Note
3671, Data Slicing Techniques for UHF ASK Receivers.
MAX7034
DATA
SLICER
Layout Considerations
A properly designed PCB is an essential part of any RF/
microwave circuit. On high-frequency inputs and outputs,
use controlled-impedance lines and keep them as short
as possible to minimize losses and radiation. At high
frequencies, trace lengths that are on the order of λ/10 or
longer act as antennas.
20
DSN
25
DATAOUT
R1
C8
Figure 2. Generating Data Slicer Threshold
Keeping the traces short also reduces parasitic inductance. Generally, 1 inch of a PCB trace adds about 20nH
of parasitic inductance. The parasitic inductance can have
a dramatic effect on the effective inductance of a passive
component. For example, a 0.5 inch trace connecting a
100nH inductor adds an extra 10nH of inductance or 10%.
MAX7034
DATA
SLICER
To reduce the parasitic inductance, use wider traces and
a solid ground or power plane below the signal traces.
Also, use low-inductance connections to ground on all
GND pins, and place decoupling capacitors close to all
power-supply pins.
R2
Control Interface Considerations
R*
When operating the MAX7034 with a +4.5V to +5.5V
supply voltage, the SHDN pin can be driven by a microcontroller with either +3.0V or +5V interface logic levels.
When operating the MAX7034 with a +3.0V to +3.6V supply, only +3.0V logic from the microcontroller is allowed.
19
DFO
23
DSP
25
DATAOUT
20
DSN
23
DSP
R1
19
DFO
R3
C8
*OPTIONAL
Figure 3. Generating Data Slicer Hysteresis
MAX7034
DATA
SLICER
25
DATAOUT
20
DSN
23
DSP
25kΩ
19
DFO
26
PDOUT
47nF
Figure 4. Using PDOUT for Faster Startup
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Maxim Integrated │ 11
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Typical Application Circuit
IF VDD IS
THEN VDD3 IS
AND EN_REG IS
3.0V TO 3.6V
CONNECTED TO VDD
GROUNDED
4.5V TO 5.5V
CREATED BY LDO,
AVAILABLE AT AVDD
(PIN 2)
CONNECTED TO VDD
VDD
VDD3
(SEE TABLE)
X1
C13
C11
C12
1
RF INPUT
2
C1
L1
3
L2
4
5
6
VDD3
C14
7
L3
C3
C2
8
9
C4
C9
10
11
12
13
14
XTAL1
XTAL2
AVDD
SHDN
LNAIN
PDOUT
DATAOUT
LNASRC
AGND
VDD5
MAX7034
LNAOUT
DSP
AVDD
DFFB
MIXIN1
OPP
MIXIN2
DSN
AGND
DFO
IRSEL
IFIN2
MIXOUT
IFIN1
DGND
XTALSEL
DVDD
EN_REG
***
28
26
R2
25
C15
24
R3
23
22
21
C7
20
19
VDD
18
17
R1
**
16
15
*
Y1
TO/FROM µP
POWER-DOWN
DATA OUT
27
C5
C6
C8
IF FILTER
C10
IN
OUT
GND
COMPONENT VALUES
IN TABLE 2
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***SEE THE MIXER SECTION.
*SEE THE PHASE-LOCKED
LOOP SECTION.
**SEE THE VOLTAGE
REGULATOR SECTION.
Maxim Integrated │ 12
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Table 2. Component Values for Typical Application Circuit
COMPONENT
VALUE FOR
fRF = 433MHz
VALUE FOR
fRF = 315MHz
DESCRIPTION
C1
100pF
100pF
5%
C2
Open
Open
±0.1pF
C3
100pF
100pF
5%
C4
100pF
100pF
5%
C5
1500pF
1500pF
10%
C6
220pF
220pF
5%
C7
470pF
470pF
5%
C8
0.47µF
0.47µF
20%
C9
220pF
220pF
10%
C10
0.01µF
0.01µF
20%
C11
0.1µF
0.1µF
20%
C12
100pF
100pF
5%
C13
100pF
100pF
5%
C14
0.01µF
0.01µF
20%
C15
0.01µF
0.01µF
20%
L1
56nH
120nH
5% or better**
L2
15nH
15nH
5% or better**
L3
27nH
51nH
5% or better**
R1
5.1kΩ
5.1kΩ
5%
R2
Open
Open
—
R3
0Ω
0Ω
—
X1 (÷64)
6.6128MHz*
4.7547MHz*
NDK or Suntsu
X1 (÷32)
13.2256MHz*
9.5094MHz*
NDK or Suntsu
Y1
10.7MHz ceramic filter
10.7MHz ceramic filter
Murata
*Crystal frequencies shown are for ÷64 (VXTALSEL = 0V) and ÷32 (VXTALSEL = VDD).
**Wire wound recommended.
Chip Information
Ordering Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 TSSOP
U28+1
21-0066
90-0171
www.maximintegrated.com
PART
TEMP RANGE
MAX7034AUI/V+T
-40°C to +125°C
PIN-PACKAGE
28 TSSOP
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Maxim Integrated │ 13
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
1/08
Initial release
—
1
3/09
Added /V designation to part number.
1
2
5/11
Updated Pin Description, Functional Diagram, Voltage Regulator section, Typical Application
Circuit, and Package Information; added Control Interface Considerations section
7, 8, 11, 12, 13
3
6/12
Updated capacitors in Data Filter section; updated Table 1 to reflect correct capacitor; updated
Figures 1, 2, 3; updated Table 2 component values and wire wound recommendation
10, 11, 13
4
11/16
Updated Electrical Characteristics table
DESCRIPTION
1, 3, 4
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2016 Maxim Integrated Products, Inc. │ 14
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