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MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering
up to 700mA Total Output Current
General Description
Benefits and Features
The MAX77655 provides a highly-integrated power supply
solution for low-power applications where size and efficiency are critical. Also, it features a single-inductor, multiple-output (SIMO) buck-boost regulator that provides four
independently programmable power rails from a single inductor to minimize total solution size. The PMIC is capable of delivering a total of 700mA output current (3.7VIN,
1.8VOUT).
● Highly Integrated
• 4x Output, Single-Inductor Multiple-Output (SIMO)
Buck-Boost Regulator
• Support Output Voltage Range from 0.5V to 4.0V
for All SIMO Channels
• 6.9μA Typical IQ with Two Outputs Enabled in
Low-Power Mode
• > 700mA Output Current at 3.7VIN and 1.8VOUT
• Up to 90% Efficiency at 3.7VIN and 1.8VOUT
A bidirectional I2C interface allows for configuring and
checking the status of the devices. An internal on/off controller provides a controlled startup sequence for the regulators and provides supervisory functionality when the devices are on. Numerous factory programmable options allow the device to be tailored for many applications, enabling faster time to market.
Applications
●
●
●
●
TWS Bluetooth™ Headphones/Hearables
Fitness, Health, Activity Monitors, and Smart Watches
Portable Devices
Sensors Nodes and Consumer Internet of Things (IoT)
● Flexible and Configurable
• I2C Compatible Interface
• Factory OTP Options Available
● Small Size
• 3.95mm2 Wafer-Level Package (WLP)
• 16-Bump, 0.5mm-Pitch, 4 x 4 Array
Ordering Information appears at end of data sheet.
Simplified Block Diagram
2.5V TO 5.5V
IN
1.5µH
LXA
LXB
BST
1.8V
SBB1
1.1V
SBB2
0.7V
SBB3
3.3V
MAX77655
nEN
VDD
10µF
SBB0
SDA
SCL
nIRQ
SDA *
SCL *
nIRQ *
PVDD
GND
PGND
*PULLUP RESISTORS NOT DRAWN
Bluetooth is a trademark of Bluetooth SIG, Inc
19-100853; Rev 1; 10/20
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
16 WLP 0.5mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics—Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics—SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics—I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MAX77655 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Part Number Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Support Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Detailed Description—Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IN POR Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IN Undervoltage Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IN Overvoltage Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Thermal Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chip Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
nEN Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
nEN Manual Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
nEN Triple-Functionality: Push-Button vs. Slide-Switch vs. Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Debounced Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
nEN Internal Pullup Resistors to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Interrupts (nIRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
On/Off Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Top Level On/Off Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Internal Wake-Up Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
On/Off Controller Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flexible Power Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
www.maximintegrated.com
Maxim Integrated | 2
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
TABLE OF CONTENTS (CONTINUED)
Startup Timing Diagram Due to nEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LPM vs. NPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Things to Avoid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Switching from LPM to NPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Detailed Description—SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SIMO Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SIMO Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Inductor Valley Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SIMO Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SIMO Channel Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Buck Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Buck-Boost Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Boost Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Channel-to-Channel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SIMO Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SIMO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SIMO Active Discharge Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bootstrap Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SIMO Supported Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bootstrap Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PVDD and VDD Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Unused Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Snubbing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PCB Layout Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Input Capacitor at IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Output Capacitors at SBBx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
www.maximintegrated.com
Maxim Integrated | 3
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
TABLE OF CONTENTS (CONTINUED)
Example PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Things to Avoid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Load Transient Between No Load and Heavy Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Overload While in LPM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Detailed Description—I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2C Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2C Interface Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I2C Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I2C Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I2C Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I2C General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I2C Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I2C Communication Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I2C Communication Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Writing to a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Writing Multiple Bytes to Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Reading from a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reading from Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Engaging HS Mode for Operation up to 3.4MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
MAX77655 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical Applications Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
www.maximintegrated.com
Maxim Integrated | 4
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
LIST OF FIGURES
Figure 1. Part Number Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2. Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. nEN Usage Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4. Debounced Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5. nEN Pullup Resistor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. On/Off Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. On/Off Controller Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. Flexible Power Sequencer Basic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Startup Timing Diagram Due to nEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. SIMO Simple Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Valley Current Control with Changing Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. LXB Snubbing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. PCB Top-Layer and Component Placement Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. I2C Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. I2C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 16. I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 17. Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 18. Slave Address Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19. Writing to a Single Register with the Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 20. Writing to Sequential Registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 21. Reading from a Single Register with the Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 22. Reading Continuously from Sequential Registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 23. Engaging HS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
www.maximintegrated.com
Maxim Integrated | 5
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
LIST OF TABLES
Table 1. Regulator Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. OTP Options Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3. On/Off Controller Transition/State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 4. SIMO Operating Mode Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5. Operating Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6. SIMO Supported Output Current for Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. I2C Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
www.maximintegrated.com
Maxim Integrated | 6
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Absolute Maximum Ratings
nEN to GND ................................................... -0.3V to VIN + 0.3V
SCL, SDA to GND .................................................... -0.3V to +6V
IN, nIRQ to GND....................................................... -0.3V to +6V
PVDD, VDD to GND............................................... -0.3V to +2.2V
SDA Continous Current ..................................................... ±20mA
IN Continuous Current (Note 1) ...................................... 1.2ARMS
LXA Continuous Current (Note 2) .................................. 1.2ARMS
LXB Continuous Current (Note 3) .................................. 1.2ARMS
SBB0, SBB1, SBB2, SBB3 to PGND (Note 2) ......... -0.3V to +6V
BST to IN .................................................................. -0.3V to +6V
BST to LXB ............................................................... -0.3V to +6V
SBB0, SBB1, SBB2, SBB3 Short-Circuit Duration......Continuous
PGND to GND........................................................ -0.3V to +0.3V
Operating Temperature Range .............................-40°C to +85°C
Junction Temperature ....................................................... +150°C
Storage Temperature Range ..............................-65°C to +150°C
Soldering Temperature (reflow) ........................................ +260°C
Continuous Power Dissipation (Multilayer Board, TA = +70°C,
derate 20.4mW/°C above +70°C) ...................................1632mW
Note 1: Do not repeatedly hot-plug a source to the IN terminal at a rate greater than 10Hz. Hot plugging low impedance sources results
in an ~8A momentary (~2μs) current spike.
Note 2: Do not externally bias LXA or LXB. LXA has internal clamping diodes to PGND and IN. LXB has an internal low-side clamping
diode to PGND and an internal high-side clamping diode that dynamically connects to a selected SIMO output. It is normal
for these diodes to briefly conduct during switching events. When the SIMO regulator is disabled, the LXB to PGND absolute
maximum voltage is -0.3V to VSBBx + 0.3V.
Note 3: When the active discharge resistor is engaged, limit its power dissipation to an average of 10mW. For example, consider the
case where the active discharge resistance is discharging the output capacitor each time the regulator turns off; the 10mW
limit allows you to discharge 80μF of capacitance charged to 5V every 100ms (P = 1/2 x C x V2/t = 1/2 x 80μF x 5V2/100ms =
10mW).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
16 WLP 0.5mm Pitch
Package Code
W161N1+1
Outline Number
21-100374A
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
49°C/W (2s2p board)
Junction to Case (θJC)
N/A
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated | 7
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Electrical Characteristics—Global Resources
(VIN = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CURRENT
Shutdown Current
Quiescent Supply
Current
ISHDN
IQ
All SBBx channels
are disabled, VIN =
3.7V, VLXA = 0V
TA = +25ºC
TA = +25°C
0.3
All channels
disabled, bias in
LPM
6.0
All channels
disabled, bias in
NPM
10
μA
μA
VOLTAGE MONITORS
Input Voltage Range
VIN
2.5
5.5
V
VOLTAGE MONITORS / POWER-ON RESET (POR)
POR Threshold
VPOR
VIN falling
1.8
V
VIN falling, UVLO_F[1:0] = 0x4
2.3
V
UVLO_H[1:0] = 0x5 (Note 4)
300
mV
VOLTAGE MONITORS / UNDERVOLTAGE LOCKOUT (UVLO)
UVLO Threshold
VINUVLO
UVLO Threshold
Hysteresis
VINUVLO_HYS
VOLTAGE MONITORS / OVERVOLTAGE LOCKOUT (OVLO)
OVLO Threshold
VINOVLO
VIN rising
5.70
5.85
6.00
V
Overtemperature
Lockout Threshold
TOTLO
TJ rising
145
°C
Thermal Alarm
Temperature 1
TJAL1
TJ rising
90
ºC
Thermal Alarm
Temperature 2
TJAL2
TJ rising
120
ºC
THERMAL MONITORS
ENABLE INPUT (nEN)
nEN Input Leakage
Current
InEN_LKG
VnEN = VIN = 5.5V
CNFG_GLBL_A.P
U_DIS = 1
nEN Input Falling
Threshold
VTH_nEN_F
nEN falling
nEN Input Rising
Threshold
VTH_nEN_R
nEN rising
Debounce Time
tDBNC_nEN
Manual Reset Time
nEN Pullup
www.maximintegrated.com
tMRST
RnEN_PU
TA = +25°C
-1
TA = +85°C
±0.001
+1
μA
±0.01
VIN - 1.6
VIN - 1.2
VIN - 1.1
V
VIN - 0.6
V
CNFG_GLBL_A.DBEN_nEN = 0
100
μs
CNFG_GLBL_A.DBEN_nEN = 1
30
ms
CNFG_GLBL_B.MRT = 0
16
CNFG_GLBL_B.MRT = 1
8
Pullup to VIN
CNFG_GLBL_A.P
U_DIS = 0
200
s
kΩ
Maxim Integrated | 8
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Electrical Characteristics—Global Resources (continued)
(VIN = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.4
V
OPEN-DRAIN INTERRUPT OUTPUT (nIRQ)
Output Low Voltage
Output Falling Edge
Time
Leakage Current
Sinking 2mA
tf_nIRQ
InIRQ_LKG
CIRQ = 25pF
1.5
VIN = 5.5V, nIRQ
set to high
impedance, VnIRQ
= 0V or 5.5V
TA = +25ºC
-1
TA = +85ºC
±0.001
ns
+1
μA
±0.01
FLEXIBLE POWER SEQUENCER
Power-Up Event Periods
tEN
See Figure 8
1.28
ms
Power-Down Event
Periods
tDIS
See Figure 8
2.56
ms
1
ms
VPVDD
1.8
V
VDD
1.8
V
BIAS
Enable Delay
PVDD Output Voltage
VDD Input Voltage
Note 4: Programmed at Maxim's factory.
Electrical Characteristics—SIMO Buck-Boost
(VIN = 3.7V, CSBBx = 22μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating temperature range
(TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
TA = +25ºC, bias
in LPM
SIMO Quiescent Supply
Current
IQ_SIMO
TA = +25ºC, bias
in NPM
Total current for the
first channel at
1.8V output
6.5
Current for each
additional channel
at 1.8V output
0.38
Current for the first
channel at 1.8V
output
230
Current for each
additional channel
at 1.8V output
61
μA
GENERAL CHARACTERISTICS / OUTPUT VOLTAGE RANGE (SBB0/1/2/3)
Programmable Output
Voltage Range
0.5
4.0
V
Output DAC Bits
8
bits
Output DAC LSB Size
25
mV
www.maximintegrated.com
Maxim Integrated | 9
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Electrical Characteristics—SIMO Buck-Boost (continued)
(VIN = 3.7V, CSBBx = 22μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating temperature range
(TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT VOLTAGE ACCURACY
Output Voltage
Accuracy
ISBBx = 1mA,
typical is based on
an average over
100ms, VDD =
1.8V, VSBBx = 1.8V
TA = +25°C
-3.0
+3.0
TA = -40°C to
+85°C
-4.0
+4.0
ISBBx = 300mA,
typical is based on
an average over
100ms, VDD =
1.8V, VSBBx = 1.8V
TA = +25°C
-2.0
+2.0
TA = -40°C to
+85°C
-4.0
+4.0
%
TIMING CHARACTERISTICS
Soft-Start Slew Rate
dV/dtSS
1.0
2.0
3.0
-1
±0.01
+1
mV/μs
POWER STAGE CHARACTERISTICS
TA = +25°C
LXA Leakage Current
All SBB channels
are disabled, VIN =
5.5V, VLXA = 0V, or
5.5V
TA = +25°C
LXB Leakage Current
All SBB channels
are disabled, VIN =
5.5V, VLXA = 0V or
5.5V, all VSBBx =
4.0V
Disabled Output
Leakage Current
Active Discharge
Impedance
www.maximintegrated.com
RAD_SBBx
TA = +85°C
μA
±0.1
-1
±0.01
TA = +85°C
±0.1
All SBB channels
are disabled,
active-discharge
disabled
(ADE_SBBx = 0),
VSBBx = 4.0V,
VLXB = 0V, VIN =
VBST = 5.5V
TA = +25°C
0.05
All SBB channels
are disabled,
active-discharge
disabled
(ADE_SBBx = 0),
VSBBx = 4.0V,
VLXB = 0V, VIN =
VBST = 5.5V
TA = +85°C
+1
μA
1
μA
All SBB channels are disabled, active
discharge enabled (ADE_SBBx = 1)
0.1
80
140
260
Ω
Maxim Integrated | 10
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Electrical Characteristics—I2C Serial Interface
(VIN = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDA AND SCL I/O STAGE
SCL, SDA Input High
Voltage
VIH
VIN = 3.7V, TA = +25ºC
SCL, SDA Input Low
Voltage
VIL
TA = +25ºC
SCL, SDA Input
Hysteresis
VHYS
TA = +25ºC
SCL, SDA Input
Leakage Current
II
SDA Output Low
Voltage
VOL
SCL, SDA Pin
Capacitance
CI
Output Fall Time from
VIH to VIL
tOF
VSCL = VSDA = VDD
0.7 x
VDD
V
0.3 x
VDD
0.05 x
VDD
-1
Sinking 20mA
V
+1
μA
0.4
V
10
(Note 5)
V
pF
120
ns
1000
kHz
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST AND FAST-MODE PLUS) (Note 5)
Clock Frequency
fSCL
0
tHD_STA
0.26
μs
SCL Low Period
tLOW
0.5
μs
SCL High Period
Hold Time (REPEATED)
START Condition
tHIGH
0.26
μs
Setup Time REPEATED
START Condition
tSU_STA
0.26
μs
Data Hold Time
tHD_DAT
0
μs
Data Setup Time
tSU_DAT
50
ns
Setup Time for STOP
Condition
tSU_STO
0.26
μs
Bus Free Time between
STOP and START
Condition
tBUF
0.5
μs
Pulse Width of
Suppressed Spikes
tSP
Maximum pulse width of spikes that must
be suppressed by the input filter
50
ns
3.4
MHz
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 100pF) (Note 5)
Clock Frequency
fSCL
Setup Time REPEATED
START Condition
tSU_STA
160
ns
Hold Time (REPEATED)
START Condition
tHD_STA
160
ns
SCL Low Period
tLOW
160
ns
SCL High Period
tHIGH
60
ns
Data Setup Time
tSU_DAT
10
ns
www.maximintegrated.com
Maxim Integrated | 11
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Electrical Characteristics—I2C Serial Interface (continued)
(VIN = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
MAX
UNITS
0
70
ns
TA = +25°C
10
40
ns
trCL1
TA = +25°C
10
80
ns
SCL Fall Time
tfCL
TA = +25°C
10
40
ns
SDA Rise Time
trDA
TA = +25°C
10
80
ns
SDA Fall Time
tfDA
TA = +25°C
10
80
ns
Data Hold Time
tHD_DAT
SCL Rise Time
trCL
Rise Time of SCL Signal
After REPEATED
START Condition and
After Acknowledge Bit
Setup Time for STOP
Condition
CONDITIONS
tSU_STO
Bus Capacitance
CB
Pulse Width of
Suppressed Spikes
tSP
MIN
TYP
160
ns
Maximum pulse width of spikes that must
be suppressed by the input filter
100
pF
10
ns
1.7
MHz
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 400pF) (Note 5)
Clock Frequency
fSCL
Setup Time REPEATED
START Condition
tSU_STA
160
ns
Hold Time (REPEATED)
START Condition
tHD_STA
160
ns
SCL Low Period
tLOW
320
ns
SCL High Period
tHIGH
120
ns
Data Setup Time
tSU_DAT
10
ns
Data Hold Time
tHD_DAT
0
150
ns
SCL Rise Time
tRCL
TA = +25°C
20
80
ns
Rise Time of SCL Signal
After REPEATED
START Condition and
After Acknowledge Bit
tRCL1
TA = +25°C
20
160
ns
SCL Fall Time
tFCL
TA = +25°C
20
80
ns
SDA Rise Time
tRDA
TA = +25°C
20
160
ns
SDA Fall Time
tFDA
TA = +25°C
20
160
ns
Setup Time for STOP
Condition
tSU_STO
Bus Capacitance
CB
Pulse Width of
Suppressed Spikes
tSP
160
ns
400
Maximum pulse width of spikes that must
be suppressed by the input filter
10
pF
ns
Note 5: Design guidance only. Not production tested.
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Maxim Integrated | 12
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Typical Operating Characteristics
(Typical Applications Circuit. VIN = 3.7V, CSBBx = 22μF, L = 1.5μH, TA = +25°C, VSBB0 = 1.8V, VSBB1 = 1.1V, VSBB2 = 0.7V, VSBB3 =
3.3V, unless otherwise noted.)
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Maxim Integrated | 13
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Typical Operating Characteristics (continued)
(Typical Applications Circuit. VIN = 3.7V, CSBBx = 22μF, L = 1.5μH, TA = +25°C, VSBB0 = 1.8V, VSBB1 = 1.1V, VSBB2 = 0.7V, VSBB3 =
3.3V, unless otherwise noted.)
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Maxim Integrated | 14
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Typical Operating Characteristics (continued)
(Typical Applications Circuit. VIN = 3.7V, CSBBx = 22μF, L = 1.5μH, TA = +25°C, VSBB0 = 1.8V, VSBB1 = 1.1V, VSBB2 = 0.7V, VSBB3 =
3.3V, unless otherwise noted.)
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Maxim Integrated | 15
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Typical Operating Characteristics (continued)
(Typical Applications Circuit. VIN = 3.7V, CSBBx = 22μF, L = 1.5μH, TA = +25°C, VSBB0 = 1.8V, VSBB1 = 1.1V, VSBB2 = 0.7V, VSBB3 =
3.3V, unless otherwise noted.)
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Maxim Integrated | 16
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Pin Configuration
MAX77655
TOP VIEW
(BUMP SIDE DOWN)
MAX77655
1
2
3
4
GND
VDD
SBB0
SBB1
SCL
nIRQ
BST
SBB2
SDA
nEN
LXB
SBB3
IN
LXA
PGND
PVDD
+
A
B
C
D
WLP
(1.99mm x 1.99mm x 0.64mm, 0.5mm PITCH)
Pin Description
PIN
NAME
FUNCTION
TYPE
TOP LEVEL
C2
nEN
Active-Low Enable Input. EN supports push-button, slide-switch, or logic
configurations. If not used, connect nEN to IN.
B2
nIRQ
Active-Low, Open-Drain Interrupt Pin. Connect a 100kΩ pullup resistor to nIRQ.
Digital Input
Digital I/O
B1
SCL
I2C Clock
C1
SDA
I2C Data
D1
IN
Digital Input
Input Voltage Connection. Bypass to GND with a 22μF ceramic capacitor.
Power Input
A1
GND
Quiet Ground. Connect GND to PGND and the low-impedance ground plane of
the PCB.
A2
VDD
Device Power Input. Connect to PVDD.
D4
PVDD
Digital Output
Ground
Power Input
1.8V Internal Supply. Bypass this pin with a 10μF ceramic capacitor and connect
to VDD. Do not connect anything else to this pin. If pullup resistors must be
connected to PVDD, ensure on the layout the connection points are as close as
possible to the capacitor and not the pin. See the PCB Layout Guide section for
more details.
Power Output
SIMO BUCK-BOOST
A3
SBB0
SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO
buck-boost. Bypass SBB0 to PGND with a 22μF ceramic capacitor. If not used,
see the Unused Outputs section.
Power Output
A4
SBB1
SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO
buck-boost. Bypass SBB1 to PGND with a 22μF ceramic capacitor. If not used,
see the Unused Outputs section.
Power Output
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Maxim Integrated | 17
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Pin Description (continued)
PIN
NAME
B4
SBB2
SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO
buck-boost. Bypass SBB2 to PGND with a 22μF ceramic capacitor. If not used,
see the Unused Outputs section.
Power Output
C4
SBB3
SIMO Buck-Boost Output 3. SBB3 is the power output for channel 3 of the SIMO
buck-boost. Bypass SBB3 to PGND with a 22μF ceramic capacitor. If not used,
see the Unused Outputs section.
Power Output
B3
BST
SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 10nF
ceramic capacitor between BST and LXB.
C3
LXB
Switching Node B. LXB is driven between PGND and SBBx when SBBx is
enabled. LXB is driven to PGND when all SIMO channels are disabled.
Power I/O
D2
LXA
Switching Node A. LXA is driven between PGND and IN when any SIMO channel
is enabled. LXA is driven to PGND when all SIMO channels are disabled.
Power I/O
D3
PGND
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FUNCTION
Power Ground for the SIMO Low-Side FETs. Connect PGND to GND, and the
low-impedance ground plane of the PCB.
TYPE
Power Input
Ground
Maxim Integrated | 18
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Detailed Description
The MAX77655 provides a power management solution for low-power applications. A single-inductor, multiple output
(SIMO) buck-boost regulator efficiently provides four independently programmable power rails (see Table 1).
A bidirectional I2C serial interface allows for configuring and checking the status of the device. An internal on/off controller
provides power sequencing and supervisory functionality for the device.
Table 1. Regulator Summary
REGULATOR
NAME
REGULATOR
TOPOLOGY
MAXIMUM IOUT
(mA)
VIN RANGE
(V)
MAX77655 VOUT RANGE/
RESOLUTION
SBB0
SIMO
Up to 700*
2.5 to 5.5
0.5V to 4.0V in 25mV steps
SBB1
SIMO
Up to 700*
2.5 to 5.5
0.5V to 4.0V in 25mV steps
SBB2
SIMO
Up to 700*
2.5 to 5.5
0.5V to 4.0V in 25mV steps
SBB3
SIMO
Up to 700*
2.5 to 5.5
0.5V to 4.0V in 25mV steps
*Shared capacity with other SBBx channels. See the SIMO Supported Output Current section for more information.
Part Number Decoding
The MAX77655 has different one-time programmable (OTP) options and variants to support a variety of applications. The
OTP options set default settings such as output voltage. See Figure 1 for how to identify these. Table 2 lists all available
OTP options. Refer to Maxim Integrated Naming Convention for more details.
MAX77655 x E W E + T
BASE PART NUMBER
OTP OPTION
OPERATING TEMP. RANGE
TAPE-AND-REEL
LEAD-FREE (RoHS)
PACKAGE TYPE
NUMBER OF PINS
Figure 1. Part Number Decode
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Maxim Integrated | 19
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Table 2. OTP Options Table
OTP LETTER AND SETTINGS
BLOCK
Global
SIMO
BIT FIELD NAME
SETTING NAME
A
CID[7:0]
OTP Identifier
0x2
PU_DIS
Pullup Disable
Disabled
BIAS_LPM
Bias Power Mode
MRT
Manual Reset Time
nEN_MODE
nEN Mode
Logic
DBEN_nEN
nEN Debounce Time
100μs
DRV_SBB[1:0]
Drive Strength
Fastest
TV_SBB0[7:0]
SBB0 VOUT
1.800V
ADE_SBB0
Active-Discharge Resistor Enable
EN_SBB0[2:0]
SBB0 Enable Control
TV_SBB1[7:0]
SBB1 VOUT
1.100V
ADE_SBB1
Active-Discharge Resistor Enable
Enabled
EN_SBB1[2:0]
SBB1 Enable Control
TV_SBB2[7:0]
SBB2 VOUT
0.700V
ADE_SBB2
Active-Discharge Resistor Enable
Enabled
EN_SBB2[2:0]
SBB2 Enable Control
TV_SBB3[7:0]
SBB3 VOUT
ADE_SBB3
Active-Discharge Resistor Enable
EN_SBB3[2:0]
SBB3 Enable Control
LPM
8s
Enabled
FPS Slot 2
FPS Slot 1
FPS Slot 0
3.300V
Enabled
FPS Slot 3
Support Materials
The following support materials are available for this device:
● MAX77655 Register Map: Full table of registers that can be read from or written to by I2C.
● MAX77655 Programmer's Guide: Basic software implementation advice.
● MAX77655 SIMO Calculator: Tool to determine if a given set of voltages and currents are supported. The tool can be
found under Design Resources in the product web page.
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Maxim Integrated | 20
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Top-Level Interconnect Simplified Diagram
Figure 2 shows the same major blocks as the Typical Applications Circuit with an increased emphasis on the routing
between each block. This diagram is intended to familiarize the user with the landscape of the device. Many of the details
associated with these signals are discussed throughout the data sheet. At this stage of the data sheet, note the addition
of the main bias and clock block that are not shown in the Typical Applications Circuit. The main bias and clock block
provides voltage, current, and clock references for other blocks as well as many resources for the top-level digital control.
MAX77655
VREF
SBBx
IN
BIAS
ADE_SBBx
EN_SBBx
TV_SBBx
SBBx_F
INUVLO
INOVLO
OTLO
POR
BIAS_LPM
SIMO
TOP-LEVEL
DIGITAL
CONTROL
nIRQ
IN
nEN
100µs/30ms
DEBOUNCE
TIMER
tDBNC_nEN
DBEN_nEN
EN
SDA
I 2C
SCL
Figure 2. Top-Level Interconnect Simplified Diagram
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Maxim Integrated | 21
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Detailed Description—Global Resources
The global resources encompass a set of circuits that serve the entire device and ensure safe, consistent, and reliable
operation.
Features and Benefits
● Voltage Monitors
• IN power-on-reset (POR) comparator generates a reset signal upon power-up
• IN undervoltage ensures repeatable behavior when power is applied to and removed from the device
• IN overvoltage monitor inhibits operation with overvoltage power sources to ensure reliability in faulty environments
● Thermal Monitors
• +145°C junction temperature shutdown
● Manual Reset
• 8s or 16s period
● Wake-up Events
• nEN input assertion
● Interrupt Handler
• All interrupts are maskable
● Push-Button/Slide-Switch/Logic On-Key (nEN)
• Configurable push-button/slide-switch/logic functionality
• 100μs or 30ms debounce timer interfaces directly with mechanical switches
● On/Off Controller
• Startup/Shutdown sequencing
• Programmable sequencing slots
● nIRQ Digital Output for Interrupts
Voltage Monitors
The device monitors the input voltage (VIN) to ensure proper operation using three comparators (POR, UVLO, and
OVLO). These comparators include hysteresis to prevent their outputs from toggling between states during noisy system
transitions.
IN POR Comparator
The IN POR comparator monitors VIN and generates a power-on reset signal (POR). When VIN is below VPOR, the
device is held in reset (RST = 1, POR = 1). When VIN rises above VPOR, the device enters shutdown state (RST = 1,
POR = 0). See Figure 6 and Table 3 for more details.
IN Undervoltage Lockout Comparator
The IN undervoltage lockout (UVLO) comparator monitors VIN and generates an INUVLO signal when the VIN falls below
the UVLO threshold. The INUVLO signal is provided to the top-level digital controller. See Figure 6 and Table 3 for
additional information regarding the UVLO comparator:
● When the device is in the Shutdown state, the UVLO comparator is disabled.
● When transitioning out of the Shutdown state, the UVLO comparator is enabled allowing the device to check for
sufficient input voltage. If VIN is above the UVLO rising threshold and a wake-up signal is received, the device can
transition to the Resource On state; otherwise, the device transitions back to the Shutdown state.
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Maxim Integrated | 22
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
IN Overvoltage Lockout Comparator
The device is rated for 5.5V maximum operating voltage (VIN) with an absolute maximum input voltage of 6.0V. An
overvoltage lockout monitor increases the robustness of the device by inhibiting operation when the supply voltage is
greater than VINOVLO. See Figure 6 and Table 3 for additional information regarding the OVLO comparator:
● When the device is in the Shutdown state, the OVLO comparator is disabled.
Thermal Monitors
The MAX77655 has three global on-chip thermal sensors:
● Junction Temperature Alarm 1 → 90°C
● Junction Temperature Alarm 2 → 120°C
● Junction Temperature Shutdown → 145°C
The junction temperature alarms have maskable rising interrupts as well as status bits (see the Register Map section
for more information). Unmasking these thermal alarms is recommended for all systems. If the first alarm is triggered,
the system software should attempt to lower system power dissipation. If the second alarm is triggered, then attempts
to lower the power dissipation were unsuccessful and the system software should turn the device off. Finally, if the
junction temperature rises to junction temperature shutdown, then the MAX77655 sets the ERCFLAG.TOVLD bit and
automatically turns itself off.
After a junction temperature shutdown event, the system can be enabled again. The system software can read the
ERCFLAG register during initialization to see ERCFLAG.TOVLD = 1 and log that an extreme thermal event has occurred.
Thermal Shutdown
The MAX77655 has on-chip thermal sensors to monitor thermal overloads. The thermal overload alarm generates a
TOVLD signal when the junction temperature exceeds +145°C (TJOVLD). The on/off controller provides TOVLD. When
TOVLD is asserted, the on/off controller forces system reset which disables all functions of the MAX77655. Once all
functions are disabled, a wake-up event is required to turn the MAX77655 on again. In the event that a wake-up event
turns the MAX77655 on when the junction temperature is still above +145°C, the MAX77655’s on/off controller promptly
forces system reset which disables all functions again. The thermal monitoring function is sampled in low-power mode to
save quiescent current. The host can check if a temperature overload occurred by reading the ERCFLAG.TOLVD flag.
Chip Identification
Different one-time programmable (OTP) variants of the MAX77655 offer different settings such as settings for default
output voltages or power sequencing. These OTP variants are identified by the Chip Identification number, which can be
read in the CID register.
nEN Enable Input
The nEN is an active-low, internally debounced digital input that typically comes from the system’s on-key. The
debounce time is programmable with CNFG_GLBL_A.DBEN_nEN. The primary purpose of this input is to generate
a wake-up signal for the PMIC, turning on the regulators. Maskable rising/falling interrupts are available for nEN
(INTM_GLBL.nEN_R and INTM_GLBL.nEN_F) for alternate functionality.
The nEN input can be configured to work with a push-button (CNFG_GLBL_A.nEN_MODE[1:0] = 0x0), a slide-switch
(CNFG_GLBL_A.nEN_MODE[1:0] = 0x1), or a logic output of an external device (CNFG_GLBL_A.nEN_MODE[1:0] =
0x2). See Figure 3 for more information. In both push-button mode and slide-switch mode, the on/off controller looks for
a falling edge on the nEN input to initiate a power-up sequence. In logic mode, the on/off controller initiates a power-up
or power-down sequence depending on the nEN value. There is no debouncing for logic mode.
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Maxim Integrated | 23
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
nEN Manual Reset
The nEN works as a manual reset input when the on/off controller is in the "Resource On" state. The manual reset
function is useful for forcing a power-down in case communication with the processor fails. When nEN is configured for
push-button mode and the input is asserted (nEN = LOW) for an extended period (tMRST), the on/off controller initiates
a power-down sequence and goes to shutdown mode. When nEN is configured for slide-switch mode and the input is
deasserted (nEN = HIGH) for an extended period (tMRST), the on/off controller initiates a power-down sequence and
goes to shutdown mode. Logic mode does not depend on a manual reset time (tMRST), so when nEN is pulled high, the
on/off controller initiates a power-down sequence and goes to shutdown mode. In all modes, the ERCFLAG.MRST flag
sets to indicate a reset occurred.
nEN Triple-Functionality: Push-Button vs. Slide-Switch vs. Logic
The nEN digital input can be configured to work with a push-button switch, a slide-switch, or a logic output. Figure 3
shows nEN's triple functionality for power-on sequencing and manual reset.
NOT DRAWN TO SCALE
STATE
SHUTDOWN
POWER-ON SEQUENCE
RESOURCE ON
POWER-DOWN SEQUENCE
INPUT VOLTAGE
APPLIED
VIN
IN
tDBNC_nEN
nEN
tDBNC_nEN
tDBNC_nEN
tMRST
PUSH-BUTTON MODE
IN
tDBNC_nEN
nEN
tMRST
tDBNC_nEN
SLIDE-SWITCH MODE
Driven by logic signal
nEN
LOGIC MODE
Figure 3. nEN Usage Timing Diagram
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Maxim Integrated | 24
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Debounced Input
The nEN is debounced on both rising and falling edges to reject undesired transitions. The input must be at a stable logic
level for the entire debounce period for the output to change its logic state. Figure 4 shows an example timing diagram
for the nEN debounce.
NOT DRAWN TO SCALE
BOUNCING IS
REJECTED
STABLE
SIGNAL IS
ACCEPTED
BOUNCING IS
REJECTED
STABLE
SIGNAL IS
ACCEPTED
nEN
tDBUF
DBEN
tDBUF
tDBNC_nEN
tDBNC_nEN
(INTERNAL)
Figure 4. Debounced Input
nEN Internal Pullup Resistors to VIN
The nEN logic thresholds are referenced to VIN. There is an internal pullup resistor between nEN and VIN (RnEN_PU),
which can be enabled by setting CNFG_GLBL_A.PU_DIS = 0. See Figure 5. While enabled, the pullup value is
approximately 200kΩ. While PU_DIS = 1, the nEN node has high impedance.
Applications using a slide-switch on-key or push-pull digital output connected to nEN can reduce quiescent current
consumption by disabling the pullup resistor. Applications using normally-open, momentary, and push-button on-keys (as
shown in Figure 5) can use the internal resistor to avoid external components.
VIN
200kΩ
ON-KEY
SWITCH CONTROL
PU_DIS
SWITCH
0b0
CLOSED
0b1
OPEN
RnEN
nEN__PU
~200kΩ
OPEN
nEN
Figure 5. nEN Pullup Resistor Configuration
Interrupts (nIRQ)
Several status, interrupt, and interrupt mask registers monitor key information and update when an interrupt event has
occurred. See the Register Map section for a comprehensive list of all interrupt bits and status registers.
Depending on OTP, some or all interrupts are masked by default. Initialization software should unmask interrupts of
interest.
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Maxim Integrated | 25
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
The nIRQ is an active-low, open-drain output typically routed to a processor's interrupt input for triggering off interrupt
events. When any unmasked interrupt occurs, this pin is asserted (LOW). A pullup resistor is required for this signal, and
is typically found inside the host processor. If one is unavailable, a board-mounted pullup resistor is required.
On/Off Controller
The on/off controller monitors multiple power-up (wake-up) and power-down (shutdown) conditions to enable or disable
resources that are necessary for the system and its processor to move between its operating modes.
Many systems have one power management controller and one processor and rely on the on/off controller to be the
master controller. In this case, the on/off controller receives the wake-up events and enables some or all of the regulators
in order to power up a processor. That processor then manages the system. To conceptualize this operation, see Figure
6 and Table 3. A typical path through the on/off controller during power-up is:
1. Apply power to IN and start in the Shutdown state.
2. Press the system's on-key (nEN = LOW) and follow transitions 2, 3A, and 4 to the Resource On state.
3. The device performs its desired functions in the Resource On state. When a manual reset occurs, the device follows
transitions 5A, 6, and 10 to the Shutdown state.
Some systems have several power management blocks, a main processor, and subprocessors. These systems can
use this device as a subpower management block for a peripheral portion of circuitry as long as there is an I2C port
available from a higher level processor. To conceptualize this slave operation, see Figure 6 and Table 3. Optionally, to
avoid delay from debouncing the nEN pin, systems should use the MAX77655 with nEN configured to be in logic mode
(CNFG_GLBL_A.nEN_MODE[1:0] = 0b10) by OTP. A typical path through the on/off controller used in this way is:
1. Apply power to IN and start in the Shutdown state.
2. When the higher level processor wants to turn on this device's resources, it pulls nEN LOW to follow transitions 2,
3A, and 4 to the Resource On state.
3. The higher level processor can control this device's resources with I2C commands (e.g., turn on/off regulators).
4. When the higher level processor is ready to turn this device off, it turns off everything through the I2C either with a
software command (CNFG_GLBL_B.SFT_CTRL[1:0]) or pulling nEN high to transition along paths 5A, 6, and 10 to
the Shutdown state.
5. If the higher level processor wants to power down outputs on the FPS but keep the bias enabled (for I2C
communication), it sends a SFT_STBY command (CNFG_GLBL_B.SFT_CTRL[1:0] = 0x3) to transition along paths
5B and 6 to the Standby state.
6. Afterward,
to
exit
standby
state,
the
processor
sends
a
SFT_EXIT_STBY
command
(CNFG_GLBL_B.SFT_CTRL[1:0] = 0x4) to transition along path 7 back to the wake-up action, eventually going back
to the Resource On state.
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Maxim Integrated | 26
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Top Level On/Off Controller
ANY
STATE
STATE
0
ACTION
SEQUENCE
1
X
SHUTDOWN ((BIAS OFF)
ALL RESOURCES OFF
I2C DISABLED
IIN = ISHDN
TRANSITION NAME
SEE ON/OFF CONTROLLER
TRANSITION/STATE TABLE
OVLO/UVLO/OTLO IN
ANY STATE
NO POWER
VIN < VPOR
8
IMMEDIATE
SHUTDOWN
9
10
DISABLE BIAS
2
7
WAKE-UP
STANDBY (BIAS ON)
CAN ENABLE/DISABLE RESOURCES
I2C ENABLED
IN (QUIESCENT) = ISHDN + IQ_SIMO
3B
3A
6
FPS POWER-UP
FPS POWER-DOWN
4
11
6
FPS POWER-DOWN
5B
RESOURCE ON (BIAS ON)
FPS DONE
CAN ENABLE/DISABLE RESOURCES
I2C ENABLED
IN (QUIESCENT) = ISHDN + IQ_SIMO
5A
ANY
STATE
Figure 6. On/Off Controller State Diagram
Table 3. On/Off Controller Transition/State
TRANSITION/STATE
CONDITION
0
IN voltage is below the POR threshold (VIN < VPOR)
1
IN voltage is above the POR threshold (VIN > VPOR)
SHUTDOWN
2
3A
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The device is waiting for a wake-up signal to enable the main bias circuits.
● This is the lowest current state of the device (IQ ~ 0.3μA)
● Main bias circuits and I2C are off. POR comparator is on
● The ERCFLAG register value is preserved
A wake-up signal is received.
● A debounced on-key (nEN) falling edge is detected (push-button or slide-switch mode) OR
● nEN is LOW (logic mode) OR
● Internal wake-up flag is set due to cold reset command
No faults detected. In the ERCFLAG register: UVLO = 0, OVLO = 0, TOVLD = 0.
Maxim Integrated | 27
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
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Table 3. On/Off Controller Transition/State (continued)
TRANSITION/STATE
3B
4
RESOURCE ON
CONDITION
Fault detected:
● System overtemperature lockout (TJ > TOTLO) OR
● System undervoltage lockout (VIN < VINUVLO + VINUVLO_HYS) OR
● System overvoltage lockout (VIN > VINOVLO)
Power-up sequence complete
Flexible power sequence (FPS) went through power-up and I2C is on. The main bias circuits are enabled.
5A
Request to power-down received.
● Software cold reset (CNFG_GLBL_B.SFT_CTRL[1:0] = 0b01) occurred OR
● Software power off (CNFG_GLBL_B.SFT_CTRL[1:0] = 0b10) occurred OR
● Manual reset occurred
5B
I2C command SFT_STBY received to enter standby mode
STANDBY
The device is waiting for a wake-up signal to restart.
● SIMO channels on the flexible power sequencer (FPS) are off.
● SIMO channels that were forced on (CNFG_SBBx_B.EN_SBBx[2:0] = 0x6 or 0x7) stay on
● The main bias circuits are enabled, and I2C is on.
● Main bias circuits are in low-power mode if CNFG_GLBL_A.BIAS_LPM = 1.
6
Power-down sequence is finished
7
Wake-up signal received.
● A debounced on-key (nEN) falling edge is detected (push-button mode) OR
● I2C wake-up command SFT_EXIT_STBY received OR
● Manual reset occurred
8
● System overtemperature lockout (TJ > TOTLO) OR
● System undervoltage lockout (VIN < VINUVLO) OR
● System overvoltage lockout (VIN > VINOVLO)
9
Immediate shutdown is finished
10
Bias is disabled
11
nEN is HIGH (logic mode)
Internal Wake-Up Flags
After transitioning to the shutdown state because of a reset, to allow the device to power-up again, internal wake-up flags
are set to remember the wake-up request. In Figure 6 and Table 3, these internal wake-up flags trigger transition 2. The
internal wake-up flags are set when any of the following happen:
● While in push-button or slide-switch mode, nEN is debounced (see the nEN Enable Input section)
• For example, after a push-button is pressed or a slide-switch is switched to HIGH
● While in logic mode, nEN is LOW (see the nEN Enable Input section)
● Software Cold Reset command sent (CNFG_GLBL.SFT_CTRL[1:0] = 0b01)
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Maxim Integrated | 28
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
On/Off Controller Actions
WAKE-UP ACTIONS
FPS POWER-UP ACTIONS
2
3A
ENABLE BIAS
CLEAR INTERNAL
WAKE-UP FLAGS
FPS POWER-DOWN ACTIONS
5A
5B
CLEAR INTERNAL
WAKE-UP FLAGS
FPS ENABLE PULSE 0
WAIT 60ms
LOAD OTP TRIM
WAIT tEN
CHECK FOR UVLO/OVLO/
OTLO
3A
SFT_CTRL[1:0] = 0b01
SET INTERNAL
WAKE-UP FLAG
WAIT tEN
8
CLEAR INTERNAL
WAKE-UP FLAGS
DISABLE ALL RESOURCES
WAIT 125ms
SFT_CTRL[1:0]
SFT_CTRL[1:0] ≠ 0b01
FPS ENABLE PULSE 1
3B
IMMEDIATE SHUTDOWN ACTIONS
9
RECORD THE CAUSE OF POWERDOWN EVENT IN EVENT RECORDER
REGISTER (ERCFLAG)
FPS DISABLE PULSE 3
FPS ENABLE PULSE 2
WAIT tDIS
WAIT tEN
FPS DISABLE PULSE 2
FPS ENABLE PULSE 3
4
WAIT tDIS
FPS DISABLE PULSE 1
WAIT tDIS
FPS DISABLE PULSE 0
WAIT 125ms
6
Figure 7. On/Off Controller Actions
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Maxim Integrated | 29
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Flexible Power Sequencer
The flexible power sequencer (FPS) allows resources to power up under hardware or software control. Additionally, each
resource can power up independently or among a group of other regulators with adjustable power-up and power-down
slots (sequencing). Figure 8 shows four resources powering up under the control of the flexible power sequencer.
The flexible sequencing structure consists of one master sequencing timer and four slave resources (SBB0, SBB1, SBB2
and SBB3). When the FPS is enabled, a master timer generates four sequencing events for device power-up and powerdown.
Therefore, the power-down sequence has a total delay up to 195.24ms (60ms + 4 x 2.56ms power-down slot delays +
125ms output discharge delay). If issuing the Software Cold Reset (CNFG_GLBL_A.SFT_CTRL[1:0]), wait more than
200ms before issuing additional commands through the I2C.
NOT DRAWN TO SCALE
ENFPS
tEN SAME FOR ALL FPS
ENABLE PULSES.
PLSFPS
0
1
2
3
3
2
1
tDIS SAME FOR ALL FPS
DISABLE PULSES.
0 tDIS = 2x tEN
FPS
RESOURCES
SBB0
SBB1
SBB2
SBB3
Figure 8. Flexible Power Sequencer Basic Timing Diagram
Startup Timing Diagram Due to nEN
NOT DRAWN TO SCALE
STATE
NO POWER
POR
SHUTDOWN
POWER-UP SEQUENCE
RESOURCE ON
POWER
CONNECTION
VIN
VPOR ~ 1.9V
tBIAS_EN
tPOR ~ 5ms
tDBNC_nEN
nEN
NOTE 1
tDBNC_nEN
NOTE 2
STAT_EN
FPS0
FPS1
tEN
FPS2
tEN
FPS3
tEN
REGULATORS
NOTES:
1 – nEN LOGIC INPUT IS CONFIGURED TO PUSH-BUTTON MODE AND HAS AN INTERNAL PULLUP TO IN.
2 – nEN ASSERTION RESULTS IN A WAKE-UP EVEN AFTER A DEBOUNCE TIME (tDBNCEN).
Figure 9. Startup Timing Diagram Due to nEN
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Maxim Integrated | 30
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Applications Information
LPM vs. NPM
In low-power mode, the MAX77655 draws less quiescent current by sampling various signals instead of continuously
monitoring them. The trade-off is higher output voltage ripple and slower transient response.
Things to Avoid
The following sections describe use cases to avoid to ensure the MAX77655 operates without faults.
Switching from LPM to NPM
Avoid switching from low-power mode to normal-power mode (writing CNFG_GLBL_A.BIAS_LPM from 1 to 0). If
switching from low-power mode to normal-power mode, the device may shut down from PVDD drooping below VPOR.
Switching from normal-power mode to low-power mode is okay.
Detailed Description—SIMO Buck-Boost
The device has a single-inductor, multiple-output (SIMO) buck-boost DC-to-DC converter designed for applications
emphasizing low quiescent current and small solution size. A single inductor is used to regulate four separate outputs,
saving board space while delivering total system efficiency better than equivalent power solutions using one buck and
linear regulators.
For battery applications, the SIMO configuration utilizes the entire battery voltage range due to its ability to create output
voltages that are above, below, or equal to the input voltage.
SIMO Features and Benefits
● Four Output Channels
● Ideal for Low-Power Designs
• Delivers > 700mA at 1.8V Output from a 3.7V Input
• ±2% Accurate Output Voltage
● Small Solution Size
• Multiple Outputs from a Single Inductor
• Small 22μF (0603) Output Capacitors
● Flexible and Easy to Use
• Automatic Transitions Between Buck, Buck-Boost, and Boost Operating Modes
• Programmable, On-Chip Active Discharge
● Long Battery Life
• High Efficiency, 90% Efficiency at 1.8V Output
• Better Total System Efficiency than a Discrete Buck + LDOs Solution
• Low Quiescent Current: 0.3μA Typical for Each Additional Output in Low-Power Mode
• Low Input Operating Voltage: 2.5V Minimum for Optimal Operation
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Maxim Integrated | 31
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
SIMO Simplified Block Diagram
1.5µH
LXA
LXB
BST
SYNCHRONOUS RECTIFIER
MAIN POWER STAGE
IN
IN
10nF
REVERSE
BLOCKING
M1
22µF
SBB0
22µF
M2
M4
M3_0
/
PGND
SIMO
CONTROLLER
/
EN_SBBx
SYNCHRONOUS
RECTIFIER (M3_1)
SYNCHRONOUS
RECTIFIER (M3_2)
SBB1
22µF
SBB2
22µF
/
SYNCHRONOUS
RECTIFIER (M3_3)
SBB3
22µF
Figure 10. SIMO Simple Block Diagram
Inductor Valley Current
The MAX77655 regulates inductor valley current or the lowest point in an inductor current cycle. Under light loads,
in which inductor valley current is 0A, the SIMO regulator operates in discontinuous conduction mode (DCM). If DCM
delivers insufficient energy to maintain any output voltage, the regulator switches to continuous conduction mode, raising
valley current above 0A. As load current increases, the valley current also increases in discrete steps. Figure 11 below
demonstrates how it increases or decreases with changing load current.
NOT DRAWN TO SCALE
INDUCTOR CURRENT
TOTAL LOAD CURRENT
INDUCTOR VALLEY CURRENT
Figure 11. Valley Current Control with Changing Load Current
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Maxim Integrated | 32
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
See the Typical Operating Characteristics section for examples.
SIMO Control Scheme
The SIMO buck-boost is designed to service multiple outputs simultaneously. A proprietary controller ensures that all
outputs are serviced in a timely manner, even while multiple outputs are contending for the energy stored in the inductor.
When no regulator needs service and low-power mode is enabled, the state machine rests in a low-power rest state.
Drive Strength
The SIMO regulator's drive strength for its internal power MOSFETs is adjustable using the
CNFG_SBB_TOP.DRV_SBB[1:0] bit field. Faster drive strength results in higher efficiency but requires stricter layout
rules or shielding to avoid additional EMI. Slower settings limit EMI in non-ideal settings (e.g., contained layout, antennae
adjacent to the device, etc.) but lower efficiency. Change the drive strength only once during system initialization.
SIMO Channel Operating Mode
Each SIMO channel can individually operate in one of three modes (buck, buck-boost, or boost) depending on the output
voltage to input voltage ratio. The operating mode is automatically chosen based on the VSBBx/VIN ratio as shown in
Table 4.
Table 4. SIMO Operating Mode Thresholds
OPERATING MODE
OUTPUT VOLTAGE TO INPUT VOLTAGE RATIO RANGE
Buck Mode
VSBBx/VIN < 0.6
Buck-Boost Mode
0.6 < VSBBx/VIN < 1.25
Boost Mode
1.25 < VSBBx/VIN
Examples
Given IN = 3.1V, SBB0 = 1.8V, SBB1 = 4.0V, SBB2 = 0.7V, and SBB3 = 3.3V, the operating mode for each channel is
shown in Table 5.
Table 5. Operating Mode Examples
VOLTAGE (V)
SBBx/IN RATIO
OPERATING MODE
SBB0
1.8
0.581
Buck
SBB1
4.0
1.290
Boost
SBB2
0.7
0.226
Buck
SBB3
3.3
1.064
Buck-Boost
Buck Mode
When an output needs service, switch M3_x remains closed and M4 remains open (see Figure 10). M1 and M2 are
toggled as in a traditional buck converter. That is, M1 is closed and M2 is open to both deliver energy to the output and
charge the inductor. Then M1 is open and M2 is closed to deliver energy stored in the inductor to the output.
Buck-Boost Mode
Unlike traditional buck-boost regulators, the SIMO regulator uses a three-state buck-boost control scheme. First, M1 and
M4 are closed to charge the inductor. Then M4 is open and M3_x is closed. This is similar to a buck regulator state,
delivering energy to the output while continuing to charge the inductor. Finally, M1 is open and M2 is closed, delivering
energy stored in the inductor to the output.
The second state improves efficiency in buck-boost mode compared to traditional control schemes.
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Maxim Integrated | 33
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Boost Mode
When an output needs service, switch M1 remains closed and M2 remains open. M3_x and M4 are toggled as in a
traditional boost converter. That is, M3_x is open and M4 is closed to charge the inductor. Then, M3_x is closed and M4
is open to deliver energy to the output from both the input and the charged inductor.
Channel-to-Channel Switching
To lower output voltage ripple, the regulator might switch directly from one channel to another using a proprietary
algorithm. During the transition from one channel to another, the LXB node is temporarily connected to ground.
SIMO Soft-Start
The soft-start feature of the SIMO limits inrush current during startup, achieved by limiting the slew rate of the output
voltage during startup (dV/dtSS).
More output capacitance results in higher input current surges during startup. The following example and set of equations
describe this phenomenon during startup.
The current into the output capacitor (ICSBB) during soft-start is:
dV
ICSBB = CSBB dt
SS
(Equation 1)
where:
● CSBB is the capacitance on the output of the regulator
● dV/dtSS is the voltage change rate of the output
The input current (IIN) during soft-start is:
IIN =
(ICSBB + ILOAD)
VSBBx
VIN
ξ
(Equation 2)
where:
●
●
●
●
●
ICSBB is from equation 1
ILOAD is the current consumed from the external load
VSBBx is the output voltage
VIN is the input voltage
ξ is the efficiency of the regulator
For example, given the following conditions, the peak input current (IIN) during soft-start is ~71mA:
Given:
●
●
●
●
●
●
VIN = 3.5V
VSBB2 = 3.3V
CSBB2 = 22µF
dV/dtSS = 2mV/µs
RLOAD2 = 330Ω (ILOAD2 = 3.3V/330Ω = 10mA)
ξ = 86%
Calculation:
● ICSBB = 22µF x 2mV/µs (from Equation 1)
● ICSBB = 44mA
3.3V
(44mA + 10mA) 3.5V
● IIN =
0.86
● IIN ~ 59.2mA
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(from Equation 1)
Maxim Integrated | 34
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
SIMO Registers
The CNFG_SBB_TOP register controls all SIMO channels, modifying the drive strength (DRV_SBB[1:0]). Each SIMO
buck-boost channel has a dedicated register to program its target output voltage (CNFG_SBBx_A.TV_SBBx[7:0]).
Additional controls are available in the CNFG_SBBx_B register for enabling/disabling the active discharge resistors
(ADE_SBBx) and enabling/disabling the SIMO buck-boost channels (EN_SBBx[2:0]). To monitor each channel in realtime for overload, read the STAT_GLBL.SBBx_S bits. To check if a channel was overloaded in the past, read the
INT_GLBL.SBBx_F flags. Note that the interrupt flags are cleared upon reading.
For a full description of bits, registers, default values, and reset conditions, see the Register Map section.
SIMO Active Discharge Resistance
Each SIMO buck-boost channel has an active-discharge resistor (RAD_SBBx) that is automatically enabled/disabled
based on a CNFG_SBBx_B.ADE_SBBx and the status of the SIMO regulator. The active discharge feature may be
enabled (CNFG_SBBx_B.ADE_SBBx = 1) or disabled (CNFG_SBBx_B.ADE_SBBx = 0) independently for each SIMO
channel. Enabling the active discharge feature helps ensure a complete and timely power down of all system peripherals.
If the active-discharge resistor is enabled, then the active-discharge resistor is enabled whenever the device is in
shutdown.
These resistors discharge the output when CNFG_SBBx_B.ADE_SBBx = 1 and the respective SIMO channel is off. If
the regulator is forced on through CNFG_SBBx_B.EN_SBBx = 0b110 or 0b111, then the resistors do not discharge the
output.
Bootstrap Refresh
The bootstrap capacitor (connected between the BST and LXB pins) is refreshed when one of the following conditions is
true:
● The capacitor has not been refreshed for a predetermined amount of time.
● While switching among three channels to service each one, none of those switching states connected LXB to ground.
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Maxim Integrated | 35
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Applications Information
SIMO Supported Output Current
Maximum supported output current is limited by inductor valley current (see the SIMO Continuous Conduction Mode
section). When the valley current is at its maximum value, channels enter overload condition, triggering their respective
fault interrupt flags. While the absolute maximum valley current is 1.2A (eight valley steps), stay below 900mA (six valley
steps) to avoid valley current occasionally reaching the absolute maximum.
In addition, if the average inductor current is above 700mA, ripple on the output channels can increase out of
specifications.
To predict if a given set of conditions is supported, estimate the average inductor current and the maximum valley current
the regulator experiences. Maxim provides a calculator (see the Support Materials section) for convenience. Table 6
shows some example results using the calculator.
Table 6. SIMO Supported Output Current for Common Applications
PARAMETERS
EXAMPLE 1
EXAMPLE 2
EXAMPLE 3
EXAMPLE 4
EXAMPLE 5
VIN
2.7V
4.0V
3.7V
3.7V
5.0V
SBB0
1.8V at 100mA
1.8V at 30mA
1.8V at 100mA
1.8V at 300mA
1.8V at 150mA
SBB1
3.3V at 200mA
3.3V at 200mA
1.1V at 120mA
1.2V at 100mA
1.2V at 70mA
SBB2
0.5V at 250mA
4.0V at 100mA
0.7V at 200mA
3.2V at 20mA
0.85V at 100mA
SBB3
4.0V at 50mA
4.0V at 100mA
3.3V at 80mA
2.85V at 100mA
2.0V at 80mA
Maximum IL,average
842mA
696mA
550mA
597mA
400mA
Maximum IL,valley
750mA
600mA
450mA
450mA
300mA
Overloaded?
No
No
No
No
No
Higher ripple?
Yes
No
No
No
No
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Maxim Integrated | 36
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
To manually estimate average inductor current, first estimate the average inductor current for each channel using the
following equations:
IL_avg =
{
VSBBx
Iout
,
3
x Iout
2
, 0.6 ≤ V
≤ 1.25 (Buck-Boost Mode) (Equation 3)
IN
VSBBx
Iout x V x η ,
IN
VIN
< 0.6 (Buck Mode)
VSBBx
VSBBx
VIN
> 1.25 (Boost Mode)
where η is efficiency (see the Typical Operating Characteristics section for efficiency values). The sum of the average
currents is the expected maximum, average inductor current. Then, using the total average inductor current, estimate the
number of valley current steps with the following equation:
IL_avg
IL_valley_steps = I
(Equation 4)
valley_step
where Ivalley_step is 150mA. If the number of steps is above the previously mentioned maximum value (8), the regulator
is overloaded. If the average inductor current is above 700mA, expect higher output voltage ripple.
Overload
While in overload condition, the output voltage can drop for any channel. A host controller can detect which channels are
"overloaded" by reading either the status bits (STAT_GLBL.SBBx_S) or the interrupt bits (INT_GLBL.SBBx_F), where x
is the channel number. Status bits convey the current state of the channel while interrupt bits indicate if a channel had
entered overload in the past. If the status bit indicates a channel is overloaded, its output voltage is most likely out of
regulation.
Inductor Selection
Choose an inductance from 1.0μH to 2.2μH; 1.5μH inductors work best for most designs. Larger inductances transfer
more energy to the output for each cycle and typically result in larger output voltage ripple and better efficiency. See the
Output Capacitor Selection section for more information on how to size the output capacitor to control ripple.
Choose an inductor whose saturation current is above the worst case peak inductor current. For example, if the worst
case occurs while drawing 700mA, the worst case peak inductor current is around 1.2A. For systems where the expected
load currents are not well known, use an inductor with saturation current ≥ 2A.
Consider the DC-resistance (DCR), AC-resistance (ACR), and package size of the inductor. Typically, smaller sized
inductors have larger DC and AC-resistance, reducing efficiency. Note that many inductor manufacturers have inductor
families containing different versions of core material to balance trade-offs between DCR, ACR (i.e., core losses), and
component cost.
Input Capacitor Selection
Choose the input bypass capacitance (CIN) to be at least 10µF. Larger values of CIN improve the decoupling for the
SIMO regulator.
The CIN reduces the current peaks drawn from the battery or input power source during SIMO regulator operation and
reduces switching noise in the system. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to
their small size, low ESR, and small temperature coefficients.
To fully utilize the available input voltage range of the device (5.5V max), use a capacitor with a voltage rating of 6.3V at
minimum.
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Maxim Integrated | 37
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Bootstrap Capacitor Selection
Choose the bootstrap capacitance (CBST) to be 10nF. Smaller values of CBST result in insufficient gate drive for M3.
Larger values of CBST (>100nF) have the potential to degrade the startup performance. Ceramic capacitors with 0201 or
0402 case size are recommended.
Output Capacitor Selection
Choose each output bypass capacitance (CSBBx) based on the target output voltage ripple (ΔVSBBx): typical value is
22μF. In addition, consider using at least 44µF for an individual channel if either the channel's output voltage is less than
1.5V or if the channel is lightly loaded while another channel is heavily loaded.
Larger values of CSBBx improve the output voltage ripple but increase the input surge currents during soft-start and
output voltage changes. The output voltage ripple is a function of the inductance (L), the output voltage (VSBBx), and
the inductor current ripple (ΔIL), which is typically 300mA to 500mA. See equation 5 to estimate the minimum effective
capacitance for a given ripple, but always have at minimum 10μF.
∆ I L2 x L
CSBBx = 2 x V
(Equation 5)
SBBx x ∆ VSBBx
Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small
temperature coefficients.
A capacitor's effective capacitance decreases with DC bias voltage. This effect is more pronounced with physically
smaller capacitors. Due to this, it is possible for 0603 capacitors to perform well while 0402 capacitors of the same
nominal capacitance performs poorly. Consider the effective output capacitance value after initial tolerance, bias voltage,
aging, and temperature derating.
PVDD and VDD Capacitors
Always have a minimum of 10μF capacitance near the PVDD pin. When PVDD and VDD are connected with a short
length trace, VDD can share PVDD's capacitor. If they are not connected, place at minimum a 1μF capacitor near the
VDD pin.
Unused Outputs
Do not leave unused outputs unconnected. If an output left unconnected is accidentally enabled, the charged inductor
experiences an open circuit, and the output voltage soars above the absolute maximum rating, damaging the device. If
an output is not used, do one of the following:
1. Disable the output (CNFG_SBBx_B.EN_SBBx[2:0] = 0x4 or 0x5) and connect the output to ground. If an unused
output is enabled by default or can be accidentally enabled, do one of the other recommendations instead.
2. Bypass the unused output with a 1µF capacitor to ground.
3. Connect the unused output to IN or a different output channel if the unused output is programmed to a lower voltage.
Since the output voltage is higher than the unused output, the regulator does not service the unused output even if it
is unintentionally enabled.
● Note that some OTP options have the active-discharge resistors enabled by default. Connecting an unused
output to IN is not recommended if the active discharge is enabled by default. If connecting the unused output
to a different channel, disable the active discharge resistor (CNFG_SBBx_B.ADE_SBBx = 0) of the unused
channel.
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Maxim Integrated | 38
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Snubbing Circuit
To reduce peak voltage on LXB during switching events, add a snubbing circuit (3.9Ω in series with 1.5nF) between LXB
and PGND as shown in Figure 12.
LXA
MAX77655
LXB
BST
3.9Ω
1.5nF
PGND
Figure 12. LXB Snubbing Circuit
Output Voltage Ripple
While the regulator is operating in CCM (inductor valley current is greater than 0A), the output voltage ripple for one
channel is affected by other channels. For example, channels may droop lower in voltage while waiting for another
channel to be serviced. In addition, while one or more channels are loaded with more than 300mA, other channels may
occasionally have larger spikes in voltage ripple. Ripple also increases with output voltage.
Ripple is highest when there is heavy load on at least one channel while other channels have less load.
Assuming at least 300mA total load current and 22µF of output capacitance, for channels whose output voltage is 2.5V
or less, the occasional spike in voltage ripple can be up to 200mV while the average ripple is < 100mV. For channels
whose output voltage is greater than 2.5V, the occasional spike in voltage ripple can be up to 300mV while the average
ripple is < 120mV.
See the Output Capacitor Selection section for recommendations on how much output capacitance to use.
PCB Layout Guide
Capacitors
Place decoupling capacitors as close as possible to the IC such that connections from capacitor pads to pin and from
capacitor pads to ground pins are short. Keeping the connections short lowers parasitic inductance and resistance,
improving performance and shrinking the physical size of hot loops.
If connections to the capacitors are through vias, use multiple vias to minimize parasitics. Also, connect loads to the
capacitor pads rather than the device pins.
Input Capacitor at IN
Minimize the parasitic inductance from PGND to input capacitor to IN to reduce ringing on the LXA voltage.
Output Capacitors at SBBx
The output capacitors experience large changes in current as the regulator charges and discharges the inductor.
Minimize parasitic inductance from SBBx to output capacitor to PGND.
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Maxim Integrated | 39
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Inductor
Keep the inductor close to the IC to reduce trace resistance. However, prioritize any regulator input/output capacitors
over the inductor. Use the appropriate trace width from LXA to inductor to LXB to support the worst case, peak inductor
current (see the Inductor Selection section). Likewise, if there are vias in the path, use an appropriate number of vias to
support the current.
Ground Connections
As the switching regulator charges and discharges the inductor, current flows from PGND to the input capacitor ground,
from output capacitor ground to PGND, or from output capacitor ground to input capacitor ground. Therefore, use a wide,
continuous copper plane to connect PGND to the capacitor grounds.
When connecting the GND and PGND pins together, ensure noise from the power ground does not enter the analog
ground (where GND is connected). For example, assuming the ground pins are connected through a solid ground plane
on an internal layer, one via connecting GND to the internal ground plane may be sufficient to protect GND from most of
the noise in the power-ground plane. Likewise, if there are other higher current or noisy circuitry near this device, avoid
connecting the GND pin directly to their grounds.
For more guidelines on grounding, visit https://www.maximintegrated.com/en/design/partners-and-technology/designtechnology/ground-layout-board-designers.html.
Example PCB Layout
Figure 13 shows an example layout.
GND
SBB0
CSBB0
GND
CSBB1
SBB1
CSBB2
SBB2
CSBB3
SBB3
nIRQ
nEN
SCL
SDA
CPVDD
CIN
IN
GND
Csnub
Rsnub
CBST
L
Figure 13. PCB Top-Layer and Component Placement Example
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Maxim Integrated | 40
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Things to Avoid
The following sections describe use cases to avoid to ensure the MAX77655 operates without faults.
Load Transient Between No Load and Heavy Load
Avoid load transients between no load and heavy load (e.g., 300mA). If this occurs while other channels are loaded, the
channel experiencing the transient may droop out of regulation. Load transients starting from or ending at ~5mA instead
of no load avoid this issue.
Overload While in LPM
If CNFG_GLBL_A.BIAS_LPM = 1, VIN < 3.1V, and the regulator is in overload condition, the device may shut down due
to PVDD drooping below VPOR.
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Maxim Integrated | 41
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Detailed Description—I2C Serial Interface
General Description
This device features a revision 3.0 I2C-compatible, 2-wire serial interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). This device acts as a slave-only device and depends on the master to generate the
clock signal. The SCL clock rates from 0Hz to 3.4MHz are supported. The I2C serial communication is an open-drain
bus and therefore SDA and SCL require pullups. Optional resistors (24Ω) in series with SDA and SCL protect the device
inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot on bus signals.
Figure 14 shows the functional diagram for the I2C based communications controller. For additional information on I2C,
refer to the I2C bus specification and user manual, which is available for free through the internet.
Features
●
●
●
●
●
I2C Revision 3.0 Compatible Serial Communications Channel
0Hz to 100kHz (Standard Mode)
0Hz to 400kHz (Fast Mode)
0Hz to 1MHz (Fast-Mode Plus)
0Hz to 3.4MHz (High-Speed Mode)
I2C Simplified Block Diagram
COMMUNICATIONS CONTROLLER
VDD
SDA
GND
INTERFACE
DECODERS
SHIFT REGISTERS
BUFFERS
COM
SCL
SIMO
Figure 14. I2C Simplified Block Diagram
I2C System Configuration
The I2C bus is a multimaster bus. The maximum number of devices that can attach to the bus is only limited by bus
capacitance.
A device on the I2C bus that sends data to the bus is called a transmitter. A device that receives data from the bus
is called a receiver. The device that initiates a data transfer and generates the SCL clock signals to control the data
transfer is a master. Any device that is being addressed by the master is considered a slave. The I2C compatible interface
operates as a slave on the I2C bus with transmit and receive capabilities.
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SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Figure 15. I2C System Configuration
I2C Interface Power
The I2C interface derives its power from VDD. Bypass the VDD pin with a local 1μF ceramic capacitor to ground.
I2C Data Transfer
One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period
of the SCL clock pulse. Changes in SDA while SCL is high are control signals. See the I2C Start and Stop Conditions
section. Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is nine
bits long: eight bits of data followed by the acknowledge bit. Data is transferred with the MSB first.
I2C Start and Stop Conditions
When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a
START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high
transition on SDA, while SCL is high. See Figure 16.
A START condition from the master signals the beginning of a transmission to a slave. The master terminates
transmission by issuing a not-acknowledge followed by a STOP condition (see the I2C Acknowledge Bit section for
information on not-acknowledge). The STOP condition frees the bus. To issue a series of commands to the slave, the
master can issue repeated start (Sr) commands instead of a STOP command to maintain control of the bus. In general,
a repeated start command is functionally equivalent to a regular start command.
S
Sr
P
SDA
tSU_STA
tSU_STO
SCL
tHD_STA
tHD_STA
Figure 16. I2C Start and Stop Conditions
I2C Acknowledge Bit
Both the I2C bus master and this device generate acknowledge bits when receiving data. The acknowledge bit is the
last bit of each nine bit data packet. To generate an acknowledge (A), the receiving device must pull SDA low before the
rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse.
See Figure 17. To generate a not-acknowledge (nA), the receiving device allows SDA to be pulled high before the rising
edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs
if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus
master should reattempt communication at a later time.
This device issues an ACK for all register addresses in the possible address space even if the particular register does
not exist.
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NOT ACKNOWLEDGE (NACK)
S
ACKNOWLEDGE (ACK)
SDA
tSU_DAT
1
SCL
2
tHD_DAT
8
9
Figure 17. Acknowledge Bit
I2C Slave Address
The I2C controller implements 7-bit slave addressing. An I2C bus master initiates communication with the slave by issuing
a START condition followed by the slave address. See Figure 18. The OTP address is factory programmable for one of
two options. See Table 7. All slave addresses not mentioned in the Table 7 are not acknowledged.
Table 7. I2C Slave Address Options
ADDRESS
7-BIT SLAVE ADDRESS
8-BIT WRITE ADDRESS
8-BIT READ ADDRESS
Main Address
(ADDR[1:0] = 0x0)*
0x40, 0b 100 0000
0x80, 0b 1000 0000
0x81, 0b 1000 0001
Main Address
(ADDR[1:0] = 0x1)*
0x44, 0b 100 0100
0x88, 0b 1000 1000
0x89, 0b 1000 1001
Main Address
(ADDR[1:0] = 0x2)*
0x48, 0b 100 1000
0x90, 0b 1001 0000
0x91, 0b 1001 0001
Main Address
(ADDR[1:0] = 0x3)*
0x52, 0b 101 0010
0xA4, 0b 1010 0100
0xA5, 0b 1010 0101
Test Mode**
0x49, 0b 100 1001
0x92, 0b 1001 0010
0x93, 0b 1001 0011
*Perform all reads and writes on the Main Address. The ADDR is a factory one-time programmable (OTP) option, allowing
for address changes in the event of a bus conflict. Contact Maxim for more information.
**When test mode is unlocked, the additional address is acknowledged. Test mode details are confidential. If possible,
leave the test mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation
with Maxim.
S
SDA
1
0
0
0
1
0
SCL
1
2
3
4
5
6
0
R/W
A
ACKNOWLEDGE
7
8
9
Figure 18. Slave Address Example
I2C Clock Stretching
In general, the clock signal generation for the I2C bus is the responsibility of the master device. The I2C specification
allows slow slave devices to alter the clock signal by holding down the clock line. The process in which a slave device
holds down the clock line is typically called clock stretching. This device does not use any form of clock stretching to hold
down the clock line.
I2C General Call Address
This device does not implement the I2C specifications general call address and does not issue an acknowledge for a
general call address (0b0000 0000).
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I2C Device ID
This device does not support the I2C Device ID feature.
I2C Communication Speed
This device is compatible with all four communication speed ranges as defined by the I2C Revision 3.0 specification:
●
●
●
●
0Hz to 100kHz (Standard Mode)
0Hz to 400kHz (Fast Mode)
0Hz to 1MHz (Fast-Mode Plus)
0Hz to 3.4MHz (High-Speed Mode)
Operating in standard mode, fast mode, and fast-mode plus does not require any special protocols. The main
consideration when changing the bus speed through this range is the combination of bus capacitance and pullup
resistors. Larger values of bus capacitance and pullup resistance increase the time constant (C x R), slowing bus
operation. Therefore, when increasing bus speeds, the pullup resistance must be decreased to maintain a reasonable
time constant. Refer to the Pullup Resistor Sizing section of the I2C bus specification and user manual (available for free
on the internet) for detailed guidance on the pullup resistor selection. In general for bus capacitances of 200pF, a 100kHz
bus needs 5.6kΩ pullup resistors, a 400kHz bus needs about a 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω
pullup resistors. Note that when the open-drain bus is low, the pullup resistor is dissipating power, lower value pullup
resistors dissipate more power (V2/R).
Operating in high-speed mode requires some special considerations. For a full list of considerations, refer to the publicly
available I2C bus specification and user manual. Major considerations with respect to this device are:
● The I2C bus master uses current source pullups to shorten the signal rise.
● The I2C slave must use a different set of input filters on its SDA and SCL lines to accommodate for the higher bus.
● The communication protocols need to utilize the high-speed master code.
At power-up and after each stop condition, the I2C input filters are set for standard mode, fast mode, and fast mode plus
(i.e., 0Hz to 1MHz). To switch the input filters for high-speed mode, use the high-speed master code protocols that are
described in the I2C Communication Protocols section.
I2C Communication Protocols
This device supports both writing and reading from its registers.
Writing to a Single Register
Figure 19 shows the protocol for the I2C master device to write one byte of data. This protocol is the same as the SMBus
specification’s write byte protocol.
The write byte protocol is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
The master sends a start command (S).
The master sends the 7-bit slave address followed by a write bit (R/W = 0).
The addressed slave asserts an acknowledge (A) by pulling SDA low.
The master sends an 8-bit register pointer.
The slave acknowledges the register pointer.
The master sends a data byte.
The slave updates with the new data.
The slave asserts an acknowledge or a not acknowledge for the data byte. The next rising edge on SDA loads the
data byte into its target register and the data becomes active.
9. The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters
are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state.
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LEGEND
MASTER TO
SLAVE
1
S
7
SLAVE TO
MASTER
1 1
SLAVE ADDRESS
0 A
8
1
REGISTER POINTER
8
A
DATA
R/W
SDA
B1
B0
ACK
1
ACK OR
NACK
1
NUMBER
OF BITS
P OR SR*
THE DATA IS
LOADED INTO THE
TARGET REGISTER
AND BECOMES
ACTIVE DURING
THIS RISING EDGE.
ACKNOWLEDGE
SCL
7
8
9
*P FORCES THE BUS FILTERS TO
SWITCH TO SUB-MEGAHERTZ
MODE. SR LEAVES THE BUS
FILTERS IN THEIR CURRENT
STATE.
Figure 19. Writing to a Single Register with the Write Byte Protocol
Writing Multiple Bytes to Sequential Registers
Figure 20 shows the protocol for writing to sequential registers. This protocol is similar to the write byte protocol described
in the Writing to a Single Register section, except the master continues to write after it receives the first byte of data.
When the master is done writing, it issues a stop or repeated start.
The protocol for writing to sequential registers is as follows:
1.
2.
3.
4.
5.
6.
7.
The master sends a start command (S).
The master sends the 7-bit slave address followed by a write bit (R/W = 0).
The addressed slave asserts an acknowledge (A) by pulling SDA low.
The master sends an 8-bit register pointer.
The slave issues an acknowledge for the register pointer.
The master sends a data byte.
The slave issues an acknowledge for the data byte. The next rising edge on SDA loads the data byte into its target
register and the data becomes active.
8. Steps 6 to 7 are repeated as many times as the master requires.
9. During the last issued acknowledge-related clock pulse, the master can issue an acknowledge or a not
acknowledge.
10. The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters
are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state.
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LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
1
7
1 1
S
SLAVE ADDRESS
8
0 A REGISTER POINTER X
1
8
1
A
DATA X
A
NUMBER
OF BITS
Α
R/W
8
1
DATA X+1
A
Α
REGISTER POINTER = X + 1
8
1
DATA N-1
A
REGISTER POINTER = N-1
8
1
DATA X+2
A
REGISTER POINTER = X + 2
8
Α
1
ACK OR
NACK
DATA N
Α
NUMBER
OF BITS
REGISTER POINTER = N
NUMBER
OF BITS
1
P OR SR*
Β
THE DATA IS
LOADED INTO THE
TARGET REGISTER
AND BECOMES
ACTIVE DURING
THIS RISING EDGE.
SDA
B1
B0
ACK
B9
9
1
ACKNOWLEDGE
SCL
7
8
DETAIL: Α
THE DATA IS
LOADED INTO THE
TARGET REGISTER
AND BECOMES
ACTIVE DURING
THIS RISING EDGE.
SDA
B1
B0
ACK
ACKNOWLEDGE
SCL
7
8
9
DETAIL: Β
*P FORCES THE
BUS FILTERS TO
SWITCH TO SUBMEGAHERTZ MODE.
SR LEAVES THE
BUS FILTERS IN
THEIR CURRENT
STATE.
Figure 20. Writing to Sequential Registers X to N
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Reading from a Single Register
Figure 21 shows the protocol for the I2C master device to read one byte of data. This protocol is the same as the SMBus
specification’s read byte protocol.
The read byte protocol is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
The master sends a start command (S).
The master sends the 7-bit slave address followed by a write bit (R/W = 0).
The addressed slave asserts an acknowledge (A) by pulling SDA low.
The master sends an 8-bit register pointer.
The slave issues an acknowledge for the register pointer.
The master sends a repeated start command (Sr).
The master sends the 7-bit slave address followed by a read bit (R/W = 1).
The addressed slave asserts an acknowledge by pulling SDA low.
The addressed slave places 8 bits of data on the bus from the location specified by the register pointer.
The master issues a not acknowledge (nA).
The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters
are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state.
Note that when this device receives a stop, the register pointer is not modified. Therefore, if the master wants to re-read
the same register, it can start at step 7 in the read byte protocol.
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHz MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
LEGEND
MASTER TO
SLAVE
1
7
S
SLAVE ADDRESS
SLAVE TO
MASTER
1 1
R/W
8
0 A REGISTER POINTER X
1 1
7
1 1
8
1
1
A Sr
SLAVE ADDRESS
1 A
DATA X
A
P or Sr*
NUMBER
OF BITS
R/W
Figure 21. Reading from a Single Register with the Read Byte Protocol
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Reading from Sequential Registers
Figure 22 shows the protocol for reading from sequential registers. This protocol is similar to the read byte protocol except
the master issues an acknowledge to signal the slave that it wants more data: when the master has all the data it requires
it issues a not acknowledge (nA) and a stop (P) to end the transmission.
The protocol for continuous read from sequential registers is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
The master sends a start command (S).
The master sends the 7-bit slave address followed by a write bit (R/W = 0).
The addressed slave asserts an acknowledge (A) by pulling SDA low.
The master sends an 8-bit register pointer.
The slave issues an acknowledge for the register pointer.
The master sends a repeated start command (Sr).
The master sends the 7-bit slave address followed by a read bit (R/W = 1).
The addressed slave asserts an acknowledge by pulling SDA low.
The addressed slave places 8 bits of data on the bus from the location specified by the register pointer.
The master issues an acknowledge (A) signaling the slave that it wishes to receive more data.
Steps 9 to 10 are repeated as many times as the master requires. Following the last byte of data, the master must
issue a not acknowledge (nA) to signal that it wishes to stop receiving data.
12. The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a stop (P) ensures that the bus
input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state.
Note that when this device receives a stop, the register pointer is not modified. Therefore, if the master wants to re-read
the same register, it can start at step 7 in the read byte protocol.
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHz MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
LEGEND
MASTER TO
SLAVE
1
7
S
SLAVE ADDRESS
SLAVE TO
MASTER
1 1
R/W
8
0 A REGISTER POINTER X
1 1
7
1 1
8
1
A SR
SLAVE ADDRESS
1 A
DATA X
A
1
8
1
A
DATA X+3
A
R/W
8
1
8
DATA X+1
A
DATA X+2
NUMBER
OF BITS
NUMBER
OF BITS
REGISTER POINTER = X + 1 REGISTER POINTER = X + 2 REGISTER POINTER = X + 3
8
1
8
1
8
1
1
DATA N-2
A
DATA N-1
A
DATA N
NA
P OR SR*
REGISTER POINTER = N-2
REGISTER POINTER = N-1
NUMBER
OF BITS
REGISTER POINTER = N
Figure 22. Reading Continuously from Sequential Registers X to N
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Engaging HS Mode for Operation up to 3.4MHz
Figure 23 shows the protocol for engaging HS mode operation. HS mode operation allows for a bus operating speed up
to 3.4MHz.
The engaging HS mode protocol is as follows:
1.
2.
3.
4.
5.
Begin the protocol while operating at a bus speed of 1MHz or lower
The master sends a start command (S).
The master sends the 8-bit master code of 0b0000 1XXX where 0bXXX are don’t care bits.
The addressed slave issues a not acknowledge (nA).
The master may increase its bus speed up to 3.4MHz and issue any read/write operation.
The master may continue to issue high-speed read/write operations until a stop (P) is issued. To continue operations in
high-speed mode, use repeated start (Sr).
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
1
8
1 1
S
HS-MASTER CODE
nA SR
FAST MODE
ANY R/W PROTOCOL
FOLLOWED BY SR
SR
ANY R/W PROTOCOL
FOLLOWED BY SR
HS MODE
SR
ANY READ/WRITE
PROTOCOL
P
FAST MODE
Figure 23. Engaging HS Mode
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Register Map
MAX77655
ADDRESS
NAME
MSB
LSB
Configuration
BIAS_LP
M
MRT
SBB1_F
SBB0_F
TJAL2_R
TJAL1_R
nEN_R
nEN_F
SBB2_F
M
SBB1_F
M
SBB0_F
M
TJAL2_R
M
TJAL1_R
M
nEN_RM
nEN_FM
SBB2_S
SBB1_S
SBB0_S
RSVD
TJAL2_S
TJAL1_S
STAT_E
N
SFT_CR
ST_F
SFT_OF
F_F
MRST
UVLO
OVLO
TOVLD
0x00
CNFG_GLBL_A[7:0]
RSVD[1:0]
PU_DIS
0x01
CNFG_GLBL_B[7:0]
0x02
INT_GLBL[7:0]
SBB3_F
SBB2_F
0x03
INTM_GLBL[7:0]
SBB3_F
M
0x04
STAT_GLBL[7:0]
SBB3_S
0x05
ERCFLAG[7:0]
0x06
CID[7:0]
0x07
CONFIG_SBB_TOP[7:0
]
0x08
CNFG_SBB0_A[7:0]
0x09
CNFG_SBB0_B[7:0]
0x0A
CNFG_SBB1_A[7:0]
0x0B
CNFG_SBB1_B[7:0]
0x0C
CNFG_SBB2_A[7:0]
0x0D
CNFG_SBB2_B[7:0]
0x0E
CNFG_SBB3_A[7:0]
0x0F
CNFG_SBB3_B[7:0]
RSVD[4:0]
RSVD[1:0]
DBEN_n
EN
nEN_MODE[1:0]
SFT_CTRL[2:0]
CID[7:0]
RSVD[5:0]
DRV_SBB[1:0]
TV_SBB0[7:0]
RSVD[1:0]
ADE_SB
B0
RSVD[1:0]
EN_SBB0[2:0]
TV_SBB1[7:0]
RSVD[1:0]
ADE_SB
B1
RSVD[1:0]
EN_SBB1[2:0]
TV_SBB2[7:0]
RSVD[1:0]
ADE_SB
B2
RSVD[1:0]
EN_SBB2[2:0]
TV_SBB3[7:0]
RSVD[1:0]
ADE_SB
B3
RSVD[1:0]
EN_SBB3[2:0]
Register Details
CNFG_GLBL_A (0x00)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[1:0]
PU_DIS
BIAS_LPM
MRT
nEN_MODE[1:0]
DBEN_nEN
Reset
0x0
0x0
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Access
Type
BITFIELD
RSVD
PU_DIS
BITS
7:6
5
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DESCRIPTION
DECODE
Reserved. These bits are don't care.
Enable or disable an internal pullup resistor at
the nEN pin.
0x0: Enable internal nEN pullup (200kΩ)
0x1: Internal pullup disabled
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MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
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BITFIELD
BITS
DESCRIPTION
DECODE
BIAS_LPM
4
Main Bias Low-Power Mode Software
Request
0x0: Main Bias forced to be in Normal-Power Mode
by software.
0x1: Main Bias request to be in Low-Power Mode
by software.
If at least one channel is serviced more than twice
in 15μs, the regulator automatically enters normalpower mode.
MRT
3
Manual Reset Time Configuration.
See the nEN Manual Reset section for more
details.
0x0: Manual Reset Time is 16s.
0x1: Manual Reset Time is 8s.
nEN Mode
0x0: Push-Button Mode
0x1: Slide-Switch Mode
0x2: Logic Mode
0x3: Reserved
Debounce Timer Enable for the nEN Pin
0x0: 100μs Debounce
0x1: 30ms Debounce
nEN_MODE
2:1
DBEN_nEN
0
CNFG_GLBL_B (0x01)
BIT
7
6
5
4
3
2
1
Field
RSVD[4:0]
SFT_CTRL[2:0]
Reset
0x0
0x0
Write, Read
Write, Read, Ext
Access
Type
BITFIELD
BITS
RSVD
7:3
SFT_CTRL
2:0
DESCRIPTION
0
DECODE
Reserved. These bits are don't care.
Software Control Functions. See the On/Off
Controller section for more information about
what each command does.
0x0: No Action
0x1: Software Cold Reset (SFT_CRST). The
device powers down, resets, and then powers up
again.
0x2: Software Off (SFT_OFF). The device powers
down, resets, and then remains off until a wake-up
event.
0x3: Software Standby (SFT_STBY). The device
powers down and goes to standby mode.
0x4: Software Exit Standby (SFT_EXIT_STBY).
The device exits standby mode and powers up
again.
0x5 - 0x7: Reserved
INT_GLBL (0x02)
BIT
Field
Reset
Access
Type
7
6
5
4
3
2
1
0
SBB3_F
SBB2_F
SBB1_F
SBB0_F
TJAL2_R
TJAL1_R
nEN_R
nEN_F
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
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MAX77655
BITFIELD
Low IQ SIMO PMIC with 4-Outputs Delivering up to
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BITS
SBB3_F
7
SBB2_F
6
SBB1_F
5
DESCRIPTION
DECODE
SBB3 Channel Fault Interrupt
0x0: SBB3 was not overloaded since the last time
this bit was read.
0x1: SBB3 was overloaded since the last time this
bit was read.
SBB2 Channel Fault Interrupt
0x0: SBB2 was not overloaded since the last time
this bit was read.
0x1: SBB2 was overloaded since the last time this
bit was read.
SBB1 Channel Fault Interrupt
0x0: SBB1 was not overloaded since the last time
this bit was read.
0x1: SBB1 was overloaded since the last time this
bit was read.
SBB0_F
4
SBB0 Channel Fault Interrupt
0x0: SBB0 was not overloaded since the last time
this bit was read.
0x1: SBB0 was overloaded since the last time this
bit was read.
TJAL2_R
3
Thermal Alarm 2 Rising Interrupt
0x0: The junction temperature has not risen above
TJAL2 since the last time this bit was read.
0x1: The junction temperature has risen above
TAJL2 since the last time this bit was read.
Thermal Alarm 1 Rising Interrupt
0x0: The junction temperature has not risen above
TJAL1 since the last time this bit was read.
0x1: The junction temperature has risen above
TAJL1 since the last time this bit was read.
nEN Rising Interrupt
0x0: No nEN rising edges have occurred since the
last time this bit was read.
0x1: A nEN rising edge as occurred since the last
time this bit was read.
nEN Falling Interrupt
0x0: No nEN falling edges have occurred since the
last time this bit was read.
0x1: A nEN falling edge as occurred since the last
time this bit was read.
TJAL1_R
2
nEN_R
1
nEN_F
0
INTM_GLBL (0x03)
BIT
7
6
5
4
3
2
1
0
Field
SBB3_FM
SBB2_FM
SBB1_FM
SBB0_FM
TJAL2_RM
TJAL1_RM
nEN_RM
nEN_FM
Reset
0b1
0b1
0b1
0b1
0b1
0b1
0b1
0b1
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Access
Type
BITFIELD
BITS
DESCRIPTION
SBB3_FM
7
SBB3 Channel Fault Interrupt Mask
SBB2_FM
6
SBB2 Channel Fault Interrupt Mask
SBB1_FM
5
SBB1 Channel Fault Interrupt Mask
SBB0_FM
4
SBB0 Channel Fault Interrupt Mask
TJAL2_RM
3
Thermal Alarm 2 Rising Interrupt Mask
TJAL1_RM
2
Thermal Alarm 1 Rising Interrupt Mask
nEN_RM
1
nEN Rising Interrupt Mask
nEN_FM
0
nEN Falling Interrupt Mask
www.maximintegrated.com
Maxim Integrated | 53
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
STAT_GLBL (0x04)
7
6
5
4
3
2
1
0
Field
BIT
SBB3_S
SBB2_S
SBB1_S
SBB0_S
RSVD
TJAL2_S
TJAL1_S
STAT_EN
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Access
Type
BITFIELD
BITS
DESCRIPTION
DECODE
SBB3_S
7
SBB3 Channel Regulation Status
0x0: SBB3 is overloaded or disabled
0x1: SBB3 is not overloaded
SBB2_S
6
SBB2 Channel Regulation Status
0x0: SBB2 is overloaded or disabled
0x1: SBB2 is not overloaded
SBB1_S
5
SBB1 Channel Regulation Status
0x0: SBB1 is overloaded or disabled
0x1: SBB1 is not overloaded
SBB0_S
4
SBB0 Channel Regulation Status
0x0: SBB0 is overloaded or disabled
0x1: SBB0 is not overloaded
RSVD
3
Reserved. This bit is a don't care.
TJAL2_S
2
Thermal Alarm 2 Status
0x0: The junction temperature is less than TJAL2
0x1: The junction temperature is greater than
TJAL2
TJAL1_S
1
Thermal Alarm 1 Status
0x0: The junction temperature is less than TJAL1
0x1: The junction temperature is greater than
TJAL1
STAT_EN
0
Debounced Status for the nEN input.
0x0: nEN is not asserted (logic HIGH)
0x1: nEN is asserted (logic LOW)
ERCFLAG (0x05)
BIT
7
6
5
4
3
2
1
0
SFT_CRST
_F
SFT_OFF_
F
MRST
UVLO
OVLO
TOVLD
Field
RSVD[1:0]
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Read Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Access
Type
BITFIELD
RSVD
SFT_CRST_
F
SFT_OFF_F
MRST
BITS
7:6
5
4
3
www.maximintegrated.com
DESCRIPTION
DECODE
Reserved. These bits are don't care.
Software Cold Reset Flag
0x0: The software cold reset has not occurred
since the last read of this register.
0x1: The software cold reset has occurred since
the last read of this register. This indicates that
software has set SFT_CTRL[1:0] = 0b01.
Software Off Flag
0x0: The SFT_OFF function has not occurred
since the last read of this register.
0x1: The SFT_OFF function has occurred since
the last read of this register. This indicates that
software has set SFT_CTRL[1:0] = 0b10.
Manual Reset Timer
0x0: A manual reset has not occurred since this
last read of this register.
0x1: A manual reset has occurred since this last
read of this register.
Maxim Integrated | 54
MAX77655
BITFIELD
UVLO
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
BITS
2
OVLO
1
TOVLD
0
DESCRIPTION
DECODE
Undervoltage Lockout
0x0: The undervoltage lockout has not occurred
since this last read of this register.
0x1: The undervoltage lockout has occurred since
the last read of this register. This indicates that the
VIN voltage fell below UVLO (~2.4V)
Overvoltage Lockout
0x0: The overvoltage lockout has not occurred
since this last read of this register.
0x1: The overvoltage lockout has occurred since
the last read of this register. This indicates that the
VIN voltage rose above OVLO (~5.85V)
Thermal Overload
0x0: The thermal overload has not occurred since
the last read of this register.
0x1: The thermal overload has occurred since the
last read of this register. This indicates that the
junction temperature exceeded +145ºC.
CID (0x06)
BIT
7
6
5
4
3
Field
CID[7:0]
Reset
0x0
Access
Type
2
1
0
Read Only
BITFIELD
BITS
CID
DESCRIPTION
7:0
Chip Identification Code. These bits track the OTP configuration.
CONFIG_SBB_TOP (0x07)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[5:0]
DRV_SBB[1:0]
Reset
0x0
0x0
Write, Read
Write, Read
Access
Type
BITFIELD
RSVD
DRV_SBB
BITS
DESCRIPTION
DECODE
7:2
Reserved. The bit is a don't care.
1:0
SIMO Buck-Boost (All Channels) Drive
Strength Trim.
See the Drive Strength section for more
details.
0x0: Fastest transition time (~0.6ns)
0x1: A little slower than 0b00 (~1.2ns)
0x2: A little slower than 0b01 (~1.8ns)
0x3: A little slower than 0b10 (~8ns)
CNFG_SBB0_A (0x08)
BIT
7
6
5
4
3
Field
TV_SBB0[7:0]
Reset
0x0
Access
Type
www.maximintegrated.com
2
1
0
Write, Read
Maxim Integrated | 55
MAX77655
BITFIELD
TV_SBB0
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
BITS
DESCRIPTION
DECODE
0x00: 0.500V
0x01: 0.525V
0x02: 0.550V
0x03: 0.575V
...
0x8B: 3.975V
0x8C: 4.000V
0x8D–0xFF: Reserved
SIMO Buck-Boost Channel 0 Target Output
Voltage. This 8-bit configuration is a linear
transfer function that starts at 0.5V and ends
at 4.0V with 25mV increments. Values of
0x8D and higher are reserved.
VSBB0 = 0.5V + 0.025V x TV_SBB0[7:0]
7:0
CNFG_SBB0_B (0x09)
BIT
7
6
5
4
3
2
1
Field
RSVD[1:0]
RSVD[1:0]
ADE_SBB0
EN_SBB0[2:0]
Reset
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
Access
Type
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:6
Reserved
RSVD
5:4
Reserved
ADE_SBB0
EN_SBB0
3
2:0
0
SIMO Buck-Boost Channel 0 ActiveDischarge Enable
0x0: The active discharge function is disabled.
When SBB0 is disabled, its discharge rate is a
function of the output capacitance and the external
load.
0x1: The active discharge function is enabled.
When SBB0 is disabled, an internal resistor
(RAD_SBB0) is activated from SBB0 to PGND to
help the output voltage discharge. The output
voltage discharge rate is a function of the output
capacitance, the external loading, and the internal
RAD_SBB0 load.
Enable Control for SIMO Buck-Boost Channel
0. Select an FPS slot that the channel powers
up and powers down in or whether the
channel is forced on or off.
After the SIMO is enabled, the bias circuits
may be programmed back to low-power
mode (CNFG_GLBL_A.BIAS_LPM = 1) to
decrease quiescent current.
0x0: FPS slot 0
0x1: FPS slot 1
0x2: FPS slot 2
0x3: FPS slot 3
0x4: Off
0x5: Same as 0x4
0x6: On
0x7: Same as 0x6
CNFG_SBB1_A (0x0A)
BIT
7
6
5
4
3
Field
TV_SBB1[7:0]
Reset
0x0
Access
Type
www.maximintegrated.com
2
1
0
Write, Read
Maxim Integrated | 56
MAX77655
BITFIELD
TV_SBB1
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
BITS
DESCRIPTION
DECODE
0x00: 0.500V
0x01: 0.525V
0x02: 0.550V
0x03: 0.575V
...
0x8B: 3.975V
0x8C: 4.000V
0x8D–0xFF: Reserved
SIMO Buck-Boost Channel 1 Target Output
Voltage. This 8-bit configuration is a linear
transfer function that starts at 0.5V and ends
at 4.0V with 25mV increments. Values of
0x8D and higher are reserved.
VSBB1 = 0.5V + 0.025V x TV_SBB1[7:0]
7:0
CNFG_SBB1_B (0x0B)
BIT
7
6
5
4
3
2
1
Field
RSVD[1:0]
RSVD[1:0]
ADE_SBB1
EN_SBB1[2:0]
Reset
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
Access
Type
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:6
Reserved
RSVD
5:4
Reserved
ADE_SBB1
EN_SBB1
3
2:0
0
SIMO Buck-Boost Channel 1 ActiveDischarge Enable
0x0: The active discharge function is disabled.
When SBB1 is disabled, its discharge rate is a
function of the output capacitance and the external
load.
0x1: The active discharge function is enabled.
When SBB1 is disabled, an internal resistor
(RAD_SBB1) is activated from SBB1 to PGND to
help the output voltage discharge. The output
voltage discharge rate is a function of the output
capacitance, the external loading, and the internal
RAD_SBB1 load.
Enable Control for SIMO Buck-Boost Channel
1. Select an FPS slot that the channel powers
up and powers down in or whether the
channel is forced on or off.
After the SIMO is enabled, the bias circuits
may be programmed back to low-power
mode (CNFG_GLBL_A.BIAS_LPM = 1) to
decrease quiescent current.
0x0: FPS slot 0
0x1: FPS slot 1
0x2: FPS slot 2
0x3: FPS slot 3
0x4: Off
0x5: Same as 0x4
0x6: On
0x7: Same as 0x6
CNFG_SBB2_A (0x0C)
BIT
7
6
5
4
3
Field
TV_SBB2[7:0]
Reset
0x0
Access
Type
www.maximintegrated.com
2
1
0
Write, Read
Maxim Integrated | 57
MAX77655
BITFIELD
TV_SBB2
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
BITS
DESCRIPTION
DECODE
0x00: 0.500V
0x01: 0.525V
0x02: 0.550V
0x03: 0.575V
...
0x8B: 3.975V
0x8C: 4.000V
0x8D–0xFF: Reserved
SIMO Buck-Boost Channel 2 Target Output
Voltage. This 8-bit configuration is a linear
transfer function that starts at 0.5V and ends
at 4.0V with 25mV increments. Values of
0x8D and higher are reserved.
VSBB2 = 0.5V + 0.025V x TV_SBB2[7:0]
7:0
CNFG_SBB2_B (0x0D)
BIT
7
6
5
4
3
2
1
Field
RSVD[1:0]
RSVD[1:0]
ADE_SBB2
EN_SBB2[2:0]
Reset
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
Access
Type
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:6
Reserved
RSVD
5:4
Reserved
ADE_SBB2
EN_SBB2
3
2:0
0
SIMO Buck-Boost Channel 2 ActiveDischarge Enable
0x0: The active discharge function is disabled.
When SBB2 is disabled, its discharge rate is a
function of the output capacitance and the external
load.
0x1: The active discharge function is enabled.
When SBB2 is disabled, an internal resistor
(RAD_SBB2) is activated from SBB2 to PGND to
help the output voltage discharge. The output
voltage discharge rate is a function of the output
capacitance, the external loading, and the internal
RAD_SBB2 load.
Enable Control for SIMO Buck-Boost Channel
2. Select an FPS slot that the channel powers
up and powers down in or whether the
channel is forced on or off.
After the SIMO is enabled, the bias circuits
may be programmed back to low-power
mode (CNFG_GLBL_A.BIAS_LPM = 1) to
decrease quiescent current.
0x0: FPS slot 0
0x1: FPS slot 1
0x2: FPS slot 2
0x3: FPS slot 3
0x4: Off
0x5: Same as 0x4
0x6: On
0x7: Same as 0x6
CNFG_SBB3_A (0x0E)
BIT
7
6
5
4
3
Field
TV_SBB3[7:0]
Reset
0x0
Access
Type
www.maximintegrated.com
2
1
0
Write, Read
Maxim Integrated | 58
MAX77655
BITFIELD
TV_SBB3
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
BITS
DESCRIPTION
DECODE
SIMO Buck-Boost Channel 3 Target Output
Voltage. This 8-bit configuration is a linear
transfer function that starts at 0.5V and ends
at 4.0V with 25mV increments. Values of
0x8D and higher are reserved.
VSBB3 = 0.5V + 0.025V x TV_SBB3[7:0]
7:0
0x00: 0.500V
0x01: 0.525V
0x02: 0.550V
0x03: 0.575V
...
0x8B: 3.975V
0x8C: 4.000V
0x8D–0xFF: Reserved
CNFG_SBB3_B (0x0F)
BIT
7
6
5
4
3
2
1
Field
RSVD[1:0]
RSVD[1:0]
ADE_SBB3
EN_SBB3[2:0]
Reset
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
Access
Type
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:6
Reserved
RSVD
5:4
Reserved
ADE_SBB3
EN_SBB3
3
2:0
www.maximintegrated.com
0
SIMO Buck-Boost Channel 3 ActiveDischarge Enable
0x0: The active discharge function is disabled.
When SBB3 is disabled, its discharge rate is a
function of the output capacitance and the external
load.
0x1: The active discharge function is enabled.
When SBB3 is disabled, an internal resistor
(RAD_SBB3) is activated from SBB3 to PGND to
help the output voltage discharge. The output
voltage discharge rate is a function of the output
capacitance, the external loading, and the internal
RAD_SBB3 load.
Enable Control for SIMO Buck-Boost Channel
3. Select an FPS slot that the channel powers
up and powers down in or whether the
channel is forced on or off.
After the SIMO is enabled, the bias circuits
may be programmed back to low-power
mode (CNFG_GLBL_A.BIAS_LPM = 1) to
decrease quiescent current.
0x0: FPS slot 0
0x1: FPS slot 1
0x2: FPS slot 2
0x3: FPS slot 3
0x4: Off
0x5: Same as 0x4
0x6: On
0x7: Same as 0x6
Maxim Integrated | 59
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Typical Application Circuits
Typical Applications Circuit
MAX77655
SBB0
IN
VIN
CIN
22µF/10V
(0603)
L
1.5µH
3.9Ω
(0201)
CBST
10nF/6.3V
(0201)
1.5nF
(0201)
VSBB0
SBB1
PGND
SBB2
VSBB2
SBB3
SIMO BUCK-BOOST
22µF
10V
(0603)
LXA
LXB
VSBB3
BST
VSBB2
PVDD
INTERNAL
SUPPLY
I2 C
GND
nEN
VIO/POWER
4.7k
(0402)
VDD
CVDD
10µF/10V
(0402)
SYSTEM
RESOURCES
VSBB1
TOP LEVEL
SDA
SCL
SDA
SCL
nIRQ
nIRQ
PROCESSOR
*
*PULLUP RESISTORS NOT DRAWN
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX77655EWE+T*
-40°C to +85°C
16 WLP
MAX77655AEWE+T
-40°C to +85°C
16 WLP
OPTIONS
See Table 2
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Custom samples only. Not for production or stock. Contact factory for more information.
www.maximintegrated.com
Maxim Integrated | 60
MAX77655
Low IQ SIMO PMIC with 4-Outputs Delivering up to
700mA Total Output Current
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
0
8/20
Initial release
1
10/20
Updated Pin Description table
PAGES
CHANGED
—
17, 18
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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