EVALUATION KIT AVAILABLE
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
General Description
Benefits and Features
The dual-input power MUX selects the higher voltage
from two different input sources to power the step-down
converter. Control circuitry ensures that only one channel
of the MUX is on at a time to prevent cross-conduction
between input sources. For single-input applications, the
MUX can be bypassed and the step-down converter can
be powered directly from the SUP pin.
●● Dual-Input Power MUX Replaces Common-Cathode
Diode Arrays
• Automatic Ideal-Diode ORing Voltage Selector
• 250mΩ MOSFETs Minimize Power Consumption,
BOM, and Solution Size
The MAX77756 is a synchronous 500mA step-down
DC-DC converter with integrated dual-input power multiplexer (MUX). The converter operates on an input supply
as low as 3.0V and as high as 24V. Default output voltage is factory-programmed to either 1.8V, 3.3V, or 5.0V.
Output voltage is further adjustable through external
resistors or an I2C serial interface.
The MAX77756 is available in a small 2.33mm x 1.42mm
(0.7mm max height), 15-bump wafer-level package
(WLP). For a similar buck converter without a power
MUX, refer to the MAX77596.
Applications
●● USB Type-C Power Delivery Accessories and
Devices
●● Notebook and Tablet Computers
●● Home Automation, Low IQ Smart Hubs
●● Battery-Powered Systems, Backup Battery,
Uninterruptible Rails
Ordering Information appears at end of data sheet.
●● Wide Input Power Supply
• 3V to 24V Supply Voltage
• 500mA (max) Output Current
• 1.8V, 3.3V, or 5.0V Factory-Set VOUT with
Optional I2C Control: 1.5V to 7.5V in 50mV Steps
• External Feedback Resistor VOUT Option (1V to
99% VSUP)
• Hardware or Software Enable
●● Low IQ Enables Always-On Rails
• 1.5μA Quiescent Current (Only SUP Powered)
• 19μA Quiescent Current (IN1/IN2 Powered)
• 88% Peak Efficiency (12VSUP, 3.3VOUT)
●● Safe and Easy to Use
• Short-Circuit Hiccup Mode and Thermal Protection
• 8ms Soft-Start
• Software-Enabled Spread Spectrum
• Pin-Programmable Inductor Peak Current Level
●● S
mall Size
• 2.33mm x 1.42mm (0.7mm max height)
Wafer-Level Package (WLP)
• 15-Bump, 0.4mm Pitch, 3 x 5 Array
Simplified Block Diagram
POWER MUX
3V TO 24V DC SOURCE 1
- MAIN BATTERY
- USB PD PROVIDER
IN1
IN2
3V TO 24V DC SOURCE 2
- BACKUP BATTERY
- SOLAR CELL ARRAY
SUP
IDEAL
BST
VIO
HARDWARE OR
SOFTWARE
ENABLE
SDA
SCL
DIGITAL
CONTROL
BUCK
CONVERTER
LX
OUT/ FB
POK
EN
PGND
AGND, ILIM , BIAS
PINS NOT DRAWN
24V, 500mA DC-DC BUCK CONVERTER WITH IDEAL-DIODE “ORING” MUX
19-8710; Rev 1; 10/17
10µH
POWER OK
VOUT
1.5V TO 7.5V
1.8V, 3.3V, 5.0V DEFAULTS
500mA MAX
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Absolute Maximum Ratings
IN1, IN2, SUP to PGND.........................................-0.3V to +26V
BIAS to PGND..........................................................-0.3V to +6V
EN to PGND...............................................-0.3V to VSUP + 0.3V
BST to LX...............................................................................+6V
BST to PGND.........................................................-0.3V to +31V
OUT/FB to PGND...................................................-0.3V to +12V
POK, ILIM to PGND..................................-0.3V to VBIAS + 0.3V
POK, SDA Sink Current......................................................20mA
VIO to PGND............................................................-0.3V to +6V
SDA, SCL to PGND.......................................-0.3V to VIO + 0.3V
AGND to PGND.....................................................-0.3V to +0.3V
IN1, IN2 Repetitive Forward Current (TA = +85°C)
10% Duty Square Wave....................................................4.1A
IN1, IN2 SUP Continuous Current.................................1.6ARMS
LX Continuous Current (Note 1)....................................1.6ARMS
OUT/FB Short-Circuit Duration..................................Continuous
Continuous Power Dissipation (TA = +70°C)
(derate 16.22mW/°C above +70°C)...........................1298mW
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Soldering Temperature (reflow)........................................+260°C
Note 1: LX has internal clamp diodes to PGND and SUP. Applications that forward bias these diodes should not exceed the IC’s package
power dissipation limits.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
15 WLP
Package Code
W151G2+1
Outline Number
21-100111
Land Pattern Number
90-100052 (Refer to Application Note 1891)
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
61.65°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated │ 2
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics
(VSUP = VEN = 12V, VIO = 1.8V, VIN1 = VIN2 = 0V, configuration registers in reset. Limits are 100% production tested at TA = +25°C,
limits over TA = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
24
V
3.0
V
STEP-DOWN CONVERTER
SUP Voltage Range
VSUP
SUP Undervoltage Lockout
VUVLO
3
VSUP rising
2.75
SUP Undervoltage Lockout
Hysteresis
SUP Shutdown Current
2.9
300
ISUP-SHDN
VEN = 0V (buck converter disabled)
0.75
mV
3.0
μA
SUP QUIESCENT CURRENT
SUP Quiescent Current
ISUP-Q
BIAS Regulator Voltage
Output Voltage Regulation
Range
VBIAS
VOUT-REG
ILOAD = 0mA, VOUT = 1.8V
6
18
ILOAD = 0mA, VOUT = 3.3V
1.5
3.0
ILOAD = 0mA, VOUT = 5.0V
2.65
5.0
ILOAD = 0mA, external feedback version
32
70
VSUP = 5.5V to 24V, BIAS not internally
connected to OUT (Note 1)
5
Internal feedback version target regulation
voltage, adjustable through I2C from 1.5V
to 7.5V in 50mV/LSB with
V_OUTREG[7:0]
1.5
μA
V
7.5
V
OUTPUT VOLTAGE ACCURACY
VOUT-REG
= 1.8V, 1.8V
factory-default
version
OUT Voltage Accuracy
VOUT
VOUT-REG
= 3.3V, 3.3V
factory-default
version
VOUT-REG
= 5.0V, 5.0V
factory-default
version
www.maximintegrated.com
VSUP = 12V,
IOUT = 250mA,
TA = +25°C
1.78
1.8
1.82
VSUP = 4.5V to 24V,
IOUT = 0mA to 500mA,
TA = -40°C to +85°C
1.746
1.8
1.854
VSUP = 12V,
IOUT = 250mA,
TA = +25°C
3.27
3.3
3.33
VSUP = 4.5V to 24V,
IOUT = 0mA to 500mA,
TA = -40°C to +85°C
3.2
3.3
3.4
VSUP = 12V,
IOUT = 250mA,
TA = +25°C
4.95
5
5.05
VSUP = 6V to 24V, IOUT
= 0mA to 500mA, TA =
-40°C to +85°C
4.85
5
5.15
V
Maxim Integrated │ 3
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics (continued)
(VSUP = VEN = 12V, VIO = 1.8V, VIN1 = VIN2 = 0V, configuration registers in reset. Limits are 100% production tested at TA = +25°C,
limits over TA = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
VSUP = 12V,
ILOAD = 250mA,
TA = +25°C
0.99
1
1.01
VSUP = 3.0V to 24V,
ILOAD = 0mA to 500mA,
TA = -40°C to +85°C
0.97
UNITS
FB VOLTAGE ACCURACY
FB Voltage Accuracy
FB Input Current
VFB
V
1.03
µA
Standby mode exit threshold,
ILOAD = 0mA, expressed as a
percentage of VOUT-REG
99
%
OUT/FB Load Regulation
0 to 300mA load, FPWM mode (Note 2)
1
%
OUT/FB Line Regulation
VSUP = 4.5V to 24V, VOUT = 3.3V,
FPWM mode (Note 2)
0.02
%/VSUP
OUT/FB Soft-Start Ramp
Time
VWAKE
tSS
VFB = 1V, external feedback version
1
0.02
OUT/FB Wake-Up
Threshold
IFB
External
feedback
version
SOFT_ST = 1
4
SOFT_ST = 0
8
ms
High-Side MOSFET
On-Resistance
RON-HS
VBIAS = 5V, ILX = 90mA
500
800
mΩ
Low-Side MOSFET
On-Resistance
RON-LS
VBIAS = 5V, ILX = 90mA
500
800
mΩ
I_PEAK[1:0] = 0b00
700
I_PEAK[1:0] = 0b01
800
High-Side MOSFET Peak
Current Limit
ILX-PEAK
I_PEAK[1:0] = 0b10
800
900
I_PEAK[1:0] = 0b11
1000
1000
mA
Low-Side MOSFET Valley
Current Threshold
ILX-VALLEY
Output overloaded (VOUT < 25% of VOUTREG), threshold below where
on-times are allowed to start
500
mA
High-Side MOSFET
Minimum Current
Threshold
ILX-PK-MIN
Inductor current ramps to at least
ILX-PK-MIN while skipping
200
mA
40
mA
80
ns
99
%
Low-Side MOSFET
Zero-Crossing Threshold
Minimum On-Time (Note 3)
IZX
tON-MIN
Maximum Duty Cycle
DMAX
Switching Frequency
fSW
Spread-Spectrum
Frequency Range
www.maximintegrated.com
∆fSW
VOUT = 3.3V
Continuous conduction
Spread-spectrum enabled
0.94
1
±6
1.06
MHz
%
Maxim Integrated │ 4
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics (continued)
(VSUP = VEN = 12V, VIO = 1.8V, VIN1 = VIN2 = 0V, configuration registers in reset. Limits are 100% production tested at TA = +25°C,
limits over TA = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
Soft-Short Output Voltage
Monitor Threshold
SYMBOL
CONDITIONS
MIN
MAX
0.25 x
VOUT-REG
VOUT-OVRLD
tRETRY
Switching stopped because
VOUT < 25% of VOUT-REG and 15
consecutive switching cycles ended by
current limit, time before converter
attempts to soft-start again
VIN1/VIN2
Minimum initial voltage to forward-bias
power MUX FET intrinsic body-diode to
activate selection logic
Output-Overloaded Retry
Timer
TYP
UNITS
V
15
ms
POWER MULTIPLEXER
IN1/IN2 Minimum Initial
Operating Voltage
VUVLO
+ 0.7
V
IN1/IN2 QUIESCENT CURRENT
IN1/IN2 Quiescent Current
IN1/IN2 to SUP On-Resistance
VOUT = 1.8V, VIN1 or VIN2 = 12V,
ILOAD = 0mA
38
100
VOUT = 3.3V, VIN1 or VIN2 = 12V,
ILOAD = 0mA
18.5
30
VOUT = 5.0V, VIN1 or VIN2 = 12V,
ILOAD = 0mA
25
40
VIN1 or VIN2 = 12V, ILOAD = 0mA,
external feedback version
42
100
RON-IN1
VIN1 = 5.5V, IIN1 = 90mA
250
400
RON-IN2
VIN2 = 5.5V, IIN2 = 90mA
250
400
IIN1-LEAK
VSUP = 12V,
VIN1 = VIN2 =
0V, IN1/IN2 to
SUP channel
is off
0.003
1
IIN1-Q/IIN2-Q
IN1/IN2 Leakage
IIN2-LEAK
Channel Selection
Hysteresis
μA
Current from IN1
mΩ
μA
Current from IN2
0.003
(Note 4)
1
400
mV
POWER-OK OUTPUT (POK)
VPOK-RISING
VOUT rising, expressed as a
percentage of VOUT-REG
90
92
94
VPOK-FALLING
VOUT falling, expressed as a
percentage of VOUT-REG
88
90
92
POK Threshold
POK Debounce Timer
tPOK-DB
POK Leakage Current
IPOK
POK = high (high impedance),
TA = +25°C
POK Low Voltage
VPOK
POK = low, sinking 1mA
www.maximintegrated.com
%
12
μs
1
μA
0.4
V
Maxim Integrated │ 5
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics (continued)
(VSUP = VEN = 12V, VIO = 1.8V, VIN1 = VIN2 = 0V, configuration registers in reset. Limits are 100% production tested at TA = +25°C,
limits over TA = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ENABLE INPUT (EN)
EN Logic-High Threshold
VEN_HI
EN Logic-Low Threshold
VEN_LO
EN Leakage Current
IEN
1.4
V
0.4
VEN = VSUP = 12V
0.1
V
μA
HIGH-SIDE CURRENT LIMIT INPUT (ILIM)
ILIM Logic-High Threshold
VILIM_HI
ILIM Logic-Low Threshold
VILIM_LO
1.4
V
0.4
V
5.5
V
SERIAL INTERFACE/I/O STAGE
VIO Voltage Range
VIO
1.7
VIO Valid Logic Threshold
1.7
VIO Bias Current
TA = +25°C
SCL, SDA Input High
Voltage
VIH
SCL, SDA Input Low
Voltage
VIL
SCL, SDA Input Hysteresis
II
SDA Output Low Voltage
VOL
SCL, SDA Pin Capacitance
tSP
0
+1
0.7 x
VIO
0.05 x
VIO
VIO = 5.5V, VSCL = VSDA = 0V or 5.5V
μA
V
0.3 x
VIO
VHYS
SCL, SDA Input Leakage
Current
Input Filter Suppressed
Spike Maximum Pulse
Width
-1
V
-10
Sinking 20mA
V
V
+10
μA
0.4
V
(Note 5)
10
pF
(Note 5)
50
ns
SERIAL INTERFACE/TIMING
Clock Frequency
fSCL
Bus Free Time Between
STOP and START
Condition
tBUF
0.5
μs
Setup Time REPEATED
START Condition
tSU;STA
260
ns
Hold Time REPEATED
START Condition
tHD;STA
260
ns
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1
MHz
Maxim Integrated │ 6
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics (continued)
(VSUP = VEN = 12V, VIO = 1.8V, VIN1 = VIN2 = 0V, configuration registers in reset. Limits are 100% production tested at TA = +25°C,
limits over TA = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Low Period
tLOW
500
ns
SCL High Period
tHIGH
260
ns
Data Setup Time
tSU;DAT
50
ns
Data Hold Time
tHD;DAT
0
μs
SDA Fall Time
tF
Setup Time for STOP
Condition
Time measured between VIO and VOL
(Note 5)
tSU;STO
120
260
ns
ns
THERMAL PROTECTION
Thermal Shutdown
Thermal Shutdown
Hysteresis
TSHDN
Junction temperature rising
+165
°C
+15
°C
Note 1: See the BIAS Regulator section.
Note 2: Forced PWM (FPWM) is an internal test mode.
Note 3: Output voltage regulation is always maintained. The device skips pulses when the duty cycle needed to regulate the output
violates the minimum on-time.
Note 4: Off channel must be half of this value higher than the on channel for switch to happen.
Note 5: Design guidance only. Not production tested.
www.maximintegrated.com
Maxim Integrated │ 7
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics
(VINx = VEN = 12V, TA = +25°C, internal feedback version, unless otherwise noted.)
SUP QUIESCENT CURRENT
vs. VOLTAGE
1.8V OUTPUT
16
toc 01
3.5
VOUT = 1.8V
TA = +85°C
8
TA = +25°C
6
TA = -40°C
4
0
10
20
1.5
TA = +25°C
1.0
0
10
20
30
0
10
20
INx QUIESCENT CURRENT vs.
VOLTAGE
1.8V OUTPUT
INx QUIESCENT CURRENT vs.
VOLTAGE
3.3V OUTPUT
60
TA = +85°C
40
TA = +25°C
30
TA = -40°C
20
toc 05
40
VOUT = 1.8V
40
TA = +25°C
30
TA = -40°C
20
10
10
0
0
10
20
30
0
10
20
INx QUIESCENT CURRENT
vs. VOLTAGE
5V OUTPUT
INx QUIESCENT CURRENT
vs. VOLTAGE
EXTERNAL FEEDBACK VERSION
25
20
15
TA = +25°C
TA = -40°C
10
50
20
0
20
SUPPLY VOLTAGE (V)
www.maximintegrated.com
30
TA = -40°C
30
0
10
TA = +25°C
40
10
TA = +25°C
TA = -40°C
10
0
10
10
20
SUPPLY VOLTAGE (V)
30
30
toc 09
TA = +85°C
1.2
TA = +25°C
1.0
0.8
TA = -40°C
0.6
0.4
0.2
VOUT = 3.3V
0
20
SHUTDOWN CURRENT
vs. TEMPERATURE
1.4
TA = +85°C
60
5
15
1.6
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
TA = +85°C
TA = +85°C
20
1.8
70
30
25
SUPPLY VOLTAGE (V)
toc 08
80
35
30
0
30
SUPPLY VOLTAGE (V)
VOUT = 5V
toc 06
VOUT = 3.3V
5
SUPPLY VOLTAGE (V)
toc 07
30
35
TA = +85°C
SUPPLY CURRENT (µA)
50
0
TA = -40°C
SUP QUIESCENT CURRENT
vs.VOLTAGE
N
EXTERNAL FEEDBACKVERSION
50
40
TA = +25°C
SUPPLY VOLTAGE (V)
VOUT = 3.3V
45
2
1
TA = -40°C
0
TA = +85°C
3
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
TA = +85°C
4
SUPPLY VOLTAGE (V)
60
SUPPLY CURRENT (µA)
2.0
0.0
30
toc 04
70
0
2.5
0.5
2
toc 03
VOUT = 5V
5
SUPPLY CURRENT (µA)
10
SUP QUIESCENT CURRENT
vs. VOLTAGE
5V OUTPUT
6
toc 02
VOUT = 3.3V
3.0
12
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
14
0
SUP QUIESCENT CURRENT
vs.VOLTAGE
3.3V OUTPUT
0.0
VOUT = 0V (SHUTDOWN)
0
10
20
30
TEMPERATURE (°C)
Maxim Integrated │ 8
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics (continued)
(VINx = VEN = 12V, TA = +25°C, internal feedback version, unless otherwise noted.)
100
90
80
60
VINx = 5V
50
40
30
VSUP = 12V
60
VINx = 12V
50
40
30
60
50
20
10
100
1000
90
80
70
EFFICIENCY vs. LOAD
3.3V OUTPUT
toc 13
100
VOUT = 3.3V
90
80
VSUP = 5V
VINx = 5V
60
1
10
100
0
0.0001 0.001 0.01
1000
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
0.1
50
40
30
70
EFFICIENCY vs. LOAD
3.3V OUTPUT
toc 14
100
VOUT = 3.3V
90
80
VSUP = 12V
VINx = 12V
60
50
40
30
70
20
10
10
100
1000
OUTPUT CURRENT (mA)
90
80
70
1
10
100
EFFICIENCY vs. LOAD
5V OUTPUT
toc 16
100
VOUT = 5V
90
VINx = 12V
60
50
40
30
70
EFFICIENCY vs. LOAD
5V OUTPUT
toc 17
100
VOUT = 5V
90
60
80
VINx = 24V
VSUP = 24V
50
40
30
70
10
10
10
OUTPUT CURRENT (mA)
www.maximintegrated.com
100
1000
0.1
1
10
OUTPUT CURRENT (mA)
10
100
1000
100
1000
EFFICIENCY vs. LOAD
EXTERNAL FEEDBACK VERSION
toc 18
VOUT = 3.3V
VSUP = 5V
VINx = 5V
30
10
1
1
40
20
0.1
0.1
50
20
0
0.0001 0.001 0.01
VINx = 24V
60
20
0
0.0001 0.001 0.01
VSUP = 24V
OUTPUT CURRENT (mA)
80
VSUP = 12V
toc 15
VOUT = 3.3V
0
0.0001 0.001 0.01
1000
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
0.1
1000
30
10
1
100
40
10
0.1
10
50
20
0
0.0001 0.001 0.01
1
EFFICIENCY vs. LOAD
3.3V OUTPUT
60
20
0
0.0001 0.001 0.01
0.1
OUTPUT CURRENT (mA)
EFFICIENCY (%)
10
VINx = 24V
30
10
0
0.0001 0.001 0.01
VSUP = 24V
40
10
1
toc 12
VOUT = 1.8V
70
20
0.1
EFFICIENCY vs. LOAD
1.8V OUTPUT
80
70
OUTPUT CURRENT (mA)
EFFICIENCY (%)
90
20
0
0.0001 0.001 0.01
EFFICIENCY (%)
100
80
VSUP = 5V
70
toc 11
VOUT = 1.8V
EFFICIENCY (%)
EFFICIENCY (%)
toc 10
VOUT = 1.8V
EFFICIENCY vs. LOAD
1.8V OUTPUT
EFFICIENCY (%)
90
EFFICIENCY (%)
100
EFFICIENCY vs. LOAD
1.8V OUTPUT
0
0.0001 0.001 0.01
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
Maxim Integrated │ 9
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics (continued)
(VINx = VEN = 12V, TA = +25°C, internal feedback version, unless otherwise noted.)
EFFICIENCY vs. LOAD
EXTERNAL FEEDBACK VERSION
toc 19
100
VOUT = 3.3V
90
80
80
70
VSUP = 12V
60
EFFICIENCY (%)
EFFICIENCY (%)
toc 20
100
VOUT = 3.3V
90
EFFICIENCY vs. LOAD
EXTERNAL FEEDBACK VERSION
VINx = 12V
50
40
30
70
40
30
20
10
10
0.1
1
10
100
VSUP = 24V
50
20
0
0.0001 0.001 0.01
VINx = 24V
60
0
0.0001 0.001 0.01
1000
OUTPUT CURRENT (mA)
LOAD REGULATION
1.8V OUTPUT
1.90
toc 21
1.84
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
100
1000
toc 22
3.33
VINx = 24V
VINx = 12V
VINx = 5V
1.82
1.80
3.32
VINx = 24V
VINx = 12V
VINx = 5V
3.31
3.30
3.29
3.28
3.27
1.78
3.26
0
100
200
300
400
3.25
500
0
OUTPUT CURRENT (mA)
toc 23
OUTPUT VOLTAGE (V)
5.06
5.04
VINx = 24V
VINx = 12V
5.00
200
300
400
4.98
LINE REGULATION
1.8V OUTPUT
1.82
5.08
5.02
100
500
OUTPUT CURRENT (mA)
LOADREGULATION
5V OUTPUT
5.10
OUTPUT VOLTAGE (V)
10
3.34
1.86
toc 24
1.82
IOUT = 100mA
1.81
IOUT = 0mA
1.81
IOUT = 250mA
1.80
1.80
1.79
IOUT = 500mA
1.79
1.78
4.96
4.94
1
LOAD REGULATION
3.3V OUTPUT
3.35
1.88
1.76
0.1
OUTPUT CURRENT (mA)
1.78
0
100
200
300
OUTPUT CURRENT (mA)
www.maximintegrated.com
400
500
1.77
0
10
20
30
SUPPLY VOLTAGE (V)
Maxim Integrated │ 10
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics (continued)
(VINx = VEN = 12V, TA = +25°C, internal feedback version, unless otherwise noted.)
LINE REGULATION
3.3V OUTPUT
3.35
toc 25
5.05
3.34
5.04
3.32
3.31
IOUT = 100mA
3.30
3.29
IOUT = 250mA
3.28
3.27
3.26
IOUT = 100mA
5.02
5.01
5.00
4.99
IOUT = 250mA
4.98
4.97
IOUT = 500mA
4.96
IOUT = 500mA
3.25
toc 26
IOUT = 0mA
5.03
IOUT = 0mA
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.33
3.24
LINE REGULATION
5V OUTPUT
4.95
0
10
20
4.94
30
0
10
SUPPLY VOLTAGE (V)
20
30
SUPPLY VOLTAGE (V)
STARTUP WAVEFORM
3.3V OUTPUT (0mA LOAD)
LOADTRANSIENT RESPONSE
1.8V OUTPUT
to c2 7
to c2 8
VINx = 12V
VEN
10V/div
3.3V
VOUT
2V/div
VBIAS
5V/div
BIAS SWITCHOVER TO OUT
0V
5V
VOUT
100mV/div
(1.8V OFFSET)
IOUT
400mA/div
3.3V
0V
ISUP
50mA/div
100µs/div
2ms/div
LOADTRANSIENT RESPONSE
3.3V OUTPUT
LOADTRANSIENT RESPONSE
5V OUTPUT
to c2 9
VINx = 12V
VOUT
100mV/div
(3.3V OFFSET)
IOUT
400mA/div
100µs/div
www.maximintegrated.com
to c3 0
VINx = 12V
100mV/div
(5V OFFSET)
VOUT
400mA/div
IOUT
100µs/div
Maxim Integrated │ 11
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics (continued)
(VINx = VEN = 12V, TA = +25°C, internal feedback version, unless otherwise noted.)
LOADTRANSIENT RESPONSE
EXTERNAL FEEDBACKVERSION
LINE TRANSIENT RESPONSE
1.8V OUTPUT
to c3 1
to c3 2
VINx = 12V
24V
100mV/div
VOUT
VIN
4V
5V/div
400mA/div
IOUT
50mV/div
(1.8V OFFSET)
VOUT
100µs/div
LINE TRANSIENT RESPONSE
3.3V OUTPUT
200µs/div
LINE TRANSIENT RESPONSE
5V OUTPUT
to c3 3
24V
VIN
to c3 4
24V
4V
5V/div
50mV/div
(3.3V OFFSET)
VOUT
VIN
4V
5V/div
50mV/div
(5V OFFSET)
VOUT
200µs/div
200µs/div
LINE TRANSIENT RESPONSE
EXTERNAL FEEDBACKVERSION
IN1/IN2 SWITCHOVER
to c3 5
24V
to c3 6
50mV/div
(AC-COUPLED)
VOUT
VSUP
TRACKING HIGHER
OF VIN1/VIN2
VIN
4V
1V/div
(7.5V OFFSET)
5V/div
VIN2
50mV/div
(3.3V OFFSET)
VOUT
200µs/div
www.maximintegrated.com
VIN1
100µs/div
Maxim Integrated │ 12
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Bump Configuration
MAX77756
1
2
3
4
5
A
IN1
SUP
BST
LX
PGND
B
VIO
SDA
EN
AGND
OUT/
FB
C
IN2
SCL
BIAS
ILIM
POK
+
15 WLP
TOP VIEW (BUMP SIDE DOWN)
Bump Description
BUMP
NAME
A1
IN1
Power MUX Input 1. IN1 and IN2 have equal priority to the power selector. Selection logic is only active
when the IC is enabled through the EN pin or EN_BIT. A diode always exists between IN1 and SUP.
Connect to PGND to force PFET between IN1 and SUP off.
C1
IN2
Power MUX Input 2. IN1 and IN2 have equal priority to the power selector. Selection logic is only active
when the IC is enabled through the EN pin or EN_BIT. A diode always exists between IN2 and SUP.
Connect to PGND to force PFET between IN2 and SUP off.
A3
BST
High-Side FET Driver Supply. Connect a 0.1μF ceramic capacitor between BST and LX.
A2
SUP
Power MUX Output and Buck Supply Input. Bypass with a 1μF ceramic capacitor to PGND as close as
possible to the IC. If using IN1/IN2 to power the IC, do not prebias the SUP capacitor or connect SUP to
external loads. If using SUP to power the IC, connect IN1 and IN2 to PGND.
A4
LX
A5
PGND
Power Ground. Connect to AGND on the PCB. Return the SUP and OUT bypass capacitors to PGND.
B4
AGND
Quiet Ground. Connect to PGND on the PCB. Return the BIAS bypass capacitor to AGND.
C5
POK
Open-Drain Power OK Output. An external pullup resistor is required.
C3
BIAS
Low-Voltage Internal IC Supply. Bypass to AGND with a 1μF ceramic capacitor. Do not load this pin
externally.
B5
OUT/FB
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FUNCTION
Switching Node. LX is high impedance when the converter is disabled.
Internal Feedback Versions (MAX77756A/B/C): Output Voltage Sense Input. Connect a 10μH inductor
between OUT and LX. Bypass OUT to PGND with a minimum 22μF ceramic capacitor.
External Feedback Version (MAX77756D): Feedback Input. Connect a resistor voltage divider between
the converter's output and AGND to set the output voltage. Connect a 5.6pF feed-forward capacitor
between the converter's output and FB. Do not route FB close to sources of EMI or noise.
Maxim Integrated │ 13
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Bump Description (continued)
BUMP
NAME
FUNCTION
B3
EN
Enable Input. Enables both the step-down converter and the power MUX. EN is compatible with the SUP
voltage domain. Drive EN to PGND to disable the device. Drive EN above VEN_HI to enable the device.
If using I2C to control the buck, the enable bit (EN_BIT) interacts with the EN pin. See the Enable Control
section.
B1
VIO
I2C Serial Interface Voltage Supply. Connect to PGND if not used.
C2
SCL
I2C Serial Interface Clock. This pin requires a pullup resistor to VIO. Connect to PGND if not used.
B2
SDA
I2C Serial Interface Data. This pin requires a pullup resistor to VIO. Connect to PGND if not used.
C4
ILIM
LX Peak Current Limit Setting Input. Connect to PGND to set ILX-PEAK to 700mA. Connect to BIAS to set
ILX-PEAK to 1000mA. I2C writes to control ILX-PEAK are only accepted while ILIM is logic-low.
See the Peak Inductor Current Limit (ILIM) section for details.
Functional Diagram
DC INPUT 1
3V TO 24V
IN1
MAX77756
CIN1
POWER MUX
SELECT
LOGIC
CIN2
DC INPUT 2
3V TO 24V
SUP
CSUP
BST
BIAS
IN2
BIAS
CBST
BIAS LDO
CBIAS
TO HOST OR
SUPERVISOR
RESET INPUT
RPU
AGND
L
COUT
EN
ILIM
VIO
SDA
SCL
www.maximintegrated.com
LX
POK
SUP
BIAS
SERIAL
HOST
STEP-DOWN
CONTROL
1.5V TO 7.5V PROGRAMMABLE OUTPUT
1.8V, 3.3V, 5.0V FACTORY DEFAULTS
500mA MAX
VOUT
OUT/FB
I2C
CONTROL
&
DIGITAL
PGND
AGND
Maxim Integrated │ 14
MAX77756
Detailed Description
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Buck Regulator Control Scheme
The MAX77756 is a small 500mA step-down DC-DC converter with integrated dual-input power multiplexer (MUX).
The step-down (buck) converter uses synchronous rectification and internal current-mode compensation. The
buck operates on a supply voltage from 3V to 24V.
Output voltage is configurable through I2C (1.5V to 7.5V
in 50mV steps) or external feedback resistors (1V to 99%
of VSUP). Factory-default voltage options of 1.8V, 3.3V,
and 5.0V are available (see the Ordering Information
table). Switching frequency in continuous conduction is
1MHz. The buck utilizes an ultra-low quiescent current
mode (1.5μA typ for 3.3VOUT) that maintains a very high
efficiency at light loads.
The step-down converter uses a PWM peak current-mode
control scheme with a load-line architecture. Peak current-mode control provides precise control of the inductor
current on a cycle-by-cycle basis and inherent compensation for input voltage variation.
The integrated dual-input power MUX automatically
selects the higher of two different voltage sources to
power the buck converter. The MUX reduces power dissipation versus common-cathode Schottky arrays by using
switches (MOSFETs) instead of diodes. The output of the
power MUX is the input to the buck (SUP). Single power
source applications should bypass the power MUX and
power SUP directly.
The PWM comparator regulates VOUT by controlling
duty cycle. The negative input of the PWM comparator is a voltage proportional to the actual output voltage
error. The positive input is the sum of the current-sense
signal through MOSFET Q1 and a slope-compensation
ramp. The PWM comparator ends an on-time when the
error voltage becomes less than the slope-compensated
current-sense signal. On-times begin again due to a fixedfrequency clock pulse. The controller's compensation
components and current-sense circuits are integrated.
This reduces the risk of routing sensitive control signals
on the PCB.
Dual-Input Power MUX
The device integrates a 24V power multiplexer (MUX) with
two inputs (IN1 and IN2) and one output (SUP). SUP is
the supply input for the buck. The input channels consist
of P-type MOSFETs. IN1 and IN2 are the individual FET
drains and SUP is the common FET source. An intrinsic
body-diode is always present in both FETs.
The MUX connects the higher of VIN1 or VIN2 to SUP to
power the buck. Only the higher voltage input channel is
on. The lower voltage input channel is off. The MUX logic
is only active while the buck converter is enabled. Both
channels are off when the buck is disabled.
The selection logic has switchover hysteresis to avoid
chattering. The off channel must be 200mV higher than
the on channel to cause a switchover. Switchover is automatic and can happen any time while the buck is enabled.
Equal priority is given to each input. Neither channel is
prioritized over the other.
On-times (MOSFET Q1 on) are started by a fixedfrequency clock and terminated by a PWM comparator.
See Figure 1. When an on-time ends (starting an off-time)
current conducts through the low-side MOSFET (Q2 on).
Shoot-through current from SUP to PGND is avoided by
introducing a brief period of dead time between switching
events when neither MOSFET is on. Inductor current conducts through Q2's intrinsic body diode during dead time.
A load-line architecture is present in the controller design.
The output voltage is positioned slightly above nominal
regulation at no load and slightly below nominal regulation
at full load. As the output load changes, a small but controlled amount of load regulation (load line) error occurs
on the output voltage. This voltage positioning architecture allows the output voltage to respond to sudden load
transients in a critically damped manner, and effectively
reduces the amount of output capacitance needed when
compared to classical integrating controllers. See the
Typical Operating Characteristics section for information
about the converter's typical voltage regulation behavior
versus load.
When powering IN1 or IN2, do not connect anything to
SUP besides a decoupling capacitor. To use the buck
without the power MUX, connect IN1 and IN2 to PGND
and power SUP directly.
www.maximintegrated.com
Maxim Integrated │ 15
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
BIAS
EN
ILIM
SUP
BIAS LDO
AGND
REGISTERS &
CONTROL
VOUT-REG
REFERENCE
CLOCK
SOFT-START
RAMP
PWM
OUT/FB
BIAS
ILX-PEAK
SLOPE
COMPENSATION
I2C SERIAL
INTERFACE
S
Q
R
Q
BST
ILIM
Q1
LX
LOGIC
BIAS
Q2
gm
ZCOMP
IZX
ILX-VALLEY
AGND
POK
PGND
Figure 1. Buck Control Scheme Diagram
SKIP Mode Operation
Enable Control
The buck converter permanently operates in SKIP mode
with the added ability to transition into a lower power
mode called standby. SKIP mode causes discontinuous
inductor current at light loads by forcing the low-side
MOSFET (Q2) off if inductor current falls below IZX (40mA
typ) during an off-time. This prevents inductor current
from sourcing back to the input (SUP) and enables high
efficiency by reducing the total number of switching cycles
required to regulate the output voltage.
When using I2C to control the MAX77756, the EN pin
interacts with the enable bit (EN_BIT). The logical relationship between the EN pin and EN_BIT is by default an
OR. The EN_CTRL bit can be used to switch this relationship to a logical AND. See Table 1.
If the output voltage is within regulation and the load is
very light then the converter automatically transitions to
standby mode. In this mode, the LX node is high impedance and the converter's internal circuit blocks are deactivated to reduce IQ consumption. A single, low-power
comparator remains on to monitor the output voltage
during standby. When VOUT drops below VWAKE (99%
of VOUT-REG typ), the converter reactivates and starts
switching again.
Raise the EN pin voltage above VEN_HI (or tie to SUP) to
enable the IC. To disable, bring EN pin voltage to PGND.
The reset state (default state) of EN_BIT and EN_CTRL
is 0. This means that the default relationship between EN
pin and EN_BIT is a logical OR.
Table 1. Enable Control Truth Table
EN_CTRL
(BIT)
0
(logical OR)
1
(logical
AND)
www.maximintegrated.com
EN (PIN)
EN_BIT
(BIT)
REGULATOR
OUTPUT
0
0
OFF
0
1
ON
1
0
ON
1
1
ON
0
0
OFF
0
1
OFF
1
0
OFF
1
1
ON
Maxim Integrated │ 16
MAX77756
BIAS Regulator
An integrated 5V (VBIAS) linear regulator provides power
to internal circuit blocks. This regulator is used during
startup for all versions of the MAX77756. For internal
feedback versions (no external programming resistors)
where VOUT-REG is programmed between (and including) 3.3V and 5.0V, the BIAS regulator is deactivated and
the BIAS node is internally connected to OUT after the
output voltage is within regulation. Switching BIAS to OUT
utilizes the buck converter's efficiency to power its own
internal circuit blocks (as opposed to a linear regulator)
and improves the IC's power efficiency. For the external
feedback version of the MAX77756, the BIAS regulator is
permanently active. Do not load BIAS externally for any
MAX77756 version.
The BIAS regulator is on whenever the EN pin is high or
VIO voltage is valid (regardless of whether the buck regulator is on or off). Connect a 1μF ceramic capacitor from
BIAS and GND.
Soft-Start
The device has an internal soft-start timer (tSS) that controls the ramp time of VOUT as the converter is starting.
The soft-start feature limits inrush current during startup.
SOFT_ST programs tSS to 8ms or 4ms. The default value
is 8ms. The converter soft-starts every time the IC is
enabled, exits a UVLO condition, and/or retries from an
overcurrent or overtemperature condition.
Power-OK (POK) Output
The device features an open-drain POK output to monitor
the output voltage. POK requires an external pullup resistor. POK goes high (high-impedance) after the regulator
output increases above 92% (VPOK-RISING) of the nominal regulated voltage (VOUT-REG). POK goes low when
the regulator output drops to below 90% (VPOK-FALLING)
of VOUT-REG.
Peak Inductor Current Limit (ILIM)
The buck converter's high-side MOSFET peak current limit (ILX-PEAK) is register or pin programmable.
Applications can use ILX-PEAK programmability to ensure
that the converter never exceeds the saturation current
rating of the inductor on the PCB.
Connect ILIM to PGND to set ILX-PEAK to 700mA. While
ILIM is logic-low, the bits in I_PEAK[1:0] can be changed
through I2C to program ILX-PEAK from 700mA to 1000mA
in 100mA steps. The value of ILX-PEAK returns to 700mA
(I_PEAK[1:0] = 0b00) if the configuration registers reset.
www.maximintegrated.com
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Connect ILIM to a voltage above VILIM_HI to program ILXPEAK to 1000mA. While ILIM is high, ILX-PEAK is fixed at
1000mA and the I_PEAK[1:0] bitfield is ignored.
Short-Circiut Hiccup Mode and
Thermal Protection
The device has fault protection designed to protect itself
from abnormal conditions. If the output is overloaded,
cycle-by-cycle current limit prevents inductor current from
increasing beyond ILX-PEAK.
The buck stops switching if VOUT falls to less than 25%
of programmed VOUT-REG and 15 consecutive on-times
are ended by current limit. After switching stops, the buck
waits for tRETRY (15ms typ) before attempting to soft-start
again (hiccup mode). While VOUT is less than 25% of
target, the converter prevents new on-times if the inductor
current has not fallen below ILX-VALLEY (500mA typ). This
prevents inductor current from increasing uncontrollably
due to the short-circuited output.
Spread-Spectrum Option
Enable spread-spectrum operation by setting the S_
SPECT bit to 1. When enabled, the switching frequency
is varied ±6% centered on 1MHz. The modulation signal
is a triangle wave with a period of 256μs.
Register Reset Condition
The device's internal configuration registers reset to
their default values if VSUP falls below the UVLO falling
threshold (VSUP-UVLO minus UVLO hysteresis, 2.6V
typ) or if the voltage on the VIO pin becomes invalid (<
1.7V). Connect VIO to PGND to ensure that configuration
registers remain in factory-configured reset. Contact the
factory to request a version of the IC that does not reset
registers when VIO becomes invalid.
Serial Interface
Overview
The MAX77756 features a revision 3.0 I2C-compatible,
2-wire serial interface consisting of a bidirectional serial
data line (SDA) and a serial clock line (SCL). The
MAX77756 acts as a slave-only devices where it relies
on the master to generate a clock signal. SCL clock
rates from 0Hz to 3.4MHz are supported. I2C is an opendrain bus, and therefore, SDA and SCL require pullups.
Optional resistors (24Ω) in series with SDA and SCL
protect the device inputs from high-voltage spikes on the
bus lines. Series resistors also minimize crosstalk and
undershoot on bus signals. For additional information
on I2C, refer the I2C bus specification and users manual
UM10204 that is readily available and free on the internet.
Maxim Integrated │ 17
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Features
●● I2C Revision 3-compatible serial communications
channel
●● 0Hz to 100kHz (standard mode)
between VIO and the next closest capacitor (≥ 0.1μF) is
less than 100mΩ in series with 10nH, then a local capacitor is not needed. Otherwise, bypass VIO to PGND with a
0.1µF ceramic capacitor.
VIO accepts voltages from 1.7V to 5.5V. Cycling VIO
resets the I2C registers.
●● 0Hz to 400kHz (fast mode)
●● 0Hz to 1MHz (fast mode plus)
I2C Data Transfer
●● 0Hz to 3.4MHz (high-speed mode)
●● Does not utilize I2C clock stretching
I2C System Configuration
The I2C bus is a multimaster bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
A device on the I2C bus that sends data to the bus in
called a transmitter. A device that receives data from the
bus is called a receiver. The device that initiates a data
transfer and generates the SCL clock signals to control
the data transfer is a master. Any device that is being
addressed by the master is considered a slave. The
MAX77756 I2C-compatible interface operates as a slave
on the I2C bus with transmit and receive capabilities.
I2C Interface Power
The IC's I2C interface derives its power from VIO.
Typically, a power input such as VIO requires a local
0.1μF ceramic bypass capacitor to ground. However,
in highly-integrated power distribution systems, a dedicated capacitor might not be necessary. If the impedance
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SCL
is high are control signals. See the I2C Start and Stop
Conditions section. Each transmit sequence is framed by
a START (S) condition and a STOP (P) condition. Each
data packet is nine bits long: eight bits of data followed by
the acknowledge bit. Data is transferred with the MSB first.
I2C Start and Stop Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is
a low-to-high transition on SDA, while SCL is high. See
Figure 3.
A START condition from the master signals the beginning
of a transmission to the MAX77756. The master terminates transmission by issuing a not acknowledge (nA)
followed by a STOP condition. See the I2C Acknowledge
Bit section for information on not acknowledge. The STOP
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Figure 2. I2C
System Configuration
S
Sr
P
SDA
tSU;STA
tSU;STO
SCL
tHD;STA
tHD;STA
Figure 3. I2C
Start and Stop Conditions
www.maximintegrated.com
Maxim Integrated │ 18
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
condition frees the bus. To issue a series of commands to
the slave, the master can issue repeated start (Sr) commands instead of a STOP command to maintain control of
the bus. In general, a repeated start command is functionally equivalent to a regular start command.
When a STOP condition or incorrect address is detected,
the IC disconnects SCL from the serial interface until
the next START condition, minimizing digital noise and
feedthrough.
I2C Acknowledge Bit
Both the I2C bus master and the MAX77756 (slave)
generate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each nine bit data packet.
To generate an acknowledge (A), the receiving device
must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low
during the high period of the clock pulse. See Figure 4.
To generate a not acknowledge (nA), the receiving device
allows SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse and leaves it high during
the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
The MAX77756 issues an ACK for all register addresses
in the possible address space even if the particular
register does not exist.
I2C Slave Address
The I2C controller implements 7-bit slave addressing in
Table 2. An I2C bus master initiates communication with
the slave by issuing a START condition followed by the
slave address. See Figure 5.
I2C Clock Stretching
In general, the clock signal generation for the I2C bus is
the responsibility of the master device. The I2C specification allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The IC does not use any form of clock stretching to hold down the clock line.
NOT ACKNOWLEDGE (NA)
S
ACKNOWLEDGE (A)
SDA
tSU;DAT
1
SCL
2
tHD;DAT
8
9
Figure 4. Acknowledge Bit
Table 2. I2C Slave Address Options
7-BIT SLAVE ADDRESS
8-BIT WRITE ADDRESS
8-BIT READ ADDRESS
0x1E, 0b 001 1110
0x3C, 0b 0011 1100
0x3D, 0b 0011 1101
S
SDA
0
0
1
1
1
1
0
R/W
A
ACKNOWLEDGE
SCL
1
2
3
4
5
6
7
8
9
Figure 5. Slave Address Example
www.maximintegrated.com
Maxim Integrated │ 19
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
I2C Communication Speed
●● The I2C slave must use a different set of input filters
on its SDA and SCL lines to accommodate for the
faster bus.
The MAX77756 is compatible with all 4 communication
speed ranges as defined by the Revision 3 I2C specification:
●● The communication protocols need to utilize the highspeed master code.
●● 0Hz to 100kHz (standard mode)
●● 0Hz to 400kHz (fast mode)
At power-up and after each stop condition, the IC input
filters are set for standard mode, fast mode, or fast mode
plus (i.e., 0Hz to 1MHz). To switch the input filters for highspeed mode, use the high-speed master code protocols
that are described in the I2C Communication Protocols
section.
●● 0Hz to 1MHz (fast mode)
●● 0Hz to 3.4MHz (high-speed mode)
Operating in standard mode, fast mode, and fast mode
plus does not require any special protocols. The main
consideration when changing the bus speed through this
range is the combination of the bus capacitance and pullup resistors. Higher time constants created by the bus
capacitance and pullup resistance (C x R) slow the bus
operation. Therefore, when increasing bus speeds, the
pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing
section of the I2C Revision 3.0 specification (UM10204)
for detailed guidance on the pullup resistor selection. In
general for bus capacitances of 200pF, a 100kHz bus
needs 5.6kΩ pullup resistors, a 400kHz bus needs about
a 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω
pullup resistors. Note that when the open-drain bus is low,
the pullup resistor is dissipating power, lower value pullup
resistors dissipate more power.
I2C Communication Protocols
The IC supports both writing and reading from its registers.
Writing to a Single Register
Figure 6 shows the protocol for the I2C master device to
write one byte of data to the MAX77756. This protocol is
the same as the SMBus specification’s write byte protocol. The write byte protocol is as follows:
1) The master sends a start command (S).
2) The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
3) The addressed slave asserts an acknowledge (A) by
pulling SDA low.
Operating in high-speed mode requires some special
considerations. The major considerations with respect to
the IC:
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
●● The I2C bus master use current source pullups to
shorten the signal rise.
7) The slave updates with the new data.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1 1
8
1
8
1
S
SLAVE ADDRESS
0 A
REGISTER POINTER
A
DATA
A OR NA
R/W
SDA
B1
B0
A
1
P OR SR*
NUMBER
OF BITS
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
ACKNOWLEDGE
SCL
7
8
9
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE .
Figure 6. Writing to a Single Register with the Write Byte Protocol
www.maximintegrated.com
Maxim Integrated │ 20
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
8) The slave acknowledges or does not acknowledge the
data byte. The next rising edge on SDA loads the data
byte into its target register and the data becomes active.
3) The addressed slave asserts an acknowledge (A) by
pulling SDA low.
9) The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
5) The slave acknowledges the register pointer.
4) The master sends an 8-bit register pointer.
6) The master sends a data byte.
7) The slave acknowledges the data byte. The next rising edge on SDA loads the data byte into its target
register and the data becomes active.
Writing Multiple Bytes to Sequential Registers
Figure 7 shows the protocol for writing to a sequential
registers. This protocol is similar to the write byte protocol above, except the master continues to write after it
receives the first byte of data. When the master is done
writing it issues a stop or repeated start.The writing to
sequential registers protocol is as follows:
8) Steps 6 to 7 are repeated as many times as the master
requires.
9) During the last acknowledge related clock pulse,
the master can issue an acknowledge or a not
acknowledge.
1) The master sends a start command (S).
10) The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
2) The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
LEGEND
MASTER TO SLAVE
1
7
S
SLAVE ADDRESS
SLAVE TO MASTER
1 1
8
1
8
1
0 A
REGISTER POINTER X
A
DATA X
A
R/W
8
1
8
1
DATA X+1
A
DATA X+2
A
8
1
REGISTER POINTER = X + 1
8
1
DATA N-1
A
REGISTER POINTER = X + (N-2)
SDA
B1
B0
Α
NUMBER
OF BITS
Α
NUMBER
OF BITS
Α
REGISTER POINTER = X + 2
A OR
NA
DATA N
Α
REGISTER POINTER = X + (N-1)
A
B9
9
1
1
P OR
SR*
NUMBER
OF BITS
Β
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
ACKNOWLEDGE
SCL
SDA
7
B1
8
B0
DETAIL: Α
A
ACKNOWLEDGE
SCL
7
8
9
DETAIL: Β
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
*P FORCES THE BUS
FILTERS TO SWITCH
TO THEIR ≤ 1MHZ
MODE. SR LEAVES
THE BUS FILTERS IN
THEIR CURRENT
STATE.
Figure 7. Writing to Sequential Registers X to N
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Maxim Integrated │ 21
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Reading from a Single Register
10) The master issues a not acknowledge (nA).
Figure 8 shows the protocol for the I2C master device to
read one byte of data to the MAX77756. This protocol is
the same as the SMBus specification’s read byte protocol.
The read byte protocol is as follows:
11) The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
1) The master sends a start command (S).
Note that when the the IC receives a stop, it does not
modify its register pointer.
2) The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
Reading from Sequential Registers
3) The addressed slave asserts an acknowledge (A) by
pulling SDA low.
Figure 9 shows the protocol for reading from sequential
registers. This protocol is similar to the read byte protocol
except the master issues an acknowledge to signal the
slave that it wants more data: when the master has all
the data it requires it issues a not acknowledge (nA) and
a stop (P) to end the transmission.The continuous read
from sequential registers protocol is as follows:
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a repeated start command (Sr).
7) The master sends the 7-bit slave address followed by
a read bit (R/W = 1).
1) The master sends a start command (S).
8) The addressed slave asserts an acknowledge by pulling SDA low.
2) The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
9) The addressed slave places 8 bits of data on the bus
from the location specified by the register pointer.
3) The addressed slave asserts an acknowledge (A) by
pulling SDA low.
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE .
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1 1
8
1 1
7
1 1
8
S
SLAVE ADDRESS
0 A
REGISTER POINTER X
A Sr
SLAVE ADDRESS
1 A
DATA X
1
1
nA P OR Sr*
NUMBER
OF BITS
R/W
R/W
Figure 8. Reading from a Single Register with the Read Byte Protocol
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1 1
8
1 1
7
1 1
8
1
S
SLAVE ADDRESS
0 A
REGISTER POINTER X
A SR
SLAVE ADDRESS
1 A
DATA X
A
1
8
1
A
DATA X+3
A
R/W
R/W
8
1
8
DATA X+1
A
DATA X+2
REGISTER POINTER = X + 1
REGISTER POINTER = X + 2
8
1
DATA N-2
A
REGISTER
POINTER = N - 2
REGISTER POINTER = X + 3
8
1
8
DATA N-1
A
DATA N
REGISTER
POINTER = N - 1
1
1
P OR
NA
SR*
NUMBER
OF BITS
NUMBER
OF BITS
NUMBER
OF BITS
REGISTER POINTER = N
Figure 9. Reading Continuously from Sequential Registers X to N
www.maximintegrated.com
Maxim Integrated │ 22
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
4) The master sends an 8-bit register pointer.
Note that when the the IC receives a stop it does not
modify its register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a repeated start command (Sr).
7) The master sends the 7-bit slave address followed by
a read bit (R/W = 1). When reading the RTC timekeeping registers, secondary buffers are loaded with
the timekeeping register data during this operation.
8) The addressed slave asserts an acknowledge by pulling SDA low.
9) The addressed slave places 8 bits of data on the bus
from the location specified by the register pointer.
Engaging High-Speed (HS) Mode for Operation
Up to 3.4MHz
Figure 10 shows the protocol for engaging HS mode
operation. HS mode operation allows for a bus operating
speed up to 3.4MHz.The procedure to engage HS mode
protocol is as follows:
●● Begin the protocol while operating at a bus speed of
1MHz or lower.
●● The master sends a start command (S).
10) The master issues an acknowledge (A) signaling the
slave that it wishes to receive more data.
●● The master sends the 8-bit master code of 0b0000
1XXX where 0bXXX are don’t care bits.
11) Steps 9 to 10 are repeated as many times as the master requires. Following the last byte of data, the master must issue a not acknowledge (nA) to signal that it
wishes to stop receiving data.
●● The master can now increase its bus speed up to
3.4MHz and issue any read/write operation.
12) The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a stop (P) ensures that
the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their
current state.
●● The addressed slave issues a not acknowledge (nA).
The master can continue to issue high-speed read/write
operations until a stop (P) is issued. Use repeated start
(Sr) to continue operations in high speed mode.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
8
1 1
S
HS MASTER CODE
nA SR
FAST MODE
ANY R/W PROTOCOL
FOLLOWED BY SR
SR
ANY R/W PROTOCOL
FOLLOWED BY SR
HS MODE
SR
ANY READ/WRITE
PROTOCOL
P
FAST MODE
Figure 10. Engaging HS Mode
www.maximintegrated.com
Maxim Integrated │ 23
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Register Map
MAX77756
ADDRESS
NAME
MSB
LSB
Configuration Registers
0x00
CONFIG_A[7:0]
0x01
CONFIG_B[7:0]
S_SPECT
SOFT_ST
I_PEAK[1:0]
RSVD
RSVD
EN_CTRL
EN_BIT
V_OUTREG[7:0]
CONFIG_A (0x00)
BIT
7
6
Field
S_SPECT
SOFT_ST
Reset
0
0
Access Type
Write, Read
Write, Read
BITFIELD
BITS
5
4
3
2
1
0
I_PEAK[1:0]
RSVD
RSVD
EN_CTRL
EN_BIT
00
OTP
0
0
0
Write, Read
Read Only
Write, Read
Write, Read
Write, Read
DESCRIPTION
DECODE
S_SPECT
7
Spread-spectrum modulation enable control.
0 = Spread-spectrum modulation off
1 = Spread-spectrum modulation on
SOFT_ST
6
Soft-start control. Sets the regulator's startup
ramp time (tSS).
0 = 8ms
1 = 4ms
5:4
High-side DMOS peak current limit threshold
control. Sets peak LX current (ILX-PEAK) only
while the ILIM pin is low. See Peak Inductor
Current Limit (ILIM) for details.
00 = 700mA
01 = 800mA
10 = 900mA
11 = 1000mA
I_PEAK
RSVD
3
Factory-set control bit. Writes are ignored.
N/A
RSVD
2
Reserved control bit. Write to 0.
N/A
EN_CTRL
1
Enable logic control bit.
Determines the logical relationship between the
EN_BIT (enable bit) and EN (enable pin).
0 = Logical OR relationship
1 = Logical AND relationship
EN_BIT
0
Regulator enable bit.
0 = Disabled
1 = Enabled
www.maximintegrated.com
Maxim Integrated │ 24
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
CONFIG_B (0x01)
BIT
7
6
5
4
3
2
Field
V_OUTREG[7:0]
Reset
0x06 / 0x24 / 0x46 (See Ordering Information)
Access Type
BITFIELD
V_OUTREG
1
0
Write, Read
BITS
7:0
DESCRIPTION
0x00 = 1.5V
0x01 = 1.55V
0x02 = 1.6V
Output Voltage Control. Programmable in
.
50mV per LSB from 0x00 (1.5V) to 0x78 (7.5V).
.
Restrict writes to this register between 0x00
0x24 = 3.3V
and 0x78. Do not program this register with
.
codes outside this range.
.
This register is a don't care for the external
0x46 = 5.0V
feedback version (MAX77756D).
.
.
0x78 = 7.5V
Applications Information
IN1/IN2/SUP Capacitor Selection
For dual-input applications, connect separate voltage
supplies to IN1 and IN2 and bypass IN1 (CIN1) and IN2
(CIN2) to PGND with 2.2μF ceramic capacitors. Bypass
SUP to PGND with a 1μF ceramic capacitor (CSUP).
The CSUP capacitor adds with the CIN1/CIN2 capacitor
to decouple the input of the buck. Larger values of CSUP
improve decoupling, but increase inrush current from
IN1 or IN2 to SUP when a power source is connected.
Limit IN1/IN2 inrush current to 4.1A. See the Absolute
Maximum Ratings section for more information.
For single input applications that do not utilize IN1 and
IN2, choose CSUP to be a 2.2μF nominal capacitor that
maintains a 1μF effective capacitance at its working voltage. Larger values improve the decoupling for the buck
regulator, but increase inrush current from the voltage
supply when connected. Connect IN1 and IN2 to PGND
to force the power MUX selection logic off for applications
that require no selector.
CIN1/CIN2 plus CSUP reduces the current peaks drawn
from the input power source during buck operation and
reduces switching noise in the system. The ESR/ESL of
CSUP and its series PCB traces should be very low (i.e.,
< 15mΩ + < 2nH) for frequencies up to 2MHz. Ceramic
www.maximintegrated.com
DECODE
capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients.
Choose the CIN1/CIN2/CSUP capacitor voltage rating to be
greater than the expected input voltage of the system. For
systems using the full input voltage range (24V max) of
the MAX77756, choose capacitors rated to 25V or greater.
All ceramic capacitors derate with DC bias voltage
(effective capacitance goes down as DC bias goes up).
Generally, small case size capacitors derate heavily compared to larger case sizes (0603 case size performs better than 0402). Consider the effective capacitance value
carefully by consulting the manufacturer's data sheet.
Output Capacitor Selection
Choose the output bypass capacitance (COUT) to be
22μF. Larger values of COUT improve load transient
performance, but increase the input surge currents during soft-start and output voltage changes. The output
filter capacitor must have low enough ESR to meet
output ripple and load transient requirements. The output
capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no load
conditions. When using high-capacitance, low-ESR
capacitors, the filter capacitor’s ESR dominates the
output voltage ripple in continuous conduction mode.
Maxim Integrated │ 25
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Therefore, the size of the output capacitor depends on the
maximum ESR required to meet the output voltage ripple
(VRIPPLE(P-P)) specifications:
VRIPPLE(P − P) = ESR × ILOAD × LIR
where LIR is the inductor's ripple current to average current ratio. Compute LIR with Equation 1.
Use Equation 2 and Equation 3 to compute IPEAK. If
IPEAK is greater than ILX-PEAK then increase the inductor
value. For VOUT ≤ 5V, a 10μH inductor is suitable across
the entire input voltage range for 500mA maximum DC
load.
Equation 2:
IP − P =
Equation 1:
LIR
=
VOUT ×
(VIN
)
− VOUT
VIN × fSW x ILOAD x L
where ILOAD is the buck's output current in the particular
application (500mA max), VIN is the application's input
voltage, and fSW is 1MHz.
Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate
with DC bias voltage (effective capacitance goes down as
DC bias goes up). Generally, small case size capacitors
derate heavily compared to larger case sizes (0603 case
size performs better than 0402). Consider the effective
capacitance value carefully by consulting the manufacturer's data sheet.
Inductor Selection
Equation 3:
(
VOUT × VIN − VOUT
VIN × fSW × L
IPEAK = ILOAD +
)
IP − P
2
where ILOAD is the buck's output current in the particular
application (500mA max), VIN is the application's largest
expected input voltage (24V max), and fSW is 1MHz.
Limiting the Peak Inrush Current
The peak inrush current from IN1 or IN2 to SUP must be
limited to less than 4.1A. This can be achieved by reducing the slew rate of the input voltage applied to IN1 or IN2,
and/or reducing the value of the SUP capacitor. The peak
inrush current through the input power MUX when voltage
is applied to IN1 or IN2 is calculated with Equation 4.
Equation 4:
IINRUSH
=
dVIN
CSUP dt
Choose an inductor with a saturation current that is
greater than or equal to the the maximum peak current
limit setting (ILX-PEAK). Inductors with lower saturation
current and higher DCR ratings are physically small.
Higher values of DCR reduce buck efficiency. Choose the
RMS current rating of the inductor (the current at which
the temperature rises appreciably) based on the system's
expected load current.
where IINRUSH is the peak inrush current, CSUP is the
SUP capacitance value, and dVIN/dt is the slew rate of the
input voltage on IN1 or IN2. For example, given the following conditions, the peak input current (IINRUSH) upon
voltage application is 500mA:
Choose an inductor value based on the VOUT setting.
See Table 3.
●● CSUP = 1μF
●● dVIN/dt = 500mV/μs
The chosen inductor value should ensure that the peak
inductor ripple current (IPEAK) is below the high-side
MOSFET peak current limit (ILX-PEAK) so that the buck
can maintain regulation.
Table 3. Inductor Value vs. Output Voltage
V OUT RANGE
MINIMUM INDUCTOR
VALUE (μH)
VOUT ≤ 5V
10
5V < VOUT ≤ 7.5V
15
7.5V < VOUT ≤ 11V
22
11V < VOUT ≤ 17V
33
VOUT > 17V
47
www.maximintegrated.com
Given:
Calculation:
●● IINRUSH =
500mV
1μF μs
●● IINRUSH = 500mA
It is not recommended to "hot insert" the input with a
precharged voltage source. The voltage slew rate of a
hot insertion is very fast and can cause inrush currents in
excess of 4.1A.
Maxim Integrated │ 26
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Setting the Output Voltage (MAX77756D)
PCB Layout Guidelines
The external feedback version of the device (MAX77756D)
uses resistors to set the output voltage between 1V and
99% of the input voltage. Connect a resistor divider
between VOUT, OUT/FB, and AGND as shown in Figure
11. Choose RBOT (OUT/FB to AGND) to be less than or
equal to 100kΩ. Calculate the value of RTOP (VOUT to
OUT/FB) for a desired output voltage with Equation 5.
Careful circuit board layout is critical to achieve lowswitching power losses and clean, stable operation.
Figure 12 shows a sketch of an example PCB top-metal
layout.
When designing the PCB, follow these guidelines:
1) The SUP capacitor should be placed immediately next
to the SUP pin of the device. Since the device operates at 1MHz switching frequency, this placement is
critical for effective decoupling of high-frequency
noise from the SUP pin.
Equation 5:
RTOP = RBOT ×
[
VOUT
VFB
−1
]
2) Similarly, the input capacitors (CIN1/CIN2) should be
placed immediately next to their respective input pins.
where VFB is 1V and VOUT is the desired output voltage.
3) Place the inductor and output capacitor close to the
part and keep the loop area small.
For the internal feedback versions (MAX77756A/
MAX77756B/MAX77756C) change the bits in V_
OUTREG[7:0] to program the output voltage between 1V
and 7.5V in 50mV steps per LSB.
4) Make the trace between LX and the inductor short and
wide. Do not to take up an excessive amount of area.
The voltage on this node is switching very quickly and
additional area creates more radiated emissions.
VOUT
MAX77756D
RTOP
5) Connect PGND and AGND together at the return terminal of the output capacitor. Do not connect them
anywhere else.
RBOT
6) Keep the power traces and load connections short
and wide. This practice is essential for high efficiency.
OUT/FB
7) Place the BIAS capacitor ground next to the AGND
pin and connect with a short and wide trace.
Figure 11. External Feedback Resistors
LX
OUT
COUT
CSUP
COUT
IN1
COUT
CBST
10μH
2520
GND
CIN1
GND
OUT
CVIO
LEGEND
CIN2
IN2
CBIAS
RPU
POK
0603
0402
0201
Figure 12. PCB Top-Metal and Component Layout Example
www.maximintegrated.com
Maxim Integrated │ 27
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Powering USB Type-C Power Delivery
Port Controllers
●● Low IQ consumption (19μA typ for dual-input) enables
the device to remain always-on. This extends battery
life and functionality by enabling the PD port controller to monitor plug attachment while the gadget is in
sleep/hibernate state.
The MAX77756 is ideal for battery-powered systems/
gadgets that use USB type-C with power delivery (PD)
to charge. These systems require a PD port controller to
monitor device attachment to the USB port, determine
roles of the attached device, and negotiate for PD voltages. See Figure 13. Applications that use the MAX77756
to power the PD controller benefit in the following ways:
●● 3V–24V input voltage range allows the device to
power the port controller over the entire PD voltage
range.
●● Hardware or software enable allows flexible control
from a host processor.
●● Dual-input power MUX allows the device to power
from VBUS or BATT ensuring the load is always
powered. This enables PD negotiation even if the gadget battery is dead.
For more information on USB type-C PD, refer to the
USB website and specification documents that are readily
available and free on the internet.
5V, 9V, 12V, 20V TYPICAL
VBUS
SUP
BUS INPUT
3.0V TO 24V
BATT INPUT
IN1
EN
IN2
BST
2.2μF
MAX77756B
LX
0.1μF
OUTPUT
3.3V, 500mA MAX
10μH
3x22μF
PGND
1S, 2S, 3S
OR 4S Li+
BATTERY
BIAS
1μF
AGND
100kΩ
POK
VIO
SCL
SDA
TXn
RXn
1μF
OUT
ILIM
D−
TO HOST
SYSTEM
CC1
VDD
USB TYPE-C
PORT CONTROLLER WITH
POWER-DELIVERY (PD)
nRST
USB TYPE-C CONNECTOR
D+
2.2μF
CC2
GND
TO HOST
SYSTEM
Figure 13. USB Type-C PD Port Controller Power Supply
www.maximintegrated.com
Maxim Integrated │ 28
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Backup Power for Always-On Clocks and Sensors
The MAX77756’s integrated dual-input power MUX is ideal for providing backup power to critical always-on circuits such
as motion sensors, light curtains, and real-time clocks (RTCs). See Figure 14. If primary power is suddenly removed, the
buck input seamlessly transitions to backup power. VOUT is nearly unaffected by the transition. See Figure 15.
18V SOLAR CELL ARRAY
OR 12V PRIMARY BATTERY STACK
SUP
PRIMARY INPUT
2.2μF
BACKUP INPUT
3.0V TO 24V
IN1
EN
IN2
BST
2.2μF
MAX77756B
LX
OUT
6V BACKUP
BATTERY
COIN CELL STACK
PGND
ILIM
BIAS
1μF
AGND
1μF
0.1μF
10μH
OUTPUT
3.3V, 500mA MAX
3x22μF
VDD
REAL-TIME CLOCK (RTC)
MOTION SENSOR
ALWAYS-ON CIRCUIT
POK
GND
VIO
SCL
SDA
Figure 14. Uninterruptible Power Supply for Always-On Circuit
Figure 15. Switchover to Backup Power after Sudden Unplug
www.maximintegrated.com
Maxim Integrated │ 29
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Creating an Instant-On System
The MAX77756 can be used to implement an instant-on
battery charging system. See Figure 16.
●● The battery charger (MAX8971 or similar) charges the
cell from USB power.
●● The dual-input power MUX selects the higher-voltage
(USB) to power the buck.
●● USB continues to power the buck even after the battery is finished charging.
Select a battery charger with automatic input-current
limiting (AICL) or minimum input-voltage regulation. The
MAX8971 switch-mode charger with AICL regulates a
minimum input (USB) voltage by reducing the charge current into the cell. This preserves a stable USB source for
the device while charging the battery with residual power
not used by the load.
This system can be extended beyond a single Li+ cell in
USB type-C power delivery applications.
USB CONNECTOR
●● The the device switches over to BATT power when
USB disconnects.
VBUS
BUS INPUT
2.2μF
SUP
3.0V TO 24V
BATTERY CHARGER
IN1
EN
IN2
BST
MAX77756B
MAX8971 OR SIMILAR
LX
OUT
BATT INPUT
1μF
0.1μF
10μH
OUTPUT
3.3V, 500mA MAX
3x22μF
PGND
2.2μF
ILIM
Li+ BATTERY
BIAS
1μF
AGND
LOAD
POK
VIO
SCL
SDA
Figure 16. Simple Instant-On Battery System
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Maxim Integrated │ 30
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Application Circuits
Always-On (EN = SUP), Dual-Input, Internal Voltage Feedback
DC SOURCE 1
3V TO 24V
DC SOURCE 2
CIN1 2.2μF
25V (0402)
SUP
IN1
IN2
BST
MAX77756A
MAX77756B
MAX77756C
CIN2 2.2μF
25V (0402)
LX
SUP
CBST
0.1μF 10V
(0402)
VOUT
1.8V/3.3V/5.0V
L 10μH
1ASAT (2520)
COUT 3x22μF
10V (0603)
OUT
EN
BIAS
VIO
SDA
SCL
CSUP 1μF
25V (0603)
CBIAS 1μF
6V (0402)
ILIM
AGND
PGND
RPU
100k (0402)
POK
POWER OK
I2C Control, Dual-Input, Internal Voltage Feedback
DC SOURCE 1
3V TO 24V
DC SOURCE 2
CIN1 2.2μF
25V (0402)
IN2
CIN2 2.2μF
25V (0402)
CVIO 0.1μF
6V (0402)
SUP
IN1
MAX77756A
MAX77756B
MAX77756C
BIAS
SDA
SCL
www.maximintegrated.com
LX
CSUP 1μF
25V (0603)
CBST
0.1μF 10V
(0402)
VOUT
1.8V/3.3V/5.0V OR
PROGRAMMABLE 1.5V – 10V
L 10μH
1ASAT (2520)
COUT 3x22μF
10V (0603)
OUT
EN
VIO
SERIAL
HOST
BST
ILIM
AGND
PGND
POK
CBIAS 1μF
6V (0402)
RPU
100k (0402)
POWER OK
Maxim Integrated │ 31
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Application Circuits (continued)
EN Pin Control, Single-Input (Power MUX Bypassed), Internal Voltage Feedback
3.0V TO 24V
DC SOURCE
SUP
IN1
IN2
MAX77756A
MAX77756B
MAX77756C
VOUT
1.8V/3.3V/5.0V
L 10μH
1ASAT (2520)
COUT 3x22μF
10V (0603)
OUT
BIAS
VIO
SDA
SCL
CBST
0.1μF 10V
(0402)
LX
EN
ENABLE
CSUP 2.2μF
25V (0603)
BST
CBIAS 1μF
6V (0402)
ILIM
AGND
PGND
POK
RPU
100k (0402)
POWER OK
EN Pin Control, Dual-Input, External Voltage Feedback
DC SOURCE 1
DC SOURCE 2
3V TO 24V
CIN1 2.2μF
25V (0402)
SUP
IN1
BST
IN2
CIN2 2.2μF
25V (0402)
MAX77756D
LX
CBST
0.1μF 10V
(0402)
EN
BIAS
VIO
SDA
SCL
www.maximintegrated.com
ILIM
AGND
PGND
POK
VOUT
1V – 99%VSUP
L 10μH
1ASAT (2520)
RTOP varies
(0402)
FB
ENABLE
CSUP 1μF
25V (0603)
CBIAS 1μF
6V (0402)
RBOT 50kΩ
(0402)
CFF 5pF
(0402)
COUT
3x22μF 10V
(0603)
RPU
100k (0402)
POWER OK
Maxim Integrated │ 32
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Ordering Information
PART
VOLTAGE FEEDBACK
OUTPUT VOLTAGE (V OUT-REG)
MAX77756AEWL+
Internal
1.8V
MAX77756BEWL+
Internal
3.3V
MAX77756CEWL+
Internal
5.0V
MAX77756DEWL+
External
N/A (set by feedback resistors)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
www.maximintegrated.com
Maxim Integrated │ 33
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Revision History
REVISION
NUMBER
REVISION
DATE
0
4/17
Initial release
10/17
Updated Benefits and Features, added Note 3, updated Figure 9, updated Inductor
Selection section and added Table 3, replaced Figure 12, added three new sections
with application diagrams to Applications Information section, replaced Typical
Application Circuits
1
PAGES
CHANGED
DESCRIPTION
—
1–7, 15, 17,
22, 25–31
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 34
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