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MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
General Description
The MAX77801 is a high-efficiency, step-up/step-down
(buck-boost) converter targeted for single-cell, Li-ion
battery-powered applications. The device maintains a
regulated output voltage from 2.6V to 4.18V across an
input voltage range of 2.3V to 5.5V. The device supports
up to 2A of output current in boost mode and up to 3A in
buck mode.
The device seamlessly transitions between buck and
boost modes. A unique control algorithm allows high-efficiency and outstanding load and line-transient response.
Dedicated enable and power-OK pins allow simple hardware control. An I2C serial interface is optionally used for
dynamic voltage scaling, system power optimization, and
fault read-back.
The MAX77801 is available in a 20-bump, 2.13mm x
1.83mm wafer-level package (WLP) and also 20-pin,
4mm x 4mm TQFN.
Applications
●
●
●
Single-Cell, Li-Ion Battery-Powered Devices
Handheld Scanners, Mobile Payment Terminals,
Security Cameras
AR/VR Headsets
Benefits and Features
● VIN Range: 2.30V to 5.5V
● VOUT Range: 2.60V to 4.18V (I2C Programmable in
12.5mV Steps)
● Up to 2A Output Current in Boost Mode (VIN = 3.0V,
VOUT = 3.4V)
● Up to 3A Output Current in Buck Mode
● Up to 97% Peak Efficiency
● SKIP Mode for Optimal Light Load Efficiency
● 55μA (Typ) Low Quiescent Current
● 3.4MHz High-Speed I2C Serial Interface
● Dynamic Voltage Scaling (DVS) Function
● Power-OK Output
● 2.5MHz Switching Frequency
● Protection Features
• Soft-Start
• Thermal Shutdown
• Overvoltage Protection
• Overcurrent Protection
● 2.13mm x 1.83mm, 20-Bump WLP
● 4mm x 4mm, 20-Pin TQFN
Typical Application Circuit
1µH
MAX77801
DC INPUT
2.3 V TO 5.5V
10μF
1μF
LX1
LX2
IN
OUT
VSYS
FB
BOOST TO BUCK
LINE TRANSIENT RESPONSE
47μF
VOUT
2.6 V TO 4.18 V
2A (BOOST MODE)
3A (BUCK MODE)
IOUT = 1.5A
VOUT = 3.3V
VIN
PGND
BOO ST
MO DE
VIO
SERIAL HOST
SDA
POK
POWER-OK
DVS
DYNAMIC V OL TA GE
SCALING
3.4V
2.9V
500mV/div
BUCK MODE
VOUT
BOO ST
MO DE
20mV/div
SCL
ENABLE
EN
100µs/div
HIGH-EFFI CIENCY BUCK-BOOST CONVERTER
WITH OPTI ONAL I2C CONTROL IN TINY 20-BUMP WL P
Ordering Information appears at end of data sheet.
19-7515; Rev 7, 1/23
© 2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A.
|
Tel: 781.329.4700
|
© 2023 Analog Devices, Inc. All rights reserved.
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Absolute Maximum Ratings
SYS, VIO to AGND................................................-0.3V to +6.0V
IN, OUT to PGND..................................................-0.3V to +6.0V
PGND to AGND.....................................................-0.3V to +0.3V
SCL, SDA to AGND.................................... -0.3V to (VIO + 0.3V)
EN, DVS, POK to AGND.........................-0.3V to (VSYS + 0.3V)
FB to AGND........................................... -0.3V to (VOUT + 0.3V)
LX1 to PGND............................................. -0.3V to (VIN + 0.3V)
LX2 to PGND......................................... -0.3V to (VOUT + 0.3V)
LX1/LX2 Continuous RMS Current.......................................3.3A
Operating Junction Temperature Range........... -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
Junction-to-Ambient Thermal Resistance (θJA)
20-Bump WLP.........................................................55.49°C/W
20-Pin TQFN................................................................39°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Buck-Boost Electrical Characteristics
(VSYS = VIN = +3.8V, VFB = VOUT = +3.3V, TJ = -40°C to +125°C, typical values are at TA ≈ TJ = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
GENERAL
Input Voltage Range
Shutdown Supply Current
Input Supply Current
Active Discharge Resistance
Thermal Shutdown
VIN
2.3
ISHDN_25C
EN = low, TA = +25°C
0.1
ISHDN_125C
EN = low, TA = +125°C
1
IQ_SKIP
SKIP mode, no switching TJ = -40°C to +85°C
55
IQ_PWM
FPWM mode, no load
6
mA
100
Ω
+165
°C
RDISCHG
TSHDN
Rising, 20°C hysteresis
VOUT
I2C programmable (12.5mV step)
µA
70
µA
H-BRIDGE
Output Voltage Range
Default Output Voltage
Output Voltage Accuracy
www.analog.com
2.60
4.1875
VOUT_DVS_L[6:0] = 0x38
3.3
VOUT_DVS_H[6:0] = 0x40,
MAX77801EWP only
3.4
VOUT_DVS_H[6:0] = 0x5C,
MAX77801ETP only
3.75
V
V
VOUT_ACC1
PWM mode, VOUT_DVS_x[6:0] = 0x40,
no load TJ = +25°C
-1.0
+1.0
VOUT_ACC2
SKIP mode, VOUT_DVS_x[6:0] = 0x40,
no load, TJ = +25°C
-1.0
+4.5
%
Analog Devices │ 2
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Buck-Boost Electrical Characteristics (continued)
(VSYS = VIN = +3.8V, VFB = VOUT = +3.3V, TJ = -40°C to +125°C, typical values are at TA ≈ TJ = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Line Regulation
VIN = 2.3V to 5.5V
0.200
%/V
Load Regulation
(Note 3)
0.125
%/A
Line Transient Response
VOS1
VUS1
IOUT = 1.5A,
VIN changes from 3.4V to 2.9V in 25µs
(20mV/µs), L = 1µH, COUT_NOM = 47µF
(Note 3)
50
mV
Load Transient Response
VOS2
VUS2
VIN = 3.4V,
IOUT changes from 10mA to 1.5A in 15µs, L
= 1µH, COUT_NOM = 47µF
(Note 3)
50
mV
Output Voltage Ramp-Up
Slew Rate
RU_SR = 0
12.5
RU_SR = 1
25
Output Voltage Ramp-down
Slew Rate
RD_SR = 0
3.125
RD_SR = 1
6.25
Typical Load Efficiency
Peak Efficiency
Maximum Output Current
ηIOUT_TYP
ηPK
95
%
(Note 3)
97
%
IOUT(MAX)
2.8V ≤ VIN ≤ 5.5V
2000
IOUT(MAX)
2.3V ≤ VIN < 2.8V
1000
High-Side PMOS ON
Resistance
RDSON
ILX = 100mA per switch, WLP
40
(PMOS)
ILX = 100mA per switch, TQFN
50
Low-Side NMOS ON
Resistance
RDSON
ILX = 100mA per switch, WLP
55
(NMOS)
ILX = 100mA per switch, TQFN
65
Switching Frequency
fSW
Minimum Effective Output
Capacitance
LX1, LX2 Leakage Current
3.70
mA
ILIM_LX
Soft-Start Time
mV/µs
IOUT = 100mA, VIN = 3.6V
(Note 3)
LX1/2 Current Limit
Turn-On Delay Time
mV/µs
PWM mode, TA = +25°C
2.25
4.70
2.50
5.70
A
mΩ
mΩ
2.75
MHz
From EN asserting to LX switching
with bias ON
100
µs
IOUT = 10mA
120
µs
0A < IOUT < 2000mA
16
µF
ILK_25
VLX1/2 = 0V or 5.5V, VOUT = 5.5V, VSYS =
VIN = 5.5V, TA = +25°C
0.1
ILK_125
VLX1/2 = 0V or 5.5V, VOUT = 5.5V, VSYS =
VIN = 5.5V, TA = +125°C
0.2
Rising threshold
80
%
Falling threshold
75
%
tON_DLY
tSS
CEFF(MIN)
1
µA
POWER-OK COMPARATOR
Output POK Trip Level
www.analog.com
Analog Devices │ 3
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Buck-Boost Electrical Characteristics (continued)
(VSYS = VIN = +3.8V, VFB = VOUT = +3.3V, TJ = -40°C to +125°C, typical values are at TA ≈ TJ = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.375
2.50
2.625
V
VSYS UNDERVOLTAGE LOCKOUT
VSYS Undervoltage Lockout
Threshold
VUVLO_R
VSYS rising
VUVLO_F
VSYS falling (default)
2.05
V
LOGIC AND CONTROL INPUTS
Input Low Level
VIL
EN, DVS, VSYS ≤ 4.5V, TA = +25°C
Input High Level
VIH
EN, DVS, VSYS ≤ 4.5V, TA = +25°C
POK Output Low Voltage
POK Output High Leakage
VOL
ISINK = 1mA
IOZH_25C
TJ = +25°C
IOZH_125C
TJ = +125°C
0.4
1.2
V
V
-1
0.4
V
+1
µA
0.1
µA
INTERNAL PULLDOWN RESISTANCE
EN, DVS
RPD
Pulldown resistor to AGND
400
800
1600
kΩ
I2C Electrical Characteristics
(VSYS = 3.8V, VIO = 1.8V, TJ = -40°C to +125°C, typical values are at TA ≈ TJ = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.6
V
POWER SUPPLY
VIO Voltage Range
VIO
1.7
SDA AND SCL I/O STAGES
SCL, SDA Input High Voltage
SCL, SDA Input Low Voltage
SCL, SDA Input Hysteresis
VIH
0.7 x VIO
V
VIL
0.3 x VIO
VHYS
SCL, SDA Input Current
II
SDA Output Low Voltage
VOL
SCL, SDA Input Capacitance
CI
Output Fall Time from VIO
to 0.3 x VIO
tOF
0.05 x VIO
VIO = 3.8V
-10
V
+10
ISINK = 20mA
V
0.4
10
µA
V
pF
120
ns
1000
kHz
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST MODE PLUS) (Note 3)
Clock Frequency
Hold Time (REPEATED)
START Condition
SCL Low Period
SCL High Period
Setup Time REPEATED
START Condition
www.analog.com
fSCL
tHD_STA
0.26
µs
tLOW
0.5
µs
tHIGH
0.26
µs
tSU_STA
0.26
µs
Analog Devices │ 4
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
I2C Electrical Characteristics (continued)
(VSYS = 3.8V, VIO = 1.8V, TJ = -40°C to +125°C, typical values are at TA ≈ TJ = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DATA Hold Time
tHD_DAT
0
µs
DATA Setup Time
tSU_DAT
50
ns
Setup Time for STOP Condition
tSU_STO
0.26
µs
Bus-Free Time Between
STOP and START
tBUF
0.5
µs
Capacitive Load for Each
Bus Line
CB
550
Maximum Pulse Width of
Spikes That Must Be Suppressed by the Input Filter
50
pF
ns
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 100pF) (Note 3)
Clock Frequency
fSCL
3.4
MHz
Set-Up Time REPEATED
START Condition
tSU_STA
160
ns
Hold Time (REPEATED)
START Condition
tHD_STA
160
ns
CLK Low Period
tLOW
160
ns
CLK High Period
tHIGH
60
ns
DATA Setup Time
tSU_DAT
10
DATA Hold Time
tHD_DAT
ns
35
ns
SCL Rise Time (Note 3)
tRCL
TJ = +25°C
10
40
ns
Rise Time of SCL Signal After
REPEATED START Condition
and After Acknowledge Bit
tRCL1
TJ = +25°C
10
80
ns
SCL Fall Time
tFCL
TJ = +25°C
10
40
ns
SDA Rise Time
tRDA
TJ = +25°C
80
ns
SDA Fall Time
tFDA
TJ = +25°C
80
ns
Setup Time for STOP Condition
Bus Capacitance
Maximum Pulse Width of
Spikes That Must Be Suppressed by the Input Filter
www.analog.com
tSU_STO
160
ns
CB
100
10
pF
ns
Analog Devices │ 5
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
I2C Electrical Characteristics (continued)
(VSYS = 3.8V, VIO = 1.8V, TJ = -40°C to +125°C, typical values are at TA ≈ TJ = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
I2C-COMPATIBLE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.7
MHz
INTERFACE TIMING (HIGH-SPEED MODE, CB = 400pF) (Note 3)
Clock Frequency
fSCL
Setup Time REPEATED
START Condition
tSU_STA
160
ns
Hold Time (REPEATED)
START Condition
tHD_STA
160
ns
SCL Low Period
tLOW
320
ns
SCL High Period
tHIGH
120
ns
DATA Setup Time
tSU_DAT
10
ns
DATA Hold Time
tHD_DAT
75
ns
SCL Rise Time
tRCL
TJ = +25°C
20
80
ns
Rise Time of SCL Signal After
REPEATED START Condition
and After Acknowledge Bit
tRCL1
TJ = +25°C
20
160
ns
SCL Fall Time
tFCL
TJ = +25°C
20
80
ns
SDA Rise Time
tRDA
TJ = +25°C
160
ns
SDA Fall Time
tFDA
TJ = +25°C
160
ns
Setup Time for STOP Condition
tSU_STO
Bus Capacitance
CB
Maximum Pulse Width of
Spikes That Must Be
Suppressed by the Input Filter
tSP
160
ns
400
10
pF
ns
Note 2: Limits are 100% production tested at TJ = +25°C. The device is tested under pulsed load conditions such that TJ ≈ TA.
Limits over the operating temperature range are guaranteed through correlation using statistical quality control methods.
Note 3: Guaranteed by design. Not production tested.
www.analog.com
Analog Devices │ 6
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Typical Operating Characteristics
(VSYS = VIN = +3.8V, VFB = VOUT = +3.3V, TA = +25°C.)
QUIESCENT CURRENT vs. SUPPLY
VOLTAGE
toc01
70
SHUTDOWN CURRENT vs. SUPPLY
VOLTAGE
toc02
2.0
60
55
SHUTDOWN CURRENT (µA)
QUIESCENT CURRENT (µA)
65
VOUT = 2.8V
VOUT = 3.3V
VOUT = 5V
50
45
40
1.5
TA = +85°C
1.0
0.5
TA = +25°C
0.0
35
30
TA = -40°C
2
3
4
5
-0.5
6
2
3
SUPPLY VOLTAGE (V)
EFFICIENCY vs. LOAD
2.8V OUTPUT
100
toc03
60
EFFICIENCY (%)
EFFICIENCY (%)
toc04
50
40
30
VIN = 3V
VIN = 3.3V
VIN = 3.8V
VIN = 4.5V
80
VIN = 3V
VIN = 3.8V
VIN = 4.5V
70
VIN = 3.8V (FPWM = 1)
20
70
60
50
40
30
VIN = 3.8V (FPWM = 1)
20
10
10
0
0.001
2.85
0.01
0.1
0
0.001
1
0.01
0.1
1
LOAD (A)
LOAD (A)
LOAD REGULATION
2.8V OUTPUT
LOAD REGULATION
3.3V OUTPUT
toc05
3.39
toc06
3.38
2.84
3.37
2.83
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
6
90
80
2.82
VIN = 3V
VIN = 3.8V
VIN = 4.5V
2.81
2.80
2.79
3.36
3.35
VIN = 3V
VIN = 3.3V
VIN = 3.8V
VIN = 4.5V
3.34
3.33
3.32
3.31
2.78
3.30
0.0
0.5
1.0
LOAD (A)
www.analog.com
5
EFFICIENCY vs. LOAD
3.3V OUTPUT
100
90
2.77
4
SUPPLY VOLTAGE (V)
1.5
2.0
3.29
0.0
0.5
1.0
1.5
2.0
LOAD (A)
Analog Devices │ 7
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Typical Operating Characteristics (continued)
(VSYS = VIN = +3.8V, VFB = VOUT = +3.3V, TA = +25°C.)
LINE REGULATION
2.8V OUTPUT
2.80
toc07
3.32
2.78
IOUT = 500mA
IOUT = 1A
IOUT = 2A
2.77
2.76
2.75
3.30
IOUT = 500mA
IOUT = 1A
IOUT = 2A
3.29
3.28
3.27
2.5
3.5
4.5
3.26
5.5
2.5
3.5
SUPPLY VOLTAGE (V)
4.5
5.5
SUPPLY VOLTAGE (V)
MAXIMUM OUTPUT CURRENT vs.
SUPPLY VOLTAGE
4.5
STARTUP WAVEFORM
3.3V OUTPUT
toc09
toc10
VOUT = 2.8V
4.0
VOUT = 3.3V
3.5
OUTPUT CURRENT (A)
toc08
3.31
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.79
2.74
LINE REGULATION
3.3V OUTPUT
2V/div
VEN
3.0
VOUT
2.5
2V/div
EN = 1
2.0
200mV/div
VLX
1.5
1.0
IIN
0.5
0.0
2A/div
VIN = 3.8V
2
3
4
5
6
40µs/div
SUPPLY VOLTAGE (V)
LOAD TRANSIENT RESPONSE
2.8V OUTPUT
LOAD TRANSIENT RESPONSE
3.3V OUTPUT
toc11
toc12
1A
1A
500mA/div
IOUT
500mA/div
IOUT
10mA
10mA
VOUT
VOUT
SLEW RATE = 0.99A/15µs
100µs/div
www.analog.com
100mV/div
100mV/div
SLEW RATE = 0.99A/15µs
100µs/div
Analog Devices │ 8
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Typical Operating Characteristics (continued)
(VSYS = VIN = +3.8V, VFB = VOUT = +3.3V, TA = +25°C.)
LINE TRANSIENT RESPONSE
2.8V OUTPUT
BOOST to BUCK
LINE TRANSIENT RESPONSE
toc13
IOUT = 1.5A
IOUT = 1.5A
VOUT = 3.3V
3.4V
VIN
2.9V
500mV/div
VOUT
20mV/div
VIN
toc14
3.4V
2.9V
500mV/div
VOUT
20mV/div
SLEW RATE = 20mV/µs
SLEW RATE = 20mV/µs
100µs/div
100µs/div
SWITCHING WAVEFORM
3.3V OUTPUT
OUTPUT RIPPLE in SKIP MODE
3.3V OUTPUT (IOUT = 100mA)
toc15
IOUT = 1A
toc16
IOUT = 100mA
1V/div
VLX
20mV/div
VOUT
FSW = 2.5MHz
100µs/div
4µs/div
OUTPUT RIPPLE in PWM
3.3V OUTPUT (IOUT = 1A)
SHORT-CIRCUIT AND RECOVERY
3.3V OUTPUT
toc17
toc18
SHORT APPLIED
IOUT = 1A
VOUT
RECOVERY/
SHORT REMOVED
HICCUP/RETRY
10mV/div
VOUT
ILX
20µs/div
www.analog.com
2V/div
2A/div
20ms/div
Analog Devices │ 9
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
A
DVS
VSYS
AGND
SDA
5
SCL
4
EN
3
VIO
2
IN
1
IN
MAX77801
15
14
13
12
11
SCL
10
LX1 16
FB
B
POK
AGND
EN
VIO
LX1 17
MAX77801
PGND 18
IN
PGND 19
LX2 20
D
OUT
LX2
PGND
LX1
+
IN
20 WLP
(2.13mm x 1.83mm, 0.4mm PITCH)
1
2
3
4
5
VSYS
LX1
FB
PGND
OUT
LX2
OUT
OUT
LX2
C
SDA
9
AGND
8
AGND
7
POK
6
DVS
20 TQFN
(4mm x 4mm, 0.75mm PITCH)
Pin Description
20-BUMP
WLP
20-PIN
TQFN
NAME
A1
5
VSYS
System (Battery) Voltage Input. Bypass to AGND with a 10V, 1µF capacitor.
A2
6
DVS
Dynamic Voltage Scaling Logic Input. Connect to AGND if not used.
A3, B3
8, 9
AGND
A4
10
SDA
I2C Serial Interface Data (High-Z in OFF State). Connect to VIO with a 1.5kΩ to 2.2kΩ pullup
resistor. Connect to AGND if not used.
A5
11
SCL
I2C Serial Interface Clock (High-Z in OFF State). Connect to VIO with a 1.5kΩ to 2.2kΩ pullup
resistor. Connect to AGND if not used.
B1
4
FB
B2
7
POK
B4
12
EN
Active-High Enable Input. This pin has an 800kΩ internal pulldown to AGND.
B5
13
VIO
I2C Supply Voltage Input. Bypass to AGND with a 0.1µF capacitor. Connect to AGND if not
used.
C1, D1
2, 3
OUT
Output. Bypass to PGND with a 10V 47μF ceramic capacitor.
Switching Node 2.
C2, D2
1, 20
LX2
C3, D3
18, 19
PGND
C4, D4
16, 17
LX1
C5, D5
14, 15
IN
www.analog.com
FUNCTION
Analog Ground. Connect to PGND on the PCB. See the PCB Layout Guidelines.
Output Voltage Sense.
Open-Drain Power-OK Output. Asserts high (high-Z) when buck-boost output reaches 80% of
target.
Power Ground. Connect to AGND on the PCB. See the PCB Layout Guidelines.
Switching Node 1.
Input. Bypass to PGND with a 10V 10µF ceramic capacitor.
Analog Devices │ 10
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Detailed Description
The MAX77801 is a synchronous step-up/step-down
(buck-boost) DC-DC converter with integrated switches.
The buck-boost operates on a supply voltage between
2.3V and 5.5V. Output voltage is configurable through
I2C from 2.60V to 4.18V in 12.5mV steps. Factory-default
startup voltage options of 3.3V, 3.4, and 3.75V are available (see the Buck-Boost Electrical Characteristics table).
●
Φ1 switch period (Phase 1: HS1 = ON, LS2 = ON)
stores energy in the inductor. Inductor current ramps
up at a rate proportional to the input voltage divided
by inductance: VIN/L.
●
Φ2 switch period (Phase 2: HS1 = ON, HS2 = ON)
ramps inductor current up or down depending on the
differential voltage across the inductor: (VIN - VOUT)/L.
●
Φ3 switch period (Phase 3: LS1 = ON, HS2 = ON)
ramps inductor current down at a rate proportional to
the output voltage divided by inductance: -VOUT/L.
Buck-Boost Control Scheme
The buck-boost converter operates using a 2.5MHz fixedfrequency pulse-width modulated (PWM) control scheme
with current-mode compensation. The buck-boost utilizes
an H-bridge topology using a single inductor and output
capacitor.
The H-bridge topology has three switching phases. See
Figure 1 for details.
BUCK-BOOST H-BRIDGE
TOPOLOGY
Boost operation (VIN < VOUT) utilizes phase 1 and phase
2 within a single clock period. See the representation of
the inductor current waveform for boost mode operation
in Figure 1.
Buck operation (VIN > VOUT) utilizes phase 2 and phase
3 within a single clock period. See the representation of
the inductor current waveform for buck mode operation
in Figure 1.
BUCK OPE RATION
IN
Ф2
OUT
Ф2
Ф3
HS1
Ф2
CHARGE/DI SCHARGE L
TSW
HS2
TSW
CLK
Ф3
DISCHARGE L
CLK
CLK
BOOST OPERATI ON
L
LS1
Ф3
LS2
Ф1
Ф1
CHARGE L
Ф2
Ф1
TSW
CLK
Ф2
TSW
CLK
CLK
Figure 1. Buck-Boost H-Bridge Topology
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Analog Devices │ 11
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
LX1
IN
1µH
LX2
HS1
HS2
OUT
10µF
CS
LS1
CS
LS2
DRIVER
47µF
DRIVER
PGND
CONTROL LOGIC
OSC
FB
ETR
CF
COMP.
R1
R2
PROT.
REF
SLOPE
COMP.
PSM
REGISTE R
CONTROL
Figure 2. Buck-Boost Block Diagram
Enable Control (EN)
Raise the EN pin voltage above VIH threshold to enable
the buck-boost output. Lower EN pin below the VIL
threshold to disable it. EN pin has an internal 800kΩ (typ)
pulldown resistor to AGND. Clear the EN_PD bit using
the I2C interface to disable the internal pulldown (making EN pin high-impedance). The EN_PD bit reset value
is 1 (pulldown enabled). Therefore, the internal pulldown
resistor is present whenever the MAX77801 starts up.
After the initial buck-boost startup, clear the EN bit
through I2C to disable the buck-boost output. Table 1
details the interaction between the EN pin and the EN bit.
Provide a valid VIO and set the EN pin logic-high to
enable the I2C serial interface. Serial reads and writes
to the EN bit may happen only while VIO is valid and EN
pin is logic-high. Setting EN pin to logic-low disables the
buck-boost (regardless of EN bit) and causes all registers
to reset to default values.
Table 1. EN Logic
EN PIN
EN BIT
I2C SERIAL INTERFACE
BUCK-BOOST OUTPUT
Low
X
Disabled
Disabled
High
0
Enabled
Disabled
High
1 (default)
Enabled
Enabled
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Analog Devices │ 12
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Dynamic Voltage Scaling (DVS)
The MAX77801 includes a DVS feature that allows output
voltage to change dynamically. The DVS pin status dictates whether the buck-boost regulates to VOUT_DVS_L or
VOUT_DVS_H. When EN pin or EN bit goes high, the DVS
pin status latches until soft-start completes, so changes
on DVS are ignored. Internal logic sets VOUT based on
DVS input only after soft-start completion.
The buck-boost converter supports a programmable
slew-rate control feature when increasing and decreasing the output voltage. The ramp-up slew rate can be
set to 12.5mV/µs or 25mV/µs through RU_SR bit. Also,
the ramp-down slew rate can be set to 3.125mV/µs or
6.25mV/µs through RD_SR bit.
Table 2. Soft-Start ILIM
ILIM_LX AFTER
SOFT-START (A)
ILIM_LX_SS DURING
SOFT-START (A)
tSS SOFTSTART TIME
(µs)
4.5
1.8
120
VOUT I2C
PROGRAMMING
VOUT_DVS_H
REGISTER
Soft-Start
The IC implements a soft-start by reducing the peak inductor current limit (ILIM_LX) for a fixed time. The soft-start time
begins immediately after the startup delay (tON_DLY). See
Table 2 for details.
ILIM_LX reduces (according to Table 2) for tSS after the
buck-boost enables through either the EN pin or EN bit.
Reducing the inductor current limit during startup controls
inrush current from the supply input (IIN) and prevents
droop caused by upstream source impedance.
VOUT_DVS_L
REGISTER
OUTPUT
VOLTAGE
CHOSEN
BY DVS
DVS = L : VOUT_DVS_L REGISTER
DVS = H : VOUT_DVS_H REGISTER
BUCK-BOOST
OUTPUT
DVS
Figure 3. DVS Functional Block Diagram
EN
VOUT
TON_DLY
TSS
ILIM_LX
ILIM_LX_SS
IL
Figure 4. Startup Waveform
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Analog Devices │ 13
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Burst Mode (Enhanced Load Response)
●
●
Table 3. ILIM Levels
The device implements a burst mode to service shortduration heavy load transients (burst loads). A summary
of burst mode operation follows:
If a heavy load transient happens that requires peak
inductor current > ILIM_LX to maintain regulation,
then the buck-boost temporarily increases the peak
inductor current limit from ILIM_LX to ILIM_LX_HIGH.
(See Table 3.)
If the heavy load causes a peak inductor current
> ILIM_LX for longer than 800µs (typ), then burst
mode deactivates and the peak inductor current limit
returns to ILIM_LX.
INDUCTOR CURRENT
LIMIT DURING NORMAL
OPERATION
ILIM_LX (A)
INDUCTOR CURRENT
LIMIT DURING BURST
MODE
ILIM_LX_HIGH (A)
4.5
5.5
SHORT
CIRCUIT
VOUT
800µs
2.2ms
ILIM_LX_HIGH
ILIM_LX
IL
12ms
Figure 5. Short-Circuit Waveform
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Analog Devices │ 14
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Power-OK (POK) Output
The device features an open-drain POK output to monitor
the output voltage. POK requires an external pullup resistor (typically 10kΩ to 100kΩ).
POK is active-high by default. Use the POK_POL bit to
change the POK polarity to active-low. See the Register
Map for details.
While POK_POL = 1 (active-high, default state), POK
goes high (high-impedance) after the buck-boost output
increases above 80% of the target regulation voltage.
POK goes low when the output drops below 75% of the
target or when the buck-boost is disabled.
Output Voltage Selection and
Slew-Rate Control
Write the VOUT_DVS_L[6:0] or VOUT_DVS_H[6:0] bit
field through I2C to configure the target output voltage
(VOUT) between 2.60V and 4.18V in 12.5mV steps. The
default value of the bit fields is factory programmable.
See the Buck-Boost Electrical Characteristics table for
the default VOUT associated with each orderable part
number. Overwriting the default value through I2C sets a
new target VOUT until registers reset.
Changing the bit fields while the buck-boost output is
enabled causes the device to respond in the following
way:
●
VOUT ramps up at a rate set by RU_SR (12.5mV/µs
or 25mV/µs) when the VOUT target is increased.
●
VOUT ramps down at a rate set by RD_SR
(3.125mV/µs or 6.25mV/µs) when the VOUT target is
decreased.
See the Register Map for details about the RU_SR and
RD_SR bits.
Output Overvoltage Protection (OVP)
The device has an internal output overvoltage protection
(OVP) circuit that monitors VOUT for overvoltage faults.
The buck-boost disables if the output exceeds the overvoltage threshold set by the OVP_TH[1:0] bit field.
Disable OVP by programming OVP_TH[1:0] to 0b00
using I2C. The default OVP threshold is 0b11 (120% of
the target VOUT).
The OVP status bit continuously mirrors the status of the
OVP circuit. See the Register Map for details.
Thermal Shutdown
The device has an internal thermal protection circuit that
monitors die temperature. The buck-boost disables if the
die temperature exceeds TSHDN (+165°C typ). The buckboost enables again after the die temperature cools by
approximately 20°C.
The TSHDN status bit continuously mirrors the status of
the thermal protection circuit. See the Register Map for
details.
I2C Serial Interface
The device features a revision 3.0 I2C-compatible, 2-wire
serial interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). The MAX77801 is a
slave-only device that that relies on an external bus master to generate SCL. SCL clock rates from 0Hz to 3.4MHz
are supported. I2C is an open-drain bus, and therefore,
SDA and SCL require pullups (of 500Ω or greater).
The device’s I2C communication controller implements
7-bit slave addressing. An I2C bus master initiates communication with the slave by issuing a START condition
followed by the slave address. The slave address of the
device is shown in Table 4.
The device uses 8-bit registers with 8-bit register addressing. They support standard communication protocols:
●
Writing to a single register
●
Writing to multiple sequential registers with an automatically incrementing data pointer
●
Reading from a single register
●
Reading from multiple sequential registers with an
automatically incrementing data pointer
For additional information on the I2C protocols, refer to
the Serial Interface section.
Table 4. I2C Slave Address
7-BIT SLAVE ADDRESS
0x18
0b 001 1000
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8-BIT WRITE ADDRESS
0x30
0b 0011 0000
8-BIT READ ADDRESS
0x31
0b 0011 0001
Analog Devices │ 15
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Applications Information
Inductor Selection
Choose a 1µH inductor with a saturation current of 7A or
higher. Table 5 recommends inductors for the MAX77801.
Always choose the inductor carefully by consulting the
manufacturer’s latest released data sheet.
Input Capacitor Selection
Choose the input capacitor (CIN) to be a 10µF ceramic
capacitor that maintains at least 2µF of effective capacitance at its working voltage. Larger values improve the
decoupling of the buck-boost. CIN reduces the current
peaks drawn from the battery or input power source and
reduces switching noise in the device. Ceramic capacitors with X5R or X7R dielectric are highly recommended
due to their small size, low ESR, and small temperature
coefficients.
All ceramic capacitors derate with DC bias voltage (effective
capacitance goes down as DC bias goes up). Generally,
small case size capacitors derate heavily as compared
to larger case sizes (0603 case size performs better than
0402). Consider the effective capacitance value carefully
by consulting the manufacturer’s data sheet.
Output Capacitor Selection
Sufficient output capacitance (COUT) is required to keep
the output-voltage ripple small and the regulation loop
stable. Choose the effective COUT to be 16µF minimum.
Considering the DC bias characteristic of ceramic capacitors, a 47μF 10V capacitor is recommended for most
applications.
Effective COUT is the actual capacitance value seen by
the buck-boost output during operation. Choose effective COUT carefully by considering the capacitor’s initial
tolerance, variation with temperature, and derating with
DC bias.
Table 5. Suggested Inductors
Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate
with DC bias voltage (effective capacitance goes down as
DC bias goes up). Generally, small case size capacitors
derate heavily as compared to larger case sizes (0603
case size performs better than 0402). Consider the effective capacitance value carefully by consulting the manufacturer’s data sheet.
PCB Layout Guidelines
Careful circuit board layout is critical to achieve low switching power losses and clean, stable operation. For the
WLP package, an HDI (high density interconnect) PCB is
required. Figure 6 shows an example HDI PCB layout for
the MAX77801 WLP package. Figure 8 shows an example
PCB layout for the MAX77801 FC2QFN package.
When designing the PCB, follow these guidelines:
1) Place the input capacitors (CIN) and output capacitors (COUT) immediately next to the IN pin and OUT
pin, respectively, of the IC. Since the IC operates at
a high switching frequency, this placement is critical
for minimizing parasitic inductance within the input
and output current loops, which can cause high-voltage spikes and may damage the internal switching
MOSFETs. See Figure 7 for an illustration.
2) Place the inductor next to the LX bumps/pins (as
close as possible) and make the traces between the
LX bumps/pins and the inductor short and wide to
minimize PCB trace impedance. Excessive PCB impedance reduces converter efficiency. When routing
LX traces on a separate layer (as in the examples),
make sure to include enough vias to minimize trace
impedance. Routing LX traces on multiple layers is
recommended to further reduce trace impedance.
Furthermore, do not make LX traces take up an
excessive amount of area. The voltage on this node
switches very quickly, and additional area creates
more radiated emissions.
TYPICAL DC
RESISTANCE
(mΩ)
CURRENT
RATING (A)
-30% (ΔL/L)
CURRENT
RATING (A)
ΔT = 40°C
RISE
DIMENSIONS
LxWxH
(mm)
MFGR.
SERIES
NOMINAL
INDUCTANCE
(µH)
Coilcraft
XAL4020-102MEB
1.0
13
8.7
9.6
4.0 x 4.0 x 2.1
Sumida
CDMT40D20HF-1R0NC
1.0
13
8.7
9.6
4.3 x 4.3 x 2.1
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Analog Devices │ 16
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
3) Prioritize the low-impedance ground plane of the
PCB directly underneath the IC, COUT, CIN, and
inductor. Cutting this ground plane risks interrupting
the switching current loops.
CSYS and the SYS bump/pin. Avoid connecting SYS
directly to the nearest IN bumps/pins without dedicated bypassing.
6) Connect the FB bump/pin to the regulating point with
a dedicated trace away from noisy nets such as LX1
and LX2.
4) AGND must carefully connect to PGND on the PCB’s
low-impedance ground plane. Connect AGND to the
low-impedance ground plane on the PCB (the same
net as PGND) away from any critical loops.
7) Keep the power traces and load connections short
and wide. This is essential for high converter efficiency.
5) The IC requires a quiet supply input (SYS) which is
often the same net as IN. Carefully bypass SYS to
AGND with a dedicated capacitor (CSYS) as close as
possible to the IC. Route a dedicated trace between
LX1
8) Do not neglect ceramic capacitor DC voltage derating. Choose capacitor values and case sizes carefully. See the Output Capacitor Selection section and
refer to Tutorial 5527 for more information.
LX2
LEGEND
L
1515 (4040)
1515 (4040)
PGND
PGND
CIN
0603
FB
DVS
POK
SCL
SDA
AGND
CVIO
0402
+ VSYS
AGND
RSYS
0402
EN
0603
0805
0402
CSYS
0402
IN
OUT
COUT
0805
IN
NON-HDI VIA
8 mil hole, 18 mil pad
HDI µVIA
4 mil hole, 8 mil pad
COMPONE NT SIZES LI STED IN
IMPERIAL (METRIC)
NOTE: PLACE C IN AND C OUT CLOSE TO THE IC TO MINIMIZE PA RASITIC INDUCTANCE WI THIN THE LOOP
Figure 6. PCB Layout Example (WLP)
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Analog Devices │ 17
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
L
LAYOUT NOTES:
N1: PLACE THE IN CAPACITOR (CIN) AND OUT CAPACITOR
(COUT) AS CLOSE TO THE IC AS POSSIBLE.
N2: CONNECT THE NEGATIVE TERMINAL OF CIN AS CLOSE
AS POSSIBLE TO THE NEGATIVE TERMINAL OF COUT WITH A
LOW-IMPEDANCE, HIGH-PRIORITY PATH TO THE
CORRESPONDING PGND BUMPS. THIS PRACTICE MINIMIZES
THE HIGH DI/DT LOOP LENGTH, REDUCING ANY VOLTAGE
SPIKES SEEN ON LX1 AND LX2.
N2
PGND
PGND
OUT
CIN
IN
COUT
N1
Figure 7. Recommended Capacitor Placement
AGND
SDA
AGND
LEGEND
RSYS
0402
CSYS
0402
CVIO
0402
IN
OUT
FB
VIO
1515 (4040)
CIN
0603
COUT
0805
+
PGND
PGND
0603
0805
0402
NON-HDI VIA
8 mil hole, 18 mil pad
L
1515 (4040)
LX1
COMPONE NT SIZES LI STED IN
IMPERIAL (METRIC)
LX2
NOTE: EVENLY DISTRIB UTE 9 VI AS ON THE PGND PAD FOR HEAT DI SSIPATION P URPOSES.
Figure 8. PCB Layout Example (TQFN)
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Analog Devices │ 18
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Serial Interface
is called a “master”. Any device that is being addressed by
the master is called a “slave”. When the MAX77801 I2Ccompatible interface is operating, it is a slave on I2C bus,
and it can be both a transmitter and a receiver.
The I2C-compatible, 2-wire serial interface is used for
regulator on/off control, setting output voltages, and other
functions. See the Register Map section for details.
Bit Transfer
The I2C serial bus consists of a bidirectional serial-data
line (SDA) and a serial clock (SCL). I2C is an open-drain
bus. SDA and SCL require pullup resistors (500Ω or
greater). Optional 24Ω resistors in series with SDA and
SCL help to protect the device inputs from high voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot on bus lines.
One data bit is transferred for each SCL clock cycle. The
data on SDA must remain stable during the high portion of
SCL clock pulse. Changes in SDA while SCL is high are
control signals (START and STOP conditions).
START and STOP Conditions
When the I2C serial interface is inactive, SDA and SCL
idle high. A master device initiates communication by
issuing a START condition (S). A START condition (S) is a
high-to-low transition on SDA with SCL high. A STOP condition (P) is a low-to-high transition on SDA with SCL high.
System Configuration
The I2C bus is a multi-master bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
Figure 9 shows an example of a typical I2C system. A
device on I2C bus that sends data to the bus is called a
“transmitter”. A device that receives data from the bus is
called a “receiver”. The device that initiates a data transfer
and generates SCL clock signals to control the data transfer
A START condition (S) from the master signals the beginning of a transmission. The master terminates transmission by issuing a NOT-ACKNOWLEDGE (nA) followed by
a STOP condition (P).
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Figure 9. Functional Logic Diagram for Communications Controller
DATA LINE STABLE
DATA VALID
CHANGE OF DATA ALLOWED
SDA
SCL
Figure 10. I2C Bit Transfer
S
Sr
P
SDA
tSU_START
SCL
tHD_START
tHD_START
tSU_STOP
Figure 11. START and STOP Conditions
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Analog Devices │ 19
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
A STOP condition (P) frees the bus. To issue a series of
commands to the slave, the master may issue REPEATED
START (Sr) conditions instead of a STOP condition (P)
in order to maintain control of the bus. In general, a
REPEATED START (Sr) command is functionally equivalent to a regular START condition (S).
When a STOP condition (P) or incorrect address is
detected, the MAX77801 internally disconnects SCL from
I2C serial interface until the next START condition (S),
minimizing digital noise and feedthrough.
Acknowledge
Both the I2C bus master and the MAX77801 (slave)
generate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each 9-bit data packet.
To generate an ACKNOWLEDGE (A), the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep
it low during the high portion of the clock pulse. To generate a NOT-ACKNOWLEDGE (nA), the receiving device
allows SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse and leaves it high during
the high portion of the clock pulse.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
Slave Address
The I2C slave address of the MAX77801 is shown in
Table 6.
Clock Stretching
In general, the clock signal generation for the I2C bus is
the responsibility of the master device. I2C specification
allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The MAX77801 does not use any form of clock
stretching to hold down the clock line.
General Call Address
The MAX77801 does not implement the I2C specification “General Call Address.” If the MAX77801 detects a
general call address (00000000b), it does not issue an
ACKNOWLEDGE (A).
Communication Speed
The MAX77801 supports the following I2C revision
3.0-compatible communication speeds:
• 0Hz to 100kHz (standard mode)
• 0Hz to 400kHz (fast mode)
• 0Hz to 1MHz (fast mode plus)
• 0Hz to 3.4MHz (high-speed mode)
Operating in standard mode, fast mode, and fast mode
plus does not require any special protocols. The main
consideration when changing the bus speed through
this range is the combination of the bus capacitance and
pullup resistors. Higher time constants created by the bus
capacitance and pullup resistance (C x R) slow the bus
operation. Therefore, when increasing bus speeds, the
pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing
section of I2C revision 3.0 specification for detailed guidance on the pullup resistor selection. In general, for bus
capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup resistors, a 400kHz bus needs about a 1.5kΩ pullup
resistors, and a 1MHz bus needs 680Ω pullup resistors.
Note that the pullup resistor is dissipating power when the
open-drain bus is low. The lower the value of the pullup
resistor, the higher the power dissipation (V2/R).
Table 6. I2C Slave Address
SLAVE ADDRESS (7 BIT)
SLAVE ADDRESS (WRITE)
SLAVE ADDRESS (READ)
0x18 (001 1000)
0x30 (0011 0000)
0x31 (0011 0001)
S
SDA
0
0
1
1
0
0
0
R/W
A
ACKNOWLEDGE
SCL
1
2
3
4
5
6
7
8
9
Figure 12. Slave Address Byte Example
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Analog Devices │ 20
MAX77801
Operating in high-speed mode requires some special considerations. For the full list of considerations, refer to the
I2C revision 3.0 specification. The major considerations
with respect to the MAX77801 are:
●
The master device shall use current source pullups
to shorten the signal rise times.
●
The slave device must use a different set of input
filters on its SDA and SCL lines to accommodate for
the higher bus speed.
●
The communication protocols need to utilize the
high-speed master code.
At power-up and after each STOP condition (P), the
MAX77801 input filters are set for standard mode, fast
mode, or fast mode plus (i.e., 0Hz to 1MHz). To switch
the input filters for high-speed mode, use the protocol
described in the Engaging in High-Speed Mode section.
Communication Protocols
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
7. The slave acknowledges the data byte. At the rising
edge of SCL, the data byte is loaded into its target
register and the data becomes active.
8. The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a STOP
condition (P) ensures that the bus input filters are set
for 1MHz or slower operation. Issuing a REPEATED
START condition (Sr) leaves the bus input filters in
their current state.
Writing to Sequential Registers
Figure 14 shows the protocol for writing to sequential registers. This protocol is similar to the “Write Byte” protocol,
except the master continues to write after the slave device
receives the first byte of data. When the master is done
writing, it issues a STOP condition (P) or a REPEATED
START condition (Sr).
The “Writing to Sequential Registers” protocol is as follows:
The MAX77801 supports both writing and reading from its
registers. The following sections show the I2C communication protocols available.
1. The master sends a START condition (S).
Writing to a Single Register
3. The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
Figure 13 shows the protocol for writing to a single register. This protocol is the same as SMBus specification’s
“Write Byte” protocol.
The “Write Byte” protocol is as follows:
1. The master sends a START condition (S).
2. The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
3. The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
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2. The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
7. The slave acknowledges the data byte. At the rising
edge of SCL, the data byte is loaded into its target
register and the data becomes active.
8. Steps 6 to 7 are repeated as many times as the master
requires. During the last acknowledge related clock
pulse, the slave issues an ACKNOWLEDGE (A).
9. The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a STOP
condition (P) ensures that the bus input filters are set
for 1MHz or slower operation. Issuing a REPEATED
START condition (Sr) leaves the bus input filters in
their current state.
Analog Devices │ 21
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
* P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE.
Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE.
1
7
1 1
8
1
8
1
1
S
SLAVE ADDRESS
0 A
REGISTER POINTER
A
DATA
A
P or Sr *
R/W
NUMBER
OF BITS
THE DATA IS LOADED INTO
THE TARGET REGISTER
AND BECOMES ACTIVE
DURING THIS RISING EDGE.
SDA
B1
B0
A
ACKNOWLEDGE
SCL
7
8
9
Figure 13. Writing to a Single Register
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
1
7
S
SLAVE ADDRESS
*P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz
MODE. Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE.
1 1
8
1
8
1
0 A
REGISTER POINTER X
A
DATA 1
A
8
1
8
1
DATA 2
A
DATA 3
A
R/W
α
REGISTER POINTER
=X+1
SDA
NUMBER
OF BITS
B1
α
REGISTER POINTER
=X+2
NUMBER
OF BITS
α
8
1
8
1
1
DATA N-1
A
DATA N
A
P or Sr*
REGISTER POINTER
= X + (N - 2)
α
REGISTER POINTER
= X + (N - 1)
B0
A
NUMBER
OF BITS
β
THE DATA IS LOADED INTO
THE TARGET REGISTER AND
BECOMES ACTIVE DURING
THIS RISING EDGE.
B9
ACKNOWLEDGE
SCL
SDA
7
B1
8
B0
9
1
DETAIL: α
THE DATA IS LOADED INTO
THE TARGET REGISTER AND
BECOMES ACTIVE DURING
THIS RISING EDGE.
A
ACKNOWLEDGE
SCL
7
8
9
DETAIL: β
Figure 14. Writing to Sequential Registers
www.analog.com
Analog Devices │ 22
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Reading from a Single Register
7. The master sends the 7-bit slave address followed by
a read bit (R/W = 1).
Figure 15 shows the protocol for reading from a single
register. This protocol is the same as SMBus specification’s “Read Byte” protocol.
8. The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
The “Read Byte” protocol is as follows:
9. The addressed slave places 8 bits of data on the bus
from the location specified by the register pointer.
1. The master sends a START condition (S).
10. The master issues a NOT-ACKNOWLEDGE (nA).
2. The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
11. The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a STOP
condition (P) ensures that the bus input filters are set
for 1MHz or slower operation. Issuing a REPEATED
START condition (Sr) leaves the bus input filters in
their current state.
3. The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a REPEATED START condition (Sr).
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
*P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE.
Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE.
1
7
1 1
8
1 1
7
1 1
8
S
SLAVE ADDRESS
0 A
REGISTER POINTER
A Sr
SLAVE ADDRESS
1 A
DATA
R/W
1
1
nA P or Sr*
NUMBER
OF BITS
R/W
Figure 15. Reading from a Single Register
www.analog.com
Analog Devices │ 23
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Reading from Sequential Registers
7. The master sends the 7-bit slave address followed by
a read bit (R/W = 1).
Figure 16 shows the protocol for reading from sequential registers. This protocol is similar to the “Read Byte”
protocol, except the master issues an ACKNOWLEDGE
(A) to signal the slave that it wants more data. When
the master has all the data it requires, it issues a NOTACKNOWLEDGE (nA) and a STOP condition (P) to end
the transmission.
8. The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
9. The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
10. The master issues an ACKNOWLEDGE (A) signaling
the slave that it wishes to receive more data.
The “Continuous Read from Sequential Registers” protocol
is as follows:
11. Steps 9 to 10 are repeated as many times as the
master requires. Following the last byte of data, the
master must issue a NOT-ACKNOWLEDGE (nA) to
signal that it wishes to stop receiving data.
1. The master sends a START condition (S).
2. The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
12. The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a STOP
condition (P) ensures that the bus input filters are set
for 1MHz or slower operation. Issuing a REPEATED
START condition (Sr) leaves the bus input filters in
their current state.
3. The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a REPEATED START condition (Sr).
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
*P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE.
Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE.
1
7
1 1
8
1 1
7
1 1
8
1
S
SLAVE ADDRESS
0 A
REGISTER POINTER X
A Sr
SLAVE ADDRESS
1 A
DATA 1
A
R/W
NUMBER
OF BITS
R/W
8
1
8
1
8
1
DATA 2
A
DATA 3
A
DATA 4
A
REGISTER POINTER
=X+1
REGISTER POINTER
=X+2
REGISTER POINTER
=X+3
8
1
8
1
8
DATA N-2
A
DATA N-1
A
DATA N
REGISTER POINTER
= X + (N - 3)
REGISTER POINTER
= X + (N - 2)
NUMBER
OF BITS
1
1
nA P or Sr*
NUMBER
OF BITS
REGISTER POINTER
= X + (N - 1)
Figure 16. Reading Continuously from Sequential Registers
www.analog.com
Analog Devices │ 24
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Engaging in High-Speed Mode
Figure 17 shows the protocol for engaging in high-speed
mode operation, which allows the bus to operate at speed
up to 3.4MHz.
The “Engage in High-Speed Mode” protocol is as follows:
1. Begin the protocol while operating at a bus speed of
1MHz or lower
2. The master sends a START condition (S).
3. The master sends the 8-bit master code of 0000 1xxx
where “xxx” are don’t care bits.
4. The addressed slave issues a NOT-ACKNOWLEDGE
(nA).
5. The master can now increase its bus speed up to
3.4MHz and issue any read/write operation.
The master may continue to issue high-speed read/write
operations until a STOP condition (P) is issued. Issuing a
STOP condition (P) ensures that the bus input filters are
set for 1MHz or slower operation.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
1
8
1 1
S
HS MASTER CODE
nA Sr
1
ANY READ/WRITE PROTOCOL
FOLLOWED BY Sr
FAST MODE
Sr
1
ANY READ/WRITE PROTOCOL
FOLLOWED BY Sr
HS MODE
Sr
1
ANY READ/WRITE PROTOCOL
P
FAST MODE
Figure 17. Engaging in High-Speed Mode
www.analog.com
Analog Devices │ 25
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Register Map
Register Reset Conditions
Registers reset to their default values when either of the following conditions become true:
●
Undervoltage Lockout (VSYS < VUVLO_F)
●
Device Disabled (EN pin = logic low)
MAX77801 Registers
I2C Device Address: 0x18 (7-bit)
ADDRESS
NAME
ACCESS
0x00
DEVICE_ID
R
MSB
LSB RESET
0x01
STATUS
R
0x02
CONFIG1
R/W
RESERVED RESERVED RU_SR
0x03
CONFIG2
R/W
RESERVED
0x04
VOUT_DVS_L
R/W
RESERVED
VOUT_DVS_L[6:0]
0x38
0x05
VOUT_DVS_H
R/W
RESERVED
VOUT_DVS_H[6:0]
varies
RESERVED
RESERVED
EN
RD_SR
̶
TSHDN POKn
OVP
OVP_TH[1:0]
AD
FPWM 0x0E
RESERVED
0x70
EN_PD POK_POL
OCP
0x00
Register Details
DEVICE ID (0x00)
BIT
7
6
5
4
3
FIELD
RESERVED[7:0]
RESET
̶
ACCESS
Read Only
BIT FIELD
RESERVED
www.analog.com
BITS
7:0
DESCRIPTION
Reserved. Bits for internal use only.
2
1
0
DECODE
N/A
Analog Devices │ 26
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
STATUS (0x01)
BIT
3
2
1
0
FIELD
7
RESERVED[7:4]
TSHDN
POKn
OVP
OCP
RESET
0b0000
0b0
0b0
0b0
0b0
ACCESS
Read Only
Read Only
Read Only
Read Only
Read Only
BIT FIELD
6
BITS
RESERVED
5
4
DESCRIPTION
7:4
DECODE
Reserved. Reads are don’t care.
N/A
TSHDN
3
Thermal Shutdown Status
0 = Junction temperature OK (TJ < TSHDN)
1 = Thermal shutdown (TJ ≥ TSHDN)
POKn
2
Power-OK Status
0 = Output OK (VOUT > 80% of target)
1 = Output not OK (VOUT < 75% of target) or disabled.
OVP
1
Output Overvoltage Status
0 = Output OK (VOUT the OVP threshold set
by OVP_TH[1:0].
OCP
0
Overcurrent Status
0 = Current OK
1 = Overcurrent
CONFIG1 (0x02)
BIT
7
6
5
4
3
2
1
0
FIELD
RESERVED
RU_SR
RD_SR
OVP_TH[1:0]
AD
FPWM
RESET
0b00
0b0
0b0
0b11
0b1
0b0
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
ACCESS
BIT FIELD
RESERVED
RU_SR
RD_SR
OVP_TH[1:0]
BITS
7:6
DESCRIPTION
DECODE
Reserved. Bits are don’t care.
N/A
5
VOUT Rising Ramp Rate Control. VOUT increases with this slope whenever the output
voltage target is modified upwards while the
converter is enabled.
0 = +12.5mV/µs
1 = +25mV/µs
4
VOUT Falling Ramp Rate Control.
VOUT decreases with this slope whenever
the output voltage target is modified downwards while the converter is enabled.
0 = -3.125mV/µs
1 = -6.25mV/µs
VOUT Overvoltage Protection (OVP)
Threshold Control
00 = No OVP (protection disabled)
01 = 110% of VOUT target
10 = 115% of VOUT target
11 = 120% of VOUT target
3:2
AD
1
Output Active Discharge Resistor Enable
0 = Disabled
1 = Enabled
FPWM
0
Converter Mode Control
0 = SKIP Mode
1 = Forced PWM (FPWM) mode
www.analog.com
Analog Devices │ 27
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
CONFIG2 (0x03)
BIT
7
6
5
4
FIELD
RESERVED
EN
EN_PD
POK_POL
RESERVED
RESET
0b0
0b1
0b1
0b1
0b0000
ACCESS
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
BIT FIELD
BITS
RESERVED
7
3
2
1
DESCRIPTION
DECODE
Reserved. Bit is a don’t care.
N/A
EN
6
Buck-boost Output Software Enable
Control. See Table 1.
While EN (pin) = logic low:
0 or 1 = Output disabled
While EN (pin) = logic high:
0 = Output disabled
1 = Output enabled
PD
5
EN Pin Input Pulldown Resistor Enable
Control
0 = Pulldown disabled
1 = Pulldown enabled
POK_POL
4
Power-OK (POK) Output Pin Polarity
Control
0 = Active-low
1 = Active-high
Reserved. Bits are don’t care.
N/A
RESERVED
3:0
0
VOUT_DVS_L (0x04)
BIT
FIELD
7
6
5
4
RESERVED
RESET
ACCESS
0b0
RESERVED
VOUT_DVS_L
www.analog.com
0b0
0b1
Read, Write
BIT FIELD
3
2
1
0
0b0
0b0
0b0
VOUT_DVS_L[6:0]
0b1
0b1
Read, Write
BITS
7
6:0
DESCRIPTION
DECODE
Reserved. Bit is a don’t care.
N/A
Output Voltage Control (DVS Logic Low).
Sets the VOUT target when DVS pin is
logic low. Configurable in 12.5mV per LSB
from 0x00 (2.60V) to 0x7F (4.1875V).
The default value of this register is preset. See the Ordering Information table.
Overwriting the default value sets a new
target output voltage.
0x00 = 2.60V
0x01 = 2.6125V
0x02 = 2.6250V
…
0x38 = 3.30V
…
0x40 = 3.40V
…
0x7E = 4.1750V
0x7F = 4.1875V
Analog Devices │ 28
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
VOUT_DVS_H (0x05)
BIT
FIELD
RESET (WLP)
RESET (TQFN)
ACCESS
BIT FIELD
RESERVED
VOUT_DVS_H
www.analog.com
7
6
5
4
RESERVED
3
0b0
0b1
0b0
0b0
0b0
0b1
0b0
0b1
Read, Write
BITS
7
6:0
2
1
0
0b0
0b0
0b0
0b0
0b1
0b1
0b0
0b0
VOUT_DVS_H[6:0]
Read, Write
DESCRIPTION
DECODE
Reserved. Bit is a don’t care.
N/A
Output Voltage Control (DVS Logic High).
Sets the VOUT target when DVS pin is
logic high. Configurable in 12.5mV per
LSB from 0x00 (2.60V) to 0x7F (4.1875V).
The default value of this register is preset. See the Ordering Information table.
Overwriting the default value sets a new
target output voltage.
0x00 = 2.60V
0x01 = 2.6125V
0x02 = 2.6250V
…
0x40 = 3.40V
…
0x5C = 3.75V
…
0x7E = 4.1750V
0x7F = 4.1875V
Analog Devices │ 29
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Ordering Information
Package Information
DEFAULT
V OUT
PIN-PACKAGE
MAX77801EWP+T
3.3V/3.4V
20 WLP
MAX77801ETP+T
3.3V/3.75V
20 TQFN
PART
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
www.analog.com
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 WLP
W201F2+1
21-0771
Refer to Application
Note 1891
20 TQFN
T2044-3C
21-0139
90-0037
Analog Devices │ 30
MAX77801
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Revision History
REVISION
NUMBER
REVISION
DATE
0
2/15
Initial release
1
4/17
Added MAX77801ETP TQFN package information, updated Benefits and Features
section, updated Communication Protocals sections, updated Figures 10─12,
updated tables for Package Thermal Characteristics, Buck-Boost Electrical
Characteristics, Register Map, VOUT_DVS_H, Ordering Information, and Package
Information
2
2/18
Corrected a typo in Figure 5
11
3
3/18
Added MAX77801ETP default VOUT to Electrical Characteristics table
2
10/19
Updated front page, Typical Operating Characteristics, Bump/Pin Configuration,
Detailed Description, Applications Information, PCB Layout Guidelines, Figures 1-8,
Register Map, Ordering Information table, deleted original Note 1 and renumbered
remaining Notes
5
11/19
Replaced Typical Application Circuit Figure, updated Absolute Maximum Ratings,
updated EC Globals, Buck-Boost Electrical Characteristics table and I2C Electrical
Characteristics table, updated Note 2, updated sub title for Typical Operating
1–10, 12, 17, 18
Characteristics, updated Bump/Pin Configurations figure and Bump/Pin Description
table, updated Figure 2, replaced OUTS with FB in the PCB Layout Guideline section,
updated Figures 6 and 8
6
7/22
Updated Register Map
1/23
Updated General Description, Benefits and Features, Absolute Maximum Ratings,
Buck-Boost Electrical Characteristics, Pin Configuration, Pin Description, Enable
Control (EN), Table 1, Dynamic Voltage Scaling (DVS), Figure 5, Output Voltage
Selection and Slew-Rate Control, Output Overvoltage Protection (OVP), Thermal
Shutdown, I2C Serial Interface, Input Capacitor Selection, Output Capacitor Selection,
PCB Layout Guidelines, Table 5, System Configuration, START and STOP Conditions,
Acknowledge, Slave Address, General Call Address, Communication Speed, Table 6,
Communication Protocols, Writing to a Single Register, Writing to Sequential Registers,
Figures 13, 14, and 15, Reading from a Single Register, Reading from Sequential
Registers, Figure 16, Engaging in High-Speed Mode, Figure 17, Register Map
4
7
PAGES
CHANGED
DESCRIPTION
—
1–3, 8,
14–19,
23, 24
1–3, 7–11,
19–24
26–28
1, 2, 4, 10,
12-17, 19-29
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use.Specifications subject to change without notice. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the
property of their respective owners.
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Analog Devices │ 31
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