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MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
General Description
The MAX77816 is a high-current, high-efficiency
buck-boost regulator targeting single-cell Li-ion batterypowered applications. It supports a wide output voltage
range from 2.60V to 5.14V. The IC allows 5A (typ) maximum switch current. In buck mode, the output current can
go as high as 4A, and in boost mode, the maximum output current can be 3A. A unique control algorithm allows
high efficiency, outstanding line/load transient response,
and seamless transition between buck and boost modes.
The IC features an I2C-compatible serial interface. The
I2C interface allows the output voltage to be dynamically
adjusted, thus enabling finer control of system power consumption. The I2C interface also provides features such
as enable control and device status monitoring.
The multifunction GPIO pin is register settable to 5
different options, such as FPWM mode enable and inductor peak current level selection. These options provide
design flexibility that allows the IC to cover a wide range
of applications and use cases.
Applications
●●
●●
●●
●●
●●
Smartphones and Tablets
Wearable Devices
Wireless Communication Devices
RF Power Amplifiers
Battery-Powered Applications
Benefits and Features
●● Buck and Boost Operation Including Seamless
Transition between Buck and Boost Modes
• 2.3V to 5.5V VIN Range
• 2.60V to 5.14V VOUT with 20mV Step
• 3A Minimum Continuous Output Current
(VINBB ≥ 3.0V, VOUTBB = 3.3V)
• Burst Current: 3.6A Minimum Output Current for
800µs (VINBB ≥ 3.0V, VOUTBB = 3.3V)
●● I2C Serial Interface Allows Dynamic VOUT
Adjustment and Provides Design Flexibility
●● 97.5% Peak Efficiency
●● 40µA Quiescent Current
●● Safety Features Enhance Device and System
Reliability
• Soft-Start
• True Shutdown™
• Thermal Shutdown and Short-Circuit Protection
●● Multifunction GPIO Pin
• MAX77816A/F: FPWM Mode Enable
• MAX77816B: Inductor Peak Current-Limit selection
• MAX77816C: Output Voltage Selection
• MAX77816D: Power-OK indicator
• MAX77816E: Interrupt Indicator
●● Small Size: 1.827mm x 2.127mm, 20-Bump WLP,
0.4mm Pitch
Typical Application Circuit
1µH
V IN
10µF
LXBB 2
INBB
OUTBB
SYS
FB_BB
1µF
1.8V
1.5kΩ
LXBB 1
MAX77816
PGNDBB
EN
1.5kΩ
SDA
GPIO
SCL
GND
Ordering Information appears at end of data sheet.
True Shutdown is a trademark of Maxim Integrated Products, Inc.
19-100055; Rev 4; 7/20
V OUT
47µF
REQUIRED WHEN
GPIO IS CONFIGURED
AS OUTPUT
1.8V
100kΩ
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Absolute Maximum Ratings
SYS to GND..........................................................-0.3V to +6.0V
INBB, OUTBB to PGNDBB...................................-0.3V to +6.0V
PGNDBB to GND..................................................-0.3V to +0.3V
SCL, SDA to GND................................... -0.3V to (VSYS + 0.3V)
EN, GPIO to GND................................... -0.3V to (VSYS + 0.3V)
FB_BB to GND....................................-0.3V to (VOUTBB + 0.3V)
LXBB1 to PGNDBB................................ -0.3V to (VINBB + 0.3V)
LXBB2 to PGNDBB.............................-0.3V to (VOUTBB + 0.3V)
LXBB to PGND (Pulsed < 5ns Voltage)..................-2.4V to 8.0V
LXBB1/LXBB2 Continuous RMS Current (Note 1)...............4.8A
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Continuous Power Dissipation at TA = +70°C
(Derate 23.8mW/°C above +70°C) ............................1905mW
Note 1: LXBB1/LXBB2 node has internal clamp diodes to PGNDBB and INBB. Applications that give forward bias to these diodes
should ensure that the total power loss does not exceed the power dissipation limit of IC package.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 2)
Junction-to-Ambient Thermal Resistance (θJA)..........55.49°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VSYS = VINBB = +3.8V, VFB_BB = VOUTBB = +3.3V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
GENERAL
Input Voltage Range
Shutdown Supply Current
Input Supply Current
Active Discharge Resistance
Thermal Shutdown
VINBB
2.3
ISHDN_25C
EN = low, TA = +25°C
1
ISHDN_85C
EN = low, TA = +85°C (Note 5)
1
IQ_SKIP
SKIP mode, no switching
40
IQ_PWM
FPWM mode, no load
6
mA
100
Ω
+165
°C
RDISCHG
TSHDN
Rising, 20°C hysteresis
VOUT
I2C programmable (20mV step)
60
µA
µA
H-BRIDGE
Output Voltage Range
Default Output Voltage
Output Voltage Accuracy
2.60
5.14
MAX77816A only, VOUT [6:0] = 0x28
3.4
MAX77816B/C/D/E/F, VOUT [6:0] = 0x23
3.3
V
V
VOUT_ACC1
PWM mode, no load
-1.0
+1.0
VOUT_ACC2
SKIP mode, no load, TA = +25°C
-1.0
+4.5
%
Line Regulation
VINBB = 2.3V to 5.5V
0.200
%/V
Load Regulation
(Note 4)
0.125
%/A
50
mV
Line Transient Response
www.maximintegrated.com
VOS1
VUS1
IOUT = 1.5A, VINB changes from 3.4V
to 2.9V in 25µs (20mV/µs), L = 1µH,
COUT_NOM = 47µF (Note 4)
Maxim Integrated │ 2
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Electrical Characteristics (continued)
(VSYS = VINBB = +3.8V, VFB_BB = VOUTBB = +3.3V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IOUT changes from 10mA to 1.5A in
15µs, L = 1µH, COUT_NOM = 47µF
(Note 4)
50
Output Voltage Ramp-Up
Slew Rate
BB_RU_SR = 0 (Note 6)
20
BB_RU_SR = 1 (Note 6)
40
Output Voltage Ramp-down
Slew Rate
BB_RD_SR = 0 (Note 6)
5
BB_RD_SR = 1 (Note 6)
10
IOUT = 100mA (Note 4)
95
%
97.5
%
Load Transient Response
Typical Load Efficiency
Peak Efficiency
VOS2
VUS2
ηIOUT_TYP
ηPK
(Note 4)
ILIM[1:0] = 11b or
GPIO_CFG[2:0] = 010b, GPIO = high
LXBB1/2 Current Limit
ILIM_LXBB
4
5
ILIM[1:0] = 10b
3.1
ILIM[1:0] = 01b or
GPIO_CFG[2:0] = 010b, GPIO = low
1.80
ILIM[1:0] = 00b
1.15
mV
mV/µs
mV/µs
5.8
A
High-Side PMOS ON
Resistance
RDSON(PMOS)
ILXBB = 100mA per switch
34
mΩ
Low-Side NMOS ON
Resistance
RDSON(NMOS)
ILXBB = 100mA per switch
45
mΩ
Switching Frequency
fSW
Turn-On Delay Time
tON_DLY
Soft-Start Time
Minimum Effective Output
Capacitance
LXBB1, LXBB2 Leakage
Current
SYS Undervoltage Lockout
Threshold
www.maximintegrated.com
PWM mode, TA = +25°C
2.25
2.50
From EN asserting to LXBB switching
(Note 6)
100
IOUT = 10mA, ILIM[1:0] = 11b or 10,
or GPIO_CFG[2:0] = 010b,
GPIO = high (Note 4)
120
IOUT = 10mA, ILIM[1:0] = 01b or 00,
or GPIO_CFG[2:0] = 010b, GPIO = low
(Note 4)
800
0A < IOUT < 3000mA
16
ILK_25
VLXBB1/2 = 0V or 5.5V, VOUTBB = 5.5V,
VSYS = VINBB = 5.5V, TA = +25°C
0.1
ILK_85
VLXBB1/2 = 0V or 5.5V, VOUTBB = 5.5V,
VSYS = VINBB = 5.5V, TA = +85°C
(Note 5)
0.2
tSS
CEFF(MIN)
VUVLO_R
VSYS rising
VUVLO_F
VSYS falling
2.75
MHz
µs
µs
µF
1
µA
2.375
2.50
2.05
2.625
V
Maxim Integrated │ 3
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Electrical Characteristics (continued)
(VSYS = VINBB = +3.8V, VFB_BB = VOUTBB = +3.3V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.4
V
ENABLE INPUT (EN)
EN Logic-Low Threshold
VEN_L
VSYS ≤ 5.5V, TA = +25°C
EN Logic-High Threshold
VEN_H
VSYS ≤ 5.5V, TA = +25°C
1.2
REN
Pulldown resistor to GND
400
EN Internal Pulldown
Resistance
V
800
1600
kΩ
0.4
V
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
Input Logic-Low Threshold
VGPI_L
GPIO[2:0] = 001b or 010b or 011b,
VSYS ≤ 4.5V, TA = +25°C
Input Logic-High Threshold
VGPI_H
GPIO[2:0] = 001b or 010b or 011b,
VSYS ≤ 4.5V, TA = +25°C
1.2
REN
GPIO[2:0] = 001b or 010b or 011b,
Pulldown resistor to GND
400
Input Internal Pulldown
Resistance
Output Low Voltage
Output Leakage Current
VGPO_L
V
800
GPIO[2:0] = 100b or 101b, ISINK = 1mA
IGPO_25C
GPIO[2:0]=100b or 101b, TA = +25°C
IGPO_85C
GPIO[2:0] = 100b or 101b, TA = +85°C
(Note 5)
0.1
VPOK_R
GPIO[2:0] = 100b, VOUTBB rising,
expressed as a percentage of VOUTBB
92.5
VPOK_F
GPIO[2:0] = 100b, VOUTBB falling,
expressed as a percentage of VOUTBB
90
POK Threshould
-1
1600
V
0.4
V
+1
µA
%
I2C-COMPATIBLE INTERFACE─I/O STAGE
SCL, SDA Input High Voltage
VIH
SCL, SDA Input Low Voltage
VIL
SCL, SDA Input Hysteresis
VHYS
SCL, SDA Input Current
II
SDA Output Low Voltage
VOL
SCL, SDA Input Capacitance
CI
Maximum Pulse Width
of Spikes that must be
suppressed by the input filter
tSP
www.maximintegrated.com
1.4
(Note 5)
V
V
+10
µA
0.4
V
10
pF
0.1
-10
ISINK = 3mA
(Note 5)
0.4
50
V
ns
Maxim Integrated │ 4
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Electrical Characteristics (continued)
(VSYS = VINBB = +3.8V, VFB_BB = VOUTBB = +3.3V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.)
(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I2C-COMPATIBLE INTERFACE─TIMING (Note 5)
Clock Frequency
Hold Time (REPEATED)
START Condition
fSCL
1
MHz
tHD_STA
0.26
µs
SCL Low Period
tLOW
0.5
µs
SCL High Period
tHIGH
0.26
µs
Setup Time REPEATED
START Condition
tSU_STA
0.26
µs
DATA Hold Time
tHD_DAT
0
µs
DATA Setup Time
tSU_DAT
50
ns
Setup Time for STOP
Condition
tSU_STO
0.26
µs
Bus-Free Time Between
STOP and START
tBUF
0.5
µs
Capacitive Load for Each
Bus Line
CB
550
pF
Note 3: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through
correlation using statistical quality control methods.
Note 4: Guaranteed by design. Not production tested.
Note 5: Guaranteed by ATE characterization. Not directly tested in production.
Note 6: Guaranteed by design. Production tested through scan.
www.maximintegrated.com
Maxim Integrated │ 5
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Typical Operating Characteristics
(VSYS = VINBB = +3.8V , VFB_BB = VOUTBB = +3.3V, TA = +25°C.)
QUIESCENT CURRENT vs.
SUPPLY VOLTAGE
70
toc01
2.0
EFFICIENCY vs. LOAD
2.8V OUTPUT
100
VOUT = 2.8V
VOUT = 3.3V
55
VOUT = 5V
50
45
40
35
2
3
4
5
6
80
TA = +85°C
1.0
0.5
TA = +25°C
0.0
-0.5
SUPPLY VOLTAGE (V)
toc03
3
4
5
30
VIN = 3.8V (FPWM = 1)
0
0.001
6
0.01
0.1
1
LOAD (A)
toc04
EFFICIENCY vs. LOAD
5V OUTPUT
100
80
VIN = 3V
VIN = 3.3V
VIN = 3.8V
VIN = 4.5V
70
60
50
EFFICIENCY (%)
EFFICIENCY (%)
40
toc05
90
80
40
30
VIN = 3.8V (FPWM = 1)
20
VIN = 3V
VIN = 3.8V
VIN = 4.5V
70
60
50
40
30
VIN = 3.8V (FPWM = 1)
20
10
10
0
0.001
0.01
0.1
0
0.001
1
0.01
LOAD REGULATION
2.8V OUTPUT
2.89
0.1
1
LOAD (A)
LOAD (A)
toc06
LOAD REGULATION
3.3V OUTPUT
3.40
2.88
toc07
3.38
2.87
2.86
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
50
10
90
2.85
2.84
VIN = 3V
VIN = 3.8V
VIN = 4.5V
2.83
2.82
2.81
3.36
3.34
VIN = 3V
VIN = 3.3V
VIN = 3.8V
3.32
VIN = 4.5V
3.30
2.80
2.79
60
20
TA = -40°C
2
VIN = 3V
VIN = 3.8V
VIN = 4.5V
70
SUPPLY VOLTAGE (V)
EFFICIENCY vs. LOAD
3.3V OUTPUT
100
1.5
EFFICIENCY (%)
60
SHUTDOWN CURRENT (µA)
QUIESCENT CURRENT (µA)
toc02
90
65
30
SHUTDOWN CURRENT vs.
SUPPLY VOLTAGE
0
1
2
LOAD (A)
www.maximintegrated.com
3
3.28
0
1
2
3
LOAD (A)
Maxim Integrated │ 6
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Typical Operating Characteristics (continued)
(VSYS = VINBB = +3.8V , VFB_BB = VOUTBB = +3.3V, TA = +25°C.)
5.20
toc08
2.83
2.82
5.10
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
5.15
VIN = 3V
VIN = 3.8V
VIN = 4.5V
5.05
5.00
4.95
LINE REGULATION
2.8V OUTPUT
toc09
3.36
IOUT = 500mA
IOUT = 1A
IOUT = 2A
2.81
2.80
2.79
2.78
0
1
2
2.77
3
LOAD (A)
2.5
3.5
4.5
3.28
3.26
2.5
3.5
5.0
VOUT = 2.8V
VOUT = 3.3V
4.0
IOUT = 500mA
IOUT = 1A
4.96
IOUT = 2A
3.5
3.0
VOUT = 5V
2.5
2.0
1.5
1.0
4.94
0.5
2.5
3.5
4.5
0.0
5.5
ILIM = HIGH
2
3
SUPPLY VOLTAGE (V)
STARTUP WAVEFORM
3.3V OUTPUT
5
LOAD TRANSIENT RESPONSE
2.8V OUTPUT
toc13
2V/div
EN = 1
4
6
SUPPLY VOLTAGE (V)
toc14
1A
2V/div
VEN
5.5
MAXIMUM OUTPUT CURRENT vs.
SUPPLY VOLTAGE
toc12
4.5
4.98
4.5
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
3.30
3.22
5.5
5.02
4.92
3.32
3.24
toc11
5.00
toc10
IOUT = 500mA
IOUT = 1A
IOUT = 2A
3.34
SUPPLY VOLTAGE (V)
LINE REGULATION
5V OUTPUT
5.04
LINE REGULATION
3.3V OUTPUT
3.38
OUTPUT VOLTAGE (V)
LOAD REGULATION
5V OUTPUT
500mA/div
IOUT
10mA
VOUT
5V/div
VLX
VOUT
IIN
100mV/div
2A/div
SLEW RATE = 0.99A/15µs
VIN = 3.8V
40µs/div
www.maximintegrated.com
100µs/div
Maxim Integrated │ 7
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Typical Operating Characteristics (continued)
(VSYS = VINBB = +3.8V , VFB_BB = VOUTBB = +3.3V, TA = +25°C.)
LOAD TRANSIENT RESPONSE
3.3V OUTPUT
LOAD TRANSIENT RESPONSE
5V OUTPUT
toc15
1A
LINE TRANSIENT RESPONSE
2.8V OUTPUT
toc16
3.4V
500mA/div
IOUT
500mA/div
IOUT
10mA
10mA
VOUT
VIN
VOUT
100mV/div
toc17
IOUT = 1A
1A
2.9V
500mV/div
100mV/div
VOUT
SLEW RATE = 0.99A/15µs
SLEW RATE = 20mV/µs
SLEW RATE = 0.99A/15µs
100µs/div
100µs/div
100µs/div
LINE TRANSIENT RESPONSE
5V OUTPUT
BOOST-TO-BUCK
LINE TRANSIENT RESPONSE
toc18
IOUT = 1A
IOUT = 1A
VOUT = 3.3V
3.4V
VIN
50mV/div
2.9V
500mV/div
VOUT
50mV/div
VIN
toc19
3.4V
2.9V
500mV/div
VOUT
50mV/div
SLEW RATE = 20mV/µs
SLEW RATE = 20mV/µs
100µs/div
100µs/div
SWITCHING WAVEFORM
3.3V OUTPUT
OUTPUT RIPPLE IN SKIP MODE
3.3V OUTPUT (IOUT = 100mA)
toc20
toc21
IOUT = 100mA
IOUT = 1A
1V/div
VLX
20mV/div
VOUT
FSW = 2.5MHz
200ns/div
www.maximintegrated.com
5µs/div
Maxim Integrated │ 8
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Bump Configuration
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
A
SYS
EN
GND
SDA
SCL
B
FB_BB
LXBB2
GPIO
LXBB1
INBB
C
OUTBB
LXBB2
PGNDBB
LXBB1
INBB
D
OUTBB
LXBB2
PGNDBB
LXBB1
INBB
+
20-BUMP WLP
(2.13mm x 1.83mm, 0.4mm PITCH)
Bump Description
BUMP
NAME
A1
SYS
A2
EN
A3
GND
Quite Ground. Star-ground connection to system GND.
A4
SDA
I2C Data I/O (Hi-Z in OFF State). This pin requires a pullup resistor to I2C power supply.
Connect to GND if not used.
A5
SCL
I2C Clock Input (Hi-Z in OFF State). This pin requires a pullup resistor to I2C power supply.
Connect to GND if not used.
B1
FB_BB
Buck-Boost Output Voltage Feedback
B2, C2, D2
LXBB2
Buck-Boost Switching Node 2
B3
GPIO
B4, C4, D4
LXBB1
B5, C5, D5
INBB
C1, D1
OUTBB
C3, D3
PGNDBB
www.maximintegrated.com
FUNCTION
System (Battery) Voltage Input. Bypass to GND with a 1µF capacitor.
Active-High, Buck-Boost External Enable Input. An 800kΩ internal pulldown resistance to the GND.
Multifunction GPIO:
MAX77816A/B/C/F: General Purpose Input. An 800kΩ internal pulldown resistance to the GND.
MAX77816D/E: Open-Drain Output. An external pullup resistor is required.
Buck-Boost Switching Node 1
Buck-Boost Input. Bypass to PGNDBB with a 10µF capacitor.
Buck-Boost Output
Buck-Boost Power Ground. Star-ground connection to system GND.
Maxim Integrated │ 9
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Detailed Description
Enable Control
When EN pin is set to high, the IC turns on the
internal bias circuitry, which takes typically 100µs
(tON_DLY) to be settled. As soon as the bias is ready, all
user registers are accessible through I2C. Write BB_EN
bit to 1 to enable (register default) buck-boost output
voltage regulation. The VOUTBB takes 800µs (tSS) to the
nominal regulated voltage after BB_EN’s setting.
When EN pin is pulled low, the IC goes into shutdown mode. This event also resets all type-O
registers to their POR default values.
Immediate Turn-Off Events
The following events initiate immediate turn-off.
●● Thermal protection (TJ > +165°C)
●● VSYS < SYS UVLO falling threshold (VUVLO_F)
●● Overcurrent protection
(ILIM is consistently hit for 3ms)
The events in this category disable buck-boost until the
hazardous conditions come back to normal conditions.
Inductor Peak Current Limit (ILIM)
The buck-boost regulator’s high-side MOSFETs peak
current limit (ILIM_LXBB) is register programmable.
Applications can use ILIM_LXBB programmability to ensure
that the regulator never exceeds the saturation current
rating of the inductor on the PCB. In MAX77816B, ILIM_
LXBB is GPIO pin programmable. See the Multifunction
GPIO Pin section.
Multifunction GPIO Pin
The IC has a general-purpose input and output (GPIO)
pin which can be configured as 5 different functions
through GPIO_CFG[2:0]. The default function of the GPIO
pin is listed below:
●● MAX77816A/MAX77816F: FPWM Mode Enable
When the GPIO pin is connected to GND, the buckboost regulator automatically transitions from SKIP
mode to fixed-frequency operation (PWM) as load
current increases. SKIP mode helps maximize the
Table 1. Enable Control Logic Truth Table
EN PIN
BB_EN BIT
OPERATING MODE
low
x
Device off
high
0
Disable output
high
1 (default)
Enable output
www.maximintegrated.com
buck-boost regulator’s efficiency at light load. When
the GPIO is connected to a voltage above VGPI_H,
forced PWM (FPWM) switching behavior is enabled.
The FPWM mode benefits applications where lowest
output ripple is required. The BB_FPWM bitfield is
ignored when GPIO_CFG[2:0] = 001b.
The MAX77816A has a 3.4V default output
voltage, and the MAX77816F has a 3.3V default output
voltage.
●● MAX77816B: Inductor Peak Current-Limit (ILIM)
Selection
The buck-boost regulator’s high-side MOSFETs peak
current limit (ILIM_LXBB) is GPIO pin programmable.
The ILIM[1:0] bitfield is ignored when GPIO_CFG[2:0]
= 010b. Connect GPIO to GND to set ILIM to 1.8A
(typ). Connect GPIO to a voltage above VGPI_H to
program ILIM to 5A (typ).
●● MAX77816C: Output Voltage Selection
The GPIO pin sets the output voltage dynamically
between VOUT[6:0] (GPIO = LOW) and VOUT_H[6:0]
(GPIO = HIGH). When EN pin is asserted, the status
of the GPIO pin is latched until completing soft-start
so that changes on the GPIO pin are ignored. After
soft-start is done, internal logic sets VOUTBB based
on the GPIO input.
●● MAX77816D: Power-OK (POK) Indicator
The device features an open-drain GPIO output to monitor the output voltage. The GPIO pin
requires an external pullup resistor. GPIO goes high
(high impedance) after the output increases above
92.5% (VPOK_R) of the nominal regulated voltage
(VOUT_REG). GPIO goes low when the regulator
output drops below 90% (VPOK_F) of VOUT_REG.
●● MAX77816E: Interrupts Indicator
The GPIO indicates the application processor that the
status of the device has changed.
INT[3:0], INT_MASK[3:0], and the GPIO pin work
together to present the buck-boost regulator’s abnormal status, including overvoltage, overcurrent, power
OK, and thermal shutdown. GPIO goes low when one
or more bits of INT[3:0] becomes 1, and the related
interrupts are not masked in INT_MASK[3:0]. GPIO
becomes high (cleared) as soon as the read action of
INT[3:0] starts.
Maxim Integrated │ 10
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Buck-Boost Regulator
OCP_INT = 1
The MAX77816 buck-boost regulator utilizes a four-switch
H-bridge configuration to realize buck, buck-boost, and
boost operating modes. In this way, this topology maintains output voltage regulation when the input voltage is
greater than, equal to, or less than the output voltage.
The MAX77816 buck-boost is ideal in Li-ion batterypowered applications providing 2.60V to 5.14V of output voltage range and up to 3A of output current. High
switching frequency and a unique control algorithm allow
the smallest solution size, low output noise, and highest efficiency across a wide input voltage and output
current range.
AND
OCP_INT_MASK = 0
OVP_INT = 1
AND
OVP_INT_MASK = 0
OR
POK_INT = 1
GPIO
AND
POK_INT_MASK = 0
THM_INT = 1
AND
THM_INT_MASK = 0
Figure 1. Interrupt Network
1µH
LXBB2
LXBB1
INBB
10µF
OUTBB
HS2
HS1
CS
LS1
47µF
CS
LS2
DRIVER
DRIVER
PGNDBB
CONTROL LOGIC
FB_BB
ETR
OSC
COMP.
CF
R1
PROT.
R2
REF
SLOPE COMP.
PSM
REGISTER
CONTROL
MAX77816
Figure 2. Buck-Boost Block Diagram
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Maxim Integrated │ 11
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
OUTBB
INBB
Ф2
HS1
HS2
CHARGE/DISCHARGE L
LXBB1
LXBB2
L
LS1
Ф3
LS2
DISCHARGE L
Ф1
CHARGE L
Figure 3. Buck-Boost Switching Intervals
H-Bridge Controller
H-bridge architecture operates at a 2.5MHz fixed frequency with a pulse-width-modulated (PWM), current-mode
control scheme. This topology is in a cascade of a boost
regulator and a buck regulator using a single inductor
and output capacitor. Buck, buck-boost, and boost stages
are 100% synchronous for highest efficiency in portable
applications.
There are three phases implemented with the H-bridge
switch topology, as shown in Figure 3:
●● Φ1 Switch period (Phase-1: HS1 = ON, LS2 =
ON) stores energy in the inductor, ramping up the
inductor current at a rate proportional to the input voltage divided by inductance; VINBB/L.
●● Φ2 Switch period (Phase-2: HS1 = ON, HS2 = ON)
ramps the inductor current up or down, depending on
the differential voltage across the inductor, divided by
inductance; ±(VINBB – VOUTBB)/L.
●● Φ3 Switch period (Phase-3: LS1 = ON, HS2 = ON)
ramps down the inductor current at a rate proportional to
the output voltage divided by inductance; -VOUTBB /L.
2-Phase buck topology is utilized when VINBB > VOUTBB.
A switching cycle is completed in one clock period. Switch
period Φ2 is followed by switch period Φ3, resulting in an
inductor current waveform similar to Figure 4.
2-Phase boost topology is utilized when VINBB < VOUTBB.
A switching cycle is completed in one clock period. Switch
period Φ1 is followed by switch period Φ2, resulting in an
inductor current waveform similar to Figure 5.
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Ф2
Ф2
Ф3
Ф3
TSW
TSW
CLK
CLK
CLK
Figure 4. 2-Phase Buck Mode Switching Current Waveforms
Ф2
Ф2
Ф1
Ф1
TSW
CLK
TSW
CLK
CLK
Figure 5. 2-Phase Boost Mode Switching Current Waveforms
Maxim Integrated │ 12
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Output Voltage Slew-Rate Control
stability. COUT must have low impedance at the switching
frequency. Ceramic capacitors with X5R or X7R dielectric
are highly recommended due to their small size, low ESR,
and small temperature coefficients. For stable operation,
buck-boost requires 16µF of minimum effective output
capacitance. Considering the DC bias characteristic of
ceramic capacitors, a 47µF 6.3V capacitor is recommended for most of applications.
The buck-boost regulator supports programmable slewrate control feature when increasing and decreasing
the output voltage. The ramp-up slew-rate can be set to
20mV/µs or 40mV/µs through the BB_RU_SR bit, while
the ramp-down slew-rate is programmable to 5mV/µs or
10mV/µs through the BB_RD_SR bit.
Output Active Discharge
PCB Layout Guidelines
Buck-boost provides an internal 100Ω resistor for output
active discharge function. If the active discharge function
is enabled (BB_AD = 1), the internal resistor discharges
the energy stored in the output capacitor to PGNDBB
whenever the regulator is disabled.
Careful circuit board layout is critical to achieve low
switching power losses and clean, stable operation.
Figure 6 shows an example HDI PCB layout for the
MAX77816 WLP package.
Either the regulator remains enabled or the active discharge function is disabled (BB_AD = 0), the internal
resistor is disconnected from the output. If the active discharge function is disabled, the output voltage decays at a
rate that is determined by the output capacitance and the
load current when the regulator is turned off.
When designing the PCB, follow these guidelines:
1) Place the input capacitors CIN and output capacitors
COUT immediately next to the IN pin and OUT pin,
respectively, of the IC. Since the IC operates at a high
switching frequency, this placement is critical for minimizing parasitic inductance within the input and output
current loops, which can cause high-voltage spikes
and may damage the internal switching MOSFETs.
Inductor Selection
Buck-boost is optimized for a 1µH inductor. The lower the
inductor DCR, the higher buck-boost efficiency is. Users
need to trade off inductor size with DCR value and choose
a suitable inductor for buck-boost.
2) Place the inductor next to the LX bumps (as close
as possible) and make the traces between the LX
bumps and the inductor short and wide to minimize
PCB trace impedance. Excessive PCB impedance
reduces converter efficiency. When routing LX traces
on a separate layer (as in the examples), make sure
to include enough vias to minimize trace impedance.
Routing LX traces on multiple layers is recommended
to further reduce trace impedance. Furthermore, do
not make LX traces take up an excessive amount of
area. The voltage on this node switches very quickly
and additional area creates more radiated emissions.
Input Capacitor Selection
The input capacitor, CIN, reduces the current peaks
drawn from the battery or input power source and reduces
switching noise in the device. The impedance of CIN at
the switching frequency should be kept very low. Ceramic
capacitors with X5R or X7R dielectrics are highly recommended due to their small size, low ESR, and small
temperature coefficients. For most applications, a 10µF
capacitor is sufficient.
3) Prioritize the low-impedance ground plane of the
PCB directly underneath the IC, COUT, CIN, and
inductor. Cutting this ground plane risks interrupting
the switching current loops.
Output Capacitor Selection
The output capacitor, COUT, is required to keep the
output voltage ripple small and to ensure regulation loop
Table 2. Suggested Inductors for Buck-Boost
MANUFACTURER
SERIES
NOMINAL
INDUCTANCE
(µH)
DC
RESISTANCE
(typ) (mΩ)
CURRENT
RATING (A)
-30% (∆L/L)
CURRENT
RATING (A)
∆T = -40°C RISE
DIMENSIONS
L x W x H (mm)
TDK
TFM201610GHM1R0MTAA
1.0
50
3.8
3.0
2.0 x 1.6 x 1.0
TOKO
DFE322512C
1.0
34
4.6
3.7
3.2 x 2.5 x 1.2
Coilcraft
XAL4020-102MEB
1.0
13
8.7
9.6
4.0 x 4.0 x 2.1
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Maxim Integrated │ 13
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
4) AGND must carefully connect to PGND on the PCB’s
low-impedance ground plane. Connect AGND to the
low-impedance ground plane on the PCB (the same
net as PGND) away from any critical loops.
Serial Interface
5) The IC requires a quiet supply input (SYS) which is
often the same net as IN. Carefully bypass SYS to
AGND with a dedicated capacitor (CSYS) as close as
possible to the IC. Route a dedicated trace between
CSYS and the SYS bump. Avoid connecting SYS
directly to the nearest IN bumps without dedicated
bypassing.
The I2C serial bus consists of a bidirectional serial-data
line (SDA) and a serial clock (SCL). I2C is an open-drain
bus. SDA and SCL require pullup resistors (of 500Ω or
greater). Optional 24Ω resistors in series with SDA and
SCL help to protect the device inputs from high voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot on bus lines.
The I2C-compatible, 2-wire serial interface is used for
regulator on/off control, setting output voltages, and other
functions. See the Register Map section for details.
6) Connect the OUTS bump to the regulating point with
a dedicated trace away from noisy nets such as LX1
and LX2.
System Configuration
The I2C bus is a multimaster bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
7) Keep the power traces and load connections short
and wide. This is essential for high converter efficiency.
Figure 8 shows an example of a typical I2C system. A
device on the I2C bus that sends data to the bus is called
a transmitter. A device that receives data from the bus is
called a receiver. The device that initiates a data transfer
and generates SCL clock signals to control the data transfer
is a master. Any device that is being addressed by the
master is considered a slave. When the MAX77816 I2C
compatible interface is operating, it is a slave on I2C bus
and it can be both a transmitter and a receiver.
8) Do not neglect ceramic capacitor DC voltage derating. Choose capacitor values and case sizes carefully. See the Output Capacitor Selection section and
refer to Tutorial 5527 for more information.
LX1
LX2
LEGEND
L
1515 (4040)
1515 (4040)
PGND
PGND
CIN
0603
COUT
0805
OUT
IN
0402
FB
RSYS
0402
AGND
CSYS
0402
EN
GPIO
SCL
SDA
+ VSYS
AGND
0603
0805
IN
NON-HDI VIA
8 mil hole, 18 mil pad
HDI µVIA
5 mil hole, 10 mil pad
COMPONENT SIZES LISTED IN
IMPERIAL (METRIC)
NOTE: PLACE CIN AND COUT CLOSE TO THE IC TO MINIMIZE PARASITIC INDUCTANCE WITHIN THE LOOP
Figure 6. PCB Layout Example (WLP)
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Maxim Integrated │ 14
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
L
LAYOUT NOTES:
N1: PLACE THE IN CAPACITOR (CIN) AND OUT CAPACITOR
(COUT) AS CLOSE TO THE IC AS POSSIBLE.
N2: CONNECT THE NEGATIVE TERMINAL OF CIN AS CLOSE
N2
AS POSSIBLE TO THE NEGATIVE TERMINAL OF COUT WITH A
LOW-IMPEDANCE HIGH-PRIORITY PATH TO THE
CORRESPONDING PGND BUMPS. THIS PRACTICE MINIMIZES
THE HIGH DI/DT LOOP LENGTH REDUCING ANY VOLTAGE
PGND
PGND
OUT
SPIKES SEEN ON LX1 AND LX2.
COUT
CIN
IN
N1
Figure 7. Recommended Capacitor Placement
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Figure 8. Functional Logic Diagram for Communications Controller
SDA
SCL
CHANGE OF DATA
ALLOWED
DATA LINE STABLE DATA VALID
Figure 9. I2C Bit Transfer
S
Sr
P
SDA
tSU;STA
tSU;STO
SCL
tHD;STA
tHD;STA
Figure 10. START and STOP Conditions
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Maxim Integrated │ 15
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Bit Transfer
One data bit is transferred for each SCL clock cycle. The
data on SDA must remain stable during the high portion of
SCL clock pulse. Changes in SDA while SCL is high are
control signals (START and STOP conditions).
START and STOP Conditions
When the I2C serial interface is inactive, SDA and SCL
idle high. A master device initiates communication by
issuing a START condition. A START condition is a highto-low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high.
A START condition from the master signals the beginning
of a transmission to the MAX77816. The master terminates transmission by issuing a NOT-ACKNOWLEDGE
followed by a STOP condition.
The STOP condition frees the bus. To issue a series of
commands to the slave, the master may issue REPEATED
START (Sr) commands instead of a STOP command
in order to maintain control of the bus. In general, a
REPEATED START command is functionally equivalent
to a regular START command.
When a STOP condition or incorrect address is detected,
the IC internally disconnects SCL from I2C serial interface
until the next START condition, minimizing digital noise
and feedthrough.
Acknowledged
related clock pulse (ninth pulse) and keep it low during
the high period of the clock pulse. To generate a NOTACKNOWLEDGE (nA), the receiving device allows SDA
to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the
high period of the clock pulse.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
Slave Address
The I2C slave address of the IC is shown in Table 3.
Clock Stretching
In general, the clock signal generation for the I2C bus is
the responsibility of the master device. The I2C specification allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The IC does not use any form of clock stretching to hold down the clock line.
General Call Address
The IC does not implement the I2C specification called a
general call address. If the IC sees a general call address
(00000000b), it will not issue an ACKNOWLEDGE (A).
Both the I2C bus master and MAX77816 (slave) generate
acknowledge bits when receiving data. The acknowledge
bit is the last bit of each nine-bit data packet. To generate an ACKNOWLEDGE (A), the receiving device must
pull SDA low before the rising edge of the acknowledge-
Table 3. I2C Slave Address
SLAVE ADDRESS (7 bit)
SLAVE ADDRESS (Write)
SLAVE ADDRESS (Read)
001 1000 (7’h18)
0x30 (0011 0000)
0x31 (0011 0001)
S
SDA
1
1
0
0
0
0
0
R/W
A
ACKNOWLEDGE
SCL
1
2
3
4
5
6
7
8
9
Figure 11. Slave Address Byte Example
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Maxim Integrated │ 16
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
LEGEND
MASTER TO SLAVE
*P FORCES THE BUS FILTERS TO SWITCH TO
THEIR ≤1MHz MODE. Sr LEAVES THE BUS
FILTERS IN THEIR CURRENT STATE.
SLAVE TO MASTER
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER
A
DATA
A
P or Sr*
THE DATA IS
LOADED INTO THE
TARGET REGISTER
AND BECOMES
ACTIVE DURING THIS
RISING EDGE.
R/nW
SDA
NUMBER OF
BITS
B1
B0
A
ACKNOWLEDGE
SCL
7
8
9
Figure 12. Writing to a Single Register with Write Byte Protocol
Communication Speed
The IC provides I2C 3.0-compatible (3.4MHz) serial interface.
●● 0Hz to 100kHz (standard mode)
●● 0Hz to 400kHz (fast mode)
●● 0Hz to 1MHz (fast mode plus)
Operating in standard mode, fast mode, and fast mode
plus does not require any special protocols. The main
consideration when changing the bus speed through
this range is the combination of the bus capacitance and
pullup resistors. Higher time constants created by the
bus capacitance and pullup resistance (C x R) slow the
bus operation. Therefore, when increasing bus speeds,
the pullup resistance must be decreased to maintain a
reasonable time constant. Refer to the Pullup Resistor
Sizing section of I2C revision 3.0 specification for detailed
guidance on the pullup resistor selection. In general, for
bus capacitances of 200pF, a 100kHz bus needs 5.6kΩ
pullup resistors, a 400kHz bus needs about 1.5kΩ pullup
resistors, and a 1MHz bus needs 680Ω pullup resistors.
Note that the pullup resistor is dissipating power when the
open-drain bus is low. The lower the value of the pullup
resistor, the higher the power dissipation (V2/R).
At power-up and after each STOP condition, the IC input
filters are set for standard mode, fast mode, or fast mode
plus (i.e., 0Hz to 1MHz).
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Communication Protocols
The IC supports both writing and reading from its registers. The following sections show the I2C communication
protocols for each functional block. The power block uses
the same communications protocols.
Writing to a Single Register
Figure 12 shows the protocol for the I2C master device to
write one byte of data to the IC. This protocol is the same
as the SMBus specification’s write byte protocol.
The write byte protocol is as follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed by
a write bit (R/nW = 0).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave acknowledges the data byte. At the rising
edge of SCL, the data byte will be loaded into its target register and the data will become active.
8) The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a STOP condition (P) ensures that the bus input filters are set for
1MHz or slower operation. Issuing a REPEATED START
(Sr) leaves the bus input filters in their current state.
Maxim Integrated │ 17
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
LEGEND
MASTER TO SLAVE
*P FORCES THE BUS FILTERS TO SWITCH
TO THEIR ≤ 1MHz MODE.
Sr LEAVES THE BUS FILTERS IN THEIR
CURRENT STATE.
SLAVE TO MASTER
1
7
1
1
8
1
8
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
DATA X
A
8
1
8
1
DATA X+1
A
DATA X+2
A
NUMBER OF
BITS
α
R/nW
α REGISTER POINTER = X + 2
REGISTER POINTER = X + 1
NUMBER OF
BITS
α
8
1
8
1
1
DATA n-1
A
DATA n
A
P or Sr*
REGISTER POINTER = X + (n-2) α REGISTER POINTER = X + (n-1)
NUMBER OF
BITS
β
THE DATA IS LOADED INTO THE TARGET
REGISTER AND BECOMES ACTIVE DURING
THIS RISING EDGE.
SDA
B1
B0
A
B9
ACKNOWLEDGE
SCL
7
8
9
1
DETAIL: α
THE DATA IS LOADED INTO THE TARGET
REGISTER AND BECOMES ACTIVE DURING
THIS RISING EDGE.
SDA
B1
B0
A
ACKNOWLEDGE
SCL
7
8
9
DETAIL: β
Figure 13. Writing to Sequential Registers X to N
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Maxim Integrated │ 18
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1
1
8
1
8
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
DATA X
A
NUMBER OF
BITS
α
R/nW
NUMBER OF
BITS
8
1
8
1
REGISTER POINTER n
A
DATA n
A
8
1
8
1
1
REGISTER POINTER Z
A
DATA Z
A
P
α
NUMBER OF
BITS
β
THE DATA IS LOADED INTO THE TARGET
REGISTER AND BECOMES ACTIVE DURING
THIS RISING EDGE.
SDA
B1
B0
A
B9
SCL
7
8
9
1
DETAIL: α
THE DATA IS LOADED INTO THE TARGET
REGISTER AND BECOMES ACTIVE DURING
THIS RISING EDGE.
SDA
B1
B0
A
ACKNOWLEDGE
SCL
7
8
9
DETAIL: β
Figure 14. Writing to Multiple Registers with Multiple Byte Register-Data Pairs Protocol
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Maxim Integrated │ 19
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Writing to a Sequential Register
Writing Multiple Bytes using
Register-Data Pairs
Figure 13 shows the protocol for writing to a sequential
register. This protocol is similar to the write byte protocol, except the master continues to write after it receives
the first byte of data. When the master is done writing, it
issues a STOP or REPEATED START.
Figure 14 shows the protocol for the I2C master device
to write multiple bytes to the IC using register-data pairs.
This protocol allows I2C master device to address the
slave only once and then send data to multiple registers
in a random order. Registers may be written continuously
until the master issues a STOP condition.
The writing to sequential registers protocol is as
follows:
The multiple byte register-data pair protocol is as
follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed by
a write bit (R/nW = 0).
1) The master sends a START command.
2) The master sends the 7-bit slave address followed by
a write bit.
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
4) The master sends an 8-bit register pointer.
6) The master sends a data byte.
5) The slave acknowledges the register pointer.
7) The slave acknowledges the data byte. At the rising
edge of SCL, the data byte will be loaded into its target register and the data will become active.
6) The master sends a data byte.
7) The slave acknowledges the data byte. At the rising
edge of SCL, the data byte will be loaded into its target register and the data will become active.
8) Steps 6 to 7 are repeated as many times as the
master requires.
8) Steps 4 to 7 are repeated as many times as the master requires.
9) During the last acknowledge related clock pulse, the
slave issues an ACKNOWLEDGE (A).
9) The master sends a STOP condition.
10) The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a STOP
condition (P) ensures that the bus input filters are set
for 1MHz or slower operation. Issuing a REPEATED
START (Sr) leaves the bus input filters in their current
state.
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHZ MODE.
Sr LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
LEGEND
MASTER TO
SLAVE
1
7
S
SLAVE ADDRESS
R/W
SLAVE TO
MASTER
1 1
8
1 1
7
0 A
REGISTER POINTER X
A Sr
SLAVE ADDRESS
1 1
8
1
1 A
DATA X
A
R/nW
8
1
8
DATA X+1
A
DATA X+2
1
8
1
A
DATA X+3
A
REGISTER POINTER = X + 1 REGISTER POINTER = X + 2
8
1
8
1
8
A
DATA n-1
A
DATA n
REGISTER POINTER =
X + (n-2)
NUMBER OF BITS
REGISTER POINTER = X + 3
DATA n-2
REGISTER POINTER =
X + (n-3)
NUMBER OF BITS
1
1
NUMBER OF BITS
nA P OR Sr*
REGISTER POINTER =
X + (n-1)
Figure 15. Reading Continuously from Sequential Registers X to N
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Maxim Integrated │ 20
MAX77816
Reading from a Single Register
The I2C master device reads one byte of data to the IC.
This protocol is the same as SMBus specification’s “Read
Byte” protocol.
The “Read Byte” protocol is as follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed by
a write bit (R/nW = 0).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA LOW.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START command
(Sr).
7) The master sends the 7-bit slave address followed by
a read bit (R/nW = 1).
8) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA LOW.
9) The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
10) The master issues a NOT-ACKNOWLEDGE (nA).
11) The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a STOP
condition (P) ensures that the bus input filters are set
for 1MHz or slower operation. Issuing a REPEATED
START (Sr) leaves the bus input filters in their current
state.
High-Efficiency Buck-Boost Regulator
with 5A Switches
Reading from a Sequential Register
Figure 15 shows the protocol for reading from sequential
registers. This protocol is similar to the read byte protocol
except the master issues an ACKNOWLEDGE (A) to signal the slave that it wants more data. When the master has
all the data it requires, it issues a NOT-ACKNOWLEDGE
(nA) and a STOP (P) to end the transmission.
The continuous read from sequential registers protocol is
as follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
by a write bit (R/nW = 0).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START command (Sr).
7) The master sends the 7-bit slave address followed
by a read bit (R/nW = 1).
8) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
9) The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
10) The master issues an ACKNOWLEDGE (A) signaling
the slave that it wishes to receive more data.
11) Steps 9 to 10 are repeated as many times as the
master requires. Following the last byte of data, the
master must issue a NOT-ACKNOWLEDGE (nA) to
signal that it wishes to stop receiving data.
12) The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a STOP
(P) ensures that the bus input filters are set for 1MHz
or slower operation. Issuing a REPEATED START
(Sr) leaves the bus input filters in their current state.
www.maximintegrated.com
Maxim Integrated │ 21
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Registers
Register Map
I2C Slave Address (W/R): 0x30 / 0x31
ADDRESS
REGISTER
NAME
BIT 7
0x00
DEVICE_ID
RSVD
0x01
STATUS
RSVD
0x02
CONFIG1
0x03
CONFIG2
RSVD
0x04
VOUT
RSVD
VOUT[6:0]
0x28/
0x23
0x05
VOUT_H
RSVD
VOUT_H[6:0]
0x78
0x06
INT_MASK
RSVD
RSVD
RSVD
RSVD
THM_INT
_MASK
POK_INT
_MASK
OVP_INT
_MASK
OCP_INT
_MASK
0x00
0x07
INT
RSVD
RSVD
RSVD
RSVD
THM_INT
POK_INT
OVP_INT
OCP_INT
—
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
VERSION[3:0]
RSVD
ILIM[1:0]
BB_EN
RSVD
RSVD
BB_RU
_SR
BB_RD
_SR
EN_PD
POK_POL
BIT 0
CHIP_REV[2:0]
TSHDN
BB_POKn
—
BB_OVP
BB_
OCP
—
BB_AD
BB
_FPWM
0xCE
BB_OVP_TH[1:0]
RSVD
RESET
VALUE
GPIO_CFG[2:0]
0x71
Register Reset Conditions
Type-O: Registers are reset when VSYS < VUVLO_F OR EN = LOW
DEVICE_ID
Device ID Register
ADDRESS
ACCESS TYPE
0x00
Read Only
TYPE: O
BIT
NAME
POR
7
RESERVED
—
6:3
VERSION[3:0]
—
Version
0000b: Default
2:0
CHIP_REV[2:0]
—
Chip Revision History
001b: PASS1
www.maximintegrated.com
RESET VALUE: N/A
DESCRIPTION
Maxim Integrated │ 22
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
STATUS
Status Register
ADDRESS
ACCESS TYPE
0x01
Read Only
TYPE: O
RESET VALUE: N/A
BIT
NAME
POR
7:4
RESERVED
—
3
TSHDN
—
Thermal Shutdown Status
0: Junction temperature (TJCT) ≤ 165°C
1: Junction temperature (TJCT) > 165°C
2
BB_POKn
—
Power-OK Status
0: VOUTBB is below the POK threshold
1: VOUTBB is above the POK threshold
—
Overvoltage Status
0: VOUTBB is below the OVP threshold
1: VOUTBB is above the OVP threshold
The OVP threshold is set by BB_OVP_TH[1:0]
—
Overcurrent Status
0: Inductor peak current is below the ILIM threshold
1: Inductor peak current is above the ILIM threshold
The ILIM threshold is set by ILIM[1:0]
1
0
BB_OVP
BB_OCP
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DESCRIPTION
Maxim Integrated │ 23
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
CONFIG1
Configuration Register1
ADDRESS
ACCESS TYPE
0x02
Read, Write
BIT
NAME
TYPE: O
POR
RESET VALUE: 0xCE
DESCRIPTION
7:6
ILIM[1:0]
11
Inductor Peak Current Limit
00b: 1.15A
01b: 1.80A
10b: 3.1A
11b: 5A
When GPIO_CFG[2:0] = 010b, ILIM[1:0] does not set inductor peak
current level. Inductor peak current level is set by GPIO
5
BB_RU_SR
0
Rising Ramp-Rate Control
0: 20mV/µs
1: 40mV/µs
4
BB_RD_SR
0
Ramp-Down Slew Rate Control
0: 5mV/µs
1: 10mV/µs
3:2
BB_OVP_TH[1:0]
11
Output OVP Threshold
00b: No OVP
01b: 110% of VOUT
10b: 115% of VOUT
11b: 120% of VOUT
1
BB_AD
1
Output Active Discharge
0: Disable active discharge
1: Enable active discharge
0
Forced PWM Enable
0: SKIP mode
1: Forced PWM
When GPIO_CFG[2:0] = 001b, BB_FPWM does not set inductor peak
current level. Inductor peak current level is set by GPIO
0
BB_FPWM
www.maximintegrated.com
Maxim Integrated │ 24
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
CONFIG2
Configuration Register2
ADDRESS
ACCESS TYPE
0x03
Read, Write
TYPE: O
RESET VALUE: 0x71
BIT
NAME
POR
7
RESERVED
0
6
BB_EN
1
0: Disable buck-boost output
1: Enable buck-boost output
5
EN_PD
1
EN Input Pulldown Resistor Enable Setting
0: Disable
1: Enable
4
POK_POL
1
0: Active low
1: Active high
3
RESERVED
0
2:0
GPIO_CFG[2:0]
www.maximintegrated.com
001
(A version)
DESCRIPTION
GPIO Pin Function Configuration
001b: FPWM mode enable, MAX77816A/MAX77816F default
010b: Inductor peak current-limit selection,
MAX77816B default
011b: Output voltage selection, MAX77816C default
100b: Power-OK status indication, MAX77816D default
101b: Interrupt indication, MAX77816E default
Maxim Integrated │ 25
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
VOUT
Output Voltage Setting Register
ADDRESS
ACCESS TYPE
0x04
Read, Write
TYPE: O
BIT
NAME
POR
7
RESERVED
0
RESET VALUE: 0x23 (MAX77816B/C/D/E/F)
0x28 (MAX77816A)
DESCRIPTION
Buck-Boost Output Voltage
GPIO_CFG[2:0] = 011b: VOUT sets the output voltage when GPIO = low
6:0
VOUT[6:0]
www.maximintegrated.com
011 1000
0x00 = 2.60V
0x20 = 3.24V
0x40 = 3.88V
0x60 = 4.52V
0x01 = 2.62V
0x21 = 3.26V
0x41 = 3.90V
0x61 = 4.54V
0x02 = 2.64V
0x22 = 3.28V
0x42 = 3.92V
0x62 = 4.56V
0x03 = 2.66V
0x23 = 3.30V
0x43 = 3.94V
0x63 = 4.58V
0x04 = 2.68V
0x24 = 3.32V
0x44 = 3.96V
0x64 = 4.60V
0x05 = 2.70V
0x25 = 3.34V
0x45 = 3.98V
0x65 = 4.62V
0x06 = 2.72V
0x26 = 3.36V
0x46 = 4.00V
0x66 = 4.64V
0x07 = 2.74V
0x27 = 3.38V
0x47 = 4.02V
0x67 = 4.66V
0x08 = 2.76V
0x28 = 3.40V
0x48 = 4.04V
0x68 = 4.68V
0x09 = 2.78V
0x29 = 3.42V
0x49 = 4.06V
0x69= 4.70V
0x0A = 2.80V
0x2A = 3.44V
0x4A = 4.08V
0x6A = 4.72V
0x0B = 2.82V
0x2B = 3.46V
0x4B = 4.10V
0x6B = 4.74V
0x0C = 2.84V
0x2C = 3.48V
0x4C = 4.12V
0x6C = 4.76V
0x0D = 2.86V
0x2D = 3.50V
0x4D = 4.14V
0x6D = 4.78V
0x0E = 2.88V
0x2E = 3.52V
0x4E = 4.16V
0x6E = 4.80V
0x0F = 2.90V
0x2F = 3.54V
0x4F = 4.18V
0x6F = 4.82V
0x10 = 2.92V
0x30 = 3.56V
0x50 = 4.20V
0x70 = 4.84V
0x11 = 2.94V
0x31 = 3.58V
0x51 = 4.22V
0x71 = 4.86V
0x12 = 2.96V
0x32 = 3.60V
0x52 = 4.24V
0x72 = 4.88V
0x13 = 2.98V
0x33 = 3.62V
0x53 = 4.26V
0x73 = 4.90V
0x14 = 3.00V
0x34 = 3.64V
0x54 = 4.28V
0x74 = 4.92V
0x15 = 3.02V
0x35 = 3.66V
0x55 = 4.30V
0x75 = 4.94V
0x16 = 3.04V
0x36 = 3.68V
0x56 = 4.32V
0x76 = 4.96V
0x17 = 3.06V
0x37 = 3.70V
0x57 = 4.34V
0x77 = 4.98V
0x18 = 3.08V
0x38 = 3.72V
0x58 = 4.36V
0x78 = 5.00V
0x19 = 3.10V
0x39 = 3.74V
0x59 = 4.38V
0x79 = 5.02V
0x1A = 3.12V
0x3A = 3.76V
0x5A = 4.40V
0x7A = 5.04V
0x1B = 3.14V
0x3B = 3.78V
0x5B = 4.42V
0x7B = 5.06V
0x1C = 3.16V
0x3C = 3.80V
0x5C = 4.44V
0x7C = 5.08V
0x1D = 3.18V
0x3D = 3.82V
0x5D = 4.46V
0x7D = 5.10V
0x1E = 3.20V
0x3E = 3.84V
0x5E = 4.48V
0x7E = 5.12V
0x1F = 3.22V
0x3F = 3.86V
0x5F = 4.50V
0x7F = 5.14V
Maxim Integrated │ 26
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
VOUT_H
Output Voltage Setting Register for MAX77816C, GPIO = HIGH
ADDRESS
ACCESS TYPE
0x05
Read, Write
TYPE: O
BIT
NAME
POR
7
RESERVED
0
RESET VALUE: 0x78
DESCRIPTION
Buck-Boost Output Voltage
GPIO_CFG[2:0]=011b: VOUT_H sets the output voltage when GPIO = high
GPIO_CFG[2:0]≠011b: VOUT_H does not control the output voltage
6:0
VOUT_H[6:0]
www.maximintegrated.com
011 1000
0x00 = 2.60V
0x20 = 3.24V
0x40 = 3.88V
0x60 = 4.52V
0x01 = 2.62V
0x21 = 3.26V
0x41 = 3.90V
0x61 = 4.54V
0x02 = 2.64V
0x22 = 3.28V
0x42 = 3.92V
0x62 = 4.56V
0x03 = 2.66V
0x23 = 3.30V
0x43 = 3.94V
0x63 = 4.58V
0x04 = 2.68V
0x24 = 3.32V
0x44 = 3.96V
0x64 = 4.60V
0x05 = 2.70V
0x25 = 3.34V
0x45 = 3.98V
0x65 = 4.62V
0x06 = 2.72V
0x26 = 3.36V
0x46 = 4.00V
0x66 = 4.64V
0x07 = 2.74V
0x27 = 3.38V
0x47 = 4.02V
0x67 = 4.66V
0x08 = 2.76V
0x28 = 3.40V
0x48 = 4.04V
0x68 = 4.68V
0x09 = 2.78V
0x29 = 3.42V
0x49 = 4.06V
0x69 = 4.70V
0x0A = 2.80V
0x2A = 3.44V
0x4A = 4.08V
0x6A = 4.72V
0x0B = 2.82V
0x2B = 3.46V
0x4B = 4.10V
0x6B = 4.74V
0x0C = 2.84V
0x2C = 3.48V
0x4C = 4.12V
0x6C = 4.76V
0x0D = 2.86V
0x2D = 3.50V
0x4D = 4.14V
0x6D = 4.78V
0x0E = 2.88V
0x2E = 3.52V
0x4E = 4.16V
0x6E = 4.80V
0x0F = 2.90V
0x2F = 3.54V
0x4F = 4.18V
0x6F = 4.82V
0x10 = 2.92V
0x30 = 3.56V
0x50 = 4.20V
0x70 = 4.84V
0x11 = 2.94V
0x31 = 3.58V
0x51 = 4.22V
0x71 = 4.86V
0x12 = 2.96V
0x32 = 3.60V
0x52 = 4.24V
0x72 = 4.88V
0x13 = 2.98V
0x33 = 3.62V
0x53 = 4.26V
0x73 = 4.90V
0x14 = 3.00V
0x34 = 3.64V
0x54 = 4.28V
0x74 = 4.92V
0x15 = 3.02V
0x35 = 3.66V
0x55 = 4.30V
0x75 = 4.94V
0x16 = 3.04V
0x36 = 3.68V
0x56 = 4.32V
0x76 = 4.96V
0x17 = 3.06V
0x37 = 3.70V
0x57 = 4.34V
0x77 = 4.98V
0x18 = 3.08V
0x38 = 3.72V
0x58 = 4.36V
0x78 = 5.00V
0x19 = 3.10V
0x39 = 3.74V
0x59 = 4.38V
0x79 = 5.02V
0x1A = 3.12V
0x3A= 3.76V
0x5A = 4.40V
0x7A = 5.04V
0x1B = 3.14V
0x3B = 3.78V
0x5B = 4.42V
0x7B = 5.06V
0x1C = 3.16V
0x3C = 3.80V
0x5C = 4.44V
0x7C = 5.08V
0x1D = 3.18V
0x3D = 3.82V
0x5D = 4.46V
0x7D = 5.10V
0x1E = 3.20V
0x3E = 3.84V
0x5E = 4.48V
0x7E = 5.12V
0x1F = 3.22V
0x3F = 3.86V
0x5F = 4.50V
0x7F = 5.14V
Maxim Integrated │ 27
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
INT_MASK
Interrupt Mask Register
ADDRESS
ACCESS TYPE
0x06
Read, Write
TYPE: O
RESET VALUE: 0x00
BIT
NAME
POR
7:4
RESERVED
0000
DESCRIPTION
3
THM_INT_MASK
0
Thermal Shutdown Interrupt Mask Bit
0: Unmask
1: Mask
2
POK_INT_MASK
0
Power-OK Interrupt Mask Bit
0: Unmask
1: Mask
1
OVP_INT_MASK
0
OVP Interrupt Mask Bit
0: Unmask
1: Mask
0
OCP_INT_MASK
0
OCP interrupt mask bit
0: Unmask
1: Mask
INT
Interrupt Status Register
ADDRESS
ACCESS TYPE
0x07
Read and Clear
TYPE: O
RESET VALUE: N/A
BIT
NAME
POR
7:4
RESERVED
0000
3
THM_INT
0
Thermal Shutdown Interrupt Bit
0: No status change or status change from 1 to 0 for TSHDN
1: Status change from 0 to 1 happened for TSHDN
2
POK_INT
0
Power-OK Interrupt Bit
0: No status change or status change from 1 to 0 for BB_POKn
1: Status change from 1 to 0 happened for BB_POKn
1
OVP_INT
0
OVP Interrupt Bit
0: No status change or status change from 1 to 0 for BB_OVP
1: Status change from 0 to 1 happened for BB_OVP
0
OCP_INT
0
OCP Interrupt Bit
0: No status change or status change from 1 to 0 for BB_OCP
1: Status change from 0 to 1 happened for BB_OCP
www.maximintegrated.com
DESCRIPTION
Maxim Integrated │ 28
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Ordering Information
PART
DEFAULT VOUT
GPIO DEFAULT TYPE
GPIO DEFAULT FUNCTION
MAX77816AEWP+T
3.4V
Input
FPWM Mode Enable
MAX77816BEWP+T
3.3V
Input
Inductor Peak Current Limit Selection
MAX77816CEWP+T
3.3V/5V
Input
Output Voltage Selection
MAX77816DEWP+T
3.3V
Output
Power-OK Status Indication
MAX77816EEWP+T*
3.3V
Output
Interrupt Indication
MAX77816FEWP+T*
3.3V
Input
FPWM Mode Enable
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Future product—Contact Maxim for availability.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN
NO.
20 WLP
W201F2+1
21-0771
Refer to
Application
Note 1891
www.maximintegrated.com
Maxim Integrated │ 29
MAX77816
High-Efficiency Buck-Boost Regulator
with 5A Switches
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
6/17
Initial release
1
3/18
Released MAX77816B and MAX77816C, added MAX77816F information
1, 2, 7, 8, 18,
21–23, 25, 26
2
6/19
Updated package measurements, added PCB Layout Guidelines section,
updated Ordering Information table
7, 11, 27
3
10/19
Updated LXBB in the Absolute Maximum Ratings section, updated Shutdown
Supply Current and LXBB1/2 Current Limit in the Electrical Characteristics
table
2, 3
4
7/20
Updated Typical Operating Characteristics section
6–8
DESCRIPTION
—
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2020 Maxim Integrated Products, Inc. │ 30
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