EVALUATION KIT AVAILABLE
MAX77826
General Description
The MAX77826 is a subpower management IC for the
latest 3G/4G smartphones and tablets. The MAX77826
contains a high-efficiency BUCK regulator, a BUCK
BOOST regulator and 15 LDOs to power up peripherals.
The MAX77826 also provides power on/off control logic
and an I2C serial interface to program individual regulator
output voltages and on/off control for complete flexibility.
The linear regulators support a remote cap feature and
provide greater than 70dB PSRR and less than 45µVRMS
noise.
The MAX77826 features I2C-compatible, 2-wire serial
interface that comprises a bidirectional serial data line
(SDA) and a serial clock line (SCL). The MAX77826 supports SCL clock rates up to 3.4MHz.
Applications
●● GSM, GPRS, EDGE, CDMA WCDMA, and LTE
Smartphones and Tablets
Ordering Information appears at end of data sheet.
Power Management IC
Benefits and Features
●● Compact Total Solution Size Allows More Peripheral
Devices in Smartphones and Tablets
• 3A High-Efficiency BUCK Regulator
• DVS (Dynamic Voltage Scaling) Through HS I2C
• ±1% (typ) Output Voltage DC Accuracy
• Low Power Mode
• 2A BUCK BOOST Regulator
• 15 Linear Regulators with Remote Cap
• 3 NMOS LDOs (VOUT Range: 0.6V to 2.1875V
with 12.5mV Step)
• 1 x 150mA
• 1 x 450mA
• 1 x 600mA
• 6 PMOSLV LDOs (VOUT Range: 0.8V to 3.975V
with 25mV Step)
• 3 x 150mA
• 3 x 300mA
• 6 PMOSLS LDOs (VOUT Range: 0.8V to 3.975V
with 25mV Step)
• 3 x 150mA
• 3 x 300mA
• ±1.5% Typical Output Voltage DC Accuracy
• 70dB PSRR at 1kHz
• Low Power Mode with 2µA (typ) for all LDOs
●● Simple Management of Power-Up/Down Sequence,
Output Voltage Setting, and Fault Detection
• High-Speed (Up to 3.4MHz) I2C Serial Interface
19-6893; Rev 1; 7/15
MAX77826
Power Management IC
Absolute Maximum Ratings
SYS, VIO, INL1, INL2, INL3,
INL4, INL5 to GND............................................-0.3V to +6.0V
INB to PGNDB......................................................-0.3V to +6.0V
INBB, OUTBB to PGNDBB...................................-0.3V to +6.0V
PGNDB, PGNDBB to GND...................................-0.3V to +0.3V
IRQB, CE, SDA, SCL to GND.................. -0.3V to (VVIO + 0.3V)
FB_B, ENBB, ENB, ENL12,
REFBYP to GND................................. -0.3V to (VSYS + 0.3V)
FB_BB to PGNDBB.............................-0.3V to (VOUTBB + 0.3V)
LXB to PGNDB......................................... -0.3V to (VINB + 0.3V)
LXBB1 to PGNDBB................................ -0.3V to (VINBB + 0.3V)
LXBB2 to PGNDBB.............................-0.3V to (VOUTBB + 0.3V)
LDO1, LDO2 to GND.............................. -0.3V to (VINL1 + 0.3V)
LDO3 to GND.......................................... -0.3V to (VINL2 + 0.3V)
LDO4, LDO5, LDO6, LDO7, LDO8,
LDO9 to GND...................................... -0.3V to (VINL3 + 0.3V)
LDO10, LDO11 to GND........................... -0.3V to (VINL4 + 0.3V)
LDO12, LDO13, LDO14,
LDO15 to GND.................................... -0.3V to (VINL5 + 0.3V)
LXB Continuous RMS Current (Note 1)...................................3A
LXBB1/LXBB2 Continuous RMS Current (Note 1)...............3.3A
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Note 1: LX_ node has internal clamp diodes to PGND_ and INB_. Applications that give forward bias to these diodes should ensure
that the total power loss does not exceed IC’s package power dissipation limits.
Package Thermal Characteristics (Note 2)
WLP
Junction-to-Ambient Thermal Resistance (θJA)...........37°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
General Electrical Characteristics
(VSYS = VIN_ = +3.7V, VIO = 1.8V, TA = -40°C to +85°C, unless otherwise noted.)
VPARAMETER
Shutdown Supply Current
Standby Current
SYMBOL
ISHDN_SYS
IQ_SYS
CONDITIONS
MIN
TYP
MAX
UNITS
CE = low
2.5
10
µA
CE = high and all regulators are off
35
µA
Shutdown VIO Current
ISHDN_VIO
All regulators are off
0
µA
No Load Supply Current 1
INO_LOAD1
BUCK is on in normal mode
(no switching)
60
µA
No Load Supply Current 2
INO_LOAD2
BUCK and BUCK BOOST are on in
normal mode (no switching)
120
µA
No Load Supply Current 3
INO_LOAD3
All regulators are on in normal
mode (no switching)
400
700
2.50
2.625
µA
VSYS UNDERVOLTAGE LOCKOUT
VSYS Undervoltage Lockout
Threshold
VUVLO_R
VSYS rising
VUVLO_F
VSYS falling (default)
2.375
2.05
V
REFERENCE
REFBYP Output Voltage
REFBYP Supply Rejection
www.maximintegrated.com
0.786
2.7V ≤ VSYS ≤ 5.5V
0.80
0.2
0.814
V
mV/V
Maxim Integrated │ 2
MAX77826
Power Management IC
General Electrical Characteristics (continued)
(VSYS = VIN_ = +3.7V, VIO = 1.8V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
THERMAL SHUTDOWN
Thermal Shutdown Threshold
TSHDN
TJ rising, 15°C hysteresis
+165
°C
Thermal Interrupt at +120°C
T120
TJ rising, 15°C hysteresis
+120
°C
Thermal Interrupt at +140°C
T140
TJ rising, 15°C hysteresis
+140
°C
LOGIC AND CONTROL INPUTS
Input Low Level
Input High Level
Logic Input Leakage Current
VIL
ENB, ENBB,
ENL12
VSYS ≤ 4.5V
TA = +25°C
CE
TA = +25°C
VIH
ENB, ENBB,
ENL12
VSYS ≤ 4.5V
TA = 25°C
CE
TA = +25°C
CE
(0V < VIO < 1.8V)
TA = +25°C
ILEAK
IRQB Output Low Voltage
VOL
ISINK = 1mA
IRQB Output High Leakage
IOZH
VIO = 5.5V
0.4
1.2
V
0.7 x VVIO
-1
TA = +85°C
+1
0.1
0.4
TA = +25°C
V
0.3 x VVIO
-1
TA = +85°C
+1
0.1
µA
V
µA
INTERNAL PULLDOWN RESISTANCE
ENB, ENBB, ENL12
www.maximintegrated.com
RPD
Pulldown resistor to GND
400
800
1600
kΩ
Maxim Integrated │ 3
MAX77826
Power Management IC
I2C Electrical Characteristics
(VSYS = VIN_ = +3.7V, VIO = 1.8V, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.6
V
POWER SUPPLY
VIO Voltage
VVIO
1.7
SCL, SDA Input High Voltage
VIH
0.7 x VVIO
SCL, SDA Input Low Voltage
VIL
SDA AND SCL I/O STAGES
SCL, SDA Input Hysteresis
0.3 x VVIO
VHYS
SCL, SDA Input Current
II
SDA Output Low Voltage
VOL
SCL, SDA Pin Capacitance
CI
Output Fall Time from
VIO to 0.3 x VIO
tOF
V
0.05 x VVIO
VIO = 3.7V
-10
ISINK = 20mA
V
V
+10
µA
0.4
V
10
pF
120
ns
1000
kHz
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST MODE PLUS) (Note 3)
Clock Frequency
Hold Time (REPEATED) START
Condition
fSCL
tHD;STA
0.26
µs
CLK Low Period
tLOW
0.5
µs
CLK High Period
tHIGH
0.26
µs
Setup Time REPEATED START
Condition
tSU;STA
0.26
µs
DATA Hold Time
tHD:DAT
0
µs
DATA Setup Time
tSU;DAT
50
ns
Setup Time for STOP Condition
tSU;STO
0.26
µs
tBUF
0.5
µs
Bus-Free Time Between
STOP and START
Capacitive Load for
Each Bus Line
Maximum Pulse Width of
Spikes That Must Be
Suppressed by the Input Filter
www.maximintegrated.com
CB
550
50
pF
ns
Maxim Integrated │ 4
MAX77826
Power Management IC
I2C Electrical Characteristics (continued)
(VSYS = VIN_ = +3.7V, VIO = 1.8V, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
CB = 100pF
MIN
TYP
CB = 400pF
MAX
MIN
TYP
MAX
UNITS
I2C-COMPATIBLE INTERFACE TIMING (HS MODE)
Clock Frequency
fSCL
3.4
1.7
MHz
Set-Up Time REPEATED
START Condition
tSU;STA
160
160
ns
Hold Time (REPEATED)
START Condition
tHD;STA
160
160
ns
CLK Low Period
tLOW
160
320
ns
CLK High Period
tHIGH
60
120
ns
DATA Setup time
tSU:DAT
10
DATA Hold Time
tHD:DAT
10
35
ns
75
ns
SCL Rise Time
(Note 3)
tRCL
TA = +25°C
10
40
20
80
ns
Rise Time of SCL Signal
After a REPEATED
START Condition and
After an Acknowledge Bit
(Note 3)
trCL1
TA = +25°C
10
80
20
160
ns
SCL Fall Time
(Note 3)
tfCL
TA = +25°C
10
40
20
80
ns
SDA Rise Time
(Note 3)
trDA
TA = +25°C
80
160
ns
SDA Fall Time
(Note 3)
tfDA
TA = +25°C
80
160
ns
Set-Up Time for STOP
Condition
Capacitive Load for Each
Bus Line
Maximum Pulse Width
of Spikes That Must Be
Suppressed by the Input
Filter
www.maximintegrated.com
tSU;STO
160
160
CB
ns
100
10
400
10
pF
ns
Maxim Integrated │ 5
MAX77826
Power Management IC
BUCK Electrical Characteristics
(VSYS = VINB = +3.7V, VFB_B = VOUT = 1.25V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 4)
PARAMETER
Input Voltage Range
CONDITIONS
Parametric
MIN
TYP
2.6
Shutdown Supply Current
(Note 3)
MAX
UNITS
5.5
V
0.1
Normal mode
22
Low power mode
8
µA
Supply Quiescent Current
(Note 3)
No switching,
No load
Output Voltage Range
I2C-programmable 6.25mV step
Output Voltage Accuracy
VINB = 2.6V to 4.5V,
VOUT = 1.25V, no load
Line Regulation
VINB = 2.6V to 4.5V
0.200
%/V
Load Regulation (Note 3)
VOUT = 1.25V
0.125
%/A
Transient Load Response,
VDROOP (Note 3)
VOUT = 1.25V, IOUT changes from 0A to 1.5A in 6µs,
COUT_ACTUAL = 22µF, L = 0.47µH
-50
mV
14
mV/µs
0.5
1.8
PWM mode, TA = +25°C
-1.0
+1.0
Low power mode
-3.0
+4.0
Soft-Start Slew Rate
RAMP[1:0] = 00b (default)
Output Voltage Ramp-Up Slew
Rate
Maximum Output Current
µA
V
%
12.5
RAMP[1:0] = 01b
25
RAMP[1:0] = 10b
50
RAMP[1:0] = 11b
100
Normal mode
mV/µs
3000
Low power mode
mA
10
Peak Current Limit
3.30
4.25
5.50
A
Valley Current Limit
3.825
A
Negative Current Limit
1.000
A
20
mA
N-FET Zero-Crossing
Threshold
Skip mode
Switching Frequency
1.8
2
2.2
MHz
Turn-On Delay Time
EN signal to LX switching with bias ON
30
µs
HS PMOS RDSON
VINB = 3.7V, INB to LX, ILX = 200mA
60
mΩ
LS NMOS RDSON
VINB = 3.7V, LX to PGNDB, ILX = 200mA
35
mΩ
Output Active Discharge
Resistance
Output disabled, resistance from FB_B to PGNDB
100
Ω
LX Leakage
VLXB = 5.5V or 0V
TA = +25°C
TA = +85°C
-1
0.1
1
+1
µA
POWER-OK COMPARATOR
Output POK Trip Level
VOUT POK rising threshold
90
%
Output POK Hysteresis
VOUT when VPOK switches
5
%
www.maximintegrated.com
Maxim Integrated │ 6
MAX77826
Power Management IC
BUCK BOOST Electrical Characteristics
(VINBB = +3.7V, VOUTBB = +3.5V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
GENERAL
Operating Input Voltage Range
Supplied from VSYS
Shutdown Supply Current
VINBB = 5.5V,
VOUTBB = 0V
Input Supply Current
Enabled, no
load
2.6
TA = +25°C
0.01
TA = +85°C
1
HSKIP mode (no switching)
60
µA
FPWM mode (switching)
9
mA
100
Ω
+165
°C
Active Discharge Resistance
Thermal Shutdown
µA
TA rising, 20°C hysteresis
H-BRIDGE
Maximum Output Current (Note 6)
VINBB = 3.0V, VOUTBB = 3.5V
2000
VINBB = 2.6V, VOUTBB = 3.5V
1500
mA
Default Output Voltage
No load, BB_VOUT[6:0] = 0x48
Output Voltage Accuracy
BB_VOUT[6:0] = 0x48,
no load
Output Voltage Range
I2C programmable (12.5mV step)
Line Regulation
VINBB = 2.6V to 5.5V
0.200
%/V
Load Regulation (Note 3)
VOUTBB = 3.5V
0.125
%/A
Transient Load Response, VDROOP
(Note 3)
VINBB = 3.8V, VOUTBB = 3.5V,
IOUT changes from 10mA to 1A in 10µs, COUT_
ACTUAL = 47µF, L = 1µH
-100
mV
Output Overvoltage Threshold
Switching Frequency
LXBB1, LXBB2 Leakage Current
With respect to
VOUTBB
3.5
PWM mode
-1.0
+1.0
HSKIP mode
TA = +25°C
-1.0
+4.0
2.6
4.1875
BB_OVP_TH[1:0] = 01b
110
BB_OVP_TH[1:0] = 10b
115
BB_OVP_TH[1:0] = 11b
(default)
120
2-phase BUCK or BOOST mode
1.6
3-phase mode
VLXBB1/2 = 0V or 5.5V,
VOUTBB = 5.5V, VSYS =
VINBB = 5.5V
LXBB1/2 Current Limit
V
1.8
0.1
TA = +85°C
0.2
3.5
4.5
V
%
2.0
0.9
TA = +25°C
%
1
5.5
MHz
µA
A
PMOS On-Resistance
ILXBB = 100mA, per switch
65
mΩ
NMOS On-Resistance
ILXBB = 100mA, per switch
55
mΩ
www.maximintegrated.com
Maxim Integrated │ 7
MAX77826
Power Management IC
BUCK BOOST Electrical Characteristics (continued)
(VINBB = +3.7V, VOUTBB = +3.5V, TA = -40°C to +85°C, typical values are at TA = +25°C, unless otherwise noted.) (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Effective Output
Capacitance
0µA < IOUT < 2000mA
16
µF
Turn-On Delay Time
From ENBB asserting to LXBB Switching with bias on
6
µs
Soft-Start Time
VOUTBB = 3.5V, IOUT = 10mA
40
µs
Output POK Trip Level
VOUTBB POK rising threshold
80
%
Output POK Hysteresis
VOUT when VPOK switches
5
%
POWER-OK COMPARATOR
LDO Electrical Characteristics
LDO
NO.
TYPE
VOUT
RANGE (V)
STEP SIZE
(mV)
IOUT
(max, mA)
DEFAULT
VOUT (V)
DEFAULT
ON/OFF
INPUT
PIN
COUT (µF)
1
NMOS
0.6–2.1875
12.5
600
1.0
Off
INL1
4.7
2
NMOS
0.6–2.1875
12.5
150
1.0
Off
INL1
1
3
NMOS
0.6–2.1875
12.5
450
1.0
Off
INL2
4.7
4
PMOSLV
0.8–3.975
25
300
1.5
Off
INL3
4.7
5
PMOSLV
0.8–3.975
25
300
1.8
Off
INL3
4.7
6
PMOSLV
0.8–3.975
25
150
1.8
Off
INL3
2.2
7
PMOSLV
0.8–3.975
25
300
1.8
Off
INL3
4.7
8
PMOSLV
0.8–3.975
25
150
1.8
Off
INL3
2.2
9
PMOSLV
0.8–3.975
25
150
1.8
Off
INL3
2.2
10
PMOSLS
0.8–3.975
25
300
2.8
Off
INL4
2.2
11
PMOSLS
0.8–3.975
25
150
2.8
Off
INL4
2.2
12
PMOSLS
0.8–3.975
25
300
3.3
Off
INL5
2.2
13
PMOSLS
0.8–3.975
25
300
3.3
Off
INL5
2.2
14
PMOSLS
0.8–3.975
25
150
3.3
Off
INL5
2.2
15
PMOSLS
0.8–3.975
25
150
3.3
Off
INL5
2.2
Note: LDO12 can also be enabled/disabled by external logic inputs, ENL12.
www.maximintegrated.com
Maxim Integrated │ 8
MAX77826
Power Management IC
LDO1 (600mA NMOS)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
CONDITIONS
VINLx must be lower than or equal to VSYS
Input Voltage Range
Input Supply Current
MIN
VSYS
VSYS
2.6
5.5
(Note 7)
1.5
Normal mode, no load
2
Low power mode, no load
2
Normal mode, no load
30
Low power mode, no load
4
Output Voltage Accuracy
Maximum Output Current
(Note 8)
Load Regulation
0.6
Maximum VOUT, Lx_VOUT[6:0] = 7’h7F
2.1875
Least significant step size
0.0125
Normal mode
IOUT = 0.1mA to IMAX
-2
Low power mode
IOUT = 0.1mA to 5mA
-5
Normal mode
µA
V
+2
%
+5
mA
5
Normal mode
IOUT = 0.1mA to IMAX
0.5
Low power mode
IOUT = 0.1mA to 5mA
0.5
%
Line Regulation
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
IOUT = 0.1mA
Normal mode
0.05
Low power mode
0.05
Dropout Voltage
Normal mode, IOUT = IMAX,
VDO = VINLx - VOUT
VSYS - VOUT = 2.5V
60
VSYS - VOUT = 1.5V
100
Output Current Limit
VOUT = 90% of
VOUT(TARGET)
Normal mode
900
Low power mode
10
Output Capacitance for Stability
DCR < 200mΩ, ESL < 20nH (Note 9)
www.maximintegrated.com
µA
600
Low power mode
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V)
V
< 0.1
Minimum VOUT, Lx_VOUT[6:0] = 7’h00
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
VINLx = VOUT + 0.3V to
VSYS
UNITS
< 0.1
Shutdown
Output Voltage Programming
MAX
VOUT
Shutdown
System Supply Current
TYP
2.35
4.7
%/V
150
1800
mV
mA
µF
Maxim Integrated │ 9
MAX77826
Power Management IC
LDO1 (600mA NMOS) (continued)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Output Noise
CONDITIONS
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
MIN
TYP
VSYS = 2.7V,
VINLx = 1.2V,
VOUT = VOUTMIN
30
VSYS = 2.7V,
VINLx = 1.8V,
VOUT = 1.0V
60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX
60
Power Supply Rejection
Normal mode, f = 1kHz, IOUT = 30mA
70
Output Load Transient
(ΔV/VOUT)
Normal mode, VSYS = 3.7V,
VINLx = 1.8V, VOUT = 1.0V,
IOUT = 1mA to ½ x IMAX to
1mA, tRISE = tFALL = 1µs
COUT = 4.7µF
±5
COUT = 10µF
±3
VSYS = VINLx = 3.7V to
3.2V to 3.7V
5
Output Line Transient
Normal mode, VOUT = 1.0V,
IOUT = 1mA, tRISE = tFALL
= 5µs
VSYS = 3.7V, VINLx =
1.8V to 1.5V to 1.8V
5
MAX
UNITS
µVRMS
dB
%
mV
Output Startup Ramp Rate
10% to 90%
30
mV/µs
Turn-On Delay Time
From Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled.
5
µs
50
mV
(Note 10)
100
Ω
TJ rising
165
TJ falling
150
Output POK Trip Level
Rising edge, VOUT when VPOK switches
87.5
%
Output POK Hysteresis
VOUT when VPOK switches
5
%
Output Overshoot during Startup
Overshoot
Output Active Discharge
Resistance
Thermal Shutdown
°C
POWER-OK COMPARATOR
www.maximintegrated.com
Maxim Integrated │ 10
MAX77826
Power Management IC
LDO2 (150mA NMOS)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 1.0µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
CONDITIONS
VINLx must be lower than or equal to VSYS
Input Voltage Range
Input Supply Current
MIN
VSYS
VSYS
2.6
5.5
(Note 7)
1.5
Normal mode, no load
2
Low power mode, no load
2
Normal mode, no load
25
Low power mode, no load
3
Output Voltage Accuracy
Maximum Output Current
(Note 8)
Load Regulation
< 0.1
Maximum VOUT, Lx_VOUT[6:0] = 7’h7F
2.1875
Least significant step size
0.0125
Normal mode
IOUT = 0.1mA to IMAX
-2
Low power mode
IOUT = 0.1mA to 5mA
-5
Normal mode
V
+2
%
+5
150
Low power mode
mA
5
Normal mode
IOUT = 0.1mA to IMAX
0.5
Low power mode
IOUT = 0.1mA to 5mA
0.5
%
Line Regulation
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
IOUT = 0.1mA
Normal mode
0.05
Low power mode
0.05
Dropout Voltage
Normal mode,
IOUT = IMAX,
VDO = VINLx - VOUT
VSYS - VOUT = 2.5V
60
VSYS - VOUT = 1.5V
100
Output Current Limit
VOUT = 90% of VOUT
Normal mode
225
(TARGET)
Low power mode
10
Output Capacitance for Stability
DCR < 200mΩ, ESL < 20nH (Note 9)
www.maximintegrated.com
µA
0.6
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V)
V
µA
Minimum VOUT, Lx_VOUT[6:0] = 7’h00
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
VINLx = VOUT + 0.3V to
VSYS
UNITS
< 0.1
Shutdown
Output Voltage Programming
MAX
VOUT
Shutdown
System Supply Current
TYP
0.5
1.0
%/V
150
450
mV
mA
µF
Maxim Integrated │ 11
MAX77826
Power Management IC
LDO2 (150mA NMOS) (continued)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 1.0µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Output Noise
CONDITIONS
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
MIN
TYP
VSYS = 2.7V,
VINLx = 1.2V,
VOUT = VOUTMIN
30
VSYS = 2.7V,
VINLx = 1.8V,
VOUT = 1.0V
60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX
60
Power Supply Rejection
Normal mode, f = 1kHz, IOUT = 30mA
70
Output Load Transient
(ΔV/VOUT)
Normal mode, VSYS = 3.7V,
VINLx = 1.8V, VOUT = 1.0V,
IOUT = 1mA to ½ x IMAX to
1mA, tRISE = tFALL = 1µs
COUT = 1.0µF
±5
COUT = 10µF
±3
VSYS = VINLx = 3.7V to
3.2V to 3.7V
5
Output Line Transient
Normal mode, VOUT = 1.0V,
IOUT = 1mA, tRISE = tFALL
= 5µs
VSYS = 3.7V, VINLx = 1.8V
to 1.5V to 1.8V
5
MAX
UNITS
µVRMS
dB
%
mV
Output Startup Ramp Rate
10% to 90%
30
mV/µs
Turn-On Delay Time
From Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled.
5
µs
50
mV
(Note 10)
100
Ω
TJ rising
165
TJ falling
150
Output POK Trip Level
Rising edge, VOUT when VPOK switches
87.5
%
Output POK Hysteresis
VOUT when VPOK switches
5
%
Output Overshoot During
Startup Overshoot
Output Active Discharge
Resistance
Thermal Shutdown
°C
POWER-OK COMPARATOR
www.maximintegrated.com
Maxim Integrated │ 12
MAX77826
Power Management IC
LDO3 (450mA NMOS)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
CONDITIONS
VINLx must be lower than or equal to VSYS
Input Voltage Range
Input Supply Current
MIN
VSYS
VSYS
2.6
5.5
(Note 7)
1.5
Normal mode, no load
2
Low power mode, no load
2
Normal mode, no load
25
Low power mode, no load
3
Output Voltage Accuracy
Maximum Output Current
(Note 8)
Load Regulation
µA
< 0.1
0.6
Maximum VOUT, Lx_VOUT[6:0] = 7’h7F
2.1875
Least significant step size
0.0125
Normal mode
IOUT = 0.1mA to IMAX
-2
Low power mode
IOUT = 0.1mA to 5mA
-5
Normal mode
+2
%
+5
mA
5
Normal mode
IOUT = 0.1mA to IMAX
0.5
Low power mode
IOUT = 0.1mA to 5mA
0.5
%
Line Regulation
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
IOUT = 0.1mA
Normal mode
0.05
Low power mode
0.05
Dropout Voltage
Normal Mode, IOUT = IMAX,
VDO = VINLx - VOUT
VSYS - VOUT = 2.5V
60
VSYS - VOUT = 1.5V
100
VOUT = 90% of VOUT
Normal mode
675
(TARGET)
Low power mode
10
Output Current Limit
Output Capacitance for Stability
www.maximintegrated.com
DCR < 200mΩ, ESL < 20nH
(Note 9)
V
450
Low power mode
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V)
V
µA
Minimum VOUT, Lx_VOUT[6:0] = 7’h00
VSYS ≥ VOUT + 1.5V
(VSYSMIN = 2.6V),
VINLx = VOUT + 0.3V to VSYS
UNITS
< 0.1
Shutdown
Output Voltage Programming
MAX
VOUT
Shutdown
System Supply Current
TYP
2.35
4.7
%/V
150
1350
mV
mA
µF
Maxim Integrated │ 13
MAX77826
Power Management IC
LDO3 (450mA NMOS) (continued)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 1.0µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Output Noise
CONDITIONS
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
MIN
TYP
VSYS = 2.7V,
VINLx = 1.2V,
VOUT = VOUTMIN
30
VSYS = 2.7V,
VINLx = 1.8V,
VOUT = 1.0V
60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX
60
Power-Supply Rejection
Normal mode, f = 1kHz, IOUT = 30mA
70
Output Load Transient
(ΔV/VOUT)
Normal mode, VSYS = 3.7V,
VINLx = 1.8V, VOUT = 1.2V,
IOUT = 1mA to ½ x IMAX to
1mA, tRISE = tFALL = 1µs
COUT = 4.7µF
±5
COUT = 10µF
±3
Output Line Transient
Normal mode, VOUT
= 1.2V, IOUT = 1mA,
tRISE = tFALL = 5µs
MAX
UNITS
µVRMS
dB
%
VSYS = VINLx = 3.7V to 3.2V to
3.7V
5
VSYS = 3.7V, VINLx = 1.8V to 1.5V
to 1.8V
5
mV
Output Startup Ramp Rate
10% to 90%
30
mV/µs
Turn-On Delay Time
From Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled
5
µs
50
mV
(Note 10)
100
Ω
TJ rising
165
TJ falling
150
Output POK Trip Level
Rising edge, VOUT when VPOK switches
87.5
%
Output POK Hysteresis
VOUT when VPOK switches
5
%
Output Overshoot during Startup
Overshoot
Output Active Discharge
Resistance
Thermal Shutdown
°C
POWER-OK COMPARATOR
www.maximintegrated.com
Maxim Integrated │ 14
MAX77826
Power Management IC
LDO4, LDO5 and LDO7 (300mA PMOSLV)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Input Voltage Range
Input Supply Current
CONDITIONS
VINLx must be lower than or equal to VSYS
MIN
1.7
Normal mode, no load
15
Low power mode, no load
1.5
Shutdown
Low power mode, no load
Output Voltage Accuracy
Maximum Output Current
(Note 8)
Load Regulation
µA
< 0.1
Maximum VOUT, Lx_VOUT[6:0] = 7’h7F
3.975
Least significant step size
0.025
V
Normal mode
IOUT = 0.1mA to IMAX
-2
+2
Low power mode
IOUT = 0.1mA to 5mA
-5
+5
Normal mode
%
300
Low power mode
mA
5
Normal mode
IOUT = 0.1mA to IMAX
0.5
Low power mode
IOUT = 0.1mA to 5mA
0.5
%
Line Regulation
VINLx = VOUT + 0.3V to
VSYS, IOUT = 0.1mA
Normal mode
0.05
Low power mode
0.05
VINLx = 3.7V
60
Dropout Voltage
Normal mode,
VSYS = 3.7V,
IOUT = IMAX,
VDO = VINLx - VOUT
VINLx = 1.7V
100
Output Current Limit
VOUT = 90% of
VOUT(TARGET)
Normal mode
600
Low power mode
40
Output Capacitance for Stability
DCR < 200mΩ, ESL < 20nH
(Note 9)
www.maximintegrated.com
V
0.3
0.8
VINLx = VOUT + 0.3V
VSYS
µA
Minimum VOUT, Lx_VOUT[6:0] = 7’h00
VINLx = VOUT + 0.3V to
VSYS
UNITS
3
Shutdown
Output Voltage Programming
MAX
< 0.1
Normal mode, no load
System Supply Current
TYP
%/V
150
mV
2.35
4.7
1120
mA
µF
Maxim Integrated │ 15
MAX77826
Power Management IC
LDO4, LDO5 and LDO7 (300mA PMOSLV) (continued)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 4.7µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Output Noise
CONDITIONS
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
25
VSYS = VINLx = 2.7V,
VOUT = 1.0V
30
VSYS = VINLx = 2.7V,
VOUT = 2.0V
40
VSYS = VINLx = 3.7V,
VOUT = 3.0V
60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX
60
Normal mode, f = 1kHz, IOUT = 30mA
Output Load Transient
(ΔV/VOUT)
Normal mode,
VSYS = VINLx = 3.7V,
VOUT = default,
IOUT = 1mA to ½ x IMAX
to 1mA,
tRISE = tFALL = 1µs
Output Line Transient
TYP
VSYS = VINLx = 2.7V,
VOUT = VOUTMIN
Power Supply Rejection
Normal mode,
VOUT = 1.2V,
IOUT = 1mA,
tRISE = tFALL = 5µs
MIN
COUT = 4.7µF
MAX
UNIT
µVRMS
70
dB
±5
%
COUT = 10µF
±3
VSYS = VINLx = 3.7V to 3.2V
to 3.7V
5
VSYS = 3.7V,
VINLx = 2.0V to 1.7V to 2.0V
5
mV
Output Startup Ramp Rate
10% to 90%
30
mV/µs
Turn-On Delay Time
From Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled
5
µs
50
mV
(Note 10)
100
Ω
TJ rising
+165
TJ falling
+150
Output POK Trip Level
Rising edge, VOUT when VPOK switches
87.5
%
Output POK Hysteresis
VOUT when VPOK switches
3
%
Output Over-shoot during
Startup Over-shoot
Output Active Discharge
Resistance
Thermal Shutdown
°C
POWER-OK COMPARATOR
www.maximintegrated.com
Maxim Integrated │ 16
MAX77826
Power Management IC
LDO6, LDO8, and LDO9 (150mA PMOSLV)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Input Voltage Range
Input Supply Current
CONDITIONS
VINLx must be lower than or equal to VSYS
MIN
1.7
Normal mode, no load
15
Low power mode, no load
1.5
Shutdown
Low power mode, no load
Output Voltage Accuracy
Maximum Output Current
(Note 8)
Load Regulation
µA
< 0.1
Maximum VOUT, Lx_VOUT[6:0] = 7’h7F
3.975
Least significant step size
0.025
V
Normal mode
IOUT = 0.1mA to IMAX
-2
+2
Low power mode
IOUT = 0.1mA to 5mA,
-5
+5
Normal mode
%
150
Low power mode
mA
5
Normal mode
IOUT = 0.1mA to IMAX
0.5
Low power mode
IOUT = 0.1mA to 5mA
0.5
%
Line Regulation
VINLx = VOUT + 0.3V to
VSYS, IOUT = 0.1mA
Normal mode
0.05
Low power mode
0.05
Dropout Voltage
Normal mode, VSYS = 3.7V,
IOUT = IMAX,
VDO = VINLx - VOUT
VINLx = 3.7V
60
VINLx = 1.7V
100
Output Current Limit
VOUT = 90% of
VOUT(TARGET)
Normal mode
300
Low power mode
40
Output Capacitance for Stability
DCR < 200mΩ, ESL < 20nH
(Note 9)
www.maximintegrated.com
V
0.3
0.8
VINLx = VOUT + 0.3V
VSYS
µA
Minimum VOUT, Lx_VOUT[6:0] = 7’h00
VINLx = VOUT + 0.3V
to VSYS
UNITS
3
Shutdown
Output Voltage Programming
MAX
< 0.1
Normal mode, no load
System Supply Current
TYP
1.1
2.2
%/V
150
560
mV
mA
µF
Maxim Integrated │ 17
MAX77826
Power Management IC
LDO6, LDO8, and LDO9 (150mA PMOSLV) (continued)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Output Noise
CONDITIONS
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
MIN
TYP
VSYS = VINLx = 2.7V,
VOUT = VOUTMIN
25
VSYS = VINLx = 2.7V,
VOUT = 1.0V
30
VSYS = VINLx = 2.7V,
VOUT = 2.0V
40
VSYS = VINLx = 3.7V,
VOUT = 3.0V
60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX
60
Power Supply Rejection
Normal mode, f = 1kHz, IOUT = 30mA
Output Load Transient
(ΔV/VOUT)
Normal mode,
VSYS = VINLx = 3.7V,
VOUT = default,
IOUT = 1mA to ½ x IMAX to
1mA, tRISE = tFALL = 1µs
Output Line Transient
Normal mode, VOUT = 1.2V,
IOUT = 1mA,
tRISE = tFALL = 5µs
COUT = 2.2µF
MAX
UNITS
µVRMS
70
dB
±5
%
COUT = 10µF
±3
VSYS = VINLx = 3.7V to
3.2V to 3.7V
5
VSYS = 3.7V, VINLx =
2.0V to 1.7V to 2.0V
5
mV
Output Startup Ramp Rate
10% to 90%
30
mV/µs
Turn-On Delay Time
From Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled
5
µs
50
mV
(Note 10)
100
Ω
TJ rising
+165
TJ falling
+150
Output POK Trip Level
Rising edge, VOUT when VPOK switches
87.5
%
Output POK Hysteresis
VOUT when VPOK switches
3
%
Output Overshoot During
Startup Overshoot
Output Active Discharge
Resistance
Thermal Shutdown
°C
POWER-OK COMPARATOR
www.maximintegrated.com
Maxim Integrated │ 18
MAX77826
Power Management IC
LDO11, LDO14 and LDO15 (150mA PMOSLS)
(VSYS = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Input Voltage Range
Input Supply Current
System Supply Current
Output Voltage Programming
Output Voltage Accuracy
Maximum Output Current
(Note 8)
Load Regulation
CONDITIONS
TYP
MAX
VINLx
2.6
5.5
VSYS
2.6
5.5
Normal mode, no load
15
Low power mode, no load
4
< 0.1
Normal mode, no load
3.25
Low power mode, no load
0.85
Shutdown
< 0.1
Minimum VOUT, Lx_VOUT[6:0] = 7’h00
0.8
Maximum VOUT, Lx_VOUT[6:0] = 7’h7F
3.975
Least significant step size
0.025
VINLx = VOUT + 0.3V to
VSYS
Normal mode
IOUT = 0.1mA to IMAX
-2
Low power mode
IOUT = 0.1mA to 5mA
-5
Normal mode
VINLx = VOUT + 0.3V
V
+2
%
+5
mA
5
Normal mode
IOUT = 0.1mA to IMAX
0.5
Low power mode
IOUT = 0.1mA to 5mA
0.5
Normal mode
0.05
Low power mode
0.05
VINLx = VOUT + 0.3V to
VSYS, IOUT = 0.1mA
Dropout Voltage
Normal mode, VSYS = VINLx = 3.7V,
IOUT = IMAX, VDO = VINLx - VOUT
Output Current Limit
VOUT = 90% of
VOUT(TARGET)
Output Capacitance for Stability
DCR < 200mΩ, ESL < 20nH (Note 9)
V
µA
150
Low power mode
UNITS
µA
Shutdown
Line Regulation
www.maximintegrated.com
MIN
%
%/V
100
200
Normal mode
300
560
Low power mode
40
0.6
2.2
mV
mA
µF
Maxim Integrated │ 19
MAX77826
Power Management IC
LDO11, LDO14 and LDO15 (150mA PMOSLS) (continued)
(VSYS = VINLx = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Output Noise
CONDITIONS
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
MIN
TYP
VSYS = VINLx = 2.7V,
VOUT = VOUTMIN
25
VSYS = VINLx = 2.7V,
VOUT = 1.0V
30
VSYS = VINLx = 2.7V,
VOUT = 2.0V
40
VSYS = VINLx = 3.7V,
VOUT = 3.0V
60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX
60
MAX
UNITS
µVRMS
Power Supply Rejection
Normal mode, f = 1kHz, IOUT = 30mA
Output Load Transient
(ΔV/VOUT)
Normal mode,
VSYS = VINLx = 3.7V,
VOUT = default, IOUT =
1mA to ½ x IMAX to 1mA,
tRISE = tFALL = 1µs
Output Line Transient
Normal mode, VINLx = 3.7V to 3.2V to 3.7V,
VOUT = default, IOUT = 1mA, tRISE = tFALL = 5µs
5
mV
Output Startup Ramp Rate
10% to 90%
30
mV/µs
Turn-On Delay Time
From Lx_EN = 1 to output rising, REFBYP enabled >
300µs prior to LDO being enabled
5
µs
50
mV
(Note 10)
100
Ω
TJ rising
165
TJ falling
150
Output POK Trip Level
Rising edge, VOUT when VPOK switches
87.5
%
Output POK Hysteresis
VOUT when VPOK switches
3
%
COUT = 2.2µF
Thermal Shutdown
dB
±5
%
COUT = 10µF
Output Overshoot During
Startup Overshoot
Output Active Discharge
Resistance
70
±3
°C
POWER-OK COMPARATOR
www.maximintegrated.com
Maxim Integrated │ 20
MAX77826
Power Management IC
LDO10, LDO12 and LDO13 (300mA PMOSLS)
(VSYS = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Input Voltage Range
Input Supply Current
System Supply Current
Output Voltage Programming
Output Voltage Accuracy
Maximum Output Current
(Note 8)
Load Regulation
CONDITIONS
TYP
MAX
VINLx
2.6
5.5
VSYS
2.6
5.5
Normal mode, no load
15
Low power mode, no load
4
< 0.1
Normal mode, no load
3.25
Low power mode, no load
0.85
Shutdown
< 0.1
Minimum VOUT, Lx_VOUT[6:0] = 7’h00
0.8
Maximum VOUT, Lx_VOUT[6:0] = 7’h7F
3.975
Least significant step size
0.025
VINLx = VOUT + 0.3V to
VSYS
Normal mode
IOUT = 0.1mA to IMAX
-2
Low power mode
IOUT = 0.1mA to 5mA
-5
Normal mode
VINLx = VOUT + 0.3V
V
+2
%
+5
mA
5
Normal mode
IOUT = 0.1mA to IMAX
0.5
Low power mode
IOUT = 0.1mA to 5mA
0.5
Normal mode
0.05
Low power mode
0.05
VINLx = VOUT + 0.3V to
VSYS, IOUT = 0.1mA
Dropout Voltage
Normal mode, VSYS = VINLx = 3.7V,
IOUT = IMAX, VDO = VINLx - VOUT
Output Current Limit
VOUT = 90% of
VOUT(TARGET)
Output Capacitance for Stability
DCR < 200mΩ, ESL < 20nH (Note 9)
V
µA
300
Low power mode
UNITS
µA
Shutdown
Line Regulation
www.maximintegrated.com
MIN
%
%/V
100
200
Normal mode
600
1120
Low power mode
40
0.6
2.2
mV
mA
µF
Maxim Integrated │ 21
MAX77826
Power Management IC
LDO10, LDO12 and LDO13 (300mA PMOSLS) (continued)
(VSYS = +3.7V, CSYS = 1.0µF, COUT = 2.2µF, CREFBYP = 100nF, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
Output Noise
CONDITIONS
Normal mode,
f = 10Hz to 100kHz,
IOUT = 10% of IMAX
MIN
TYP
VSYS = VINLx = 2.7V,
VOUT = VOUTMIN
25
VSYS = VINLx = 2.7V,
VOUT = 1.0V
30
VSYS = VINLx = 2.7V,
VOUT = 2.0V
40
VSYS = VINLx = 3.7V,
VOUT = 3.0V
60
VSYS = VINLx = 5.5V,
VOUT = VOUTMAX
60
MAX
UNITS
µVRMS
Power Supply Rejection
Normal mode, f = 1kHz, IOUT = 30mA
Output Load Transient
(ΔV/VOUT)
Normal mode,
VSYS = VINLx = 3.7V,
VOUT = default, IOUT =
1mA to ½ x IMAX to 1mA,
tRISE = tFALL = 1µs
Output Line Transient
Normal mode, VINLx = 3.7V to 3.2V to 3.7V, VOUT =
default, IOUT = 1mA, tRISE = tFALL = 5µs
5
mV
Output Startup Ramp Rate
10% to 90%
30
mV/µs
Turn-On Delay Time
From Lx_EN = 1 (or ENL12 = high) to output rising,
REFBYP enabled > 300µs prior to LDO being enabled
5
µs
50
mV
(Note 10)
100
Ω
TJ rising
+165
TJ falling
+150
Output POK Trip Level
Rising edge, VOUT when VPOK switches
87.5
%
Output POK Hysteresis
VOUT when VPOK switches
3
%
COUT = 2.2µF
Thermal Shutdown
dB
±5
%
COUT = 10µF
Output Overshoot During
Startup Overshoot
Output Active Discharge
Resistance
70
±3
°C
POWER-OK COMPARATOR
Note 3: Guaranteed by design. Not production tested.
Note 4: 100% production tested at TA = +25°C, limits over the operating range are guaranteed by design.
Note 5: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through
correlation using statistical quality control methods.
Note 6: The maximum output current spec is not directly tested. Instead, it is guaranteed by LX NMOS current limit test.
Note 7: For NMOS LDOs, VSYS must be at least 1.5V above VOUT (VSYS ≥ VOUT + 1.5V).
Note 8: The maximum output current is guaranteed by the output voltage accuracy tests.
Note 9: For stability, guaranteed by design and not production tested.
Note 10: There is an n-channel MOSFET in series with the output active discharge resistance. This NMOS requires VSYS > 1.2V to
be enhanced.
www.maximintegrated.com
Maxim Integrated │ 22
MAX77826
Power Management IC
Pin Configurations
MAX77826
1
2
3
4
5
6
7
A
INB
INB
SYS
LDO1
LDO3
LDO7
LDO6
B
LXB
LXB
FB_B
INL1
INL2
LDO8
LDO5
C
PGNDB
PGNDB
VIO
CE
REFBYP
LDO2
INL3
D
LDO12
LDO15
SDA
SCL
ENB
LDO9
LDO4
E
LDO13
LDO14
IRQB
ENL12
FB_BB
ENBB
GND
F
INL5
INL4
OUTBB
LXBB2
PGNDBB
LXBB1
INBB
G
LDO10
LDO11
OUTBB
LXBB2
PGNDBB
LXBB1
INBB
+
Pin Description
PIN
NAME
FUNCTION
C4
CE
Active-High Chip Enable Input. When CE = high (standby), the I2C interface is enabled
and regulators are ready to be turned on. When CE = low (shutdown), all regulators
are turned off and all Type-O registers are reset to their POR default values.
D5
ENB
E6
ENBB
Active-High BUCK BOOST External Enable Input. An 800kΩ internal pulldown
resistance to the GND. If this pin is not used, leave it unconnected.
E4
ENL12
Active-High LDO12 External Enable Input. An 800kΩ internal pulldown resistance to
the GND. If this pin is not used, leave it unconnected.
B3
FB_B
BUCK Output Voltage Feedback
E5
FB_BB
E7
GND
Ground
A1, A2
INB
BUCK Input. Bypass to PGNDB with a 10µF capacitor.
F7, G7
INBB
www.maximintegrated.com
Active-High BUCK External Enable Input. An 800kΩ internal pull-down resistance to
the GND. If this pin is not used, leave it floating.
BUCK BOOST Output Voltage Feedback
BUCK BOOST Input
Maxim Integrated │ 23
MAX77826
Power Management IC
Pin Description (continued)
PIN
NAME
B4
INL1
Input for LDO1 and 2. Bypass to GND with a 4.7µF capacitor.
B5
INL2
Input for LDO3. Bypass to GND with a 1µF capacitor.
C7
INL3
Input for LDO4, 5, 6, 7, 8, and 9. Bypass to GND with a 4.7µF capacitor.
F2
INL4
Input for LDO10 and 11. Bypass to GND with a 4.7µF capacitor.
F1
INL5
Input for LDO12, 13, 14, and 15. Bypass to GND with a 4.7µF capacitor.
E3
IRQB
Interrupt Output. A 100kΩ external pullup resistor to VIO is required.
B1, B2
LXB
BUCK Switching Node
F6, G6
LXBB1
BUCK BOOST Switching Node 1
F4, G4
LXBB2
BUCK BOOST Switching Node 2
A4
LDO1
LDO1 (600mA NMOS) Output. Bypass to GND with a 4.7µF capacitor.
C6
LDO2
LDO2 (150mA NMOS) Output. Bypass to GND with a 1µF capacitor.
A5
LDO3
LDO3 (450mA NMOS) Output. Bypass to GND with a 4.7µF capacitor.
D7
LDO4
LDO4 (300mA PMOSLV) Output. Bypass to GND with a 4.7µF capacitor.
B7
LDO5
LDO5 (300mA PMOSLV) Output. Bypass to GND with a 4.7µF capacitor.
A7
LDO6
LDO6 (150mA PMOSLV) Output. Bypass to GND with a 2.2µF capacitor.
A6
LDO7
LDO7 (300mA PMOSLV) Output. Bypass to GND with a 4.7µF capacitor.
B6
LDO8
LDO8 (150mA PMOSLV) Output. Bypass to GND with a 2.2µF capacitor.
D6
LDO9
LDO9 (150mA PMOSLV) Output. Bypass to GND with a 2.2µF capacitor.
G1
LDO10
LDO10 (300mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.
G2
LDO11
LDO11 (150mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.
D1
LDO12
LDO12 (300mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.
E1
LDO13
LDO13 (300mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.
E2
LDO14
LDO14 (150mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.
D2
LDO15
LDO15 (150mA PMOSLS) Output. Bypass to GND with a 2.2µF capacitor.
F3, G3
OUTBB
BUCK BOOST Output
C1, C2
PGNDB
BUCK Power GND
F5, G5
PGNDBB
BUCK BOOST Power GND
C5
REFBYP
LDO Reference Bypass Node. Connect a 0.1µF Cap to GND.
D4
SCL
I2C Clock Input. High Impedance in Off State.
A 1.5kΩ~2.2kΩ of pullup resistor to VIO is required.
D3
SDA
I2C Data I/O. High Impedance in Off State. A 1.5kΩ–2.2kΩ of pullup resistor to VIO is
required.
A3
SYS
System (Battery) Voltage Input. Bypass to GND with a 1µF capacitor.
C3
VIO
IO Supply Voltage Input. Bypass to GND with a 0.1µF capacitor.
www.maximintegrated.com
FUNCTION
Maxim Integrated │ 24
MAX77826
Power Management IC
Block Diagram
SYS
GND
REFBYP
INB
SBIAS, REF, UVLO,
TSHDN
BUCK
3A
FB_B
LXB
PGNDB
VIO
800kΩ
VIO
ENB
IRQB
INBB
SCL
LXBB1
SDA
BUCK-BOOST
2A
CE
MAX77826
INL1
LDO1
LDO1
(N600)
LDO2
LDO2
(N150)
INL2
LDO3
LXBB2
FB_BB
OUTBB
PGNDBB
800kΩ
ENBB
ON/OFF CONTROL
AND
I2C INTERFACE
INL4
LDO3
(N450)
INL3
LDO10
(P300LS)
LDO10
LDO11
(P150LS)
LDO11
LDO4
LDO4
(P300LV)
ENL12
LDO5
LDO5
(P300LV)
INL5
LDO6
LDO6
(P150LV)
LDO7
LDO7
(P300LV)
LDO8
LDO9
www.maximintegrated.com
LDO12
(P300LS)
LDO12
LDO13
(P300LS)
LDO13
LDO8
(P150LV)
LDO14
(P150LS)
LDO14
LDO9
(P150LV)
LDO15
(P150LS)
LDO15
800kΩ
Maxim Integrated │ 25
MAX77826
Detailed Description
Top System Management
System Faults
The MAX77826 monitors the system for the following
faults: global thermal, local thermal shutdown, and undervoltage lockout.
Global Thermal Fault
The MAX77826 has a centralized thermal protection
circuit which monitors temperature on the die. If the die
temperature exceeds +165°C (TSHDN), a thermal shutdown event initiates, and the MAX77826 enters its global
shutdown state.
In addition to the +165°C threshold, there are two additional comparators that trip at +120°C and +140°C.
Interrupts are generated in the event the die temperature
reaches +120°C or +140°C.
There is a 15°C thermal hysteresis. After the thermal shutdown, if the die temperature reduces by 15°C, the thermal
shutdown bus deasserts.
Local Thermal Shutdown
If any of the BUCK BOOST or LDOs reach the thermal
shutdown threshold, the MAX77826 shuts down the corresponding block locally. If the temperature goes below a
threshold, that block goes back to normal operation.
Undervoltage Lockout
When VSYS falls below VUVLO_F (typ 2.05V), the
MAX77826 enters its undervoltage lockout (UVLO) mode.
UVLO forces the MAX77826 to a dormant state until the
source voltage is high enough to allow the MAX77826
to be securely functional. I2C does not function and the
Type-O register contents are reset to their default values
in UVLO mode. UVLO rising threshold is set to 2.5V by
an OTP option.
Chip Enable (CE)
A logic-high on CE pin puts the MAX77826 into standby
mode (enabled). In standby mode, all user registers are
accessible through I2C so that the host processor can
www.maximintegrated.com
Power Management IC
overwrite the default output voltages of regulators and
each regulator can be enabled by either I2C or the GPIO
input if applicable.
When the CE pin goes high, the MAX77826 turns on the
top-level bias circuitry, and it takes typically 85µs to settle.
As soon as the top-level bias is ready, BUCK BOOST is
ready to be turned on. However, BUCK and LDOs require
additional 85µs (typ) for REFBYP to settle. Total, it takes
170µs (85µs + 85µs) for REFBYP to settle from CE =
high. In the worst-case scenario, it can take up to 230µs.
Once REFBYP is ready, all the regulators are allowed
to be tuned on through I2C or the ENx pins. In case the
regulars are enabled before the bias circuitry is ready, the
regulators require longer time to startup.
When CE pin is pulled low, the MAX77826 goes into
shutdown mode (disabled) and turns off all the regulators
regardless of ENx pins. This event also resets all Type-O
registers to their POR default values.
Immediate Shutdown Events
The following events initiate immediate shutdown: thermal protection (TJ > +165°C), VSYS < VSYS UVLO
falling threshold (VUVLO_F), VIO < VIO OK threshold
(VTH_VIO_OK)
The events in this category are associated with potentially
hazardous system states. Powering down the host processor and resetting all Type-O registers help mitigate any
issues that can occur due to these potentially hazardous
conditions. Note that the MAX77826 cannot be enabled
until the junction temperature drops below +150°C in case
thermal protection caused the immediate shutdown.
Operating Mode (OPMD)
Each regulator (BUCK, BUCK BOOST, and LDO) has
independent register bits to control its operating mode.
These bits determines on/off operation during initial
startup, output enable control, and sleep mode operation
based on the enable control logic of each regulator. The
POR default values of output enable bits (x_EN) are 0
(output off).
Maxim Integrated │ 26
MAX77826
Power Management IC
Enable Control Logic1
Interrupt and Mask
BUCK, BUCK BOOST, and LDO12 have independent
I2C enable bits and dedicated GPIO enable pins (ENB,
ENBB, and ENL12). As shown in Table 1, regulators can
be turned on/off by ENx or I2C control bits.
IRQB pin is used to indicate to the host processor that
the status on the MAX77826 has changed. IRQB signal is
asserted whenever one or more interrupts are triggered.
The host processor reads the interrupt source register
(ADDR 0x00) and the interrupt registers as indicated by
the interrupt source register in order to see the cause of
interrupt event.
Enable Control Logic 2
LDO1–LDO11 and LDO13–LDO15 have independent I2C
enable bits. As shown in Table 2, regulators can be turned
on/off by the I2C control bits.
Reset Conditions
System Reset
When VSYS voltage drops below its POR threshold
(≈1.55V), all Type-S1 registers are reset to their POR
default values.
Off Reset
Off reset occurs by any power-off events. This condition
resets all Type-O registers to their POR default values.
Table 1. Enable Control
Logic 1 Truth Table
CE
ENx
B_EN
BB_EN
L12_EN
B_LPM
L12_LPM
Low
x
x
x
Device off
High
Low
0
x
Output off
High
High
x
1
Output on (low
power mode*)
Each interrupt can be masked (disabled) by setting the
corresponding interrupt mask register bit. In case an interrupt mask bit is set (masked), the corresponding interrupt
bit is not supposed to be set even when the interrupt condition is met. As a result, the IRQB pin stays high for this
event. If the mask bit is cleared for an active interrupt, the
corresponding interrupt bit is set to pull the IRQB pin low.
OPERATING
MODE
High
High
x
0
Output on
High
x
1
1
Output on (low
power mode*)
High
x
1
0
Output on
*The BUCK BOOST regulator does not have a low power
mode.
Table 2. Enable Control
Logic 2 Truth Table
CE
Lx_EN
Lx_LPM
Low
x
x
Device off
High
0
x
Output off
High
1
1
Output on
(low power mode)
High
1
0
Output on
www.maximintegrated.com
Each interrupt register can be read at a time. IRQB pin
goes high (cleared) as soon as the read sequence finishes. If an interrupt is captured during the read sequence,
IRQB pin is held low. Note that the interrupt source register is cleared when the corresponding interrupt registers
are read by the host processor.
OPERATING MODE
CE
B_EN (I2C)
B_LPM (I2C)
BB_EN (I2C)
L12_EN (I2C)
EN
LOGIC 1
LPM
BUCK,
BUCK BOOST,
LDO12
L12_LPM (I2C)
LOGIC 1: OPERATING
MODE CONTROL
ENx
Figure 1. Enable Control Logic 1
CE
Lx_EN (I2C)
Lx_LPM (I2C)
EN
LOGIC 2
LPM
LDO1– LDO11,
LDO13–LDO15
LOGIC 2: OPERATING
MODE CONTROL
Figure 2. Enable Control Logic 2
Maxim Integrated │ 27
MAX77826
BUCK Regulator
The MAX77826 includes a 3A current-mode BUCK regulator. In normal operation, BUCK consumes only 22µA
quiescent current. In low power mode, the quiescent
current is decreased to 8µA with reduced load capability.
The summary of features is:
●● 3A of maximum output current rating
●● 2.6V to 5.5V input voltage range
Power Management IC
The BUCK regulator supports starting into a prebiased
output. For example, if the output capacitor has an initial voltage of 0.4V when the regulator is enabled, the
regulator gradually increases the capacitor voltage to the
required target voltage such as 1.0V. This is unlike other
regulators without the start into prebias feature in which
they can force the output capacitor voltage to 0V before
the soft-start ramp begins.
●● Automatic SKIP/PWM or forced PWM modes
The BUCK regulator has a soft-start rate of 14mV/µs. The
controlled soft-start rate and BUCK regulator current limit
(ILIMP) limit the input inrush current to the output capacitor (IINRUSH). IINRUSH = min (ILIMP and COUT x dv/dt).
Note that the input current of BUCK regulator is lower
than the inrush current to the output capacitor by the ratio
of output to input voltage.
●● > 90% peak efficiency
Output Voltage Setting
●● Programmable slew rate for increasing output voltage
settings
The output voltage is programmable from 0.50V to 1.80V
in 6.25mV steps to allow fine adjustment to the processor
supply voltage under light load conditions to minimize
power loss within the processor. The default output voltage is set by an OTP option at the factory. The default output voltage can be overwritten by changing the contents
in B_VOUT[7:0] register prior to enabling the regulator.
The output voltage can also be adjusted during normal
operation.
●● Output voltage range from 0.50V to 1.80V in 6.25mV
steps
●● ±1% (typ) output voltage DC accuracy
●● 2MHz (typ) switching frequency
Operating Mode Control
The operating mode bit resides in the top level that controls the enable/disable state of BUCK through the B_EN
register and also controls the operating mode (low power
or normal mode) through the B_LPM register.
SKIP/Forced PWM Operation
In normal operating mode, BUCK automatically transitions
from SKIP mode to fixed frequency operation as load current increases. For operating modes where lowest output
ripple is required, forced PWM switching behavior can be
enabled by writing 1 to B_FPWM bit.
Low Power Mode Operation
In low power mode, the quiescent current is reduced from
22µA to 8µA. The output current is limited to 10mA. It
is not recommended to adjust the output voltage in low
power mode. The regulator does not automatically enter/
exit low power mode. The host processor needs to control
low power mode operation in times of known low power
states through the I2C serial interface.
Startup and Soft-Start
When starting up BUCK regulator, the bias circuitry must
be enabled and provided with adequate time to settle. The
bias circuitry is guaranteed to settle within 250µs, at which
time, the BUCK regulators’ power-up sequences can
commence. Note that attempting to implement a powerup sequence before BIASOK signal is generated results
in all enabled regulators starting up at the same time.
www.maximintegrated.com
Changing Output Voltage While Operating
In a typical smartphone or tablet application, there are
several power domains in which the operating frequency
of the processor increases or decreases (DVFS). When
the operating frequency needs to be changed, it is
expected that BUCK regulator responds to a command to
change the output voltages to new target values quickly.
The high peak current limit, coupled with low inductance
and small output capacitance, allows the BUCK regulator
to respond to a positive step change in output voltage and
settle to the new target value quickly. The BUCK regulator
provides programmable ramp-up slew rates to accommodate different requirements.
For a negative step change in output voltage, the settling
time is not critical. In forced PWM mode (either B_FPWM
bit or B_FSRAD bit is enabled), the negative inductor
current through NMOS discharges energy from the output capacitor to help the output voltage decrease to the
new target value faster. In skip mode, negative inductor
current is not allowed so that the output voltage settling
time is dependent on the load current and the output
capacitance.
Maxim Integrated │ 28
MAX77826
Power Management IC
Output Voltage Slew Rate Control
The BUCK regulator supports programmable slew rate
control feature when increasing and decreasing the output
voltage. The ramp-up slew rate can be set to 12.5mV/µs,
25mV/µs, 50mV/µs or 100mV/µs independently through
the B_RAMP[1:0] bits, while the ramp-down slew rate is
fixed to 6.25mV/µs.
Output Active Discharge Resistance
BUCK provides an internal 100Ω resistor for output active
discharge function. If the active discharge function is
enabled (B_AD = 1), the internal resistor discharges the
energy stored in the output capacitor to GND whenever
the regulator is disabled.
Either the regulator remains enabled or the active discharge function is disabled (B_AD = 0), the internal resistor is disconnected from the output. If the active discharge
function is disabled, the output voltage decays at a rate
that is determined by the output capacitance and the load
current when the regulator is turned off.
ommended due to their small size, low ESR, and small
temperature coefficients. For most applications, a 10µF
capacitor is sufficient.
Output Capacitor Selection
The output capacitor, COUT, is required to keep the output voltage ripple small and to ensure regulation loop
stability. COUT must have low impedance at the switching
frequency. Ceramic capacitors with X5R or X7R dielectric
are highly recommended due to their small size, low ESR,
and small temperature coefficients. Due to the unique
feedback network, the output capacitance can be very
low. The recommended minimum output capacitance for
BUCK is 22µF.
BUCK BOOST Regulator
Input Capacitor Selection
The MAX77826 BUCK BOOST regulator utilizes a fourswitch H-bridge configuration to realize BUCK, BUCK
BOOST, and BOOST operating modes. In this way, this
topology maintains output voltage regulation when the
input voltage is greater than, equal to, or less than the
output voltage. The MAX77826 BUCK BOOST is ideal
in Li-ion battery powered applications, providing 2.6V
to 4.1875V output voltage and up to 2A output current
across the input voltage range. High switching frequency
and a unique control algorithm allow the smallest solution
size, low output noise, and highest efficiency across a
wide input voltage and output current range.
The input capacitor, CIN, reduces the current peaks
drawn from the battery or input power source and reduces
switching noise in the IC. The impedance of CIN at the
switching frequency should be kept very low. Ceramic
capacitors with X5R or X7R dielectrics are highly rec-
The MAX77826 BUCK BOOST regulator typically generates a 3.50V output voltage. The input current limit is set
to 3.5A (typ) to guarantee delivery of 2A at 3.50V from
3.0V input. Internal soft-start limits the inrush current at
startup.
Inductor Selection
BUCK is optimized for a 0.47µH inductor. The lower the
inductor DCR, the higher BUCK efficiency is. Users need
to trade off inductor size with DCR value and choose a
suitable inductor for BUCK.
Table 3. Suggested Inductors for BUCK
SERIES
NOMINAL
INDUCTANCE
(µH)
DC
RESISTANCE
(typ, mΩ)
CURRENT
RATING (A)
-30% (∆L/L)
CURRENT
RATING (A)
∆T = +40°C
RISE
DIMENSIONS
LxWxH
(mm)
Semco
CIGT201610G
MR47MNE
0.47
35
4.0
2.9
2.0 x 1.6 x 1.0
Toko
DFE201610-H
-R47N
0.47
37
3.5
3.5
2.0 x 1.6 x 1.0
MANUFACTURER
www.maximintegrated.com
Maxim Integrated │ 29
MAX77826
Power Management IC
LXBB
LXBB1
VINBB
1µH
LXBB2
P1
VOUTBB
P2
10µF
P1 CS
N1
N2
DRIVER
P2 CS
DRIVER
2x 22µF
PGNDBB
CONTROL LOGIC
OSC
SHUTDOWN
REGISTER
CONTROL
SNSBB
R1
BUFFER
R2
REF
Figure 3. BUCK BOOST Block Diagram
H-Bridge Controller
The H-bridge architecture operates at 3MHz fixed frequency with a pulse width modulated (PWM), current
mode control scheme. This topology is in a cascade of
a BOOST regulator and a BUCK regulator using a single
inductor and output capacitor. BUCK, BUCK BOOST,
and BOOST stages are 100% synchronous for highest
efficiency in portable applications.
There are three phases implemented with the H-bridge
switch topology, as shown in Figure 4:
Φ1 switch period (Phase 1: P1 = on, N2 = on) stores
energy in the inductor, ramping up the inductor current at
a rate proportional to the input voltage divided by inductance; VINBB/L.
Φ2 switch period (Phase 2: P1 = on, N3 = on) ramps the
inductor current up or down, depending on the differential voltage across the inductor, divided by inductance;
±(VINBB - VOUTBB)/L.
VINBB
VOUTBB
Ф2
P1
CHARGE/
DISCHARGE L
LXBB1
P2
LXBB2
L
N1
Ф3
N2
DISCHARGE L
Ф1
CHARGE L
Figure 4. BUCK BOOST Switching Intervals
Φ3 switch period (Phase 3: N1 = on, N3 = on) ramps
down the inductor current at a rate proportional to the
output voltage divided by inductance, -VOUTBB/L.
www.maximintegrated.com
Maxim Integrated │ 30
MAX77826
Power Management IC
2-Phase BUCK topology is utilized when VINBB > VOUTBB.
A switching cycle is completed in one clock periods.
Switch period Φ2 is followed by switch period Φ3, resulting in an inductor current waveform similar to Figure 5.
3-Phase BUCK topology is utilized when VINBB > VOUTBB
and 2-Phase BUCK cannot support VO. Switch period is:
Φ1 Φ2 Φ3. Switch period Φ1 is fixed. This results in
an inductor current waveform similar to Figure 6.
2-Phase BOOST topology is utilized when VINBB <
VOUTBB. A switching cycle is completed in one clock
periods. Switch period Φ1 is followed by switch period
Φ2, resulting in an inductor current waveform similar to
Figure 7.
3-Phase BOOST topology is utilized when VINBB <
VOUTBB and 2-Phase BOOST cannot support VO. Switch
period is: Φ1 Φ2 Φ3. Switch period Φ3 is fixed. This
results in an inductor current waveform similar to Figure 8.
Inductor Selection
BUCK BOOST is optimized for a 1µH inductor. The lower
the inductor DCR, the higher BUCK BOOST efficiency is.
Ф2
Ф2
Ф3
tSW1
CLK
Output Capacitor Selection
The output capacitor, COUT, is required to keep the output voltage ripple small and to ensure regulation loop
stability. COUT must have low impedance at the switching
frequency. Ceramic capacitors with X5R or X7R dielectric
are highly recommended due to their small size, low ESR,
and small temperature coefficients. Due to the unique
feedback network, the output capacitance can be very
low. The recommended minimum output capacitance for
BUCK BOOST is 47µF.
Ф2
tSW1
CLK
CLK
Ф1
Ф3
Ф1
tSW2
CLK
Ф1
tSW2
CLK
tSW1
CLK
CLK
Ф2
Ф3
Ф1
tSW2
CLK
Figure 6. 3-Phase BUCK Switching Current Waveforms When
VINBB > VOUTBB
Ф1
Ф2
Figure 7. 2-Phase BOOST Mode Switching Current Waveform
Ф2
Ф3
Ф1
tSW1
CLK
Ф2
The input capacitor, CIN, reduces the current peaks
drawn from the battery or input power source and reduces
switching noise in the IC. The impedance of CIN at the
switching frequency should be kept very low. Ceramic
capacitors with X5R or X7R dielectrics are highly recommended due to their small size, low ESR, and small
temperature coefficients. For most applications, a 10µF
capacitor is sufficient.
Ф3
Figure 5. 2-Phase BUCK Switching Current Waveforms
Ф3
Users need to trade off inductor size with DCR value and
choose a suitable inductor for BUCK BOOST.
CLK
Ф2
tSW2
CLK
CLK
Figure 8. BOOST Mode Switching Current Waveforms When
VINBB < VOUTBB
Table 4. Suggested Inductors for BUCK BOOST
SERIES
NOMINAL
INDUCTANCE
(µH)
DC
RESISTANCE
(typ, mΩ)
CURRENT
RATING (A)
-30% (∆L/L)
CURRENT
RATING (A)
∆T = +40°C
RISE
DIMENSIONS
LxWxH
(mm)
TFM201610GHM
-1R0MTAA
1.0
50
3.8
3.0
2.0 x 1.6 x 1.0
MANUFACTURER
TDK
www.maximintegrated.com
Maxim Integrated │ 31
MAX77826
Linear Regulators
The MAX77826 provides 15 low dropout linear regulators including 3 NMOS LDOs, 6 PMOSLV LDOs,
and 6 PMOSLS LDOs. Each of these regulators draws
27µA/18µA (NMOS/PMOS) of quiescent current in normal
operating mode and < 5µA in low power mode. PMOSLV
LDOs allow input voltages as low as 1.7V for optimized
system efficiency.
All regulators can be operated in low power mode that
supports up to 5mA of maximum load current.
The summary of features is:
●● 3 NMOS LDOs (VOUT range: 0.6V to 2.1875V with
12.5mV step)
• 1 x 150mA
• 1 x 450mA
• 1 x 600mA
●● 6 PMOSLV LDOs (VOUT range: 0.8V to 3.975V with
25mV step)
• 3 x 150mA
• 3 x 300mA
●● 6 PMOSLS LDOs (VOUT range: 0.8V to 3.975V with
25mV step)
•
•
•
•
3 x 150mA
3 x 300mA
±1.5% typical Output Voltage DC Accuracy
70dB PSRR at 1kHz
LDO Reference
The MAX77826 has a single LDOREF bias rail. LDOREF
is enabled or disabled along with the central bias block
(SBIA) so that LDOREF is ready whenever any LDO turns
on. It has a very low quiescent current of 2µA typical.
Operating Mode Control
The operation mode bits for each LDO reside in the top
level that controls the enable/disable state for each LDO
through the Lx_EN signal and also controls the operation
modes (low power or normal mode) for each LDO through
the Lx_LPM signal.
Low Power Mode
In low power mode, the quiescent current of each LDO
is reduced from 27µA/18µA (NMOS/PMOS) to less than
5µA. The output current of each LDO is limited to 5mA if
operating in low power mode. Each LDO can be individually enabled to operate in low power mode.
www.maximintegrated.com
Power Management IC
Soft-Start and Dynamic Voltage Change
When a regulator is enabled, the output voltage ramps to
the final voltage at the slew rate of 30mV/µs. The 30mV/
µs ramp rate results in around 30mA inrush current with
a 1.0µF output capacitor under no load condition. For a
1.8V LDO ramping from 0V, the output voltage regulation
is achieved within 60µs. The soft-start ramp rate is also
the rate of change at the output when switching dynamically between two output voltages without disabling. The
soft-start circuitry of LDOs supports starting into a prebiased output.
Output Active Discharge
Each LDO provides an internal 100Ω resistor for output
active discharge function. If the active discharge function
is enabled (Lx_AD = 1), the internal resistor discharges
the energy stored in the output capacitor to GND whenever the regulator is disabled.
Either the regulator remains enabled or the active discharge function is disabled (Lx_AD = 0), the internal resistor is disconnected from the output. If the active discharge
function is disabled, the output voltage decays at a rate
that is determined by the output capacitance and the load
current when the regulator is turned off.
Thermal Considerations
In most applications, the MAX77826 does not dissipate
much heat because of its high efficiency. However, in
applications where the MAX77826 runs with heavy loads
at high ambient temperature, the junction temperature
can exceed the maximum operating temperature. In case
the junction temperature reaches approximately +165°C,
the thermal overload protection triggers. The maximum
power dissipation of the MAX77826 depends on the thermal resistance of the IC package and PCB. The power
dissipated in the device is:
PD = POUT x (1/η - 1)
where η is the efficiency of the regulator and POUT is the
output power delivered to the load.
The maximum allowed power dissipation is:
PMAX = (TJMAX - TA)/θJA
TJMAX - TA is the temperature difference between the
maximum rated junction temperature and the ambient
temperature, θJA is the thermal resistance between the
junction and the ambient.
Maxim Integrated │ 32
MAX77826
Power Management IC
Serial Interface
Bit Transfer
The I2C-compatible, 2-wire serial interface is used for
One data bit transfers for each SCL clock cycle. The data
on SDA must remain stable during the high portion of SCL
clock pulse. Changes in SDA while SCL is high are control
signals (START and STOP conditions).
regulator on/off control, setting output voltages, and other
functions. See the Register Map for details.
The I2C serial bus consists of a bidirectional serial-data
line (SDA) and a serial clock (SCL). I2C is an open-drain
bus. SDA and SCL require pullup resistors (500Ω or
greater). Optional 24Ω resistors in series with SDA and
SCL help to protect the device inputs from high voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot on bus lines.
START and STOP Conditions
When the I2C serial interface is inactive, SDA and SCL
idle high. A master device initiates communication by
issuing a START condition. A START condition is a highto-low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high.
System Configuration
A START condition from the master signals the beginning
of a transmission to the MAX77826. The master terminates transmission by issuing a NOT ACKNOWLEDGE
followed by a STOP condition.
The figure above shows an example of a typical I2C system. A device on I2C bus that sends data to the bus in
called a transmitter. A device that receives data from the
bus is called a receiver. The device that initiates a data
transfer and generates SCL clock signals to control the
data transfer is a master. Any device that is addressed by
the master is considered a slave. When the MAX77826
I2C-compatible interface is operating in normal mode, it is
a slave on I2C bus, and it can be both a transmitter and
a receiver.
A STOP condition frees the bus. To issue a series of commands to the slave, the master can issue REPEATED
START (Sr) commands instead of a STOP command to
maintain control of the bus. In general, a REPEATED
START command is functionally equivalent to a regular
START command.
I2C bus is a multimaster bus. The maximum number of
devices that can attach to the bus is only limited by bus
capacitance.
When a STOP condition or incorrect address is detected,
the MAX77826 internally disconnects SCL from the I2C
serial interface until the next START condition, minimizing
digital noise and feedthrough.
SDA
SCL
MASTER
TRANSIMTTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
SLAVE
TRANSIMTTER/
RECEIVER
MASTER
TRANSIMTTER/
RECEIVER
Figure 9. Functional Logic Diagram for Communications Controller
S
SDA
Sr
P
SDA
SCL
DATA LINE STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
tHD;STA
Figure 10. I2C Bit Transfer
www.maximintegrated.com
tSU;STO
tSU;STA
SCL
tHD;STA
Figure 11. START and STOP Conditions
Maxim Integrated │ 33
MAX77826
Power Management IC
Acknowledge
Both the I2C bus master and MAX77826 (slave) generate
acknowledge bits when receiving data. The acknowledge
bit is the last bit of each 9-bit data packet. To generate an
ACKNOWLEDGE (A), the receiving device must pull SDA
low before the rising edge of the acknowledge-related clock
pulse (ninth pulse) and keep it low during the high period of
the clock pulse. To generate a NOT-ACKNOWLEDGE (nA),
the receiving device allows SDA to be pulled high before
the rising edge of the acknowledge-related clock pulse and
leaves it high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
Slave Address
The I2C slave address of the MAX77826 is shown in
Table 5.
In general, the clock signal generation for the I2C bus is
the responsibility of the master device. The I2C specification allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The MAX77826 does not use any form of clock
stretching to hold down the clock line.
General Call Address
The MAX77826 does not implement I2C specification
general call address. If the MAX77826 sees the general call address (00000000b), it does not issue an
ACKNOWLEDGE (A).
Communication Speed
The MAX77826 provides an I2C 3.0-compatible (3.4MHz)
serial interface.
●● I2C revision 3-compatible serial communications
channel
•
•
•
•
•
0Hz to 100kHz (standard mode)
0Hz to 400kHz (fast mode)
0Hz to 1MHz (fast mode plus)
0Hz to 3.4MHz (high-speed mode)
Does not utilize I2C clock stretching
Operating in standard mode, fast mode and fast mode
plus do not require any special protocols. The main consideration when changing the bus speed through this
range is the combination of the bus capacitance and pullup resistors. Higher time constants created by the bus
capacitance and pullup resistance (C x R) slow the bus
operation. Therefore, when increasing bus speeds the
pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing
section of I2C revision 3.0 specification for detailed guidance on the pullup resistor selection. In general for bus
capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup
resistors, a 400kHz bus needs about a 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω pullup resistors. Note
that the pullup resistor dissipates power when the opendrain bus is low. The lower the value of the pullup resistor,
the higher the power dissipation is (V2/R).
Operating in high-speed mode requires some special
considerations. For the full list of considerations, refer to
the I2C 3.0 specification. The major considerations with
respect to the MAX77826 are:
●● The I2C bus master uses current source pullups to
shorten the signal rise times.
●● The I2C slave must use a different set of input filters
on its SDA and SCL lines to accommodate for the
higher bus speed.
Table 5. Power Management Slave
Address
SLAVE
ADDRESS
(7 bit)
SLAVE
ADDRESS
(Write)
SLAVE
ADDRESS
(Read)
110 0000
0xC0 (1100 0000)
0xC1 (1100 0001)
●● The communication protocols need to utilize the highspeed master code.
S
SDA
1
1
0
0
0
0
0
R/W
A
ACKNOWLEDGE
SCL
1
2
3
4
5
6
7
8
9
Figure 12. Slave Address Byte Example for Power Block
www.maximintegrated.com
Maxim Integrated │ 34
MAX77826
Power Management IC
At power-up and after each STOP condition, the MAX77826
inputs filters are set for standard mode, fast mode, or fast
mode plus (i.e., 0Hz to 1MHz). To switch the input filters
for high-speed mode, use the high-speed master code
protocols that are described in Communication Protocols
section.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data
8) The slave acknowledges or does not acknowledges
the data byte. The next rising edge on SDA loads
the data byte into its target register and the data
becomes active.
Communication Protocols
The MAX77826 supports both writing and reading from
its registers. Table TBD shows the I2C communication
protocols for each functional block. The power block uses
the same communications protocols.
9) The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a P ensures
that the bus input filters are set for 1MHz or slower
operation. Issuing a REPEATED START (Sr) leaves
the bus input filters in their current state.
Writing to a Single Register
Figure 13 shows the protocol for the I2C master device to
write one byte of data to the MAX77826. This protocol is
the same as the SMBus specification’s write byte protocol. The write byte protocol is as follows:
Writing to Sequential Registers
Figure 14 shows the protocol for writing to a sequential
registers. This protocol is similar to the write byte protocol, except the master continues to write after it receives
the first byte of data. When the master is done writing,
it issues a STOP or REPEATED START. The writing to
sequential registers protocol is as follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
by a write bit (R/W = 0).
1) The master sends a START command (S).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
2) The master sends the 7-bit slave address followed
by a write bit (R/W = 0).
4) The master sends an 8-bit register pointer.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
NUMBER OF
BITS
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER
A
DATA
A OR nA
P OR Sr*
R/W
THE DATA IS LOADED INTO
THE TARGET REGISTER AND
BECOMES ACTIVE DURING
THIS RISING EDGE.
SDA
B1
B0
A
ACKNOWLEDGE
SCL
7
8
9
*P FORCES THE BUS FILTERS TO SWITCH
TO THEIR ≤ 1MHz MODE. Sr LEAVES THE
BUS FILTERS IN THEIR CURRENT STATE.
Figure 13. Writing to a Single Register with Write Byte Protocol
www.maximintegrated.com
Maxim Integrated │ 35
MAX77826
Power Management IC
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA LOW.
8) Steps 6 and 7 are repeated as many times as the
master requires.
4) The master sends an 8-bit register pointer.
9) During the last acknowledge related clock pulse, the
master can issue an ACKNOWLEDGE (A) or a NOT
ACKNOWLEDGE (nA).
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
10) The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a P ensures
that the bus input filters are set for 1MHz or slower
operation. Issuing a REPEATED START (Sr) leaves
the bus input filters in their current state.
7) The slave acknowledges the data byte. The next
rising edge on SDA loads the data byte into its target
register, and the data becomes active.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1
1
8
1
8
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
DATA X
A
NUMBER OF
BITS
Α
R/NW
8
1
DATA X+1
8
1
A
DATA X+2
A
8
1
Α
REGISTER POINTER = X +
2
8
DATA N-1
A
REGISTER POINTER =
X+1
DATA N
NUMBER OF
BITS
Α
1
A OR NA
Α
REGISTER POINTER =
X + (N - 2)
SDA
B1
B0
NUMBER OF
BITS
1
P OR SR*
Β
REGISTER POINTER =
X + (N - 1)
A
B9
9
1
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE
ACKNOWLEDGE
SCL
7
8
DETAIL: Α
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE
SDA
B1
B0
A
ACKNOWLEDGE
SCL
7
8
9
DETAIL: Β
*P FORCES THE BUS
FILTERS TO SWITCH TO
THEIR ≤ 1MHz MODE. Sr
LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
Figure 14. Writing to Sequential Registers X to N
www.maximintegrated.com
Maxim Integrated │ 36
MAX77826
Power Management IC
Writing Multiple Bytes using Register-Data Pairs
4) The master sends an 8-bit register pointer.
Figure 15 shows the protocol for I2C master device to
write multiple bytes to the MAX77826 using register-data
pairs. This protocol allows I2C master device to address
the slave only once and then send data to multiple registers in a random order. Registers can be written continuously until the master issues a STOP condition. The
multiple byte register-data pair protocol is as follows:
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave acknowledges the data byte. The next
rising edge on SDA loads the data byte into its target
register and the data becomes active.
8) Steps 4 to 7 are repeated as many times as the
master requires.
1) The master sends a START command.
9) The master sends a STOP condition. During the rising edge of the stop related SDA edge, the data byte
that was previously written is loaded into the target
register and becomes active.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1
1
8
1
8
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
DATA X
A
NUMBER OF BITS
α
R/nW
8
1
8
1
REGISTER POINTER n
A
DATA n
A
NUMBER OF BITS
α
8
1
8
REGISTER POINTER Z
A
DATA Z
1
NUMBER OF BITS
1
A P
β
SDA
B1
B0
A
B9
9
1
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE
ACKNOWLEDGE
SCL
7
8
DETAIL: α
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE
SDA
B1
B0
A
ACKNOWLEDGE
SCL
7
8
9
DETAIL: β
Figure 15. Writing to Multiple Registers with Multiple Byte Register-Data Pairs Protocol
www.maximintegrated.com
Maxim Integrated │ 37
MAX77826
Reading from a Single Register
The I2C master device reads one byte of data to the
MAX77826. This protocol is the same as SMBus specification’s read byte protocol. The read byte protocol is as
follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
by a write bit (R/W = 0).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START command
(Sr).
7) The master sends the 7-bit slave address followed
by a read bit (R/W = 1).
8) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
9) The addressed slave places 8 bit of data on the bus
from the location specified by the register pointer.
10) The master issues a NOT ACKNOWLEDGE (nA).
11) The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a P ensures
that the bus input filters are set for 1MHz or slower
operation. Issuing a REPEATED START (Sr) leaves
the bus input filters in their current state.
Note that every time MAX77826 receives a STOP, its
register pointer is set to 0x00. If reading register 0x00
after a STOP has been issued, steps 1 to 6 in the above
algorithm can be skipped.
Reading from Sequential Registers
Figure 16 shows the protocol for reading from sequential registers. This protocol is similar to the read byte
protocol except the master issues an ACKNOWLEDGE
(A) to signal the slave that it wants more data. When
the master has all the data it requires, it issues a NOT
ACKNOWLEDGE (nA) and a STOP (P) to end the transmission. The continuous read from sequential registers
protocol is as follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
by a write bit (R/W = 0).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA LOW.
www.maximintegrated.com
Power Management IC
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START command
(Sr).
7) The master sends the 7-bit slave address followed
by a read bit (R/W = 1).
8) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
9) The addressed slave places 8 bit of data on the bus
from the location specified by the register pointer.
10) The master issues an ACKNOWLEDGE (A) signaling
the slave that it wishes to receive more data.
11) Steps 9 to 10 are repeated as many times as the
master requires. Following the last byte of data, the
master must issue a NOT ACKNOWLEDGE (nA) to
signal that it wishes to stop receiving data.
12) The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a STOP (P)
ensures that the bus input filters are set for 1MHz or
slower operation. Issuing a REPEATED START (Sr)
leaves the bus input filters in their current state.
Note that every time the MAX77826 receives a STOP its
register pointer is set to 0x00. If reading register 0x00
after a STOP has been issued, steps 1 to 6 in the above
algorithm can be skipped.
Engaging HS-Mode for Operation up to 3.4MHz
Figure 17 shows the protocol for engaging HS mode
operation. HS mode operation allows for a bus operating
speed up to 3.4MHz. The engaging HS mode protocol is
as follows:
1) Begin the protocol while operating at a bus speed of
1MHz or lower.
2) The master sends a START command (S).
3) The master sends the 8-bit master code of
00001xxxb where xxxb are don’t care bits.
4) The addressed slave issues a NOT ACKNOWLEDGE (nA).
5) The master may now increase its bus speed up to
3.4MHz and issue any read/write operation.
6) The master may continue to issue high-speed read/
write operations until a STOP (P) is issued. Issuing
a STOP (P) ensures that the bus input filters are
set for 1MHz or slower operation. After a STOP has
been issued, steps 1 to 6 in the above algorithm may
be skipped.
Maxim Integrated │ 38
MAX77826
Power Management IC
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHz MODE. Sr
LEAVES THE BUS FILTERS IN THEIR
CURRENT STATE.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1
1
8
1 1
7
1
1
8
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A Sr
SLAVE ADDRESS
1
A
DATA X
A
8
1
8
DATA X + 2
A
R/W
R/W
8
1
DATA X + 1
A
REGISTER POINTER =
X+1
REGISTER POINTER =
X+2
8
1
DATA n-2
A
REGISTER POINTER =
X + (N - 3)
NUMBER OF
BITS
1
A
REGISTER POINTER =
X+3
8
1
DATA n-1
A
REGISTER POINTER =
X + (N - 2)
DATA X + 3
NUMBER OF
BITS
NUMBER OF
BITS
8
1
1
DATA n
nA
P OR Sr*
REGISTER POINTER =
X + (N - 1)
Figure 16. Reading Continuously from Sequential Registers with X to N
LEGEND
MASTER TO SLAVE
1
8
S
HS MASTER CODE
SLAVE TO MASTER
1
1
NA SR
FAST MODE
ANY READ/WRITE PROTOCOL
ANY READ/WRITE PROTOCOL
SR
SR ANY READ/WRITE PROTOCOL
FOLLOWED BY SR
FOLLOWED BY SR
HS MODE
P
FAST MODE
Figure 17. Engaging HS Mode
PMIC Registers
Register Reset Conditions
Type-S1: Registers are reset when VSYS < POR (≈1.55V)
Type-O: Registers are reset when VSYS < VUVLO OR VIO < VTH_VIO_OK OR CE = LOW
www.maximintegrated.com
Maxim Integrated │ 39
www.maximintegrated.com
Type-O
Type-O
Type-O
Type-O
Type-O
Type-O
TOPSYS
_INT_M
REG_
INT1_M
REG_
INT2_M
BB_
INT_M
TOPSYS_
STAT
REG_
STAT1
REG_
STAT2
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
LDO_
OPMD1
Type-O
INT_
SRC_M
0x05
0x10
Type-O
BB_
INT
0x04
RSVD
Type-S1
REG_
INT2
0x03
0x0E–
0x0F
Type-S1
REG_
INT1
0x02
BB_
STAT
Type-S1
SYS_INT
0x01
0x0D
Type-S1
INT_SRC
0x00
Type-O
Type-O
Type-O
NAME
ADDR
RESET
TYPE
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/C
R/C
R/C
R/C
R
R/W
L4_EN
RSVD
B_POKn
LDO8_
POKn
RSVD
RSVD
B_
POKn_M
LDO8_
POKn_M
RSVD
RSVD
RSVD
B_POKn
LDO8_
POKn
RSVD
RSVD
BIT7
I2C Slave Address (W/R): 0xC0/0xC1
Register Map
L4_LPM
RSVD
LDO15_
POKn
LDO7_
POKn
RSVD
RSVD
LDO15_
POKn_M
LDO7_
POKn_M
RSVD
RSVD
RSVD
LDO15_
POKn
LDO7_
POKn
RSVD
RSVD
BIT6
L3_EN
RSVD
LDO14_
POKn
LDO6_
POKn
RSVD
RSVD
LDO14_
POKn_M
LDO6_
POKn_M
RSVD
RSVD
RSVD
LDO14_
POKn
LDO6_
POKn
RSVD
RSVD
BIT5
L3_LPM
RSVD
LDO13_
POKn
LDO5_
POKn
RSVD
RSVD
LDO13_
POKn_M
LDO5_
POKn_M
RSVD
RSVD
RSVD
LDO13_
POKn
LDO5_
POKn
RSVD
RSVD
BIT4
L2_EN
RSVD
LDO12_
POKn
LDO4_
POKn
RSVD
RSVD
LDO12_
POKn_M
LDO4_
POKn_M
RSVD
RSVD
RSVD
LDO12_
POKn
LDO4_
POKn
RSVD
RSVD
BIT3
L2_LPM
BB_
POKn
LDO11_
POKn
LDO3_
POKn
RSVD
BB_
POKn_M
LDO11_
POKn_M
LDO3_
POKn_M
RSVD
BB_
INT_M
BB_POKn
LDO11_
POKn
LDO3_
POKn
RSVD
BB_INT
BIT2
TJCT_
140C
TJCT_
120C
L1_EN
BB_
OVP
LDO10_
POKn
LDO2_
POKn
TJCT_
120C
BB_
OVP_M
LDO10_
POKn_M
LDO2_
POKn_M
TJCT_
120C_M
REG_
INT_M
BB_
OVP
LDO10_
POKn
L1_
LPM
BB_
OCP
LDO9_
POKn
LDO1_
POKn
TJCT_
140C
BB_
OCP_M
LDO9_
POKn_M
LDO1_
POKn_M
TJCT_
140C_M
TOPSYS
_INT_M
BB_OCP
LDO9_
POKn
LDO1_
POKn
TOPSYS
_INT
REG_
INT
LDO2_
POKn
BIT0
BIT1
0x00
—
—
—
—
0x07
0xFF
0xFF
0x03
0x07
0x00
0x00
0x00
0x00
0x00
RESET
VALUE
MAX77826
Power Management IC
Maxim Integrated │ 40
www.maximintegrated.com
Type-O
Type-O
Type-O
Type-O
LDO4_
CFG
LDO5_
CFG
LDO6_
CFG
LDO7_
CFG
LDO8_
CFG
0x23
0x24
0x25
0x26
0x27
Type-O
Type-O
LDO3_
CFG
0x22
LDO11
_CFG
Type-O
LDO2_
CFG
0x21
0x2A
Type-O
LDO1_
CFG
0x20
Type-O
Type-O
RSVD
0x15–
0x1F
LDO10_
CFG
Type-O
B_BB_
OPMD
0x14
0x29
Type-O
LDO_
OPMD4
0x13
Type-O
Type-O
LDO_
OPMD3
0x12
LDO9_
CFG
Type-O
LDO_
OPMD2
0x11
0x28
RESET
TYPE
NAME
ADDR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
L11_AD
L10_AD
L9_AD
L8_AD
L7_AD
L6_AD
L5_AD
L4_AD
L3_AD
L2_AD
L1_AD
RSVD
RSVD
L12_EN
L8_EN
BIT7
RSVD
RSVD
L12_
LPM
L8_LPM
BIT6
I2C Slave Address (W/R): 0xC0/0xC1 (continued)
Register Map (continued)
RSVD
L15_EN
L11_EN
L7_EN
BIT5
RSVD
L9_VOUT[6:0]
L8_VOUT[6:0]
L7_VOUT[6:0]
L6_VOUT[6:0]
L5_VOUT[6:0]
L4_VOUT[6:0]
L3_VOUT[6:0]
L2_VOUT[6:0]
L1_VOUT[6:0]
BB_EN
L14_EN
L10_EN
L6_EN
BIT3
L11_VOUT[6:0]
L10_VOUT[6:0]
L15_LPM
L11_LPM
L7_LPM
BIT4
RSVD
L14_LPM
L10_LPM
L6_LPM
BIT2
B_EN
L13_
EN
L9_EN
L5_EN
BIT1
B_
LPM
L13_
LPM
L9_
LPM
L5_
LPM
BIT0
0xD0
0xD0
0xA8
0xA8
0xA8
0xA8
0xA8
0x9C
0xA0
0xA0
0xA0
0x00
0x00
0x00
0x00
RESET
VALUE
MAX77826
Power Management IC
Maxim Integrated │ 41
RESET
TYPE
Type-O
Type-O
Type-O
Type-O
Type-O
Type-O
Type-O
Type-O
Type-O
Type-O
NAME
LDO12
_CFG
LDO13_
CFG
LDO14_
CFG
LDO15_
CFG
RSVD
BUCK_
CFG
BUCK_
VOUT
BB_CFG
BB_
VOUT
RSVD
BUCK_
SS_FREQ
UVLO_
FALL
RSVD
ADDR
0x2B
0x2C
0x2D
www.maximintegrated.com
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34–
0x3F
0x40
0x41
0x42–
0xFF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT6
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
B_RAMP[1:0]
L15_AD
L14_AD
L13_AD
L12_AD
BIT7
I2C Slave Address (W/R): 0xC0/0xC1 (continued)
Register Map (continued)
RSVD
RSVD
B_AD
L15_VOUT[6:0]
L14_VOUT[6:0]
L13_VOUT[6:0]
L12_VOUT[6:0]
BIT3
RSVD
B_SS
RSVD
RSVD
BB_VOUT[6:0]
BB_AD
B_VOUT[7:0]
RSVD
BIT4
BB_OVP_TH[1:0]
RSVD
BIT5
RSVD
BB_
HSKIP
B_FPWM
BIT2
RSVD
B_
FSRADE
BIT0
UVLO_F[1:0]
B_FREQ[2:0]
BB_
FPWM
RSVD
BIT1
0x01
0x04
0x48
0x3C
0x78
0x09
0xE4
0xE4
0xE4
0xE4
RESET
VALUE
MAX77826
Power Management IC
Maxim Integrated │ 42
MAX77826
Power Management IC
INT_SRC
Interrupt Source Register
ADDRESS
MODE
0x00
R
TYPE: O
RESET VALUE: 0x00
BIT
NAME
POR
DESCRIPTION
7:3
RSVD
0000 0
2
BB_INT
0
1: Interrupt event on BUCK BOOST is detected.
1
REG_INT
0
1: Interrupt event on BUCK or LDOs is detected.
0
TOPSYS_INT
0
1: Interrupt event on TOPSYS is detected.
TOPSYS_INT
TOPSYS Interrupt Register
ADDRESS
MODE
0x01
R/C
TYPE: S1
RESET VALUE: 0x00
BIT
NAME
POR
DESCRIPTION
7:2
RSVD
0000 00
1
TJCT_120C
0
1: Junction temperature (TJCT ) is higher than +120°C.
0
TJCT_140C
0
1: Junction temperature (TJCT ) is higher than +140°C.
REG_INT1
Regulators Interrupt Register1
ADDRESS
MODE
0x02
R/C
TYPE: S1
BIT
NAME
POR
7
LDO8_POKn
0
1: LDO8 POKn is triggered.
6
LDO7_POKn
0
1: LDO7 POKn is triggered.
5
LDO6_POKn
0
1: LDO6 POKn is triggered.
4
LDO5_POKn
0
1: LDO5 POKn is triggered.
3
LDO4_POKn
0
1: LDO4 POKn is triggered.
2
LDO3_POKn
0
1: LDO3 POKn is triggered.
1
LDO2_POKn
0
1: LDO2 POKn is triggered.
0
LDO1_POKn
0
1: LDO1 POKn is triggered.
www.maximintegrated.com
RESET VALUE: 0x00
DESCRIPTION
Maxim Integrated │ 43
MAX77826
Power Management IC
REG_INT2
Regulators Interrupt Register2
ADDRESS
MODE
0x03
R/C
TYPE: S1
BIT
NAME
POR
7
B_POKn
0
1: BUCK POKn is triggered.
6
LDO15_POKn
0
1: LDO15 POKn is triggered.
5
LDO14_POKn
0
1: LDO14 POKn is triggered.
4
LDO13_POKn
0
1: LDO13 POKn is triggered.
3
LDO12_POKn
0
1: LDO12 POKn is triggered.
2
LDO11_POKn
0
1: LDO11 POKn is triggered.
1
LDO10_POKn
0
1: LDO10 POKn is triggered.
0
LDO9_POKn
0
1: LDO9 POKn is triggered.
RESET VALUE: 0x00
DESCRIPTION
BB_INT
BUCK BOOST Interrupt Register
ADDRESS
MODE
0x04
R/C
TYPE: S1
RESET VALUE: 0x00
BIT
NAME
POR
DESCRIPTION
7:3
RSVD
0000 0
2
BB_POKn
0
1: BUCK BOOST POKn is triggered.
1
BB_OVP
0
1: BUCK BOOST OVP is triggered.
0
BB_OCP
0
1: BUCK BOOST OCP is triggered.
INT_SRC_M
Interrupt Source Mask Register
ADDRESS
MODE
0x05
R/W
TYPE: O
RESET VALUE: 0x07
BIT
NAME
POR
7:3
RSVD
0000 0
2
BB_INT_M
1
0: Enable BUCK BOOST interrupt events.
1: Mask BUCK BOOST interrupt events.
1
REG_INT_M
1
0: Enable REG interrupt events.
1: Mask REG interrupt events.
0
TOPSYS_INT_M
1
0: Enable TOPSYS interrupt events.
1: Mask TOPSYS interrupt events.
www.maximintegrated.com
DESCRIPTION
Maxim Integrated │ 44
MAX77826
Power Management IC
TOPSYS_INT_M
TOPSYS Interrupt Mask Register
ADDRESS
MODE
0x05
R/W
TYPE: O
BIT
NAME
POR
7:2
RSVD
0000 00
1
TJCT_120C_M
1
0: Enable TJCT_120 interrupt.
1: Mask TJCT_120 interrupt.
0
TJCT_140C_M
1
0: Enable TJCT_140 interrupt.
1: Mask TJCT_140 interrupt.
RESET VALUE: 0x03
DESCRIPTION
REG_INT1_M
Regulators Interrupt Mask Register 1
ADDRESS
MODE
0x07
R/W
TYPE: O
RESET VALUE: 0xFF
BIT
NAME
POR
7
LDO8_POKn_M
1
0: Enable LDO8 POKn interrupt.
1: Mask LDO8 POKn interrupt.
6
LDO7_POKn_M
1
0: Enable LDO7 POKn interrupt.
1: Mask LDO7 POKn interrupt.
5
LDO6_POKn_M
1
0: Enable LDO6 POKn interrupt.
1: Mask LDO6 POKn interrupt.
4
LDO5_POKn_M
1
0: Enable LDO5 POKn interrupt.
1: Mask LDO5 POKn interrupt.
3
LDO4_POKn_M
1
0: Enable LDO4 POKn interrupt.
1: Mask LDO4 POKn interrupt.
2
LDO3_POKn_M
1
0: Enable LDO3 POKn interrupt.
1: Mask LDO3 POKn interrupt.
1
LDO2_POKn_M
1
0: Enable LDO2 POKn interrupt.
1: Mask LDO2 POKn interrupt.
0
LDO1_POKn_M
1
0: Enable LDO1 POKn interrupt.
1: Mask LDO1 POKn interrupt.
www.maximintegrated.com
DESCRIPTION
Maxim Integrated │ 45
MAX77826
Power Management IC
REG_INT2_M
Regulators Interrupt Mask Register 2
ADDRESS
MODE
0x08
R/W
TYPE: O
RESET VALUE: 0xFF
BIT
NAME
POR
DESCRIPTION
7
B_POKn_M
1
0: Enable BUCK POKn interrupt.
1: Mask BUCK POKn interrupt.
6
LDO15_POKn_M
1
0: Enable LDO15 POKn interrupt.
1: Mask LDO15 POKn interrupt.
5
LDO14_POKn_M
1
0: Enable LDO14 POKn interrupt.
1: Mask LDO14 POKn interrupt.
4
LDO13_POKn_M
1
0: Enable LDO13 POKn interrupt.
1: Mask LDO13 POKn interrupt.
3
LDO12_POKn_M
1
0: Enable LDO12 POKn interrupt.
1: Mask LDO12 POKn interrupt.
2
LDO11_POKn_M
1
0: Enable LDO11 POKn interrupt.
1: Mask LDO11 POKn interrupt.
1
LDO10_POKn_M
1
0: Enable LDO10 POKn interrupt.
1: Mask LDO10 POKn interrupt.
0
LDO9_POKn_M
1
0: Enable LDO9 POKn interrupt.
1: Mask LDO9 POKn interrupt.
BB_INT_M
BUCK BOOST Interrupt Mask Register
ADDRESS
MODE
0x09
R/W
TYPE: O
RESET VALUE: 0x07
BIT
NAME
POR
7:3
RSVD
0000 0
2
BB_POKn_M
1
0: Enable BUCK BOOST POKn interrupt.
1: Mask BUCK BOOST POKn interrupt.
1
BB_OVP_M
1
0: Enable BUCK BOOST OVP interrupt.
1: Mask BUCK BOOST OVP interrupt.
0
BB_OCP_M
1
0: Enable BUCK BOOST OCP interrupt.
1: Mask BUCK BOOST OCP interrupt.
www.maximintegrated.com
DESCRIPTION
Maxim Integrated │ 46
MAX77826
Power Management IC
TOPSYS_STAT
TOPSYS Status Register
ADDRESS
MODE
0x0A
R
TYPE: O
RESET VALUE: N/A
BIT
NAME
POR
DESCRIPTION
7:2
RSVD
—
1
TJCT_120C
—
0: Junction temperature (TJCT) ≤ +120°C
1: Junction temperature (TJCT) > +120°C
0
TJCT_140C
—
0: Junction temperature (TJCT) ≤ +140°C
1: Junction temperature (TJCT) > +140°C
REG_STAT1
Regulators Status Register 1
ADDRESS
MODE
0x0B
R
TYPE: O
BIT
NAME
POR
7
LDO8_POKn
0
LDO8 POKn status
6
LDO7_POKn
0
LDO7 POKn status
5
LDO6_POKn
0
LDO6 POKn status
4
LDO5_POKn
0
LDO5 POKn status
3
LDO4_POKn
0
LDO4 POKn status
2
LDO3_POKn
0
LDO3 POKn status
1
LDO2_POKn
0
LDO2 POKn status
0
LDO1_POKn
0
LDO1 POKn status
RESET VALUE: 0x00
DESCRIPTION
REG_STAT2
Regulators Status Register 2
ADDRESS
MODE
0x0C
R
TYPE: O
BIT
NAME
POR
7
B_POKn
0
BUCK POKn status
6
LDO15_POKn
0
LDO15 POKn status
5
LDO14_POKn
0
LDO14 POKn status
4
LDO13_POKn
0
LDO13 POKn status
3
LDO12_POKn
0
LDO12 POKn status
2
LDO11_POKn
0
LDO11 POKn status
1
LDO10_POKn
0
LDO10 POKn status
0
LDO9_POKn
0
LDO9 POKn status
www.maximintegrated.com
RESET VALUE: 0x00
DESCRIPTION
Maxim Integrated │ 47
MAX77826
Power Management IC
BB_STAT
BUCK BOOST Status Register
ADDRESS
MODE
0x0D
R
TYPE: O
BIT
NAME
POR
7:3
RSVD
0000 0
2
BB_POKn
0
BUCK BOOST POKn status
1
BB_OVP
0
BUCK BOOST OVP status
0
BB_OCP
0
BUCK BOOST OCP status
RESET VALUE: 0x00
DESCRIPTION
Note: 0x0E–0x0F: RSVD.
LDO_OPMD1
LDO Operating Mode Register 1
ADDRESS
MODE
0x10
R/W
TYPE: O
BIT
NAME
POR
7
L4_EN
0
0: Output off
1: Output on
6
L4_LPM
0
0: Normal mode
1: Low power mode
5
L3_EN
0
0: Output off
1: Output on
4
L3_LPM
0
0: Normal mode
1: Low power mode
3
L2_EN
0
0: Output off
1: Output on
2
L2_LPM
0
0: Normal mode
1: Low power mode
1
L1_EN
0
0: Output off
1: Output on
0
L1_LPM
0
0: Normal mode
1: Low power mode
www.maximintegrated.com
RESET VALUE: 0x00
DESCRIPTION
Maxim Integrated │ 48
MAX77826
Power Management IC
LDO_OPMD2
LDO Operating Mode Register 2
ADDRESS
MODE
0x11
R/W
BIT
NAME
TYPE: O
POR
RESET VALUE: 0x00
DESCRIPTION
7
L8_EN
0
0: Output off
1: Output on
6
L8_LPM
0
0: Normal mode
1: Low power mode
5
L7_EN
0
0: Output off
1: Output on
4
L7_LPM
0
0: Normal mode
1: Low power mode
3
L6_EN
0
0: Output off
1: Output on
2
L6_LPM
0
0: Normal mode
1: Low power mode
1
L5_EN
0
0: Output off
1: Output on
0
L5_LPM
0
0: Normal Mode
1: Low Power Mode
LDO_OPMD3
LDO Operating Mode Register 3
ADDRESS
MODE
0x12
R/W
ADDRESS
BIT
NAME
POR
7
L12_EN
0
0: Output off
1: Output on
6
L12_LPM
0
0: Normal mode
1: Low power mode
5
L11_EN
0
0: Output off
1: Output on
4
L11_LPM
0
0: Normal mode
1: Low power mode
3
L10_EN
0
0: Output off
1: Output on
2
L10_LPM
0
0: Normal mode
1: Low power mode
1
L9_EN
0
0: Output off
1: Output on
0
L9_LPM
0
0: Normal mode
1: Low power mode
www.maximintegrated.com
RESET VALUE: 0x00
DESCRIPTION
Maxim Integrated │ 49
MAX77826
Power Management IC
LDO_OPMD4
LDO Operating Mode Register 4
ADDRESS
MODE
0x13
R/W
TYPE: O
BIT
NAME
POR
7:6
RSVD
5
L15_EN
0
0b: Output off
1b: Output on
4
L15_LPM
0
0b: Normal mode
1b: Low power mode
3
L14_EN
0
0b: Output off
1b: Output on
2
L14_LPM
0
0b: Normal mode
1b: Low power mode
1
L13_EN
0
0b: Output off
1b: Output on
0
L13_LPM
0
0b: Normal mode
1b: Low power mode
RESET VALUE: 0x00
DESCRIPTION
B_BB_OPMD
BUCK and BUCK BOOST Operating Mode Register
ADDRESS
MODE
0x14
R/W
TYPE: O
BIT
NAME
POR
7:4
RSVD
0000
3
BB_EN
0
2
RSVD
0
1
B_EN
0
0: BUCK output off
1: BUCK output on
0
B_LPM
0
0: Normal mode
1: Low power mode
RESET VALUE: 0x00
DESCRIPTION
0: BUCK BOOST output off
1: BUCK BOOST output on
Note: 0x14–0x1F: RSVD.
www.maximintegrated.com
Maxim Integrated │ 50
MAX77826
Power Management IC
LDO1_CFG
LDO1 Configuration Register
ADDRESS
MODE
0x20
R/W
TYPE: O
BIT
NAME
POR
7
L1_AD
1
RESET VALUE: 0xA0
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
NMOS LDO Output Voltage
6:0
L1_VOUT[6:0]
www.maximintegrated.com
010 0000
0x00 = 0.6000V
0x20 = 1.0000V
0x40 = 1.4000V
0x60 = 1.8000V
0x01 = 0.6125V
0x21 = 1.0125V
0x41 = 1.4125V
0x61 = 1.8125V
0x02 = 0.6250V
0x22 = 1.0250V
0x42 = 1.4250V
0x62 = 1.8250V
0x03 = 0.6375V
0x23 = 1.0375V
0x43 = 1.4375V
0x63 = 1.8375V
0x04 = 0.6500V
0x24 = 1.0500V
0x44 = 1.4500V
0x64 = 1.8500V
0x05 = 0.6625V
0x25 = 1.0625V
0x45 = 1.4625V
0x65 = 1.8625V
0x06 = 0.6750V
0x26 = 1.0750V
0x46 = 1.4750V
0x66 = 1.8750V
0x07 = 0.6875V
0x27 = 1.0875V
0x47 = 1.4875V
0x67 = 1.8875V
0x08 = 0.7000V
0x28 = 1.1000V
0x48 = 1.5000V
0x68 = 1.9000V
0x09 = 0.7125V
0x29 = 1.1125V
0x49 = 1.5125V
0x69 = 1.9125V
0x0A = 0.7250V
0x2A = 1.1250V
0x4A = 1.5250V
0x6A = 1.9250V
0x0B = 0.7375V
0x2B = 1.1375V
0x4B = 1.5375V
0x6B = 1.9375V
0x0C = 0.7500V
0x2C = 1.1500V
0x4C = 1.5500V
0x6C = 1.9500V
0x0D = 0.7625V
0x2D = 1.1625V
0x4D = 1.5625V
0x6D = 1.9625V
0x0E = 0.7750V
0x2E = 1.1750V
0x4E = 1.5750V
0x6E = 1.9750V
0x0F = 0.7875V
0x2F = 1.1875V
0x4F = 1.5875V
0x6F = 1.9875V
0x10 = 0.8000V
0x30 = 1.2000V
0x50 = 1.6000V
0x70 = 2.0000V
0x11 = 0.8125V
0x31 = 1.2125V
0x51 = 1.6125V
0x71 = 2.0125V
0x12 = 0.8250V
0x32 = 1.2250V
0x52 = 1.6250V
0x72 = 2.0250V
0x13 = 0.8375V
0x33 = 1.2375V
0x53 = 1.6375V
0x73 = 2.0375V
0x14 = 0.8500V
0x34 = 1.2500V
0x54 = 1.6500V
0x74 = 2.0500V
0x15 = 0.8625V
0x35 = 1.2625V
0x55 = 1.6625V
0x75 = 2.0625V
0x16 = 0.8750V
0x36 = 1.2750V
0x56 = 1.6750V
0x76 = 2.0750V
0x17 = 0.8875V
0x37 = 1.2875V
0x57 = 1.6875V
0x77 = 2.0875V
0x18 = 0.9000V
0x38 = 1.3000V
0x58 = 1.7000V
0x78 = 2.1000V
0x19 = 0.9125V
0x39 = 1.3125V
0x59 = 1.7125V
0x79 = 2.1125V
0x1A = 0.9250V
0x3A = 1.3250V
0x5A = 1.7250V
0x7A = 2.1250V
0x1B = 0.9375V
0x3B = 1.3375V
0x5B = 1.7375V
0x7B = 2.1375V
0x1C = 0.9500V
0x3C = 1.3500V
0x5C = 1.7500V
0x7C = 2.1500V
0x1D = 0.9625V
0x3D = 1.3625V
0x5D = 1.7625V
0x7D = 2.1625V
0x1E = 0.9750V
0x3E = 1.3750V
0x5E = 1.7750V
0x7E = 2.1750V
0x1F = 0.9875V
0x3F = 1.3875V
0x5F = 1.7875V
0x7F = 2.1875V
Maxim Integrated │ 51
MAX77826
Power Management IC
LDO2_CFG
LDO2 Configuration Register
ADDRESS
MODE
0x21
R/W
TYPE: O
BIT
NAME
POR
7
L2_AD
1
RESET VALUE: 0xA0
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
NMOS LDO Output Voltage
6:0
L2_VOUT[6:0]
www.maximintegrated.com
010 0000
0x00 = 0.6000V
0x20 = 1.0000V
0x40 = 1.4000V
0x60 = 1.8000V
0x01 = 0.6125V
0x21 = 1.0125V
0x41 = 1.4125V
0x61 = 1.8125V
0x02 = 0.6250V
0x22 = 1.0250V
0x42 = 1.4250V
0x62 = 1.8250V
0x03 = 0.6375V
0x23 = 1.0375V
0x43 = 1.4375V
0x63 = 1.8375V
0x04 = 0.6500V
0x24 = 1.0500V
0x44 = 1.4500V
0x64 = 1.8500V
0x05 = 0.6625V
0x25 = 1.0625V
0x45 = 1.4625V
0x65 = 1.8625V
0x06 = 0.6750V
0x26 = 1.0750V
0x46 = 1.4750V
0x66 = 1.8750V
0x07 = 0.6875V
0x27 = 1.0875V
0x47 = 1.4875V
0x67 = 1.8875V
0x08 = 0.7000V
0x28 = 1.1000V
0x48 = 1.5000V
0x68 = 1.9000V
0x09 = 0.7125V
0x29 = 1.1125V
0x49 = 1.5125V
0x69 = 1.9125V
0x0A = 0.7250V
0x2A = 1.1250V
0x4A = 1.5250V
0x6A = 1.9250V
0x0B = 0.7375V
0x2B = 1.1375V
0x4B = 1.5375V
0x6B = 1.9375V
0x0C = 0.7500V
0x2C = 1.1500V
0x4C = 1.5500V
0x6C = 1.9500V
0x0D = 0.7625V
0x2D = 1.1625V
0x4D = 1.5625V
0x6D = 1.9625V
0x0E = 0.7750V
0x2E = 1.1750V
0x4E = 1.5750V
0x6E = 1.9750V
0x0F = 0.7875V
0x2F = 1.1875V
0x4F = 1.5875V
0x6F = 1.9875V
0x10 = 0.8000V
0x30 = 1.2000V
0x50 = 1.6000V
0x70 = 2.0000V
0x11 = 0.8125V
0x31 = 1.2125V
0x51 = 1.6125V
0x71 = 2.0125V
0x12 = 0.8250V
0x32 = 1.2250V
0x52 = 1.6250V
0x72 = 2.0250V
0x13 = 0.8375V
0x33 = 1.2375V
0x53 = 1.6375V
0x73 = 2.0375V
0x14 = 0.8500V
0x34 = 1.2500V
0x54 = 1.6500V
0x74 = 2.0500V
0x15 = 0.8625V
0x35 = 1.2625V
0x55 = 1.6625V
0x75 = 2.0625V
0x16 = 0.8750V
0x36 = 1.2750V
0x56 = 1.6750V
0x76 = 2.0750V
0x17 = 0.8875V
0x37 = 1.2875V
0x57 = 1.6875V
0x77 = 2.0875V
0x18 = 0.9000V
0x38 = 1.3000V
0x58 = 1.7000V
0x78 = 2.1000V
0x19 = 0.9125V
0x39 = 1.3125V
0x59 = 1.7125V
0x79 = 2.1125V
0x1A = 0.9250V
0x3A = 1.3250V
0x5A = 1.7250V
0x7A = 2.1250V
0x1B = 0.9375V
0x3B = 1.3375V
0x5B = 1.7375V
0x7B = 2.1375V
0x1C = 0.9500V
0x3C = 1.3500V
0x5C = 1.7500V
0x7C = 2.1500V
0x1D = 0.9625V
0x3D = 1.3625V
0x5D = 1.7625V
0x7D = 2.1625V
0x1E = 0.9750V
0x3E = 1.3750V
0x5E = 1.7750V
0x7E = 2.1750V
0x1F = 0.9875V
0x3F = 1.3875V
0x5F = 1.7875V
0x7F = 2.1875V
Maxim Integrated │ 52
MAX77826
Power Management IC
LDO3_CFG
LDO3 Configuration Register
ADDRESS
MODE
0x22
R/W
TYPE: O
BIT
NAME
POR
7
L3_AD
1
RESET VALUE: 0xA0
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
NMOS LDO Output Voltage Table
6:0
L3_VOUT[6:0]
www.maximintegrated.com
010 0000
0x00 = 0.6000V
0x20 = 1.0000V
0x40 = 1.4000V
0x60 = 1.8000V
0x01 = 0.6125V
0x21 = 1.0125V
0x41 = 1.4125V
0x61 = 1.8125V
0x02 = 0.6250V
0x22 = 1.0250V
0x42 = 1.4250V
0x62 = 1.8250V
0x03 = 0.6375V
0x23 = 1.0375V
0x43 = 1.4375V
0x63 = 1.8375V
0x04 = 0.6500V
0x24 = 1.0500V
0x44 = 1.4500V
0x64 = 1.8500V
0x05 = 0.6625V
0x25 = 1.0625V
0x45 = 1.4625V
0x65 = 1.8625V
0x06 = 0.6750V
0x26 = 1.0750V
0x46 = 1.4750V
0x66 = 1.8750V
0x07 = 0.6875V
0x27 = 1.0875V
0x47 = 1.4875V
0x67 = 1.8875V
0x08 = 0.7000V
0x28 = 1.1000V
0x48 = 1.5000V
0x68 = 1.9000V
0x09 = 0.7125V
0x29 = 1.1125V
0x49 = 1.5125V
0x69 = 1.9125V
0x0A = 0.7250V
0x2A = 1.1250V
0x4A = 1.5250V
0x6A = 1.9250V
0x0B = 0.7375V
0x2B = 1.1375V
0x4B = 1.5375V
0x6B = 1.9375V
0x0C = 0.7500V
0x2C = 1.1500V
0x4C = 1.5500V
0x6C = 1.9500V
0x0D = 0.7625V
0x2D = 1.1625V
0x4D = 1.5625V
0x6D = 1.9625V
0x0E = 0.7750V
0x2E = 1.1750V
0x4E = 1.5750V
0x6E = 1.9750V
0x0F = 0.7875V
0x2F = 1.1875V
0x4F = 1.5875V
0x6F = 1.9875V
0x10 = 0.8000V
0x30 = 1.2000V
0x50 = 1.6000V
0x70 = 2.0000V
0x11 = 0.8125V
0x31 = 1.2125V
0x51 = 1.6125V
0x71 = 2.0125V
0x12 = 0.8250V
0x32 = 1.2250V
0x52 = 1.6250V
0x72 = 2.0250V
0x13 = 0.8375V
0x33 = 1.2375V
0x53 = 1.6375V
0x73 = 2.0375V
0x14 = 0.8500V
0x34 = 1.2500V
0x54 = 1.6500V
0x74 = 2.0500V
0x15 = 0.8625V
0x35 = 1.2625V
0x55 = 1.6625V
0x75 = 2.0625V
0x16 = 0.8750V
0x36 = 1.2750V
0x56 = 1.6750V
0x76 = 2.0750V
0x17 = 0.8875V
0x37 = 1.2875V
0x57 = 1.6875V
0x77 = 2.0875V
0x18 = 0.9000V
0x38 = 1.3000V
0x58 = 1.7000V
0x78 = 2.1000V
0x19 = 0.9125V
0x39 = 1.3125V
0x59 = 1.7125V
0x79 = 2.1125V
0x1A = 0.9250V
0x3A = 1.3250V
0x5A = 1.7250V
0x7A = 2.1250V
0x1B = 0.9375V
0x3B = 1.3375V
0x5B = 1.7375V
0x7B = 2.1375V
0x1C = 0.9500V
0x3C = 1.3500V
0x5C = 1.7500V
0x7C = 2.1500V
0x1D = 0.9625V
0x3D = 1.3625V
0x5D = 1.7625V
0x7D = 2.1625V
0x1E = 0.9750V
0x3E = 1.3750V
0x5E = 1.7750V
0x7E = 2.1750V
0x1F = 0.9875V
0x3F = 1.3875V
0x5F = 1.7875V
0x7F = 2.1875V
Maxim Integrated │ 53
MAX77826
Power Management IC
LDO4_CFG
LDO4 Configuration Register
ADDRESS
MODE
0x23
R/W
TYPE: O
BIT
NAME
POR
7
L4_AD
1
RESET VALUE: 0x9C
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLV LDO Output Voltage Table
6:0
L4_VOUT[6:0]
www.maximintegrated.com
001 1100
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 54
MAX77826
Power Management IC
LDO5_CFG
LDO5 Configuration Register
ADDRESS
MODE
0x24
R/W
TYPE: O
BIT
NAME
POR
7
L5_AD
1
RESET VALUE: 0xA8
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLV LDO Output Voltage Table
6:0
L5_VOUT[6:0]
www.maximintegrated.com
010 1000
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 55
MAX77826
Power Management IC
LDO6_CFG
LDO6 Configuration Register
ADDRESS
MODE
0x25
R/W
TYPE: O
BIT
NAME
POR
7
L6_AD
1
RESET VALUE: 0xA8
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLV LDO Output Voltage
6:0
L6_VOUT[6:0]
www.maximintegrated.com
010 1000
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 56
MAX77826
Power Management IC
LDO7_CFG
LDO7 Configuration Register
ADDRESS
MODE
0x26
R/W
TYPE: O
BIT
NAME
POR
7
L7_AD
1
RESET VALUE: 0xA8
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLV LDO Output Voltage
6:0
L7_VOUT[6:0]
www.maximintegrated.com
010 1000
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 57
MAX77826
Power Management IC
LDO8_CFG
LDO8 Configuration Register
ADDRESS
MODE
0x27
R/W
TYPE: O
BIT
NAME
POR
7
L8_AD
1
RESET VALUE: 0xA8
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLV LDO Output Voltage
6:0
L8_VOUT[6:0]
www.maximintegrated.com
010 1000
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 58
MAX77826
Power Management IC
LDO9_CFG
LDO9 Configuration Register
ADDRESS
MODE
0x28
R/W
TYPE: O
BIT
NAME
POR
7
L9_AD
1
RESET VALUE: 0xA8
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLV LDO Output Voltage
6:0
L9_VOUT[6:0]
www.maximintegrated.com
010 1000
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 59
MAX77826
Power Management IC
LDO10_CFG
LDO10 Configuration Register
ADDRESS
MODE
0x29
R/W
TYPE: O
BIT
NAME
POR
7
L10_AD
1
RESET VALUE: 0xD0
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLS LDO Output Voltage
6:0
L10_VOUT[6:0]
www.maximintegrated.com
101 0000
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 60
MAX77826
Power Management IC
LDO11_CFG
LDO11 Configuration Register
ADDRESS
MODE
0x29
R/W
TYPE: O
BIT
NAME
POR
7
L10_AD
1
RESET VALUE: 0xD0
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLS LDO Output Voltage
6:0
L10_VOUT[6:0]
www.maximintegrated.com
101 0000
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 61
MAX77826
Power Management IC
LDO12_CFG
LDO12 Configuration Register
ADDRESS
MODE
0x2B
R/W
TYPE: O
BIT
NAME
POR
7
L12_AD
1
RESET VALUE: 0xE4
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLS LDO Output Voltage
6:0
L12_VOUT[6:0]
www.maximintegrated.com
110 0100
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 62
MAX77826
Power Management IC
LDO13_CFG
LDO13 Configuration Register
ADDRESS
MODE
0x2C
R/W
TYPE: O
BIT
NAME
POR
7
L13_AD
1
RESET VALUE: 0xE4
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLS LDO Output Voltage
6:0
L13_VOUT[6:0]
www.maximintegrated.com
110 0100
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 63
MAX77826
Power Management IC
LDO14_CFG
LDO14 Configuration Register
ADDRESS
MODE
0x2D
R/W
TYPE: O
BIT
NAME
POR
7
L14_AD
1
RESET VALUE: 0xE4
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLS LDO Output Voltage
6:0
L14_VOUT[6:0]
www.maximintegrated.com
110 0100
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Maxim Integrated │ 64
MAX77826
Power Management IC
LDO15_CFG
LDO15 Configuration Register
ADDRESS
MODE
0x2E
R/W
TYPE: O
BIT
NAME
POR
7
L15_AD
1
RESET VALUE: 0xE4
DESCRIPTION
Output Active Discharge
0: Disable
1: Enable
PMOSLS LDO Output Voltage
6:0
L15_VOUT[6:0]
110 0100
0x00 = 0.800V
0x20 = 1.600V
0x40 = 2.400V
0x60 = 3.200V
0x01 = 0.825V
0x21 = 1.625V
0x41 = 2.425V
0x61 = 3.225V
0x02 = 0.850V
0x22 = 1.650V
0x42 = 2.450V
0x62 = 3.250V
0x03 = 0.875V
0x23 = 1.675V
0x43 = 2.475V
0x63 = 3.275V
0x04 = 0.900V
0x24 = 1.700V
0x44 = 2.500V
0x64 = 3.300V
0x05 = 0.925V
0x25 = 1.725V
0x45 = 2.525V
0x65 = 3.325V
0x06 = 0.950V
0x26 = 1.750V
0x46 = 2.550V
0x66 = 3.350V
0x07 = 0.975V
0x27 = 1.775V
0x47 = 2.575V
0x67 = 3.375V
0x08 = 1.000V
0x28 = 1.800V
0x48 = 2.600V
0x68 = 3.400V
0x09 = 1.025V
0x29 = 1.825V
0x49 = 2.625V
0x69 = 3.425V
0x0A = 1.050V
0x2A = 1.850V
0x4A = 2.650V
0x6A = 3.450V
0x0B = 1.075V
0x2B = 1.875V
0x4B = 2.675V
0x6B = 3.475V
0x0C = 1.100V
0x2C = 1.900V
0x4C = 2.700V
0x6C = 3.500V
0x0D = 1.125V
0x2D = 1.925V
0x4D = 2.725V
0x6D = 3.525V
0x0E = 1.150V
0x2E = 1.950V
0x4E = 2.750V
0x6E = 3.550V
0x0F = 1.175V
0x2F = 1.975V
0x4F = 2.775V
0x6F = 3.575V
0x10 = 1.200V
0x30 = 2.000V
0x50 = 2.800V
0x70 = 3.600V
0x11 = 1.225V
0x31 = 2.025V
0x51 = 2.825V
0x71 = 3.625V
0x12 = 1.250V
0x32 = 2.050V
0x52 = 2.850V
0x72 = 3.650V
0x13 = 1.275V
0x33 = 2.075V
0x53 = 2.875V
0x73 = 3.675V
0x14 = 1.300V
0x34 = 2.100V
0x54 = 2.900V
0x74 = 3.700V
0x15 = 1.325V
0x35 = 2.125V
0x55 = 2.925V
0x75 = 3.725V
0x16 = 1.350V
0x36 = 2.150V
0x56 = 2.950V
0x76 = 3.750V
0x17 = 1.375V
0x37 = 2.175V
0x57 = 2.975V
0x77 = 3.775V
0x18 = 1.400V
0x38 = 2.200V
0x58 = 3.000V
0x78 = 3.800V
0x19 = 1.425V
0x39 = 2.225V
0x59 = 3.025V
0x79 = 3.825V
0x1A = 1.450V
0x3A = 2.250V
0x5A = 3.050V
0x7A = 3.850V
0x1B = 1.475V
0x3B = 2.275V
0x5B = 3.075V
0x7B = 3.875V
0x1C = 1.500V
0x3C = 2.300V
0x5C = 3.100V
0x7C = 3.900V
0x1D = 1.525V
0x3D = 2.325V
0x5D = 3.125V
0x7D = 3.925V
0x1E = 1.550V
0x3E = 2.350V
0x5E = 3.150V
0x7E = 3.950V
0x1F = 1.575V
0x3F = 2.375V
0x5F = 3.175V
0x7F = 3.975V
Note: 0x2F: RSVD.
www.maximintegrated.com
Maxim Integrated │ 65
MAX77826
Power Management IC
BUCK_CFG
BUCK Configuration Register
ADDRESS
MODE
0x30
R/W
BIT
NAME
TYPE: O
POR
RESET VALUE: 0x09
DESCRIPTION
Rising Ramp Rate Control
00b: 12.5mV/µs
01b: 25mV/µs
10b: 50mV/µs
11b: 100mV/µs
7:6
B_RAMP[1:0]
00
5:4
RSVD
00
3
B_AD
1
Output Active Discharge
0: Disable
1: Enable
Forced PWM
0: Turn off Forced PWM
(Automatic SKIP mode operation under light load)
1: Turn on Forced PWM Mode
2
B_FPWM
0
1
RSVD
0
0
B_FSRAD
1
Falling Slew Rate Active Discharge
0: Disable Active Discharge
BUCK is allowed to operate in SKIP mode during the time the output voltage
decreases (only if B3_FPWM = 0). In SKIP mode, BUCK cannot sink
current from the output capacitor and the output voltage falling slew rate is
a function of the external load. If the load is heavy, the output voltage falling
slew rate is limited to 6.25mV/µs. If the load is light, the output voltage falling
slew rate is a function of the output capacitance and the load. Note that the
internal feedback string always imposes a 2µA load on the output.
1: Enable Active Discharge
BUCK operates in forced PWM mode during the time the output voltage
decreases. In forced PWM mode, BUCK can sink current from the output
capacitor to ensure that the output voltage falls at the rate of 6.25mV/µs.
To ensure a smooth output voltage ramp-down, forced PMW mode remains
engaged for 50µs after the output voltage decreases to its target voltage.
www.maximintegrated.com
Maxim Integrated │ 66
MAX77826
Power Management IC
BUCK_VOUT
BUCK Output Voltage Setting Register
ADDRESS
MODE
0x31
R/W
TYPE: O
RESET VALUE: 0x78
BIT
NAME
POR
DESCRIPTION
7:0
B_VOUT[7:0]
0111 1000
BUCK Output Voltage (see table immediately below)
BUCK Output Voltage
0x00 =
0.50000V
0x20 =
0.70000V
0x40 =
0.90000V
0x60 =
1.10000V
0x80 =
1.30000V
0xA0 =
1.50000V
0xC0 =
1.70000V
0xE0 =
1.80000V
0x01 =
0.50625V
0x21 =
0.70625V
0x41 =
0.90625V
0x61 =
1.10625V
0x81 =
1.30625V
0xA1 =
1.50625V
0xC1 =
1.70625V
0xE1 =
1.80000V
0x02 =
0.51250V
0x22 =
0.71250V
0x42 =
0.91250V
0x62 =
1.11250V
0x82 =
1.31250V
0xA2 =
1.51250V
0xC2 =
1.71250V
0xE2 =
1.80000V
0x03 =
0.51875V
0x23 =
0.71875V
0x43 =
0.91875V
0x63 =
1.11875V
0x83 =
1.31875V
0xA3 =
1.51875V
0xC3 =
1.71875V
0xE3 =
1.80000V
0x04 =
0.52500V
0x24 =
0.72500V
0x44 =
0.92500V
0x64 =
1.12500V
0x84 =
1.32500V
0xA4 =
1.52500V
0xC4 =
1.72500V
0xE4 =
1.80000V
0x05 =
0.53125V
0x25 =
0.73125V
0x45 =
0.93125V
0x65 =
1.13125V
0x85 =
1.33125V
0xA5 =
1.53125V
0xC5 =
1.73125V
0xE5 =
1.80000V
0x06 =
0.53750V
0x26 =
0.73750V
0x46 =
0.93750V
0x66 =
1.13750V
0x86 =
1.33750V
0xA6 =
1.53750V
0xC6 =
1.73750V
0xE6 =
1.80000V
0x07 =
0.54375V
0x27 =
0.74375V
0x47 =
0.94375V
0x67 =
1.14375V
0x87 =
1.34375V
0xA7 =
1.54375V
0xC7 =
1.74375V
0xE7 =
1.80000V
0x08 =
0.55000V
0x28 =
0.75000V
0x48 =
0.95000V
0x68 =
1.15000V
0x88 =
1.35000V
0xA8 =
1.55000V
0xC8 =
1.75000V
0xE8 =
1.80000V
0x09 =
0.55625V
0x29 =
0.75625V
0x49 =
0.95625V
0x69 =
1.15625V
0x89 =
1.35625V
0xA9 =
1.55625V
0xC9 =
1.75625V
0xE9 =
1.80000V
0x0A =
0.56250V
0x2A =
0.76250V
0x4A =
0.96250V
0x6A =
1.16250V
0x8A =
1.36250V
0xAA =
1.56250V
0xCA =
1.76250V
0xEA =
1.80000V
0x0B =
0.56875V
0x2B =
0.76875V
0x4B =
0.96875V
0x6B =
1.16875V
0x8B =
1.36875V
0xAB =
1.56875V
0xCB =
1.76875V
0xEB =
1.80000V
0x0C =
0.57500V
0x2C =
0.77500V
0x4C =
0.97500V
0x6C =
1.17500V
0x8C =
1.37500V
0xAC =
1.57500V
0xCC =
1.77500V
0xEC =
1.80000V
0x0D =
0.58125V
0x2D =
0.78125V
0x4D =
0.98125V
0x6D =
1.18125V
0x8D =
1.38125V
0xAD =
1.58125V
0xCD =
1.78125V
0xED =
1.80000V
0x0E =
0.58750V
0x2E =
0.78750V
0x4E =
0.98750V
0x6E =
1.18750V
0x8E =
1.38750V
0xAE =
1.58750V
0xCE =
1.78750V
0xEE =
1.80000V
0x0F =
0.59375V
0x2F =
0.79375V
0x4F =
0.99375V
0x6F =
1.19375V
0x8F =
1.39375V
0xAF =
1.59375V
0xCF =
1.79375V
0xEF =
1.80000V
www.maximintegrated.com
Maxim Integrated │ 67
MAX77826
Power Management IC
BUCK Output Voltage (continued)
0x10 =
0.60000V
0x30 =
0.80000V
0x50 =
1.00000V
0x70 =
1.20000V
0x90 =
1.40000V
0xB0 =
1.60000V
0xD0 =
1.80000V
0xF0 =
1.80000V
0x11 =
0.60625V
0x31 =
0.80625V
0x51 =
1.00625V
0x71 =
1.20625V
0x91 =
1.40625V
0xB1 =
1.60625V
0xD1 =
1.80000V
0xF1 =
1.80000V
0x12 =
0.61250V
0x32 =
0.81250V
0x52 =
1.01250V
0x72 =
1.21250V
0x92 =
1.41250V
0xB2 =
1.61250V
0xD2 =
1.80000V
0xF2 =
1.80000V
0x13 =
0.61875V
0x33 =
0.81875V
0x53 =
1.01875V
0x73 =
1.21875V
0x93 =
1.41875V
0xB3 =
1.61875V
0xD3 =
1.80000V
0xF3 =
1.80000V
0x14 =
0.62500V
0x34 =
0.82500V
0x54 =
1.02500V
0x74 =
1.22500V
0x94 =
1.42500V
0xB4 =
1.62500V
0xD4 =
1.80000V
0xF4 =
1.80000V
0x15 =
0.63125V
0x35 =
0.83125V
0x55 =
1.03125V
0x75 =
1.23125V
0x95 =
1.43125V
0xB5 =
1.63125V
0xD5 =
1.80000V
0xF5 =
1.80000V
0x16 =
0.63750V
0x36 =
0.83750V
0x56 =
1.03750V
0x76 =
1.23750V
0x96 =
1.43750V
0xB6 =
1.63750V
0xD6 =
1.80000V
0xF6 =
1.80000V
0x17 =
0.64375V
0x37 =
0.84375V
0x57 =
1.04375V
0x77 =
1.24375V
0x97 =
1.44375V
0xB7 =
1.64375V
0xD7 =
1.80000V
0xF7 =
1.80000V
0x18 =
0.65000V
0x38 =
0.85000V
0x58 =
1.05000V
0x78 =
1.25000V
0x98 =
1.45000V
0xB8 =
1.65000V
0xD8 =
1.80000V
0xF8 =
1.80000V
0x19 =
0.65625V
0x39 =
0.85625V
0x59 =
1.05625V
0x79 =
1.25625V
0x99 =
1.45625V
0xB9 =
1.65625V
0xD9 =
1.80000V
0xF9 =
1.80000V
0x1A =
0.66250V
0x3A =
0.86250V
0x5A =
1.06250V
0x7A =
1.26250V
0x9A =
1.46250V
0xBA =
1.66250V
0xDA =
1.80000V
0xFA =
1.80000V
0x1B =
0.66875V
0x3B =
0.86875V
0x5B =
1.06875V
0x7B =
1.26875V
0x9B =
1.46875V
0xBB =
1.66875V
0xDB =
1.80000V
0xFB =
1.80000V
0x1C =
0.67500V
0x3C =
0.87500V
0x5C =
1.07500V
0x7C =
1.27500V
0x9C =
1.47500V
0xBC =
1.67500V
0xDC =
1.80000V
0xFC =
1.80000V
0x1D =
0.68125V
0x3D =
0.88125V
0x5D =
1.08125V
0x7D =
1.28125V
0x9D =
1.48125V
0xBD =
1.68125V
0xDD =
1.80000V
0xFD =
1.80000V
0x1E =
0.68750V
0x3E =
0.88750V
0x5E =
1.08750V
0x7E =
1.28750V
0x9E =
1.48750V
0xBE =
1.68750V
0xDE =
1.80000V
0xFE =
1.80000V
0x1F =
0.69375V
0x3F =
0.89375V
0x5F =
1.09375V
0x7F =
1.29375V
0x9F =
1.49375V
0xBF =
1.69375V
0xDF =
1.80000V
0xFF =
1.80000V
www.maximintegrated.com
Maxim Integrated │ 68
MAX77826
Power Management IC
BB_CFG
BUCK BOOST Configuration Register
ADDRESS
MODE
0x32
R/W
TYPE: O
BIT
NAME
POR
7:6
RSVD
00
RESET VALUE: 0x3C
DESCRIPTION
5:4
BB_OVP_TH[1:0]
11
Output OVP Threshold
00b: No OVP
01b: 110% of VOUT
10b: 115% of VOUT
11b: 120% of VOUT
3
BB_AD
1
Output Active Discharge
0: Disable 1kΩ active discharge.
1: Enable 1kΩ active discharge.
1
High-Skip Mode Enable
0: Disable high-skip mode.
1: Enable high-skip mode.
HSKIP function is active only when BB_FPWM = 0 and BB_HSKIP = 1.
Forced PWM Enable
0: HSKIP mode
HSKIP function is active when BB_FPWM = 0 and BB_HSKIP = 0.
1: Forced PWM
2
BB_HSKIP
1
BB_FPWM
0
0
RSVD
0
www.maximintegrated.com
Maxim Integrated │ 69
MAX77826
Power Management IC
BB_VOUT
BUCK BOOST Output Voltage Setting Register
ADDRESS
MODE
0x33
R/W
TYPE: O
BIT
NAME
POR
7
RSVD
0
RESET VALUE: 0x48
DESCRIPTION
Write 0.
BUCK BOOST Output Voltage
6:0
BB_VOUT[6:0]
100 0000
0x00 = 2.6000V
0x20 = 3.0000V
0x40 = 3.4000V
0x60 = 3.8000V
0x01 = 2.6125V
0x21 = 3.0125V
0x41 = 3.4125V
0x61 = 3.8125V
0x02 = 2.6250V
0x22 = 3.0250V
0x42 = 3.4250V
0x62 = 3.8250V
0x03 = 2.6375V
0x23 = 3.0375V
0x43 = 3.4375V
0x63 = 3.8375V
0x04 = 2.6500V
0x24 = 3.0500V
0x44 = 3.4500V
0x64 = 3.8500V
0x05 = 2.6625V
0x25 = 3.0625V
0x45 = 3.4625V
0x65 = 3.8625V
0x06 = 2.6750V
0x26 = 3.0750V
0x46 = 3.4750V
0x66 = 3.8750V
0x07 = 2.6875V
0x27 = 3.0875V
0x47 = 3.4875V
0x67 = 3.8875V
0x08 = 2.7000V
0x28 = 3.1000V
0x48 = 3.5000V
0x68 = 3.9000V
0x09 = 2.7125V
0x29 = 3.1125V
0x49 = 3.5125V
0x69 = 3.9125V
0x0A = 2.7250V
0x2A = 3.1250V
0x4A = 3.5250V
0x6A = 3.9250V
0x0B = 2.7375V
0x2B = 3.1375V
0x4B = 3.5375V
0x6B = 3.9375V
0x0C = 2.7500V
0x2C = 3.1500V
0x4C = 3.5500V
0x6C = 3.9500V
0x0D = 2.7625V
0x2D = 3.1625V
0x4D = 3.5625V
0x6D = 3.9625V
0x0E = 2.7750V
0x2E = 3.1750V
0x4E = 3.5750V
0x6E = 3.9750V
0x0F = 2.7875V
0x2F = 3.1875V
0x4F = 3.5875V
0x6F = 3.9875V
0x10 = 2.8000V
0x30 = 3.2000V
0x50 = 3.6000V
0x70 = 4.0000V
0x11 = 2.8125V
0x31 = 3.2125V
0x51 = 3.6125V
0x71 = 4.0125V
0x12 = 2.8250V
0x32 = 3.2250V
0x52 = 3.6250V
0x72 = 4.0250V
0x13 = 2.8375V
0x33 = 3.2375V
0x53 = 3.6375V
0x73 = 4.0375V
0x14 = 2.8500V
0x34 = 3.2500V
0x54 = 3.6500V
0x74 = 4.0500V
0x15 = 2.8625V
0x35 = 3.2625V
0x55 = 3.6625V
0x75 = 4.0625V
0x16 = 2.8750V
0x36 = 3.2750V
0x56 = 3.6750V
0x76 = 4.0750V
0x17 = 2.8875V
0x37 = 3.2875V
0x57 = 3.6875V
0x77 = 4.0875V
0x18 = 2.9000V
0x38 = 3.3000V
0x58 = 3.7000V
0x78 = 4.1000V
0x19 = 2.9125V
0x39 = 3.3125V
0x59 = 3.7125V
0x79 = 4.1125V
0x1A = 2.9250V
0x3A = 3.3250V
0x5A = 3.7250V
0x7A = 4.1250V
0x1B = 2.9375V
0x3B = 3.3375V
0x5B = 3.7375V
0x7B = 4.1375V
0x1C = 2.9500V
0x3C = 3.3500V
0x5C = 3.7500V
0x7C = 4.1500V
0x1D = 2.9625V
0x3D = 3.3625V
0x5D = 3.7625V
0x7D = 4.1625V
0x1E = 2.9750V
0x3E = 3.3750V
0x5E = 3.7750V
0x7E = 4.1750V
0x1F = 2.9875V
0x3F = 3.3875V
0x5F = 3.7875V
0x7F = 4.1875V
Note: 0x34–0x3F: RSVD.
www.maximintegrated.com
Maxim Integrated │ 70
MAX77826
Power Management IC
BUCK_SS_FREQ
BUCK Soft-Start and Switching Frequency Configuration Register
ADDRESS
MODE
0x40
R/W
TYPE: O
BIT
NAME
POR
7:5
RSVD
000
4
B_SS
0
BUCK Soft-Start Slew Rate
0: 14mV/µs
1: 25mV/µs
3
RSVD
0
Write 0.
2:0
B_FREQ[2:0]
100
RESET VALUE: 0x04
DESCRIPTION
Write 0.
Multiphase Current Mode BUCK Switching Frequency
000b: 3.6MHz
001b: 3.2MHz
010b: 2.8MHz
011b: 2.4MHz
100b: 2.0MHz
101b: 1.6MHz
110b: 1.2MHz
111b: 0.8MHz
UVLO_FALL
VSYS UVLO Falling Threshold Program Register
ADDRESS
MODE
0x41
R/W
TYPE: O
BIT
NAME
POR
7:2
RSVD
0000 00
1:0
UVLO_F[1:0]
01
RESET VALUE: 0x01
DESCRIPTION
Write 0000 00.
VSYS UVLO Falling Threshold
00b: Not used
01b: 2.05V
10b: 2.25V
11b: 2.45V
Note: 0x42–0xFF: RSVD.
www.maximintegrated.com
Maxim Integrated │ 71
MAX77826
Power Management IC
Typical Application Circuit
BATT
INB
SYS
GND
1µF
REFBYP
FB_B
SBIAS, REF,
UVLO, TSHDN
BUCK
3A
0.1µF
1.5kΩ x 2
VIO
VIO
800kΩ
ENB
INBB
SCL
LXBB1
SDA
CE
INL1
4.7µF
LDO1
(N600)
LDO2
LDO2
(N150)
INL2
1µF
LDO3
4.7µF
BUCK-BOOST
2A
MAX77826
LDO1
1µF
BUCK
BATT
1µH
10µF
LXBB2
FB_BB
3x 22µF
OUTBB
PGNDBB
800kΩ
ON/OFF
CONTROL
AND
I2C INTERFACE
ENBB
INL4
LDO3
(N450)
LDO10
(P300LS)
LDO10
LDO11
(P150LS)
LDO11
INL3
2.15V
4.7µF
2x 22µF
VIO
IRQB
BUCK
4.7µF
0.47µH
4.7µF
4.7µF
2.2µF
ENL12
LDO4
LDO4
(P300LV)
LDO5
LDO5
(P300LV)
LDO6
LDO6
(P150LV)
2.2µF
4.7µF
2.2µF
LDO7
LDO7
(P300LV)
LDO8
LDO8
(P150LV)
LDO9
2.2µF
www.maximintegrated.com
BATT
2.2µF
INL5
4.7µF
BATT
PGNDB
0.1µ
F
100kΩ
LXB
10µF
LDO9
(P150LV)
4.7µF
800kΩ
LDO12
(P300LS)
LDO12
LDO13
(P300LS)
LDO13
LDO14
(P150LS)
LDO14
LDO15
(P150LS)
LDO15
BB
2.2µF
2.2µF
2.2µF
2.2µF
Maxim Integrated │ 72
MAX77826
Power Management IC
Ordering Information
Package Information
PART
TEMP RANGE
PIN-PACKAGE
MAX77826EWJ+
-40°C to +85°C
49 Bumps (7 x 7)
0.4mm Pitch
+Denotes a lead(Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: S18B
www.maximintegrated.com
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
49 WLP
W493E3+1
21-0728
Refer to
Application
Note 1891
Maxim Integrated │ 73
MAX77826
Power Management IC
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
6/15
Initial release
1
7/15
Corrected typos and updated notes in Electrical Characteristics table.
—
4, 7
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2015 Maxim Integrated Products, Inc. │ 74
工商网监
湘ICP备2023018690号
