19-4504; Rev 4; 6/11
KIT
ATION
EVALU
E
L
B
AVAILA
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Features
The MAX8649/MAX8649A high-efficiency DC-to-DC stepdown switching regulators deliver up to 1.8A of output current. The device operates from a 2.5V to 5.5V input
voltage range, making it future proof for next-generation
battery technologies. The output voltage is I2C programmable from 0.75V to 1.38V. Remote sense ensures precise DC regulation at the load. Total output error is less
than 2% over load, line, and temperature.
The ICs operate at a 3.25MHz fixed frequency. The high
operating frequency minimizes the size of external components. The switching frequency of the converter can be
synchronized to the master clock of the application. When
synchronizing to an external clock, the ICs measure the
frequency of the external clock to ensure that the clock is
stable before changing the switching frequency to the
external clock frequency.
An on-board DAC allows adjustment of the output voltage in 10mV steps. The output voltage can be programmed directly through the I 2 C interface, or by
preloading a set of on-board registers and using the
two VID logic signals to select the appropriate register.
Other features include internal soft-start control circuitry
to reduce inrush current, output overvoltage, overcurrent, and overtemperature protection.
The ICs feature different I2C addresses so that devices
may be used in a system. For a 2.5A version of this
device, refer to the MAX8952 data sheet.
o 1.8A Guaranteed Output Current
o I2C Programmable VOUT (750mV to 1.38V in 10mV
Steps)
o Operates from 2.5V to 5.5V Input Supply
o On-Chip FET and Synchronous Rectifier
o Fixed 3.25MHz PWM Switching Frequency
o Synchronizes to 13MHz, 19.2MHz, or 26MHz
System Clock when Available
o Small 1.0µH Inductor
o Initial Accuracy 0.5% at 1.25V Output
o 2% Output Accuracy Over Load, Line, and
Temperature
o Power-Save Mode Increases Light Load Efficiency
o Overvoltage and Overcurrent Protection
o Thermal Shutdown Protection
o 400kHz I2C Interface
o < 1µA Shutdown Current
o 16-Bump, 2mm x 2mm WLP Package
Applications
Cell Phones and Smartphones
PDAs and MP3 Players
Ordering Information
PART
+
IN1
A1
AGND
A2
VID1
A3
IN2
16 WLP (0.5mm pitch)
0xC0/0xC1
0xC4/0xC5
MAX8649EWE+T
+Denotes a lead(Pb)-free/RoHS-compliant package.
Note: All devices operate over the -40°C to +85°C temperature
range.
Typical Operating Circuit
1.8V TO
3.6V
B1
EN
B2
LX
MAX8649
MAX8649A IN2
A4
B3
LX
2.5V TO
5.5V
VDD
10μF
0.1μF
SNS+
I2C ADDRESS
(WRITE/READ)
MAX8649AEWE+T 16 WLP (0.5mm pitch)
Bump Configuration
TOP VIEW
(BUMPS ON BOTTOM)
PIN-PACKAGE
2.5V TO
5.5V
B4
LX
SCL
11Ω
0.1μF
1μH
10μF
SDA
0.1μF
VOUT
(0.75V TO
1.38V)
PGND
IN1
SNS-
VID0
PGND
C1
C2
C3
PGND
C4
VDD
SDA
SCL
SYNC
D1
D2
D3
D4
2.2μF
0.1μF
FSYNC
SNS+
EN
VID0
CPU
VID1
SNSAGND
WLP 0.5mm PITCH
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX8649/MAX8649A
General Description
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
ABSOLUTE MAXIMUM RATINGS
IN1, IN2 to AGND ..................................................-0.3V to +6.0V
VDD to AGND.........................................................-0.3V to +4.0V
LX, SNS+, VID0, VID1, EN to AGND..........-0.3V to (VIN1 + 0.3V)
SCL, SDA, SYNC to AGND.........................-0.3V to (VDD + 0.3V)
PGND, SNS- to AGND...........................................-0.3V to +0.3V
RMS LX Current ..............................................................1800mA
Continuous Power Dissipation (TA = +70°C)
16-Bump WLP 0.5mm Pitch
(derate 13mW/°C above +70°C) ............................1040mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
WLP
Junction to Ambient Thermal Resistance (θJA)............76°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
MAX
UNITS
IN1, IN2 Operating Range
PARAMETER
2.5
5.5
V
VDD Operating Range
1.8
3.6
V
1.35
V
VDD Undervoltage Lockout
(UVLO) Threshold
CONDITIONS
MIN
VDD falling
0.54
VDD UVLO Hysteresis
IN_ Undervoltage Lockout
(UVLO) Threshold
TYP
0.865
50
VIN falling
2.10
IN_ UVLO Hysteresis
2.15
mV
2.20
70
VDD Shutdown Supply Current
VIN1 = VIN2 = 5.5V,
EN = VDD = AGND
TA = +25°C
0.01
TA = +85°C
0.01
IN1, IN2 Shutdown Supply
Current
VIN1 = VIN2 = 5.5V,
EN = VDD = AGND
TA = +25°C
0.25
TA = +85°C
0.25
IN1, IN2 Standby Supply Current
VIN1 = VIN2 = 5.5V, SCL = SDA =
VDD, EN = AGND, I2C ready
TA = +25°C
0.35
TA = +85°C
0.35
VIN1 = VIN2 = VDD = 3.6V,
SCL = SDA = VDD, EN = AGND,
I2C ready
TA = +25°C
0.02
VDD Standby Supply Current
TA = +85°C
0.02
Logic Input High Voltage (VIH)
VIN1 = VIN2 = 2.5V to 5.5V,
VDD = 1.8V to 3.6V
EN, VID0, VID1
Logic Input Low Voltage (VIL)
VIN1 = VIN2 = 2.5V to 5.5V,
VDD = 1.8V to 3.6V
EN, VID0, VID1
SDA, SCL, SYNC Logic Input
Current
VIL = 0V or VIH = 3.6V,
EN = AGND
TA = +25°C
V
mV
1
1
1
µA
µA
µA
1
µA
LOGIC INTERFACE
2
SYNC, SCL, SDA
1.4
V
0.7 x VDD
0.4
SYNC, SCL, SDA
TA = +85°C
0.3 x VDD
-1
0.01
0.01
_______________________________________________________________________________________
+1
V
µA
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA =
+25°C.) (Note 2)
PARAMETER
VID0, VID1, EN Logic Input
Pulldown Resistor
CONDITIONS
Controlled by I2C command:
VID0_PD = 1
VID1_PD = 1
EN_PD = 1
MIN
TYP
MAX
UNITS
200
320
450
kΩ
0.03
0.4
V
400
kHz
I2C INTERFACE
SDA Output Low Voltage
ISDA = 3mA
2
I C Clock Frequency
Bus-Free Time Between START
and STOP
tBUF
1.3
Hold Time Repeated START
Condition
tHD_STA
0.6
0.1
µs
SCL Low Period
tLOW
1.3
0.2
µs
SCL High Period
tHIGH
0.6
0.2
µs
Setup Time Repeated START
Condition
tSU_STA
0.6
0.1
µs
SDA Hold Time
tHD_DAT
0
-0.01
µs
SDA Setup Time
tSU_DAT
0.1
0.05
µs
Setup Time for STOP Condition
tSU_STO
0.6
0.1
µs
µs
STEP-DOWN DC-DC REGULATOR
IN1 + IN2
Supply Current
OPERATION_MODE_ = 0, VOUT = 1.27V, no switching
54
OPERATION_MODE_ = 1, VOUT = 1.27V, fsw = 3.25MHz
9
mA
Minimum Output Capacitance
Required for Stability
VOUT = 0.75V to 1.38V,
IOUT = 0 to 1.8A
10
µF
OUT Voltage Range
10mV steps
0.750
Output Overvoltage Protection
Rising, 50mV hysteresis (typ)
1.65
1.8
70
µA
1.380
V
1.9
V
_______________________________________________________________________________________
3
MAX8649/MAX8649A
ELECTRICAL CHARACTERISTICS (continued)
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA =
+25°C.) (Note 2)
PARAMETER
OUT Voltage Accuracy
Load Regulation
RAMP Timer
CONDITIONS
MIN
TYP
MAX
No load, VIN_ = 2.5V to 5.5V, VOUT = 1.27V
OPERATION_MODE_ = 1
-0.5
+0.5
IOUT = no load, VIN_ = 2.5V to 5.5V, VOUT = 0.75V,
OPERATION_MODE_ = 1
-1.0
+1.0
IOUT = no load, VIN_ = 2.5V to 5.5V, VOUT = 1.38V,
OPERATION_MODE_ = 1
-0.5
+0.5
RL is the resistance from LX to SNS+ (output)
RL/25
RAMP[2:0] = 000
32.50
RAMP[2:0] = 001
16.25
RAMP[2:0] = 010
8.125
RAMP[2:0] = 011
4.063
RAMP[2:0] = 100
2.031
RAMP[2:0] = 101
1.016
RAMP[2:0] = 110
0.508
RAMP[2:0] = 111
0.254
UNITS
%
V/A
mV/µs
Peak Current Limit
(p-Channel MOSFET)
PWM and hysteretic mode
2.3
2.8
3.2
A
Valley Current Limit
(n-Channel MOSFET)
Hysteretic mode
1.8
2.4
3.0
A
Negative Current Limit
(n-Channel MOSFET)
PWM mode
2.0
2.5
3.0
A
n-Channel Zero-Crossing
Threshold
50
mA
LX pFET On-Resistance
IN2 to LX, ILX = -200mA
0.08
0.16
Ω
LX nFET On-Resistance
OPERATION_MODE = 0
LX to PGND, ILX = 200mA
0.06
0.12
Ω
LX Leakage
VLX = 5.5V or 0V
0.03
+1
Operating Frequency
4
TA = +25°C
-1
TA = +85°C
0.05
Internal oscillator, PWM
2.82
3.25
3.56
Internal oscillator, power-save mode before entering
PWM mode
2.43
3.25
4.06
13MHz option
fSYNC/4
19.2MHz option
fSYNC/6
26MHz option
fSYNC/8
_______________________________________________________________________________________
µA
MHz
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA =
+25°C.) (Note 2)
PARAMETER
Minimum Duty Cycle
CONDITIONS
MIN
Forced PWM mode only, minimum duty cycle in
(OPERATION_MODE_ = 1) = 0%
Maximum Duty Cycle
60
Minimum On- and Off-Time
30
OUT Discharge Resistance
TYP
During shutdown or UVLO, from SNS+ to PGND
MAX
UNITS
16
%
50
ns
%
40
Ω
650
SNS+, SNS- Input Impedance
VOUT = 0.75V (OUT_MODEx [5:0] = 0b000000)
Time Delay from PWM
to Power-Save Mode
Time required for error amplifier to stabilize before
switching mode
400
600
850
kΩ
70
µs
Time Delay from Power-Save
Mode to PWM
Time required for error amplifier to stabilize before
switching mode
140
µs
SYNCHRONIZATION (SYNC)
SYNC Capture Range
SYNC Pulse Width
SYNC = 00 default
18.9
26.0
38.0
SYNC = 1X default
14.2
19.2
28.5
SYNC = 01 default
9.5
13.0
19.0
MHz
13
ns
20
°C
+160
°C
PROTECTION CIRCUITS
Thermal-Shutdown Hysteresis
Thermal Shutdown
Note 2: All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design.
_______________________________________________________________________________________
5
MAX8649/MAX8649A
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25°C, unless otherwise noted.)
60
VIN = 3.2V
3.6V
4.2V
50
40
80
40
20
20
FORCED PWM
VIN = 3.2V
3.6V
4.2V
50
30
80
0.001
0.01
0.1
1
0.01
0.1
1
0.001
0.01
0.1
1
EFFICIENCY vs. LOAD CURRENT
(1.3V OUTPUT, 26MHz SYNC)
60
40
30
30
20
20
FORCED PWM
10
0.001
0.01
0.1
1
VIN = 3.2V
3.6V
4.2V
50
70
60
VIN = 3.2V
3.6V
4.2V
50
40
30
20
FORCED PWM
10
0
0.0001
10
80
EFFICIENCY (%)
70
POWER SAVE
90
0.001
0.01
0.1
1
FORCED PWM
10
0
0.0001
10
0.001
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
SWITCHING FREQUENCY
vs. LOAD CURRENT
SWITCHING FREQUENCY
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT vs.
SUPPLY VOLTAGE (POWER SAVE)
TRANSITION TO PWM
2.0
1.5
POWER SAVE
3.4
3.3
3.2
0.3
0.6
0.9
1.2
LOAD CURRENT (A)
1.5
1.8
MAX8649/49A toc09
0.5
0.4
26MHz SYNC
0.3
0.2
0.1
NO SYNC
1.3V OUTPUT, 500mA LOAD
3.0
0
10
NO SYNC
3.1
VIN = 3.6V
VOUT = 1.3V
0.5
3.5
0.6
SUPPLY CURRENT (mA)
2.5
MAX8649/49A toc08
FORCED PWM
3.6
SWITCHING FREQUENCY (MHz)
MAX8649/49A toc07
3.5
10
MAX8649/49A toc06
80
EFFICIENCY (%)
40
POWER SAVE
90
100
MAX8649/49A toc05
100
MAX8649/49A toc04
VIN = 3.2V
3.6V
4.2V
0
0
0.0001
10
EFFICIENCY vs. LOAD CURRENT
(1.1V OUTPUT, 26MHz SYNC)
50
1.0
0.001
EFFICIENCY vs. LOAD CURRENT
(0.9V OUTPUT, 26MHz SYNC)
60
3.0
FORCED PWM
10
LOAD CURRENT (A)
70
0
0.0001
40
LOAD CURRENT (A)
POWER SAVE
80
VIN = 3.2V
3.6V
4.2V
50
LOAD CURRENT (A)
100
90
60
20
FORCED PWM
0
0.0001
10
70
30
10
0
0.0001
EFFICIENCY (%)
60
30
10
6
70
POWER SAVE
90
EFFICIENCY (%)
70
EFFICIENCY (%)
EFFICIENCY (%)
80
POWER SAVE
90
100
MAX8649/49A toc02
POWER SAVE
90
100
MAX8649/49A toc01
100
EFFICIENCY vs. LOAD CURRENT
(1.3V OUTPUT, SYNC OFF)
EFFICIENCY vs. LOAD CURRENT
(1.1V OUTPUT, SYNC OFF)
MAX8649/49A toc03
EFFICIENCY vs. LOAD CURRENT
(0.9V OUTPUT, SYNC OFF)
SWITCHING FREQUENCY (MHz)
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
2.5
3.5
4.5
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5.5
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
26MHz SYNC
8
6
4
MAX8649/49A toc11
TA = +85NC
1.30
1.29
TA = -40NC
1.28
POWER SAVE
1.115
1.110
OUTPUT VOLTATGE (V)
12
FORCED PWM
1.105
1.100
1.095
POWER SAVE
1.090
1.27
2
VOUT = 1.1V
VOUT = 1.3V
1.085
1.26
0
3.5
5.5
4.5
0
0.4
0.8
1.2
1.6
2.0
0
0.3
0.6
0.9
1.2
1.5
1.8
LOAD CURRENT (A)
LOAD CURRENT (A)
SUPPLY VOLTAGE (V)
LIGHT LOAD SWITCHING WAVEFORMS
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8649/49A toc14
0.910
MAX8649/49A toc13
2.5
FORCED PWM
0.905
OUTPUT VOLTATGE (V)
SUPPLY CURRENT (mA)
14
TA = +25NC
1.31
OUTPUT VOLTAGE (V)
NO SYNC
16
10
1.32
MAX8649/49A toc10
18
OUTPUT VOLTAGE vs. LOAD CURRENT
OUTPUT VOLTAGE vs. LOAD CURRENT
20
MAX8649/49A toc12
NO-LOAD SUPPLY CURRENT vs.
SUPPLY VOLTAGE (FORCED PWM)
VOUT
20mV/div
0.900
VLX
2V/div
0.895
POWER SAVE
0.890
0.885
IL
VOUT = 0.9V
0.880
0
0.3
0.6
0.9
1.2
1.5
200mA/div
10mA LOAD, VOUT = 1.3V
1.8
2μs/div
LOAD CURRENT (A)
MEDIUM LOAD SWITCHING
WAVEFORMS
HEAVY LOAD SWITCHING WAVEFORMS
MAX8649/49A toc16
MAX8649/49A toc15
VOUT
20mV/div
2V/div
VLX
20mV/div
VOUT
VLX
2V/div
IL
IL
500mA LOAD
VOUT = 1.3V
500mA/div
200ns/div
1A/div
1.8A LOAD
VOUT = 1.3V
200ns/div
_______________________________________________________________________________________
7
MAX8649/MAX8649A
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25°C, unless otherwise noted.)
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25°C, unless otherwise noted.)
LIGHT LOAD STARTUP WAVEFORMS
HEAVY LOAD STARTUP WAVEFORMS
MAX8649/49A toc17
10I LOAD
MAX8649/49A toc18
1V/div
VOUT
1V/div
1I LOAD
VOUT
100mA/div
IIN
200mA/div
IIN
500mA/div
IL
5V/div
VEN
500mA/div
IL
5V/div
VEN
200μs/div
200μs/div
PREBIAS STARTUP WAVEFORMS
(FORCED PWM)
LINE TRANSIENT RESPONSE (4.2V TO
3.2V TO 4.2V) SYNC OFF
MAX8649/49A toc19
MAX8649/49A toc20
OUTPUT PREBIASED TO 1.3V
STARTUP TO 1.1V
VOUT
1V/div
VIN
500mV/div
VOUT
IL
20mV/div
1A/div
200mA/div
IL
5V/div
300mA LOAD
VEN
200μs/div
20μs/div
LINE TRANSIENT RESPONSE (4.2V TO
3.2V TO 4.2V) 26MHz SYNC
LOAD TRANSIENT RESPONSE
(1mA TO 1A)
MAX8649/49A toc21
MAX8649/49A toc22
1V/div
VIN
50mV/div
VOUT
VOUT
20mV/div
500mA/div
IL
IL
200mA/div
300mA LOAD
20μs/div
8
1A/div
IOUT
40μs/div
_______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
LOAD TRANSIENT RESPONSE
(1A to 1mA)
LOAD TRANSIENT RESPONSE
(5mA TO 1.8A)
MAX8649/49A toc23
MAX8649/49A toc24
50mV/div
VOUT
VOUT
50mV/div
IL
1A/div
IL
500mA/div
1A/div
IOUT
1A/div
IOUT
40μs/div
40μs/div
LOAD TRANSIENT RESPONSE
(1.8A to 5mA)
SYNCHRONIZATION RESPONSE
(26MHz SYNC)
MAX8649/49A toc26
MAX8649/49A toc25
FORCED PWM, NO LOAD
2V/div
VSYNC
VOUT
100mV/div
IL
VOUT
20mV/div
2V/div
VLX
1A/div
IOUT
IL
200mA/div
1A/div
1μs/div
20μs/div
OUTPUT VOLTAGE CHANGE RESPONSE
MAX8649/49A toc27
10I LOAD,
POWER SAVE
32mV/μs RAMP
VVID0
2V/div
1.3V
0.9V
0.9V
VOUT
500mV/div
IL
200mA/div
40μs/div
_______________________________________________________________________________________
9
MAX8649/MAX8649A
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25°C, unless otherwise noted.)
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
MAX8649/MAX8649A
Bump Description
10
PIN
NAME
A1
IN1
A2
AGND
FUNCTION
Analog Supply Voltage Input. The input voltage range is 2.5V to 5.5V. Place an 11Ω resistor between
IN1 and the input supply. Bypass IN1 to analog ground with a 0.1µF ceramic capacitor as close as
possible to the IC. Connect IN1 and IN2 to the same power source.
Analog Ground. Connect AGND to the PCB ground plane.
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
A3
VID1
A4
IN2
B1
SNS+
Output Voltage Remote Sense, Positive Input. Connect SNS+ directly to the output at the load.
B2
EN
Logic Enable Input. Drive EN high to enable the DC-DC step-down regulator, or low to place in
shutdown mode. In shutdown mode, this logic input has an internal pulldown resistor to AGND.
B3, B4
LX
Inductor Connection. LX is connected to the drains of the internal p-channel and n-channel
MOSFETs. LX is high impedance during shutdown.
C1
SNS-
Output Voltage Sense, Negative Input. Connect to a quiet ground directly at the IC.
C2
VID0
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
C3, C4
PGND
D1
VDD
Logic Input Supply Voltage. Connect VDD to the logic supply driving SDA, SCL, and SYNC. Bypass
VDD to AGND with a 0.1µF ceramic capacitor. When VDD drops below the UVLO threshold, the I2C
registers are reset, but the EN control is still active in this mode.
D2
SDA
I2C Data Input. Data is read on the rising edge of SCL and data is clocked out on the falling edge of SCL.
D3
SCL
I2C Clock Input
D4
SYNC
Power-Supply Voltage Input. The input voltage range is from 2.5V to 5.5V. IN2 powers the internal
p-channel and n-channel MOSFETs. Bypass IN2 to PGND with 10µF and 0.1µF ceramic capacitors
as close as possible to the IC. Connect IN1 and IN2 to the same power source.
Power Ground. Connect both PGND bumps to the PCB ground plane.
External Clock Synchronization Input. Connect SYNC to a 13MHz, 19.2MHz, or 26MHz system clock.
The DC-DC regulator can be forced to synchronize to this external clock depending on I2C setting. See
Table 8. SYNC does not have an internal pulldown. Connect SYNC to AGND if not used.
______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
MAX8649/MAX8649A
SYNC
OSC
CLOCK GEN
IN2
VDD
SCL
I2C INTERFACE
PWM LOGIC
LX
SDA
IN1
PGND
EN
VID0
VID1
SNS+
VDAC
VOLTAGE
CONTROL, VREF,
BIAS, ETC.
SNS-
MAX8649
MAX8649A
AGND
Figure 1. Block Diagram
Detailed Description
The MAX8649/MAX8649A high-efficiency, 3.25MHz
step-down switching regulator delivers up to 1.8A of
output current. The device operates from a 2.5V to 5.5V
input voltage range, and the output voltage is I2C programmable from 0.75V to 1.38V in 10mV increments.
Remote sense ensures precise DC regulation at the
load. Total output error is less than 2% over load, line,
and temperature. The ICs feature different I2C addresses so that multiple devices may be used in a system
(see the Ordering Information section.)
Dynamic Voltage Scaling
The output voltage is dynamically adjusted by use of
the VID0 and VID1 logic inputs, allowing selection
between four predefined operation modes/voltage
configurations.
For each of the different output modes, the following
parameters are programmable:
•
Output voltage from 0.75V to 1.38V in 10mV steps
•
•
Mode of operation: Forced PWM or power save
Enable/disable of synchronization of switching
frequency to external clock source
The relation between the VID0/VID1 and operation
mode is given by Table 1.
The VID_ inputs have internal pulldown resistors. These
pulldown resistors can be disabled through the CONTROL
register after the ICs are enabled, achieving lowest
possible quiescent current. When EN is low, the CONTROL register is reset to default, enabling the pulldown
resistors (see Table 7).
Table 1. VID0 and VID1 Configuration
VID1
VID0
MODE
I2C REGISTER
DEFAULT
SWITHCING
MODE
DEFAULT
SYNCHRONIZATION
DEFAULT
OUTPUT
VOLTAGE (V)
0
0
MODE0
Table 3
FORCED PWM
OFF
1.27
0
1
MODE1
Table 4
POWER SAVE
OFF
1.05
1
0
MODE2
Table 5
FORCED PWM
OFF
1.23
1
1
MODE3
Table 6
FORCED PWM
OFF
1.05
______________________________________________________________________________________
11
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Enable
The DC-DC step-down regulators are enabled/disabled
using the EN logic input. The EN input is able to handle
input voltages up to VIN1, ensuring that the EN logic
input can be controlled by a wide variety of
signals/supplies.
The EN input has an internal pulldown resistor that
ensures EN is discharged during off conditions. This
pulldown resistor can be disabled through the
CONTROL register (see Table 7) once the ICs are
enabled, achieving lowest possible quiescent current.
When EN is low, the CONTROL register is reset to
default, enabling the pulldown resistors on EN, VID0,
and VID1. See Figures 2 and 3 for detailed information
on power-up and power-down sequencing and operation mode changes.
DC-DC Regulator Operating Modes
The ICs operate in one of four modes determined by
the state of the VID_ inputs (see Table 1). At power-up,
the ICs are default set to operate in power-save operation for MODE1 and forced-PWM mode for MODE0,
MODE2, and MODE3. For each of the operation modes,
MODE0 to MODE3, the DC-DC step-down regulators
can be set to operate in either power-save mode or
A
B
forced-PWM mode. This is done by writing to the
MODE_ registers (see Table 3 to Table 6). The mode of
operation can be changed at any time.
In power-save mode, the PWM switching frequency
depends on the load current. For medium to high load
condition, the ICs operate in fixed-frequency PWM
mode. For light load conditions, the ICs operate in hysteretic mode. The proprietary hysteretic PWM control
scheme ensures high efficiency, fast switching, and
fast transient response. This control scheme is simple:
when the output voltage is below the regulation threshold, the error comparator begins a switching cycle by
turning on the high-side switch. This switch remains on
until the minimum on-time expires and the output voltage is above the regulation threshold plus hysteresis
or the inductor current is above the current-limit
threshold. Once off, the high-side switch remains off
until the minimum off-time expires and the output voltage falls again below the regulation threshold. During
the off period, the low-side synchronous rectifier turns
on and remains on until either the high-side switch
turns on again or the inductor current approaches
zero. The internal synchronous rectifier eliminates the
need for an external Schottky diode.
C
D
E
IN
1.27V
1.23V
1.05V
OUT
EN
VID1
VID0
VDD
A: POWER CONNECTED TO IN1 AND IN2.
B: EN LOGIC INPUT PULLED HIGH, OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I2C REGISTER FOR MODE0 (SEE TABLE 1).
C: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE I2C REGISTER FOR MODE1.
D: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF I2C REGISTER FOR MODE3.
E: VDD PULLED HIGH, ENABLING I2C INTERFACE.
Figure 2. Power-Up Sequence
12
______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
MAX8649/MAX8649A
A
B
IN
OUT
EN
VDD
A: VDD PULLED LOW, I2C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1) AND THE OUTPUT VOLTAGE CHANGES TO THE DEFAULT VALUE.
B: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS SHUTDOWN MODE.
Figure 3a. Shutdown by Pulling VDD Low Before EN
A
B
IN
OUT
EN
VDD
A: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS I2C READY MODE, OUTPUT DISABLED.
B: VDD PULLED LOW, I2C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).
Figure 3b. Shutdown by Pulling EN Low Before VDD
A
IN1
OUT
EN
VDD
A: IN1 DROPS BELOW UVLO, IC ENTERS SHUTDOWN MODE, I2C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).
Figure 3c. Shutdown Due to IN1 Undervoltage Lockout
______________________________________________________________________________________
13
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
The transition between PWM and hysteretic operation is
based on the number of consecutive zero-crossing
cycles. When more than 16 consecutive zero-crossing
cycles are detected, the DC-DC step-down converter
enables the bias for hysteretic operation. Once correctly biased and the number of consecutive zero-crossing
cycles exceeds 24, the DC-DC step-down converter
begins hysteretic operation.
During hysteretic operation, there is a silent DC offset
due to the use of valley regulation. See Figure 4.
When operating in power-save mode and the load current is increased so that the number of consecutive
zero-crossing cycles is less than 16, the PWM mode is
biased. Once fully biased and the number of zerocrossing cycles drops below 8, the DC-DC converter
then begins PWM operation. Since there is a delay
between the increase in load current and the
REGULATION
THRESHOLD
OUTPUT
RIPPLE
Figure 4. Output Regulation in Hysteretic Operation
DC-DC converter starting PWM, the converter supports
full current on the output during hysteretic operation.
See Figure 5 for a detailed state diagram.
Power-save operation offers improved efficiency at light
loads by changing to hysteretic mode, reducing the
switching frequency depending on the load condition.
With moderate to heavy loading, the regulator switches
at a fixed switching frequency as it does in forced-PWM
mode. In power-save mode, the transition from hysteretic mode to fixed-frequency switching occurs at the
load current specified in the following equation:
V −V
VOUT
IOUT = IN OUT ×
2×L
VIN × fOSC
In forced-PWM mode, the regulator operates with a
constant (3.25MHz or synchronized to external clock
source) switching frequency regardless of output load.
Forced-PWM mode is ideal for low-noise systems
because switching harmonics occur at multiples of the
constant switching frequency and are easily filtered.
However, light-load power consumption in forced-PWM
mode is higher than that of power-save mode.
MORE THAN 16 CONSECUTIVE
ZERO-CROSSING CYCLES
PWM MODE
WITH POWER-SAVE
MODE BIASED
PWM
MODE
POWER SAVE NOT READY
LESS THAN 8 CONSECUTIVE
ZERO-CROSSING CYCLES
MORE THAN 24 CONSECUTIVE
ZERO-CROSSING CYCLES
AND POWER-SAVE MODE READY
LESS THAN 8 CONSECUTIVE
ZERO-CROSSING CYCLES
AND PWM MODE READY
MORE THAN 24 CONSECUTIVE
ZERO-CROSSING CYCLES
PWM NOT READY
POWER-SAVE
MODE WITH
PWM BIASED
POWER-SAVE
MODE
LESS THAN 16 CONSECUTIVE
ZERO-CROSSING CYCLES
Figure 5. Mode Change for DC-DC Step-Down Converter
14
______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Synchronous Rectification
An internal n-channel synchronous rectifier eliminates
the need for an external Schottky diode and improves
efficiency. The synchronous rectifier turns on during the
second half of each switching cycle (off-time). During
this time, the voltage across the inductor is reversed,
and the inductor current ramps down. In PWM mode,
the synchronous rectifier turns off at the end of the
switching cycle. In power-save mode, the synchronous
rectifier turns off when the inductor current falls below
50mA (typ) or at the end of the switching cycle,
whichever occurs first.
mode. When the regulator is set for power-save mode
and the RAMP_DOWN bit is cleared, the ramp-down is
not actively controlled, and the regulator output voltage
ramps down at the rate determined by the output
capacitance and the external load. Small loads result in
an output-voltage decay that is slower than that specified by RAMP; large loads result in an output-voltage
decay that is no faster than that specified by RAMP
When the RAMP_DOWN bit is set in power-save mode,
the zero-cross comparator is disabled during the rampdown condition. Active ramp-down functionality is
inherent in forced-PWM operation.
Calculate the maximum and minimum values for the
ramp rate as follows:
V
1
tRAMP _ MIN = OUT _ LSB ×
RAMP
_ CODE
tCLK _ MAX 2
V
1
tRAMP _ MAX = OUT _ LSB ×
tCLK _ MIN 2RAMP _ CODE
where:
Ramp-Rate Control
VOUT _ LSB = 10mV
The output voltage has an actively controlled variable
ramp rate, set with the I2C interface (see Figures 6, 7,
and 8). The value set in the RAMP register controls the
output voltage ramp rate. The RAMP_DOWN bit controls the active ramp-down behavior in power-save
OUTPUT
VOLTAGE
tCLK _ MAX =
tCLK _ MIN =
1
fSW _ MIN
1
fSW _ MAX
fSW = 3.25MHz ±10% for PWM operation
fSW = 3.25MHz ±25% for hysteretic operation
DELTA V = 10mV
VOUT'
f
fSW = SYNC
n
10mV/RAMP RATE
VOUT
TIME
fSYNC = frequency of external clock
n = 4 for 13MHz, 6 for 19.2MHz, and 8 for 26MHz
RAMP_CODE = value of the RAMP[2:0] register (see
Table 9)
Figure 6. Ramp-Up Function
FINAL
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
VOUT
DELTA
V = 10mV
VOUT'
10mV/RAMP
RATE
TIME
Figure 7. Ramp-Down Function
MODE CHANGE
TO HIGHER VOUT
MODE CHANGE
TO LOWER VOUT
Figure 8. Mode Change Before Final Value is Reached
______________________________________________________________________________________
15
MAX8649
Soft-Start
The ICs include internal soft-start circuitry that eliminates
inrush current at startup, reducing transients on the
input source (see the Typical Operating Characteristics). Soft-start is particularly useful for high-impedance input sources, such as Li+ and alkaline cells.
When enabling the ICs into a prebiased output, the ICs
perform a complete soft-start cycle.
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
SDA
SCL
DATA LINE STABLE DATA VALID
CHANGE OF DATA ALLOWED
Figure 9. I2C Bit Transfer
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the ICs. When internal thermal sensors detect a
die temperature in excess of +160°C (typ), the
DC-DC step-down regulator is shut down, allowing the
IC to cool. The DC-DC step-down regulator is turned on
again after the junction cools by 20°C (typ), resulting in
a pulsed output during continuous thermal-overload
conditions.
During thermal overload, the I 2 C interface remains
active and all register values are maintained.
I2C Interface
An I2C-compatible, 2-wire serial interface controls the
step-down converter output voltage, ramp rate, operating mode, and synchronization. The serial bus consists
of a bidirectional serial-data line (SDA) and a serialclock input (SCL). The master initiates data transfer on
the bus and generates SCL to permit data transfer.
I2C is an open-drain bus. SDA and SCL require pullup
resistors (500Ω or greater). Optional (24Ω) in series
with SDA and SCL protect the device inputs from highvoltage spikes on the bus lines. Series resistors also
minimize crosstalk and undershoot on bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse (see Figure 9).
Changes in SDA while SCL is high are control signals
(see the START and STOP Conditions section for more
information).
16
Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is 9
bits long; 8 bits of data followed by the acknowledge
bit. The ICs support data transfer rates with SCL frequencies up to 400kHz.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by
issuing a START (S) condition. A START condition is a
high-to-low transition on SDA with SCL high. A STOP
(P) condition is a low-to-high transition on SDA, while
SCL is high (Figure 10).
SDA
SCL
START
CONDITION
Figure 10. I2C START and STOP Conditions
______________________________________________________________________________________
STOP
CONDITION
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
MAX8649/MAX8649A
SDA
SCL
MASTER
TRANSMITTER/RECEIVER
SLAVE
TRANSMITTER/RECEIVER
SLAVE RECEIVER
Figure 11. I2CMaster/Slave Configuration
A START condition from the master signals the beginning of a transmission to the ICs. The master terminates transmission by issuing a not acknowledge
followed by a STOP condition (see the Acknowledge
section for more information). The STOP condition frees
the bus. To issue a series of commands to the slave,
the master can issue REPEATED START (Sr) commands instead of a STOP command to maintain control
of the bus. In general, a REPEATED START command
is functionally equivalent to a regular START command.
When a STOP condition or incorrect address is detected, the MAX8649/MAX8649A internally disconnects
SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough.
System Configuration
A device on the I2C bus that generates a message is
called a transmitter and a device that receives the message is a receiver. The device that controls the message is the master and the devices that are controlled
by the master are called slaves. See Figure 11.
Acknowledge
The number of data bytes between the START and
STOP conditions for the transmitter and receiver are
unlimited. Each 8-bit byte is followed by an acknowledge bit. The acknowledge bit is a high-level signal put
on SDA by the transmitter during which time the master
generates an extra acknowledge-related clock pulse. A
slave receiver that is addressed must generate an
acknowledge after each byte it receives. Also, a master
receiver must generate an acknowledge after each
byte it receives that has been clocked out of the slave
transmitter. See Figure 12.
SDA OUTPUT
FROM TRANSMITTER
D7
D6
D0
NOT ACKNOWLEDGE
SDA OUTPUT
FROM RECEIVER
SCL FROM
MASTER
START CONDITION
ACKNOWLEDGE
1
2
8
9
CLOCK PULSE FOR
ACKNOWLEDGEMENT
Figure 12. I2C Acknowledge
The device that acknowledges must pull down the
DATA line during the acknowledge clock pulse, so that
the DATA line is stable low during the high period of the
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this case, the transmitter must leave SDA high
to enable the master to generate a STOP (P) condition.
Register Reset
The I2C resisters reset back to their default values when
the voltage at either IN1 or V DD drops below the
corresponding UVLO threshold (see the Electrical
Characteristics table).
______________________________________________________________________________________
17
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
A
B
C
D
E
OUT
SDA
S
SLAVE ID
ASr
REG PTR
ASr
DATA
A
P
VID0
VID1
VDD
A: I2C START COMMAND.
B: I2C SLAVE ADDRESS OF SEND OUT.
C: I2C REGISTER POINTER SEND OUT.
D: DATA SEND OUT.
E: ISSUE ACKNOWLEDGE AND CHANGES THE OUTPUT VOLTAGE ACCORDING TO NEW I2C SETTINGS.
Figure 13. Update Output Operation
Update of Output Operation Mode
If updating the output voltage or Operation Mode register for the mode that the ICs are currently operating in,
the output voltage/operation mode is updated at the
same time the ICs send the acknowledge for the I2C
data byte (see Figure 13).
Slave Address
A bus master initiates communication with a slave
device (MAX8649/MAX8649A) by issuing a START (S)
condition followed by the slave address (the slave
address byte consists of 7 address bits (1100 000x for
MAX8649; 1100 010x for MAX8649A) and a read/write
bit (R/W)). After receiving the proper address, the ICs
issues an acknowledge by pulling SDA low during the
ninth clock cycle.
The ICs provide different I2C slave addresses, allowing
up to two devices to be used in a system without causing bus collisions. Contact the factory for availability.
Write Operations
The ICs recognize the write byte protocol as defined in
the SMBus specification and shown in Figures 14a and
14b. The write byte protocol allows the I2C master device
to send 1 byte of data to the slave device. The write byte
protocol requires a register pointer address for the subsequent write. The ICs acknowledge any register pointer
even though only a subset of those registers actually
exists in the device. The write byte protocol is as follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
18
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6)
7)
8)
9)
The master sends a data byte.
The slave acknowledges the data byte.
The slave updates with the new data.
The master sends a STOP (P) condition.
In addition to the write-byte protocol, the ICs can write to
multiple registers as shown in Figure 14b. This protocol
allows the I2C master device to address the slave only
once and then send data to a sequential block of registers starting at the specified register pointer.
Use the following procedure to write to a sequential
block of registers:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends the 8-bit register pointer of the
first register to write.
5) The slave acknowledges the register pointer.
6)
7)
8)
9)
The master sends a data byte.
The slave acknowledges the data byte.
The slave updates with the new data.
Steps 6 to 8 are repeated for as many registers in
the block, with the register pointer automatically
incremented each time.
10) The master sends a STOP condition.
______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL
1
S
7
SLAVE ADDRESS
1
1
8
1
8
1
1
0
A
REGISTER POINTER
A
DATA
A
P
1
1
8
1
8
1
NUMBER OF BITS
R/W
b) WRITING TO MULTIPLE REGISTERS
1
S
7
SLAVE ADDRESS
0
A
REGISTER POINTER X
R/W
8
...
DATA X+n-1
8
DATA X
A
DATA X+1
1
8
1
NUMBER OF BITS
A
DATA X+n
A
NUMBER OF BITS
1
A
...
A P
Figures 14a and 14b. Writing to the ICs
Read Operations
The method for reading a single register (byte) is
shown in Figure 15a. To read a single register:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a repeated START (S) condition.
7) The master sends the 7-bit slave address followed
by a read bit.
8) The slave asserts an acknowledge by pulling SDA low.
9) The slave sends the 8-bit data (contents of the
register).
10) The master asserts a not acknowledge by keeping
SDA high.
11) The master sends a STOP (P) condition.
In addition, the MAX8649/MAX8649A can read a block of
multiple sequential registers as shown in Figure 15b. Use
the following procedure to read a sequential block of registers:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer of the
first register in the block.
5) The slave acknowledges the register pointer.
6) The master sends a repeated START condition.
7) The master sends the 7-bit slave address followed
by a read bit.
8) The slave asserts an acknowledge by pulling SDA low.
9) The slave sends the 8-bit data (contents of the register).
10) The master asserts an acknowledge by pulling SDA
low when there is more data to read, or a not
acknowledge by keeping SDA high when all data
has been read.
11) Steps 9 and 10 are repeated for as many registers
in the block, with the register pointer automatically
incremented each time.
12) The master sends a STOP condition.
______________________________________________________________________________________
19
MAX8649/MAX8649A
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) READING A SINGLE REGISTER
1
7
S
SLAVE ADDRESS
1
1
8
1
0
A
REGISTER POINTER
1
A Sr
7
1
1
8
1
1
SLAVE ADDRESS
1
A
DATA
A
P
8
1
R/W
NUMBER OF BITS
R/W
b) READING MULTIPLE REGISTERS
1
7
S
1
SLAVE ADDRESS
1
8
A
0
1
REGISTER POINTER X
A
1
7
SLAVE ADDRESS
Sr
R/W
8
...
1
A ...
DATA X+1
1 1
8
DATA X+n-1
1
A
R/W
1
A
DATA X
8
A
DATA X+n
NUMBER OF BITS
...
1
1
NUMBER OF BITS
A P
Figures 15a and 15b. Reading from the ICs
SDA
tSU_STA
tSU_DAT
tLOW
tBUF
tHD_STA
tSU_STO
tHD_DAT
tHIGH
SCL
tHD_STA
tR
START CONDITION
tF
REPEATED START CONDITION
STOP
CONDITION
Figure 16. I2C Timing Diagram
20
______________________________________________________________________________________
START
CONDITION
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
POINTER
REGISTER
POR
BIT7
BIT6
0x00
MODE0
0xB4
OPER
MODE
SYNC
MODE
OUT MODE0[5:0]
0x01
MODE1
0x1E
OPER
MODE
SYNC
MODE
OUT MODE1[5:0]
0x02
MODE2
0xB0
OPER
MODE
SYNC
MODE
OUT MODE2[5:0]
0x03
MODE3
0x9E
OPER
MODE
SYNC
MODE
OUT MODE3[5:0]
0x04
CONTROL
0xE0
EN_PD
VID0_PD
0x05
SYNC
0x00
0x06
RAMP
0x01
0x08
CHIP_ID1
0x20
DIE TYPE[7:4]
DIE TYPE[3:0]
0x09
CHIP_ID2
0x0E
DASH[3:0]
MASK REV[3:0]
SYNC[1:0]
BIT5
BIT4
VID1_PD
—
RAMP[2:0]
BIT3
BIT2
—
—
—
—
—
FORCE_HYS FORCE_OSC
BIT1
BIT0
—
—
—
—
—
—
RAMP_DOWN
—
Table 3. I2C Register: MODE0
This register contains output voltage and operation mode control for MODE0, VID0 = GND, VID1 = GND.
REGISTER NAME
MODE0
Address
0x00h
Reset Value
0xB4h
Type
Read/write
Special Features
BIT
B7 (MSB)
B6
Reset upon VDD or IN1 UVLO
NAME
DESCRIPTION
DEFAULT
VALUE
OPERATION_MODE0
DC-DC Step-Down Converter Operation Mode for MODE0
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
1
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
1 = DC-DC converter synchronizes to external SYNC input when available.
0
SYNC_MODE0
B5
B4
B3
B2
B1
B0 (LSB)
OUT_ MODE0 [5:0]
Output Voltage Selection for MODE0
000000 = 0.75V
000001 = 0.76V
110011 = 1.26V
110100 = 1.27V
110101 = 1.28V
111110 = 1.37V
111111 = 1.38V
110100
______________________________________________________________________________________
21
MAX8649/MAX8649A
Table 2. I2C Register Map
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Table 4. I2C Register: MODE1
This register contains output voltage and operation mode control for MODE1, VID1 = GND, VID0 = VDD.
REGISTER NAME
MODE1
Address
0x01h
Reset Value
0x1Eh
Type
Read/write
Special Features
BIT
B7 (MSB)
B6
Reset upon VDD or IN1 UVLO
NAME
DESCRIPTION
DEFAULT
VALUE
OPERATION_MODE1
DC-DC Step-Down Converter Operation Mode for MODE1
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
0
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
1 = DC-DC converter synchronizes to external SYNC input when available.
0
SYNC_MODE1
B5
B4
B3
B2
B1
B0 (LSB)
22
OUT_MODE1[5:0]
Output Voltage Selection for MODE1
000000 = 0.75V
000001 = 0.76V
011101 = 1.04V
011110 = 1.05V
011111 = 1.06V
111110 = 1.37V
111111 = 1.38V
______________________________________________________________________________________
011110
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
This register contains output voltage and operation mode control for MODE2, VID1 = VDD, VID0 = GND.
REGISTER NAME
MODE2
Address
0x02h
Reset Value
0xB0h
Type
Read/write
Special Features
BIT
B7 (MSB)
B6
Reset upon VDD or IN1 UVLO
NAME
DESCRIPTION
DEFAULT
VALUE
OPERATION_MODE2
DC-DC Step-Down Converter Operation Mode for MODE2
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
1
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
1 = DC-DC converter synchronizes to external SYNC input when available.
0
SYNC_MODE2
B5
B4
B3
B2
B1
B0 (LSB)
OUT_MODE2[5:0]
Output Voltage Selection for MODE2
000000 = 0.75V
000001 = 0.76V
101110 = 1.21V
101111 = 1.22V
110000 = 1.23V
111110 = 1.37V
111111 = 1.38V
110000
______________________________________________________________________________________
23
MAX8649/MAX8649A
Table 5. I2C Register: MODE2
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Table 6. I2C Register: MODE3
This register contains output voltage and operation mode control for MODE3, VID1 = VDD, VID0 = VDD.
REGISTER NAME
MODE3
Address
0x03h
Reset Value
0x9Eh
Type
Read/write
Special Features
BIT
B7 (MSB)
B6
Reset upon VDD or IN1 UVLO
NAME
DESCRIPTION
DEFAULT
VALUE
OPERATION_MODE3
DC-DC Step-Down Converter Operation Mode for MODE3
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
1
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
1 = DC-DC converter synchronizes to external SYNC input when available.
0
SYNC_MODE3
B5
B4
B3
B2
B1
B0 (LSB)
24
OUT_MODE3[5:0]
Output Voltage Selection for MODE3
000000 = 0.75V
000001 = 0.76V
011101 = 1.04V
011110 = 1.05V
011111 = 1.06V
111110 = 1.37V
111111 = 1.38V
______________________________________________________________________________________
011110
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
This register enables or disables pulldown resistors.
REGISTER NAME
CONTROL
Address
0x04h
Reset Value
0xE0h
Type
Read/write
Special Features
Reset upon VDD, IN1 UVLO or EN pulled low
BIT
NAME
B7 (MSB)
EN_PD
B6
DESCRIPTION
DEFAULT
VALUE
0 = Pulldown on EN input is disabled.
1 = Pulldown on EN input is enabled.
1
VID0_PD
0 = Pulldown on VID0 input is disabled.
1 = Pulldown on VID0 input is enabled.
1
B5
VID1_PD
0 = Pulldown on VID1 input is disabled.
1 = Pulldown on VID1 input is enabled.
1
B4
—
Reserved for future use.
0
B3
—
Reserved for future use.
0
B2
—
Reserved for future use.
0
B1
—
Reserved for future use.
0
B0 (LSB)
—
Reserved for future use.
0
______________________________________________________________________________________
25
MAX8649/MAX8649A
Table 7. I2C Register: CONTROL
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Table 8. I2C Register: SYNC
This register specifies the clock frequency of external clock source.
REGISTER NAME
SYNC
Address
0x05h
Reset Value
0x00h
Type
Read
Special Features
BIT
Reset upon VDD or IN1 UVLO
NAME
B7 (MSB)
SYNC[1:0]
B6
26
DESCRIPTION
DEFAULT
VALUE
Sets Clock Frequency of External Clock Present on SYNC Input
00 = 26MHz
01 = 13MHz
10 = 19.2MHz
11 = 19.2MHz
00
B5
—
Reserved for future use.
0
B4
—
Reserved for future use.
0
B3
—
Reserved for future use.
0
B2
—
Reserved for future use.
0
B1
—
Reserved for future use.
0
B0 (LSB)
—
Reserved for future use.
0
______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
This register controls of ramp-up/down function.
REGISTER NAME
RAMP
Address
0x06h
Reset Value
0x01h
Type
Read
Special Features
BIT
Reset upon VDD or IN1 UVLO
NAME
B7 (MSB)
B6
RAMP[2:0]
B5
DESCRIPTION
Control the RAMP Timing
000 = 32mV/µs
001 = 16mV/µs
010 = 8mV/µs
011 = 4mV/µs
100 = 2mV/µs
101 = 1mV/µs
110 = 0.5mV/µs
111 = 0.25mV/µs
DEFAULT
VALUE
000
FORCE_HYS
Only Valid When Converter is Operating in OPERATION_MODE 0
0 = Automatically change between power-save mode and PWM mode,
depending on load current.
1 = Converter always operates in power-save mode regardless of load
current as long as OPERATION_MODE = 0. If OPERATION_MODE =
1, this setting is ignored.
0
B3
FORCE_OSC
Force Oscillator While Running in Hysteretic Mode
0 = Internal oscillator is disabled in power save when operating in
hysteretic mode.
1 = Internal oscillator is enabled in power save even when operating in
hysteretic mode.
0
B2
—
Reserved for future use.
0
Active Ramp-Down Control for Power-Save Mode
0 = Active ramp disabled for power-save mode.
1 = During ramp-down, the error crossing detector is disabled allowing
negative current to flow thought the nMOS device.
0
Reserve for future use.
1
B4
B1
RAMP_DOWN
B0 (LSB)
—
______________________________________________________________________________________
27
MAX8649/MAX8649A
Table 9. I2C Register: RAMP
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Table 10. I2C Register: CHIP_ID1
This register contains the die type number (20).
REGISTER NAME
CHIP_ID1
Address
0x08h
Reset Value
0x20h
Type
Read
Special Features
BIT
—
NAME
DEFAULT
VALUE
DESCRIPTION
B7 (MSB)
B6
B5
DIE_TYPE[7:4]
BCD character (2)
0010
DIE_TYPE[3:0]
BCD character (0)
0000
B4
B3
B2
B1
B0 (LSB)
Table 11. I2C Register: CHIP_ID2
This register contains the die type dash number and mask revision level.
REGISTER NAME
CHIP_ID2
Address
0x09h
Reset Value
0x0Eh
Type
Read
Special Features
BIT
—
NAME
DESCRIPTION
DEFAULT
VALUE
B7 (MSB)
B6
B5
DASH
BCD character 0
0000
MASK_REV
BCD character E
1110
B4
B3
B2
B1
B0 (LSB)
28
______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Inductor Selection
Calculate the inductor value (LIDEAL) using the following formula:
LIDEAL =
4 × VIN × D × (1- D)
IOUT(MAX ) × fOSC
This sets the peak-to-peak inductor current ripple to 1/4
the maximum output current. The oscillator frequency,
fOSC, is 3.25MHz, and the duty cycle, D, is:
V
D = OUT
VIN
Given LIDEAL, the peak-to-peak inductor ripple current is
0.25 x IOUT(MAX). The peak inductor current is 1.125 x
IOUT(MAX). Make sure that the saturation current of the
inductor exceeds the peak inductor current, and the
rated maximum DC inductor current exceeds the maximum output current IOUT(MAX). Inductance values smaller than LIDEAL can be used to reduce inductor size;
however, if much smaller values are used, peak inductor
current rises and a larger output capacitance may be
required to suppress output ripple. Larger inductance
values than LIDEAL can be used to obtain higher output
current, but typically require a physically larger inductor
size. See Table 12 for recommended inductors.
Table 12. Recommended Inductors
MANUFACTURER
SERIES
INDUCTANCE
(µH)
DC RESISTANCE
(Ω typ)
CURRENT RATING
(mA)
DIMENSIONS
L x W x H (mm)
KSLI-2520AG
Multilayer
1.0
1.5
2.2
0.075
0.075
0.115
1800
1800
1400
2.5 x 2.0 x 1.0
KLSI-2016AG
0.75
1.0
1.5
0.09
0.09
0.13
1500
1500
1100
2.0 x 1.6 x 1.0
MIPSA2520D
Multilayer
0.5
1.3
1.6
2.0
0.11
0.10
0.09
0.06
2000
2000
2000
2000
2.5 x 2.0 x 0.5
CKP3216
Multilayer
1.0
1.5
2.2
0.11
0.13
0.14
1100
1000
900
3.2 x 1.6 x 0.9
NR3015
1.0
1.5
0.03
0.04
2100
1800
3.0 x 3.0 x 1.5
VLS3015T
1.0
2.2
0.048
0.070
2000
1400
3.0 x 3.0 x 1.5
DE2812C
0.56
1.2
1.5
2.0
0.032
0.044
0.050
0.067
2300
1800
1500
1400
3.2 x 3.0 x 1.2
LPS3008
0.56
0.80
1.0
1.5
2.2
0.072
0.092
0.125
0.134
1800
1600
1400
1150
3.0 x 3.0 x 0.8
LPS3010
0.68
1.0
1.5
1.8
2.2
0.070
0.080
0.085
0.120
0.150
2300
1800
1600
1300
1200
3.0 x 3.0 x 1.0
Hitachi Metals
FDK
Taiyo Yuden
TDK
TOKO
Coilcraft
______________________________________________________________________________________
29
MAX8649/MAX8649A
Applications Information
MAX8649/MAX8649A
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Input Capacitor Selection
Power Dissipation
The input capacitor in a step-down DC-DC regulator
reduces current peaks drawn from the battery or other
input power source and reduces switching noise in the
controller. A 10µF ceramic capacitor in parallel with a
0.1µF ceramic capacitor is recommended for most applications. The impedance of the input capacitor at the
switching frequency should be less than that of the input
source so that high-frequency switching currents do not
pass through the input source. The input capacitor must
meet the input ripple-current requirement imposed by
the step-down regulator. Ceramic capacitors are preferred due to their resilience to power-up surge currents.
Choose the input capacitor so that the temperature rises
due to input ripple current do not exceed approximately
+10°C. For a step-down DC-DC regulator, the maximum
input ripple current is 1/2 of the output. This maximum
input ripple current occurs when the step-down regulator
operates at 50% duty factor (VIN = 2 x VOUT). Refer to
the MAX8649 Evaluation Kit data sheet for specific input
capacitor recommendations.
The ICs have a thermal-shutdown feature that protects
the IC from damage when the die temperature exceeds
+160°C. See the Thermal-Overload Protection section
for more information. To prevent thermal overload and
allow the maximum load current on each regulator, it is
important to ensure that the heat generated by the ICs
can be dissipated into the PCB.
When properly mounted on a multilayer PCB, the junction-to-ambient thermal resistance (θ JA ) is typically
76°C/W.
Output Capacitor Selection
The step-down DC-DC regulator output capacitor
keeps output ripple small and ensures control-loop
stability. A 10µF ceramic capacitor in parallel with a
0.1µF ceramic capacitor is recommended for most
applications. The output capacitor must also have low
impedance at the switching frequency. Ceramic, polymer, and tantalum capacitors are suitable, with ceramic
exhibiting the lowest ESR and lowest high-frequency
impedance.
Output ripple due to capacitance (neglecting ESR) is
approximately:
VRIPPLE =
Chip Information
PROCESS: BiCMOS
IL (PEAK)
2π × fOSC × COUT
Additional ripple due to capacitor ESR is:
VRIPPLE (ESR) = IL (PEAK) × ESR
Refer to the MAX8649 Evaluation Kit data sheet for specific output capacitor recommendations.
30
PCB Layout
Due to fast switching waveforms and high current paths,
careful PCB layout is required to achieve optimal performance. Due to fast switching waveforms and high current paths, careful PCB layout is required to achieve
optimal performance. Minimize trace lengths between
the ICs and the inductor, the input capacitor, and the
output capacitor; keep these traces short, direct, and
wide. The ground connections of CIN and COUT should
be as close together as possible and connected to
PGND. Connect AGND and PGND directly to the ground
plane. The MAX8649 Evaluation Kit illustrates an example PCB layout and routing scheme. Special care should
be taken when routing the remote sense signals. Use a
wide SNS+ trace to minimize parasitic inductance in the
SNS+ feedback trace. Do not use vias on the SNS+
trace because they introduce additional inductance.
Connect SNS- to the local AGND plane for the ICs.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE OUTLINE
CODE
NO.
16 WLP
0.5mm Pitch
W162B2+1
21-0200
LAND
PATTERN NO.
Refer to Application
Note 1891
______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
PAGES
CHANGED
REVISION
NUMBER
REVISION
DATE
0
9/09
Initial release
1
2/10
Corrected errors in Table 1 and Figure 2
2
9/10
Added MAX8649A to data sheet
1–31
3
2/11
Updated the PCB Layout section
30
4
6/11
Updated remote sense, Typical Operating Circuit, SNS+ and SNS- input impedance
entry, C1 bump description, Figure 1, and PCB Layout section
DESCRIPTION
—
11, 12
1, 5, 10,
11, 30
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX8649/MAX8649A
Revision History
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