19-4113; Rev 1; 10/10
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
Features
The MAX8686 current-mode, synchronous PWM stepdown regulator with integrated MOSFETs operates from
a 4.5V to 20V input supply and generates an adjustable
output voltage from 0.7V to 5.5V while delivering up to
25A per phase.
The MAX8686 employs a peak current-mode architecture that operates with an adjustable switching frequency
from 300kHz to 1MHz. An adjustable current-limit threshold allows for optimization for different applications with
different load currents. Inductor current sense is
achieved either using an external sense resistor or using
a lossless inductor current-sense scheme. The foldback
and hiccup current limit reduces the power dissipation
during overload or short-circuit conditions and allows for
autorecovery when the fault condition is removed.
o Operating Range from 4.5V to 20V Input Supply
The MAX8686 offers the ability to start up monotonically
even when there is a prebias output voltage. In addition, an adjustable soft-start capability allows for a controlled turn-on. The MAX8686 features an accurate 1%
reference and offers a reference input that allows for a
higher accuracy reference to be used for voltage tracking applications such as DDR memory.
The MAX8686 can be paralleled (up to eight) together
in a true multiphase mode to deliver up to 200A of output current. When operating in this mode, this device
achieves better than 10% current balance between
phases at full load. The MAX8686 supports programmable phase shedding to improve system efficiency
during light load conditions.
Other features include an enable input and a power-OK
(POK) indicator used for power sequencing. The
MAX8686 also features latch overvoltage protection
that turns on the low-side MOSFET when the output
voltage exceeds 120% of the nominal voltage. The
MAX8686 is offered in a thermally enhanced 40-pin,
6mm x 6mm TQFN package.
o Thermal-Overload Protection
o 1% Reference Voltage Accuracy Over Temperature
o Reference Input (REFIN) for Output Tracking or
System Reference Voltage
o Adjustable Switching Frequency from 300kHz
to 1MHz
o Single/Multiphase Operation Delivers Up to
25A/200A with Integrated MOSFETs
o Adjustable Current Limit
o Monotonic Output Voltage at Startup (Prebias)
o Output Sink and Source Current Capability
o Adjustable Soft-Start
o Output Overvoltage Protection
o Thermally Enhanced 6mm x 6mm TQFN
Package (4W)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX8686ETL+
-40°C to +85°C
40 TQFN-EP*
+Denotes a lead-free package.
*EP = Exposed pad.
Typical Application Circuit
VIN = 12V
IN
BST
VOUT = 1.2V/25A
LX
PGND
Applications
REFIN
POL Power Supplies
Module Replacements
MAX8686
RS-
PHASE/REFO
CS+
COMP
CS-
Telecom Equipment
POK
Networking Equipment
Servers
RS+
POK
OUTPUT
EN/SLOPE
ENABLE
INPUT
DDR Memory
FREQ
SS GND
ILIM
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX8686
General Description
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
ABSOLUTE MAXIMUM RATINGS
IN, INA to PGND.....................................................-0.3V to +22V
BST, DH to LX...........................................................-0.3V to +6V
BST to PGND..........................................................-0.3V to +28V
LX to PGND...........................-0.3V to (VIN + 0.3V) (-2V for 50ns)
BST to VL................................................................-0.3V to +22V
AVL to GND.................................................-0.3V to (VVL + 0.3V)
COMP, ILIM, FREQ, PHASE/REFO, RS+, RS-, POK, REFIN,
CS+, CS- to GND ..................................-0.3V to (VAVL + 0.3V)
VL to PGND ..............................................................-0.3V to +6V
EN/SLOPE to GND ...................................................-0.3V to +6V
RTN to PGND to GND to GFREQ ..........................-0.3V to +0.3V
IN Continuous Current.....................................................20ARMS
LX Continuous Current ....................................................25ARMS
Continuous Power Dissipation (TA = +70°C) (Note 1)
40-Pin TQFN (derate 50mW/°C above +70°C) ..........4000mW
θJC (thermal resistance from junction to exposed pad)
(Note 1) ......................................................................3.5°C/W
θJT (thermal resistance from junction to top) (Note 1) ...3.9°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations see www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VINA = 12V, VL = AVL, VREFIN = 1V, VRS+ - VRS- = 1V, VRS- = 0V, VEN/SLOPE = 1.25V, VCS+ = VCS- = 1V, RILIM = 122kΩ, CVL = 1μF,
CAVL = 0.22μF, CFREQ = 270pF, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
20
V
5.5
V
GENERAL
Operating Input-Voltage Range
VINA = VIN , TA = -40°C to +85°C
Operating Input-Voltage Range
VIN = VINA = VVL = VAVL, TA = -40°C to +85°C
IN/INA Shutdown Supply Current
VEN/SLOPE = 0V,
VIN = VINA = 20V
IN/INA Quiescent Supply Current
VRS+ = 1.1V, no switching; VIN = VINA = 20V,
TA = -40°C to +85°C
AVL Undervoltage Lockout Trip
Level
VL Output Voltage
6
4.5
TA = +25°C
450
TA = +85°C
500
Rising, TA = -40°C to +85°C
4.2
Falling
6V ≤ VIN = VINA ≤ 20V, 1mA ≤ IVL ≤ 30mA,
TA = -40°C to +85°C
μA
5.5
6.6
4.35
4.45
4.03
5.2
5.4
5.5
mA
V
V
SOFT-START (SS)
SS Shutdown Resistance
VEN/SLOPE = 0V (master mode)
SS Soft-Start Current
VSS = 0.4V and 1.1V, TA = -40°C to +85°C
20
100
Ω
19
25
31
μA
3.267
3.300
3.333
V
PHASE COMPARATOR AND REFERENCE (PHASE/REFO)
Reference Output Voltage
Measured at PHASE/REFO (master mode),
TA = -40°C to +85°C
PHASE Comparator Offset
VRS- = VAVL (slave mode), VPHASE = 0.3V and 2.5V,
TA = -40°C to +85°C
-20
+20
mV
VREFIN = 0.7V or 3.3V
-500
+500
nA
0
3.3
V
REFIN INPUT
REFIN Input Bias Current
REFIN Input Voltage Range
2
_______________________________________________________________________________________
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
(VIN = VINA = 12V, VL = AVL, VREFIN = 1V, VRS+ - VRS- = 1V, VRS- = 0V, VEN/SLOPE = 1.25V, VCS+ = VCS- = 1V, RILIM = 122kΩ, CVL = 1μF,
CAVL = 0.22μF, CFREQ = 270pF, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
VREFIN = 3.3V
3.267
3.3
3.333
VREFIN = 0.7V
0.693
0.7
0.707
2.6
UNITS
ERROR AMPLIFIER
Remote-Sense Accuracy
(Including Error Amplifier Offset)
Measure as VRS+ - VRS(TA = -40°C to +85°C)
Transconductance
TA = -40°C to +85°C
1.1
1.7
COMP Source Current
VRS+ - VRS- = 1.3V
220
300
COMP Sink Current
VRS+ - VRS- = 0.7V
220
300
COMP Shutdown Resistance
VEN/SLOPE = 0V
RS+/RS- Input Leakage Current
RS+ Input Common-Mode Range VIN = VINA = VVL = VAVL = 4.5V, VRS- = 100mV
RS- Input Common-Mode Range
V
mS
μA
μA
20
100
Ω
0.2
1.5
μA
0
3.4
V
-100
+100
mV
+1.5
mV
32.0
V/V
+4
μA
μA
CURRENT-SENSE AMPLIFIER
Input Offset Voltage
Measure at CS+ and CS-, VCS+ = VCS- = 0.7V and 5.5V
(TA = -40°C to +85°C)
-1.5
Current-Sense Amplifier Gain
VCS- = 0 to 5V, VCS+ - VCS- = 30mV,
TA = -40°C to +85°C
29.0
Input Bias Current
VCS+ = VCS- = 5.5V and 0V
-4
ILIM Output Current
VILIM = 2V, TA = -40°C to +85°C
9
10
11
Current-Limit Threshold
Measure as VCS+ - VCS(TA = -40°C to +85°C)
RILIM = 122kΩ
16
20
23
RILIM = 275kΩ
38
45
52
COMP Clamp Voltage High
RILIM = 275kΩ, VREFIN = 3.3V, VRS+ - VRS- = 2V
3.6
3.8
4.0
V
COMP Clamp Voltage Low
VREFIN = 3.3V, VRS+ - VRS- = 3.35V
0.54
0.6
0.66
V
Maximum Peak Positive Current
Threshold
RILIM = 275kΩ, no slope compensation
30.5
CURRENT LIMIT
54
mV
mV
_______________________________________________________________________________________
3
MAX8686
ELECTRICAL CHARACTERISTICS (continued)
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VINA = 12V, VL = AVL, VREFIN = 1V, VRS+ - VRS- = 1V, VRS- = 0V, VEN/SLOPE = 1.25V, VCS+ = VCS- = 1V, RILIM = 122kΩ, CVL = 1μF,
CAVL = 0.22μF, CFREQ = 270pF, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VFREQ = 2V, TA = -40°C to +85°C
480
500
520
μA
CFREQ = 180pF
0.8
1
1.2
MHz
CFREQ = 580pF
240
300
360
kHz
OSCILLATOR (FREQ)
Source Current
Switching Frequency
Minimum On-Time
100
FREQ Discharge Resistance
10
50
Ω
VAVL/2
2.85
V
Ramp Peak Voltage
2.60
ns
SLOPE COMPENSATION (EN/SLOPE)
VSLOPE Range
1.25
SLOPE Source Current
8
10
2.50
V
12
μA
THERMAL PROTECTION
Thermal Shutdown
Rising temperature
Thermal-Shutdown Hysteresis
160
°C
30
°C
POWER-OK (POK)
POK Threshold
VOUT rising
87
VOUT falling
POK Output Voltage Low
VRS+ - VRS- = 0.8V, IPOK = 2mA
POK Leakage Current
VPOK = 5.5V
90
93
87
%VOUT
25
200
mV
0.001
1
μA
120
125
%
OVERVOLTAGE OUTPUT PROTECTION (OVP)
Overvoltage Fault Trip Level
VREFIN = 3.3V, VRS+ rising, percentage of VOUT in
regulation
115
ENABLE (EN/SLOPE)
EN Logic-High
1.2
V
EN Logic-Low
0.7
V
BST
Internal PMOS On-Resistance
8
Note 2: Specifications to TA = -40°C are guaranteed by design and not production tested.
4
_______________________________________________________________________________________
Ω
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
SINGLE-PHASE EFFICIENCY
vs. LOAD CURRENT (VIN = 5V)
85
VOUT = 2.5V
VOUT = 1.8V
82.5
VOUT = 1.8V
85.0
82.5
VOUT = 1.2V
77.5
10
15
20
25
5
10
15
20
SWITCHING FREQUENCY
vs. CFREQ CAPACITANCE
CLOSED-LOOP FREQUENCY RESPONSE
(IOUT = 160A, 8 PHASES)
MAX8686 toc04
1200
1100
1000
GAIN (dB)
900
800
700
600
MAX8686 toc05
40
PHASE
1.2040
144
1.2035
108
20
72
10
36
0
0
GAIN
-36
500
-20
-72
400
-30
-108
300
-40
-144
-50
200
100 150 200 250 300 350 400 450 500 550 600 650 700
10
OUTPUT VOLTAGE vs. INPUT VOLTAGE
OUTPUT LOAD TRANSIENT
AIRFLOW = 300 LFM
1.2025
1.2020
1.2015
1.2010
1.2005
1.2000
0
5
10
15
25
20
SOFT-START WITH EN CONTROL
(IOUT = 10A)
MAX8686 toc08
1.25
20
17
OUTPUT CURRENT (A)
FREQUENCY (kHz)
IOUT = 10A
14
1.2030
1k
100
CFREQ CAPACITANCE (pF)
MAX8686 toc07
1.30
-180
1
11
OUTPUT VOLTAGE vs. OUTPUT CURRENT
180
30
-10
8
LOAD CURRENT (A)
LOAD CURRENT (A)
50
5
25
LOAD CURRENT (A)
1300
SWITCHING FREQUENCY (kHz)
0
AIRFLOW = 300 LFM
OUTPUT VOLTAGE (V)
5
564kHz
79
PHASE (DEGREES)
75.0
0
82
80
CIRCUIT OF FIGURE 3
AIRFLOW = 300 LFM
AIRFLOW = 300 LFM
75.0
467kHz
83
81
80.0
77.5
379kHz
84
MAX8686 toc06
85.0
87.5
EFFICIENCY (%)
87.5
80.0
OUTPUT VOLTAGE (V)
270kHz
86
90.0
EFFICIENCY (%)
90.0
EFFICIENCY (%)
VOUT = 2.5V
92.5
87
MAX8686 toc02
VOUT = 3.3V
92.5
EFFICIENCY vs. LOAD CURRENT
95.0
MAX8686 toc01
95.0
MAX8686 toc03
SINGLE-PHASE EFFICIENCY
vs. LOAD CURRENT
MAX8686 toc09
EN
2V/div
VOUT
200mV/div
AC-COUPLED
SS
2V/div
1.20
VOUT
500mV/div
IOUT
42A/div
CIRCUIT OF FIGURE 4
AIRFLOW = 300 LFM
1.15
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
100μs/div
POK
5V/div
CIRCUIT OF FIGURE 4
1ms/div
INPUT VOLTAGE (V)
_______________________________________________________________________________________
5
MAX8686
Typical Operating Characteristics
(VIN = 12V, fSW = 500kHz, single phase, circuit of Figure 2, unless otherwise noted.)
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
Typical Operating Characteristics (continued)
(VIN = 12V, fSW = 500kHz, single phase, circuit of Figure 2, unless otherwise noted.)
SHUTDOWN WITH EN CONTROL
(IOUT = 10A)
SOFT-START WITH EN CONTROL
(IOUT = 10A)
MAX8686 toc11
MAX8686 toc10
EN
2V/div
EN
2V/div
VOUT
500mV/div
CIRCUIT OF FIGURE 4
MAX8686 toc12
EN
2V/div
SS
5V/div
SS
5V/div
VOUT
500mV/div
VOUT
500mV/div
POK
5V/div
POK
5V/div
SS
2V/div
POK
5V/div
SHUTDOWN WITH EN CONTROL
(IOUT = 100A)
CIRCUIT OF FIGURE 4
CIRCUIT OF FIGURE 4
200μs/div
1ms/div
200μs/div
SHORT-CIRCUIT PROTECTION
SHORT-CIRCUIT RECOVERY
MAX8686 toc13a
IOUT
42A/div
MAX8686 toc13b
IOUT
42A/div
SS
500mV/div
SS
500mV/div
VOUT
500mV/div
VOUT
500mV/div
POK
5V/div
POK
5V/div
400μs/div
400μs/div
LX_ SWITCHING WAVEFORM FOR
PHASES 1, 2, 3, AND 4
CURRENT-SHARING ACCURACY
MAX8686 toc15
MAX8686 toc14
25.0
22.5
PHASE CURRENT (A)
20.0
17.5
CIRCUIT OF FIGURE 4
LX1
5V/div
15.0
12.5
LX2
5V/div
LX3
5V/div
10.0
7.5
5.0
2.5
CIRCUIT OF FIGURE 4
AIRFLOW = 300 LFM
LX4
5V/div
0
0 10 20 30 40 50 60 70 80 90 100110 120 130 140
200ns/div
LOAD CURRENT (A)
6
_______________________________________________________________________________________
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
LX_ SWITCHING WAVEFORM FOR
PHASES 4, 5, 6, AND 1
REFO OUTPUT vs. TEMPERATURE
MAX8686 toc16
MAX8686 toc17
3.33
CIRCUIT OF FIGURE 4
REFO OUTPUT (V)
3.32
LX4
5V/div
LX5
5V/div
LX6
5V/div
3.31
3.30
3.29
3.28
LX1
5V/div
3.27
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
200ns/div
TEMPERATURE (°C)
PHASE SHEDDING FROM 6 PHASES
TO 2 PHASES (IOUT = 30A)
PHASE RECOVERY FROM 2 PHASES
TO 6 PHASES (IOUT = 30A)
CIRCUIT OF FIGURE 4
CIRCUIT OF FIGURE 4
MAX8686 toc18
MAX8686 toc19
PS
2V/div
PS
2V/div
LX1
10V/div
LX1
10V/div
LX2
10V/div
LX2
10V/div
LX5
10V/div
SAFE OPERATING AREA
SAFE OPERATING AREA
400 LFM
23
0 LFM
300 LFM
IOUT (A)
21
200 LFM
19
17
15
13
13
11
100 LFM
19
15
9
400 LFM
23
100 LFM
21
IOUT (A)
25
MAX8686 toc21
1μs/div
MAX8686 toc20
1μs/div
25
17
LX5
10V/div
200 LFM
0 LFM
300 LFM
11
TJ = +125°C, VOUT = 1.2V
9
TJ = +125°C, VOUT = 3.3V
25 30 35 40 45 50 55 60 65 70 75 80 85
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX8686
Typical Operating Characteristics (continued)
(VIN = 12V, fSW = 500kHz, single phase, circuit of Figure 2, unless otherwise noted.)
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
MAX8686
Pin Description
PIN
8
NAME
FUNCTION
1
CS-
Negative Differential Current-Sense Input. Connect CS- to the output side of the inductor for lossless
current sense or to the load side of the current-sense resistor.
2
CS+
Positive Differential Current-Sense Input. Connect CS+ to the inductor through an RC network for
lossless current sense or to the inductor side of the current-sense resistor.
3
GFREQ
CFREQ Capacitor Return Terminal. Connect the frequency-setting capacitor CFREQ to GFREQ as close
as possible to the device.
4
EN/SLOPE
Enable and Slope Compensation Input. Connect a resistor from EN/SLOPE to GND to set the desired
slope compensation ramp voltage. An internal 10μA current source pulls up EN/SLOPE. The device
shuts down when the voltage at EN/SLOPE is less than 0.7V. Connect EN/SLOPE to an open-drain or
open-collector output for system enable or phase-shedding function.
5, 16
LX
6
RTN
7–15
PGND
17
N.C.
18–26
IN
Inductor Connection. LX is high impedance during shutdown.
Power Ground for Low-Side Gate Driver. Connect RTN to PGND plane at the return terminal of the IN
bypass capacitor.
Power Ground. Low-side MOSFET source connection.
No Connection. Not internally connected.
Power Input. Connect IN to the input voltage source. Connect input bypass capacitor from IN to PGND
as close as possible to the device. Connect IN, INA, and VL together for 5V operation (see Figure 3).
27
INA
Input of the Internal VL Linear Regulator. Bypass INA with a 0.1μF capacitor to PGND.
28
GND
Analog Ground
29
AVL
Input Voltage to the Device’s Internal Analog Circuitry. Connect AVL to VL through a lowpass RC filter.
30
VL
Internal 5.4V Linear Regulator Output. Connect a ceramic capacitor of at least 1μF from VL to RTN. INA
is the input to this linear regulator. Connect VL to INA when VINA is less than 5.5V. VL provides power
for the MOSFET drivers.
31
BST
Boost Capacitor Connection. Connect a 0.22μF ceramic capacitor from BST to LX.
32
POK
Power-Good Output. POK is an open-drain output that is high impedance when the output voltage is at
its nominal regulated voltage. The POK rising threshold is 90% of the reference voltage at REFIN. POK
is internally pulled low during shutdown. Connect POK to GND for slave mode operation.
_______________________________________________________________________________________
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
PIN
NAME
33
FREQ
34
SS
Soft-Start Input. For master-mode or single-phase operation, connect a capacitor from SS to GND to
set the soft-start time. A 25μA internal current source charges the capacitor. SS is pulled to GND in
shutdown. Connect SS to GND for slave mode operation.
35
ILIM
Analog Programmable Current Limit. Connect a resistor from ILIM to GND to set the current limit. A
10μA current source through this resistor sets the current-limit threshold. In multiphase applications,
connect ILIM of the master and all slave devices together.
36
37
REFIN
FUNCTION
Frequency-Setting Input. Connect a capacitor from FREQ to GFREQ to set the switching frequency.
The triangle ramp runs between 0 and AVL/2. In multiphase applications, connect FREQ of the master
and all slave devices together. FREQ is internally pulled to GFREQ during shutdown.
Voltage Error-Amplifier Reference Input. For master-mode or single-phase operation, connect REFIN to
PHASE/REFO through a resistor-divider to set the output voltage from 0 to 3.3V. To use an external
reference, connect REFIN to the system reference voltage, and use an RC network at REFIN to
implement soft-start if the external reference does not provide this function. Connect REFIN to GND for
slave mode operation.
Phase Selection Input/Reference Voltage Output. For single-phase or master-mode operation, the 3.3V
output with 1% accuracy can be used as a reference voltage. For multiphase operation, connect
PHASE/REFO PHASE/REFO of each slave device to the center tap of a resistor-divider from the master AVL to GND.
The resistor values are selected to set phase delay between phases. The PWM cycle starts 60ns after
the rising edge of VFREQ crosses VPHASE.
Compensation and Output of the Voltage-Error Amplifier. Connect a Type II compensation network at
COMP. COMP is internally pulled to GND in shutdown. In multiphase applications, connect COMP of
the master and all slave devices together.
38
COMP
39
RS+
Positive Input of the Output-Voltage Remote Sense. For master-mode or single-phase operation,
connect RS+ to the output-voltage sense point at the load. Connect RS+ to AVL (slave) for slave mode
operation.
40
RS-
Negative Input of the Output-Voltage Remote Sense. For master-mode or single-phase operation,
connect RS- to the remote ground at the load. Connect RS- to AVL (slave) for slave mode operation.
—
GND_EP
—
IN_EP
Input Exposed Paddle. Connect IN_EP to IN.
—
LX_EP
LX Exposed Paddle. Connect LX_EP to LX.
Ground Exposed Paddle. Connect GND_EP to GND.
_______________________________________________________________________________________
9
MAX8686
Pin Description (continued)
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
MAX8686
Functional Diagram
BST
INA
IN
10μA
EN/SLOPE
5.4V LDO
GENERATOR
LEVEL
SHIFT
UVLO
VL
LX
THERMAL
SHDN
AVL
VOLTAGE
REFERENCE
VL
TO S4
EN/SLOPE
VREF
PWM
CONTROL
LOGIC
PGND
SS
500μA
SLAVE MODE = S1, S2, S3, S5, S6 OPEN
MASTER MODE = S1, S2, S5, S6 CLOSE
SLAVE MODE
DETECTION
RTN
AVL
S6
SOFT-START
CIRCUITRY
S2
RAMP
GENERATOR
REFIN
ERROR
AMPLIFIER
RS+
FB
FREQ
PWM
COMPARATOR
gM
GFREQ
CLOCK
GENERATOR
S1
PHASE/REFO
RSCOMP
CS+
30.5
CURRENTSENSE
AMPLIFIER
VSUM
UV
0.9
CURRENT-LIMIT
CONTROL LOGIC
SLOPE
COMP
1.2
OV
PEAK CURRENTLIMIT COMPARATOR
30.5
CS-
REFIN
FB
POK
AVL
S3
ILIM
1/2
EN/SLOPE
10μA
S4
GND
10
AVL
MAX8686
S5
______________________________________________________________________________________
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
DC-DC Converter Control Architecture
The MAX8686 step-down regulator uses a PWM, current-mode control scheme. An internal transconductance amplifier establishes an integrated error voltage.
The heart of the PWM controller is a PWM comparator
that compares the integrated voltage-feedback signal
against the amplified current-sense signal plus an
adjustable slope-compensation ramp, which is
summed with the current signal to ensure stability. At
each rising edge of the internal clock, the internal highside MOSFET turns on until the PWM comparator trips
or the maximum duty cycle is reached. During this ontime, current ramps up through the inductor, storing
energy in the inductor while sourcing current to the
output. The current-mode feedback system regulates the
peak inductor current as a function of the output-voltage
error signal. The circuit acts as a switch-mode transconductance amplifier and pushes an output LC filter pole
normally found in a voltage-mode PWM to a higher frequency. See the Functional Diagram.
During the second half of the cycle, the internal high-side
MOSFET turns off and the internal low-side MOSFET
turns on. The inductor releases the stored energy as the
current ramps down, providing current to the load. The
output capacitor stores charge when the inductor current exceeds the required load current and discharges
when the inductor current is lower, smoothing the voltage across the load. Under soft-overload conditions,
when the peak inductor current exceeds the selected
current limit (see the Current-Limit Circuit section), the
high-side MOSFET is turned off immediately and the
low-side MOSFET is turned on and remains on to let the
inductor current ramp down until the next clock cycle.
Under severe-overload or short-circuit conditions, the
foldback/hiccup current limit is enabled to reduce
power dissipation.
The MAX8686 operates in a forced-PWM mode. The
converter maintains a constant switching frequency,
regardless of load, to allow for easier filtering of the
switching noise.
Internal Linear Regulator (VL)
The MAX8686 contains an internal LDO regulator that
provides a 5.4V supply for the MOSFET gate drivers.
Connect at least a 1μF ceramic capacitor from VL to
RTN. VL also provides power to the internal analog circuit through AVL. Connect an RC lowpass filter (R =
10Ω, C = 0.22μF) from VL to AVL.
Undervoltage Lockout
When AVL drops below 4.03V, the MAX8686 assumes
that the supply voltage is too low to make valid decisions, so the undervoltage-lockout (UVLO) circuitry
inhibits switching and turns off both power MOSFETs.
When AVL rises above 4.35V, the regulator enters the
startup sequence and then resumes normal operation.
When operating in a multiphase configuration, the AVL
of all the devices must exceed the UVLO threshold
before any switching begins. This is achieved through
the shared ILIM pin, which is pulled low in UVLO.
Startup, Soft-Start, and Prebias Operation
The internal soft-start circuitry gradually ramps up the
reference voltage in order to control the rate of rise of
the output voltage and reduce input surge currents during startup. The soft-start time is determined by the
value of the capacitor from SS to GND and is approximately equal to 50ms per microfarad of the capacitor.
In addition, the MAX8686 features monotonic outputvoltage rise (prebias); therefore, both power MOSFETs
are kept off if the voltage between the remote sense
input (RS+, RS-) is higher than the voltage at REFIN.
This allows the MAX8686 to start up into a prebiased
output without pulling the output voltage down.
Before the MAX8686 can begin the soft-start and
power-up sequence, the following conditions must be
met: AVL exceeds the 4.35V UVLO threshold, EN is at
logic-high, and the thermal limit is not exceeded.
Reference Output
(PHASE/REFO)/Reference Input (REFIN)
The reference voltage REFO can be used to set the output voltage by scaling this voltage down with a resistive
divider and using it as the input voltage to the reference
input, REFIN. The 3.3V reference voltage is 1% accurate
over temperature and can source up to 20μA.
The reference input REFIN allows the reference value of
the device to be set by an external reference. In most
applications, the 3.3V voltage with 1% accuracy from
the PHASE/REFO pin should be used as the reference.
This can be achieved by dividing the 3.3V voltage to
the desired output voltage.
______________________________________________________________________________________
11
MAX8686
Detailed Description
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
For using an external reference on REFIN, SS needs to
be tied to REFIN either directly or indirectly through a
resistor for soft-start. For REFIN voltage lower than
1.25V, connect a resistor between SS and REFIN such
that the voltage drop across the resistor due to the softstart current (31μA max) coming out of SS, causing the
final SS voltage to be at least 1.25V (see Figure 1a).
The external reference should be able to sink at least
31μA. Calculate RREFIN as follows:
RREFIN =
1.25 − VEXT
19μA
where VEXT is the external reference voltage.
In a multiphase converter, only REFIN of the master
device is connected to a reference voltage, and the
REFIN of all slave devices should be tied to GND.
The REFIN also allows for coincident voltage tracking of
multiple converters during power-up/power-down by
applying the same voltage on REFIN of the master
device in each converter.
Enable, Phase Shedding, and
Slope Compensation Input (EN/SLOPE)
An internal 10μA current source pulls the EN/SLOPE
input high. The device shuts down when the voltage at
the EN/SLOPE falls below 0.7V. By connecting an
open-drain or open-collector switch to the EN/SLOPE,
this pin can be used to enable/disable a single-phase
or multiphase converter system.
A separate system signal can be used to shed some
phases of the converter at light load to eliminate all the
power loss from these phases and thus improve the system efficiency. The phase shedding signal is connected
to the EN/SLOPE pins of the slave devices to be shed.
SS
MAX8686
RREFIN
REFIN
Figure 1a. Using an External Reference
12
VEXT
The right timing of the phase shedding signal from the
system is critical for the safe operation of the multiphase
converter. Only after the load current drops below a certain level, should the phase shedding signal become
high. When the open-drain or open-collector switch is
logic-low, it shuts down the slave phases connected to
the switch to reduce power loss. Before the load current
increases to a certain level, the phase shedding signal
should become logic-high to release the EN/SLOPE of
these slave devices, thus turning these phases back on
again to prepare for the higher load current. A minimum
load of 2A per phase in the remaining phases is
required for the shedded phase(s) to turn on.
The transfer function of the power stage is different with a
different number of phases. As the number of phases
increases, the power stage gain increases. The compensation network should be designed such that the converter is always stable with the maximum number of phases.
The EN/SLOPE input is also used to set the slope compensation ramp voltage by connecting a resistor from this
input to GND. The slope compensation is used to stabilize the converters when the duty cycle is more than 40%.
High-Side Gate-Drive Supply (BST)
A flying capacitor between BST and LX generates the
gate-drive voltage for the internal high-side n-channel
MOSFET. When the low-side MOSFET is turned on, the
capacitor is charged by VL to 5.4V minus the drop
across the internal boost switch. When the low-side
MOSFET is turned off, the stored voltage of the capacitor is stacked above LX to provide the necessary turnon voltage (VGS) for the high-side MOSFET. An internal
switch between BST and the internal high-side MOSFET’s
gate closes to turn the MOSFET on.
Current-Sense Amplifier
The current-sense circuit amplifies the differential currentsense voltage (VCS+ - VCS-). This amplified current-sense
signal and the internal-slope-compensation signal are
summed (VSUM) together and fed into the PWM comparator’s inverting input. The high-side MOSFET is turned
on by the clock in the device and is shut off when VSUM
exceeds the error-amplifier output voltage (VCOMP) at
the noninverting input of the PWM comparator. The differential current sense is also used to provide peak
inductor current limiting. The limit can be set by adjusting the analog current-limit input (ILIM).
The current-sense amplifier is used to measure the current across the inductor by connecting to the inductor
through an RC network for lossless current sensing or
connecting to a current-sense resistor for higher accuracy. The input common-mode voltage range of the
current-sense amplifier is from 0 to 5.5V.
______________________________________________________________________________________
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
Current Sharing
Accurate current sharing is required in a multiphase converter to prevent some phases from overheating during
soft-start, steady-state, and load transient. For a converter with current-mode control, the current is proportional
to the error-amplifier output in the voltage feedback loop.
The error-amplifier output (COMP) of the master is connected to the current comparator input of all slave
devices. The current-sharing accuracy is determined by
the tolerances of the inductance and inductor DCR, the
input offset voltage, the gain of the current-sense amplifiers, and the slope compensation circuits.
The peak current-mode control is an open-loop currentsharing scheme, and therefore no compensation for
current sharing is needed and no stability issue exists.
The FREQ inputs of the master and slave devices need
to be connected together. FREQ is internally pulled
down to GFREQ during shutdown.
Phase Selection Input (PHASE/REFO)
For single-phase or master device operation, the
PHASE/REFO can be used as a reference for the converter output voltage (see the Reference Output
(PHASE/REFO)/Reference Input (REFIN) section). For
multiphase operation, connect the PHASE/REFO of
each slave device to the center tap of the resistordivider from AVL of the master to GND. The resistor values are selected to set delay time between phases (see
the Calculating the Phase Voltage section). The PWM
clock cycle of slave devices starts 60ns after the rising
edge of the voltage at FREQ crosses the voltage at
PHASE/REFO. The PWM clock cycle of the master
device starts at the beginning of the ramp.
Remote Sense Input (RS+, RS-)
For single-phase or master operation, connect RS+ to
the sense point at the load and RS- to the GND sense
point of the load. The connections should be at the output regulation point to eliminate the voltage-sense error
caused by voltage drop between the device and load.
The RS+ and RS- traces should be laid out in parallel to
reduce noise coupling. A common-mode filter to each
sense trace should be added if further noise reduction
is needed.
For an output voltage higher than 3.3V, tie
PHASE/REFO to REFIN and use a resistor-divider from
the output regulation point to the remote sense inputs
(RS+, RS-), as shown in Figure 1b.
For multiphase operation, connect RS+ and RS- to AVL
(slave) to select the slave mode.
VOUT
PHASE/REFO
REFIN
Switching Frequency and
Ramp Generation (FREQ)
The MAX8686 has an adjustable internal oscillator that
can be set to any frequency from 300kHz to 1MHz. To set
the switching frequency, connect a capacitor from the
FREQ to GFREQ (see Setting the Switching Frequency
section).
A triangle ramp from 0 to AVL/2 is generated across
FREQ capacitor. In a multiphase application, the
capacitor needs to be connected to the master device.
R1
LOAD
RS+
MAX8686
R2
RS-
Figure 1b. Output Voltage Above 3.3V
______________________________________________________________________________________
13
MAX8686
Current-Limit Circuit
The current-limit threshold is set by a resistor between
ILIM and GND. Under soft-overload conditions, when
the peak inductor current exceeds the selected current
limit, the high-side MOSFET is turned off immediately
and the low-side MOSFET is turned on and remains on
to let the inductor current ramp down until the next
clock cycle. The converter does not stop switching and
the output voltage regulation is not guaranteed. Under
severe-overload or short-circuit conditions, the foldback
and hiccup current limit is simultaneously activated to
reduce power dissipation in the inductor, internal power
MOSFETs, and the upstream power source. Thus, the
circuit can withstand short-circuit conditions continuously without causing overheating of any component. If
the device experiences a persistent overload condition,
the device will autoretry with a soft-start. The converter
will resume normal operation after the overload condition is removed.
The current-limit input is also used to communicate faults
between the devices in a multiphase configuration. With
any fault on the slave or master device (such as UVLO or
overtemperature), the ILIM input is pulled low, which
causes the other devices to turn off both MOSFETs.
Overvoltage Protection
Power-OK (POK) Signal
The MAX8686 provides output overvoltage protection
(OVP). The OVP threshold is set at 20% above the set
output voltage. When the overvoltage condition is experienced, the output is latched to PGND through the lowside MOSFET. To clear the latch, the EN/SLOPE input
should be pulled logic-low and then reinitialized. The
output starts up in a soft-start mode. To prevent the
overvoltage protection from initializing during power-up,
some consideration should be given to the soft-start
timing to reduce the inrush current. In addition, the
proper compensation network would prevent overshoot
during power-up.
POK is an open-drain output that monitors the output voltage. When the output is above 90% of its nominal regulation voltage, POK goes high impedance. There is a 3%
hysteresis to prevent the POK output from chattering. The
POK indicator can be used for sequencing.
C16
0.22μF
R13
10Ω
C17
1μF
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8686. When the junction temperature
exceeds +160°C, an internal thermal sensor shuts
down the device, allowing it to cool down. The thermal
sensor turns the device on again after the junction temperature cools by 30°C, resulting in a pulsed output
during continuous thermal-overload conditions. See
Figures 2, 3, and 4.
C15
0.1μF
R12
10Ω
32
C1
330pF
GFREQ
33
C2
15pF
C3
10nF
34
R2
150kΩ
R4
115kΩ
R3
200kΩ
21
BST
IN
POK
IN
FREQ
IN
U1
MAX8686
N.C.
SS
LX
35
ILIM
36
REFIN
PGND
37
PGND
PHASE/REFO
C4
150pF
PGND
GFREQ
C11
10μF
20
19
18
17
L11
0.56μH
16
15
R11
270Ω
OUTPUT
1.2V/25A
C14
1μF
C6
220μF
14
13
12
R14
270Ω
11
PGND
PGND
C12
10μF
10
PGND
9
PGND
8
PGND
7
RTN
6
LX
5
EN/SLOPE
4
+
GFREQ
RS-
3
40
PGND
RS+
CS+
39
2
C4
R5
2.2nF 5.6kΩ
COMP
CS-
38
ENABLE
(EN)
C13
10μF
IN
22
IN
23
IN
24
IN
25
IN
26
IN
27
INA
28
GND
31
LX
POWEROK
29
VL
C18
0.22μF
AVL
R1
10kΩ
30
INPUT
6V TO 20V
1
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
LX
R16
162kΩ
Figure 2. Single-Phase Application Circuit Operating at VIN = 12V
14
______________________________________________________________________________________
C7
220μF
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
C17
1μF
MAX8686
C16
0.22μF
R13
10Ω
C15
0.1μF
32
C1
330pF
GFREQ
33
C2
15pF
C3
10nF
34
R2
130kΩ
R4
115kΩ
R3
200kΩ
21
BST
IN
POK
IN
FREQ
IN
U1
MAX8686
SS
N.C.
LX
35
ILIM
36
REFIN
PGND
37
PGND
PHASE/REFO
C4
150pF
PGND
PGND
GFREQ
C11
10μF
20
19
18
17
L11
0.56μH
16
15
R11
270Ω
OUTPUT
1.2V/25A
C14
1μF
C6
220μF
C7
220μF
14
13
12
R14
270Ω
11
PGND
PGND
C12
10μF
10
PGND
9
PGND
8
PGND
7
RTN
6
LX
5
EN/SLOPE
4
1
+
3
RS-
GFREQ
RS+
CS+
40
COMP
2
39
CS-
38
C5
R5
2.2nF 5.6kΩ
ENABLE
(EN)
C13
10μF
IN
22
IN
23
IN
24
IN
25
IN
26
IN
27
INA
28
GND
31
LX
POWEROK
29
VL
C18
0.22μF
AVL
R1
10kΩ
30
INPUT
4.5V TO 5.5V
LX
R16
162kΩ
Figure 3. Single-Phase Application Circuit Operating at VIN = 5V
______________________________________________________________________________________
15
C49
10pF
R2
150kΩ
C2
33nF
C1
270pF
C18
0.22μF
R46
124kΩ
AVL4
R45
16.5kΩ
R44
54.9kΩ
AVL1
LX4
AVL4
OUTPUT: 1.2V/150A
ENABLE
(EN)
R16
124kΩ
C4
R5
2.2nF 5.6kΩ
C3
150pF
R4
115kΩ
GFREQ
LX1
POWER
OK
C48
0.22μF
C47
1μF
R3
200kΩ
SS
FREQ
POK
BST
PHASE/REFO
REFIN
ILIM
SS
FREQ
POK
BST
C46
0.22μF
R43
10Ω
RS-
RS+
COMP
PHASE/REFO
COMP
39 RS+
40
RS-
38
37
36
35
34
33
32
31
40
39
38
37
35
ILIM
36
REFIN
34
33
32
31
28
GFREQ
GFREQ
C15
0.1μF
R12
10Ω
MAX8686
U1
26
C71–C94
100μF x 24
C45
0.1μF
R42
10Ω
LX1
MAX8686
U4
LX4
R17
270Ω
11
12
13
14
15
16
17
18
19
20
C14
1μF
R11
270Ω
C44
1μF
R48
270Ω
C41
10μF
C11
10μF
PHASE
SHEDDING
(PS)
11
12
13
14
15
16
17
18
19
20
R47
270Ω
PGND
PGND
PGND
PGND
PGND
LX
N.C.
IN
IN
IN
C42
10μF
PGND
PGND
PGND
PGND
PGND
LX
N.C.
IN
IN
IN
C12
10μF
L41
0.56μH
C59
10pF
L11
0.56μH
C29
10pF
R56
124kΩ
AVL5
R55
16.5kΩ
AVL1
LX5
AVL5
R26
124kΩ
R54
35.7kΩ
AVL2
R25
16.5kΩ
R24
267kΩ
AVL1
LX2
AVL2
C58
0.22μF
C57
1μF
C28
0.22μF
C27
1μF
PHASE/REFO
REFIN
ILIM
SS
FREQ
POK
BST
PHASE/REFO
REFIN
ILIM
SS
FREQ
POK
BST
C56
0.22μF
R53
10Ω
COMP
39 RS+
40
RS-
38
37
36
35
34
33
32
31
COMP
39 RS+
40
RS-
38
37
36
35
34
33
32
31
C26
0.22μF
R23
10Ω
28
GFREQ
GFREQ
C25
0.1μF
R22
10Ω
26
C17
1μF
1
30
R1
10kΩ
C16
0.22μF
R13
10Ω
29
2
MAX8686
U2
C55
0.1μF
R52
10Ω
LX2
MAX8686
U5
LX5
R27
270Ω
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
R57
270Ω
PGND
PGND
PGND
PGND
PGND
LX
N.C.
IN
IN
IN
C52
10μF
PGND
PGND
PGND
PGND
PGND
LX
N.C.
IN
IN
IN
C2
10μF
C24
1μF
R21
270Ω
C54
1μF
R51
270Ω
C51
10μF
C21
10μF
L51
0.56μH
C69
10pF
L21
0.56μH
C39
10pF
AVL6
R66
124kΩ
R65
16.5kΩ
R64
24.3kΩ
AVL1
LX6
AVL6
R36
124kΩ
AVL3
R35
16.5kΩ
R34
97.6kΩ
AVL1
LX2
AVL3
C68
0.22μF
C67
1μF
C38
0.22μF
C37
1μF
BST
PHASE/REFO
REFIN
ILIM
SS
FREQ
POK
PHASE/REFO
REFIN
ILIM
SS
FREQ
POK
BST
C66
0.22μF
R63
10Ω
COMP
39 RS+
40
RS-
38
37
36
35
34
33
32
31
COMP
39 RS+
40
RS-
38
37
36
35
34
33
32
31
C36
0.22μF
R33
10Ω
28
GFREQ
GFREQ
C35
0.1μF
R32
10Ω
26
INPUT: 6V-20V
30
VL
1
AVL
CS+
29
CS-
VL
3
28
AVL
CS+
2
CS-
GND
3
27
4
27
GFREQ
GND
GFREQ
26
INA
4
5
25
25
EN/SLOPE
INA
EN/SLOPE
6
IN
5
IN
21
IN
24
24
LX
IN
7
RTN
6
LX
IN
PGND
7
IN
23
8
22
IN
23
IN
PGND
8
RTN
IN
PGND
IN
PGND
1
30
PGND
9
29
2
PGND
10
21
IN
22
IN
PGND
9
PGND
10
30
VL
1
AVL
CS+
29
CSVL
3
28
AVL
CS+
2
CS-
GND
3
27
4
27
GFREQ
GND
GFREQ
INA
4
5
26
21
IN
25
25
EN/SLOPE
INA
EN/SLOPE
IN
5
IN
6
LX
IN
LX
24
7
24
RTN
6
IN
PGND
7
IN
23
8
22
IN
23
IN
PGND
8
RTN
IN
PGND
IN
PGND
1
30
PGND
9
29
2
PGND
10
21
IN
22
IN
PGND
9
PGND
10
30
VL
1
AVL
CS+
29
CSVL
3
28
AVL
CS+
2
CS-
GND
3
27
4
27
GFREQ
GND
GFREQ
INA
4
U3
MAX8686
C65
0.1μF
R62
10Ω
LX3
5
26
MAX8686
U6
LX6
21
LX
N.C.
IN
IN
IN
11
12
13
14
15
11
12
13
14
15
16
17
18
19
20
R67
270Ω
PGND
PGND
PGND
PGND
PGND
LX
N.C.
IN
IN
IN
C62
10μF
PGND
PGND
PGND
PGND
16
17
18
19
20
C32
10μF
PGND
IN
25
25
EN/SLOPE
INA
IN
5
IN
6
LX
IN
LX
24
7
24
RTN
6
IN
PGND
7
IN
23
8
22
IN
PGND
8
RTN
IN
PGND
IN
PGND
23
IN
PGND
9
PGND
10
21
IN
22
IN
PGND
9
PGND
10
16
EN/SLOPE
R37
270Ω
C64
1μF
R61
270Ω
C61
10μF
C31
10μF
L31
0.56μH
L61
0.56μH
C34
1μF
R31
270Ω
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
Figure 4. Multiphase Application at VIN = 12V
______________________________________________________________________________________
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
robust current-mode control. The following equation
can be used as a guideline.
Setting the Output Voltage
To set the output voltage for the MAX8686, connect
REFIN to the center of an external resistor-divider from
PHASE/REFO to GND (R3 and R4 of Figures 2, 3, or 4).
The sum of R3 and R4 should exceed 165kΩ.
Preselect R4 and calculate R3 using the following
equation:
⎛ 3.3
⎞
R3 = R4 × ⎜
− 1⎟
V
⎝ OUT
⎠
where V OUT is the desired output voltage and 3.3V
comes from the reference voltage (VPHASE/REFO). The
resistor-divider should be placed as close as possible to
REFIN. If an external reference is used, see the
Reference Output (PHASE/REFO)/Reference Input
(REFIN) section for more details.
Inductor Selection
The output inductor is selected based on the desired
amount of inductor ripple current. A larger inductance
value minimizes output ripple current and increases
efficiency but slows down the output-inductor-current
slew rate during a load transient. LIR is the ratio of ripple current to the total current per phase. For the best
tradeoff of efficiency and transient response, an LIR of
30% to 60% is recommended (LIR = 0.3 to 0.6).
Choose a higher LIR when more phases are used to
take advantage of ripple-current cancellation. The
inductor value is determined from:
L≥
VOUT × (1 − D) × N
LIR × fSW × IOUT _ MAX
where f SW is the per-phase switching frequency,
IOUT_MAX is the maximum-rated output current, D is the
duty ratio (VOUT/VIN), N is the number of phases, and
V OUT is the output voltage. The selected inductor
should have low DC resistance, and the saturation current should be greater than the peak inductor current,
IPEAK. IPEAK is found from:
IPEAK =
IOUT _ MAX
N
⎛ LIR ⎞
× ⎜1+
⎟
⎝
2 ⎠
When the DC resistance (RDC) of the output inductor is
used for current sensing, the DC resistance should be
selected to ensure a sufficient current-sense signal for
IOUT _ MAX
N
× LIR × RDC ≥ 10mV
where RDC is the sense resistance value of the inductor
or sense resistor at the highest operating temperature.
It is also important to choose lower LIR to keep the current-sense signal below 45mV, which is the maximum
current limit:
IOUT _ MAX ⎡ LIR
⎢1+
⎣
N
2
⎤
⎥ x RDC ≤ 45mV
⎦
If this condition is not met, then the LIR must be adjusted or the input signal to the current-sense amplifier
must be scaled down with a resistor-divider.
Setting the Switching Frequency
To set the switching frequency, connect a capacitor
from FREQ to GFREQ. Calculate the capacitor value
from the following equation:
CFREQ =
5 x 10 5 − 30 x fSW
2.7 x fSW
where fSW is the desired switching frequency in kilohertz and CFREQ is the total capacitance in picofarads.
The operating frequency range is from 300kHz to
1MHz, so the capacitance at FREQ should be between
600pF and 180pF. Parasitic capacitance from device
pads and PCB layout should be deducted from the
above calculation especially at high switching frequencies. In the estimation of parasitic capacitance, 15pF
per phase should be used. GFREQ may be connected
to GND (quiet ground).
Setting the Slope Compensation
For most applications where the duty cycle is less than
40%, set EN/SLOPE = 1.25V. For applications with a
duty cycle greater than 40%, set the slope compensation with a resistor (RSLOPE) from EN/SLOPE to GND.
Calculate the RSLOPE using the following formula:
RSLOPE =
1.22 x 107 RDC
x ( VOUT − 0.182 x VIN _ MIN)
fSW x L
where R DC is the DC resistance of the inductor,
VIN_MIN is the minimum operating input voltage, and
fSW is the switching frequency.
______________________________________________________________________________________
17
MAX8686
Design Procedures
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
Setting the Peak Current Limit
Calculating the Phase Voltage
The peak current-limit threshold (VCS+ - VCS-) is set by
a resistor connected from ILIM to GND. An internal
10µA current source flows through this resistor to set a
voltage that is 61 times higher than the current-limit
threshold. For example, a 300kΩ resistor sets the current-limit threshold at (10µA x 300kΩ)/61 or 49mV:
In the multiphase converter, the phases are interleaved
to reduce the output voltage ripple. The master starts
conduction at the beginning of the FREQ ramp. The
phase delay time, tPHASE, is the conduction delay time
of slaves from the master. Determine the phase delay
time as follows:
VTH = VCS+ − VCS − =
10 x RILIM
61
where RILIM is in kilohms, VTH is in millivolts, and corresponds to the peak voltage across the sensing element
(inductor resistance or current-sense resistor).
This allows a maximum average DC output current of
(ILIM):
V
I
ILIM = TH − P − P
RDC
2
where RDC is the DC resistance of the inductor or sense
resistor and IP-P is the peak-to-peak inductor current.
To ensure maximum output current, use the minimum
value of VTH from each setting and the maximum RDC
values at the highest expected operating temperature.
The DC resistance of the inductor’s copper wire has a
+0.38%/°C temperature coefficient.
When using a sense resistor, the current through the
sense resistor sets a voltage compared with the peak
current limit.
To provide a more efficient and lower cost design, the
current can be measured through the inductor using a
DCR method (voltage across the DC resistance of the
inductor) as shown in Figure 5.
An RC circuit is connected across the inductor. The RC
time constant is set to be 1.1 to 1.2 times the inductor
time constant (L/RDC). Pick the value of C1 in the 1µF to
4.7µF range, and then calculate R1 from:
tPHASEX =
X
fSW x 103 x N
where X is the number of the slave (X = 1 to 5 for 6
phase converters) fSW is the switching frequency per
phase in kilohertz, and N is the total number of phases.
Calculate the phase voltage of each slave from:
t
x 5 x 108 − 30
VPHASEX = PHASEX
CFREQ
where CFREQ is the total capacitance (in picofarads) at
FREQ (see the Setting the Switching Frequency section). For better jitter immunity, VPHASE should be limited between 0.3V and 2.5V.
Then determine resistor-divider for each slave.
Preselect more than 10kΩ for phase resistor RX5 (X = 2
to 6, R25, R35, R45, R55, and R65) in Figure 4, and calculate RX4 (R24, R34, R44, R54, and R64) as follows:
RX4 = RX 5 ×
5.4V − VPHASE(X)
VPHASE(X)
Input Capacitor
The input capacitor reduces the peak current drawn
from the power source and reduces the noise and voltage ripple on the input DC voltage bus caused by the
circuit’s switching. The input capacitors must meet the
L1
1.2 x L1
R1 =
RDC x C1
VOUT
LX
R1
C1
R2 is added in some applications to scale down the
current signal. R2 and LIR should be selected to meet
the following condition.
MAX8686
CS+
R2
IOUT _ MAX ⎛
LIR ⎞
R2
≤ 45mV
x ⎜1 +
⎟ x RDC x
⎝
2 ⎠
N
R1 + R2
CS-
Figure 5. Current Sense Using the Inductor’s DC Resistance
18
______________________________________________________________________________________
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
IRMS = D × IOUT _ MAX ×
1
−1
N×D
for (N x D) ≤ 1:
IRMS = D × IOUT _ MAX ×
3
−
N×D
2
(N × D)
2
−1
for (N x D) > 1.
where N is the number of phases, D is the duty cycle,
and IOUT_MAX is the maximum output current.
Use the minimum input voltage for calculating the duty
cycle to obtain the worst-case input-capacitor RMS ripple current. Low-ESR aluminum electrolytic, polymer, or
ceramic capacitors should be used to avoid large voltage transients at the input during a large step load
change at the output. The ripple-current specifications
provided by the manufacturer should be carefully
reviewed for temperature derating. Additional smallvalue, low-ESL ceramic capacitors (1μF to 10μF with
proper voltage rating) can be used in parallel to reduce
any high-frequency ringing.
where I2OUT_MAX and I2OUT_MIN are the initial and final
values of the load current during the worst-case load
dump, VINIT2 is the voltage prior to the load dump, VFIN
is the steady-state voltage after the load dump, and
VOV is the allowed voltage overshoot above VFIN. The
term (VFIN + VOV) represents the maximum transient
output voltage reached during the load dump. The
above equation is an approximation, and the output
capacitance value obtained serves as a good starting
point. The final value should be obtained from actual
measurements. For ceramic output capacitors, the output capacitor requirement is determined mostly by load
dump requirements due to their low ESR and ESL. See
Figures 7 and 8.
Compensation Design
The MAX8686 uses an internal transconductance error
amplifier whose output compensates the control loop.
The external inductor, output capacitor, compensation
POWER
MODULATOR
CLOSED LOOP
GAIN
(dB)
ERROR
AMPLIFIER
Output Capacitor
fC
0
The minimum output capacitance, C OUT(MIN) , is
required to meet load-dump requirements. The worstcase load dump is a sudden transition from full load
current (I 2 OUT_MAX ) to minimum load current
(I2OUT_MIN). COUT(MIN) is estimated based on energy
balance from:
(
L
2
× IOUT
− I2
_ MAX OUT _ MIN
N
COUT(MIN) ≥
(VFIN + VOV )2 − VINIT2
)
fpMOD
VOLTAGEDIVIDER
FREQUENCY (Hz)
fzMOD
Figure 7. Simplified Gain Plot for the fzMOD > fC Case
CLOSED LOOP
POWER
MODULATOR
COMP
RC
MAX8686
GAIN
(dB)
ERROR
AMPLIFIER
CF
0
fpMOD
CC
VOLTAGEDIVIDER
Figure 6. Compensation Components
FREQUENCY (Hz)
fzMOD
fC
Figure 8. Simplified Gain Plot for the fzMOD < fC Case
______________________________________________________________________________________
19
MAX8686
ripple-current requirement (I RMS ) imposed by the
switching currents as defined by the following equations:
MAX8686
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
resistor, and compensation capacitors determine the
loop stability. The inductor and output capacitor are
chosen based on performance, size, and cost.
Additionally, the compensation resistor and capacitors
are selected to optimize control-loop stability. The component values, shown in Figures 2, 3, and 4, yield stable
operation over the given range of input-to-output voltages.
The regulator uses a current-mode control scheme that
regulates the output voltage by forcing the required
current through the external inductor. The voltage drop
across the DC resistance of the inductor or the alternate series current-sense resistor is used to measure
the inductor current. Current-mode control eliminates
the double pole in the feedback loop caused by the
inductor and output capacitor resulting in a smaller
phase shift and requiring a less elaborate error-amplifier compensation than voltage-mode control. A simple
series RC and CC is all that is needed to have a stable,
high-bandwidth loop in applications where ceramic
capacitors are used for output filtering. For other types
of capacitors, due to the higher capacitance and ESR,
the frequency of the zero created by the capacitance
and ESR is lower than the desired closed-loop crossover
frequency. To stabilize a nonceramic output-capacitor
loop, add another compensation capacitor from COMP
to GND to cancel this ESR zero. See Figure 6.
The basic regulator loop is modeled as a power modulator, an output feedback divider, and an error amplifier.
The power modulator has DC gain set by gmc x RLOAD,
with a pole and zero pair set by RLOAD, the output capacitor (COUT), and its equivalent series resistance (ESR).
Below are equations that define the power modulator:
RLOAD
GMOD(DC) = gmc ×
⎡ RLOAD
⎤
× ⎡⎣(KS × (1 − D)) − 0..5⎤⎦⎥
⎢1+
⎣ L × fSW
⎦
where RLOAD = VOUT/[IOUT(MAX)/N], fSW is the switching frequency, L is the output inductance, g mc =
1/(AVCS x RDC), where AVCS is the gain of the currentsense amplifier (30.5 typ), RDC is the DC resistance of
the inductor, the duty cycle D = VOUT/VIN. KS is a slope
20
compensation factor calculated from the following
equation:
V
− 0.182 x VIN _ MIN
KS = 1+ OUT
fSW x L x (VIN − VOUT)
Find the pole and zero frequencies created by the
power modulator as follows:
fpMOD =
⎡
⎤
N
N
+⎢
× [KS × (1 − D) − 0.5]⎥
2 π × RLOAD × COUT ⎣ 2 π × L × fSW × COUT
⎦
fzMOD =
1
2π × COUT × ESR
when COUT comprises “n” identical capacitors in parallel, the resulting COUT = n x COUT(EACH), and ESR =
ESR(EACH)/n. Note that the capacitor zero for a parallel
combination of like capacitors is the same as for an
individual capacitor.
The transconductance error amplifier has a DC gain,
GEA(DC) = gmEA x RO, where gmEA is the error-amplifier transconductance, which is equal to 1.7mS, and RO
is the output resistance of the error amplifier, which is
30MΩ. A dominant pole (fpdEA) is set by the compensation capacitor (CC), the amplifier output resistance
(RO), and the compensation resistor (RC); a zero (fzEA)
is set by the compensation resistor (RC) and the compensation capacitor (CC). There is an optional pole
(fpEA) set by CF and RC to cancel the output capacitor
ESR zero if it occurs near the crossover frequency (fC).
Thus:
1
2π × CC × (RO + RC )
1
fzEA =
2π × CC × RC
fpdEA =
fpEA =
1
2π × CF × RC
The crossover frequency, fC, should be much higher
than the power-modulator pole fPMOD. Also, fC should
______________________________________________________________________________________
Single/Multiphase, Step-Down,
DC-DC Converter Delivers Up to 25A Per Phase
The error-amplifier gain at fC is:
MAX8686
be less than or equal to 1/5 the switching frequency.
Select a value for fC in the range:
f
GEA(fc) = gmEA × RC × zMOD
fC
f
fpMOD
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