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MAX9248EVKIT+

MAX9248EVKIT+

  • 厂商:

    AD(亚德诺)

  • 封装:

    -

  • 描述:

    EVAL KIT FOR MAX9248

  • 数据手册
  • 价格&库存
MAX9248EVKIT+ 数据手册
19-4940; Rev 0; 9/09 MAX9247/MAX9248 Evaluation Kit The MAX9247/MAX9248 evaluation kit (EV kit) provides a proven design to evaluate the MAX9247 27-bit, 2.5MHz to 42MHz DC-balanced LVDS serializer and the MAX9248 27-bit, 2.5MHz to 42MHz DC-balanced LVDS deserializer. The MAX9247 serializes 27 bits of parallel input data, 18 bits of video, and 9 bits of control to a serial data stream. The MAX9248 deserializes the LVDS serial input, which converts to 18 bits of parallel video data and 9 bits of parallel control data. The EV kit PCB has a MAX9247ECM+ or MAX9247GCM+ and a MAX9248ECM+ or MAX9248GCM+ installed. Features S 27-Bit Parallel Interface S Rosenberger Connector (Cable Included) S Independent Evaluation of the MAX9247/MAX9248 Serializer/Deserializer (SerDes) S Proven PCB Layout S Fully Assembled and Tested Ordering Information PART TYPE MAX9247EVKIT+ or MAX9248EVKIT+ EV Kit +Denotes lead(Pb)-free and RoHS compliant. Component List DESIGNATION QTY DESCRIPTION DESIGNATION QTY C1–C15, C27–C41 0 Not installed, ceramic capacitors (0603) P1, P2 2 C16–C20, C48, C58–C61 10 10FF Q10%, 16V X5R ceramic capacitors (0805) Murata GRM21BR61C106K LVDS connectors, waterblue (with EMI/EMC washer) Rosenberger D4S20D-40ML5-Z P3, P4 2 SMA vertical-mount connectors R1, R2, R3, R6, R7, R9, R10, R11, R13, R15, R16, R20–R48 0 Not installed, resistors (0603) R4, R14 2 82.5I Q5% resistors (0603) R5, R12 2 130I Q5% resistors (0603) R8, R19 2 49.9I Q1% resistors (0603) R17, R18 2 1kI Q1% resistors (0603) U1 1 27-bit deserializer (48 LQFP) Maxim MAX9248ECM+ or Maxim MAX9248GCM+ U2 1 27-bit serializer (48 LQFP) Maxim MAX9247ECM+ or Maxim MAX9247GCM+ — 1 Cable assembly (2m) MD Elektronik PT1482 — 16 Shunts — 1 PCB: MAX9247/9248 EVALUATION KIT+ C21, C25, C42, C44, C46, C51, C54, C57, C62, C64 10 C22, C23, C24, C26, C43, C45, C47, C49, C50, C52, C53, C55, C56, C63, C65 15 0.001FF Q10%, 50V X7R ceramic capacitors (0603) Murata GRM188R71H102K 0.1FF Q10%, 16V X7R ceramic capacitors (0603) Murata GCM188R71C104K JU1–JU5 5 4-pin headers JU6, JU7, JU8 3 3-pin headers JU9–JU21 13 2-pin headers H1, H2 2 2 x 20 shrouded-plug connectors (0.100in centers) 7 2 x 10 shrouded-plug connectors (0.100in centers) H3–H9 DESCRIPTION ________________________________________________________________ Maxim Integrated Products   1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Evaluates: MAX9247/MAX9248 General Description Evaluates: MAX9247/MAX9248 MAX9247/MAX9248 Evaluation Kit Component Suppliers SUPPLIER PHONE MD Elektronik GmbH 011-49-86-38-604-0 Murata Electronics North America, Inc. 770-436-1300 Rosenberger Hochfrequenztechnik GmbH 011-49-86 84-18-0 WEBSITE www.md-elektronik-gmbh.de www.murata-northamerica.com www.rosenberger.de  Note: Indicate that you are using the MAX9247 and the MAX9248 when contacting these component suppliers. Quick Start Required Equipment • MAX9247/MAX9248 EV kit (cable included) • Two 3.3V DC power supplies • Digital data generator (e.g., HP/Agilent 16522A) • T  wo low-phase-noise clock generators (e.g., HP/ Agilent 8133A) • L  ogic analyzer or data-acquisition system (e.g., HP/ Agilent 16500C) • H  igh-performance oscilloscope (e.g., HP/Agilent DSO80304B; see the Pseudo-Random Bit Sequence (PRBS) Mode section) Procedure The MAX9247/MAX9248 EV kit is fully assembled and tested. Follow the steps below to verify board operation. Caution: Do not turn on the power supplies or signal sources until all connections are completed. 1) V  erify that all jumpers (JU1–JU21) are in their default positions, as shown in Table 1. 2) C  onnect the first 3.3V power supply across the DVCC1 and GND1 pads of the EV kit. 4) Connect the GND1 and GND2 pads together. 5) C  onnect the Rosenberger cable from the P1 to the P2 connector of the EV kit. 6) C  onnect the data generator to the H6–H9 connectors and set to generate 27-bit parallel data at LVCMOS/ LVTTL levels. See Table 2 for input bit locations. 7) C  onnect the first clock generator to the P4 SMA connector and set its output frequency between 2.5MHz and 42MHz (see Table 3 for PCLK_IN location). 8) C  onnect the second clock generator to the P3 SMA connector and set to within Q2% of the MAX9247 serializer PCLK_IN frequency (see Table 3 for REFCLK location). 9) C  onnect the logic analyzer or data-acquisition system to connectors H1 and H2, as shown in Table 4. 10) Turn on the power supplies. 11) Enable the clock generators. 12) Enable the data generator. 13) E  nable the logic analyzer or data-acquisition system and begin sampling data. 3) C  onnect the second 3.3V power supply across the DVCC2 and GND2 pads of the EV kit. Table 1. MAX9247/MAX9248 EV Kit Jumper Descriptions (JU1−JU21) JUMPER JU1 FUNCTION SHUNT POSITION MAX9248 falling latch edge 1-2* Connects the R/F pin of the MAX9248 to GND2 for falling output latch edge MAX9248 latch edge 1-3 Connects the R/F pin of the MAX9248 to header H4-9 MAX9248 rising latch edge 1-4 Connects the R/F pin of the MAX9248 to DVCC2 for rising output latch edge DESCRIPTION 2   _______________________________________________________________________________________ MAX9247/MAX9248 Evaluation Kit JUMPER JU2 JU3 JU4 JU5 JU6 JU7 FUNCTION SHUNT POSITION MAX9248 LVTLL/ LVCMOS range input 1-2* Connects the RNG1 pin of the MAX9248 to GND2 for logic 0 (see the MAX9248 IC data sheet to determine the frequency range) MAX9248 LVTLL/ LVCMOS range input 1-3 Connects the RNG1 pin of the MAX9248 to header H4-7 MAX9248 LVTLL/ LVCMOS range input 1-4 Connects the RNG1 of the MAX9248 to DVCC2 for logic 1 (see the MAX9248 IC data sheet to determine the frequency range) MAX9248 LVTLL/ LVCMOS range input 1-2* Connects the RNG0 pin of the MAX9248 to GND2 for logic 0 (see the MAX9248 IC data sheet to determine frequency range) MAX9248 LVTLL/ LVCMOS range input 1-3 Connects the RNG0 pin of the MAX9248 to header H4-5 MAX9248 LVTLL/ LVCMOS range input 1-4 Connects RNG0 pin of the MAX9248 to DVCC2 for logic 1 (see the MAX9248 IC data sheet to determine the frequency range) MAX9248 power-down 1-2 Pulls the PWRDWN pin of the MAX9248 to low for shutdown MAX9248 power-down 1-3 Connects the PWRDWN pin of the MAX9248 to header H4-3 MAX9248 power-down 1-4* Pulls the PWRDWN pin of the MAX9248 high for full functionality MAX9248 spread spectrum 1-2 Connects the SS pin of the MAX9248 to GND2 for data and clock output spread ±2% relative to REFCLK MAX9248 spread spectrum 1-3 Connects the SS pin of the MAX9248 to header H4-1 MAX9248 spread spectrum 1-4* Connects the SS pin of the MAX9248 to DVCC2 for data and clock output spread ±4% relative to REFCLK MAX9247 hardwired inputs 1-2* Connects even pins of headers H5–H9 to DVCC2 MAX9247 hardwired inputs 2-3 Connects even pins of headers H5–H9 to GND2 MAX9247 preemphasis or MOD1 1-2* Connects the PRE pin of the MAX9247 to DVCC2 for enabling preemphasis MAX9247 preemphasis or MOD1 2-3 Connects the PRE pin of the MAX9247 to GND2 for disabling preemphasis or used for PRBS mode DESCRIPTION _______________________________________________________________________________________   3 Evaluates: MAX9247/MAX9248 Table 1. MAX9247/MAX9248 EV Kit Jumper Descriptions (JU1−JU21) (continued) Evaluates: MAX9247/MAX9248 MAX9247/MAX9248 Evaluation Kit Table 1. MAX9247/MAX9248 EV Kit Jumper Descriptions (JU1−JU21) (continued) JUMPER JU8 FUNCTION SHUNT POSITION MAX9247 MOD0 1-2* Connects the I.C. pin (24) of the MAX9247 to DVCC MAX9247 MOD0 2-3 Connects the I.C. pin (24) of the MAX9247 to GND2 for enabling PRBS mode DESCRIPTION JU9 MAX9247 IN+ Open* Used for probing IN+ JU10 MAX9247 IN- Open* Used for probing IN- JU11 MAX9247 REFCLK Open* Used for probing REFCLK JU12 MAX9248 OUT- Open* Used for probing OUT- JU13 MAX9248 OUT+ Open* Used for probing OUT+ MAX9247 LVTLL/LVCMOS range input 1-2* Connects the RNG1 pin of the MAX9247 to DVCC1 for logic 1 (see the MAX9247 IC data sheet to determine the frequency range) MAX9247 LVTLL/LVCMOS range input Open Internally connects the RNG1 pin of the MAX9247 to ground when left unconnected MAX9247 LVTLL/LVCMOS range input 1-2* Connects the RNG0 pin of the MAX9247 to DVCC1 for logic 1 (see the MAX9247 IC data sheet to determine the frequency range) MAX9247 LVTLL/LVCMOS range input Open Internally connects the RNG0 pin of the MAX9247 to ground when left unconnected Board-supply connectivity 1-2* Board-supply connectivity Open Board-supply connectivity 1-2* Board-supply connectivity Open Disconnects DVCC2 from LVCC2. The 2-pin header can be utilized for supply current measurements. Board-supply connectivity 1-2* Connects DVCC2 to OVCC. This shunt reduces the number of supplies required to operate the EV kit. Board-supply connectivity Open Board-supply connectivity 1-2* Board-supply connectivity Open Board-supply connectivity 1-2* Board-supply connectivity Open JU14 JU15 JU16 JU17 JU18 JU19 JU20 Connects DVCC2 to PVCC2. This shunt reduces the number of supplies required to operate the EV kit. Disconnects DVCC2 from PVCC2. The 2-pin header can be utilized for supply current measurements. Connects DVCC2 to LVCC2. This shunt reduces the number of supplies required to operate the EV kit. Disconnects DVCC2 from OVCC. The 2-pin header can be utilized for supply current measurements. Connects DVCC1 to IVCC. This shunt reduces the number of supplies required to operate the EV kit. Disconnects DVCC1 from IVCC. The 2-pin header can be utilized for supply current measurements. Connects DVCC1 to PVCC1. This shunt reduces the number of supplies required to operate the EV kit. Disconnects DVCC1 from PVCC1. The 2-pin header can be utilized for supply current measurements. 4   _______________________________________________________________________________________ MAX9247/MAX9248 Evaluation Kit JUMPER JU21 FUNCTION SHUNT POSITION Board-supply connectivity 1-2* Board-supply connectivity Open DESCRIPTION Connects DVCC1 to LVCC1. This shunt reduces the number of supplies required to operate the EV kit. Disconnects DVCC1 from LVCC1. The 2-pin header can be utilized for supply current measurements. *Default position. Table 2. Video and Control Data Inputs INPUT SIGNALS DESIGNATION DESCRIPTION RGB_IN0 H9-1 Input video bit 0 RGB_IN1 H9-3 Input video bit 1 RGB_IN2 H9-5 Input video bit 2 RGB_IN3 H9-7 Input video bit 3 RGB_IN4 H9-9 Input video bit 4 RGB_IN5 H9-11 Input video bit 5 RGB_IN6 H9-13 Input video bit 6 RGB_IN7 H8-1 Input video bit 7 RGB_IN8 H8-3 Input video bit 8 RGB_IN9 H8-5 Input video bit 9 RGB_IN10 H8-7 Input video bit 10 RGB_IN11 H8-9 Input video bit 11 RGB_IN12 H8-11 Input video bit 12 RGB_IN13 H8-13 Input video bit 13 RGB_IN14 H7-1 Input video bit 14 RGB_IN15 H7-3 Input video bit 15 RGB_IN16 H7-5 Input video bit 16 RGB_IN17 H7-7 Input video bit 17 CNTL_IN0 H7-9 Input control bit 0 CNTL_IN1 H7-11 Input control bit 1 CNTL_IN2 H7-13 Input control bit 2 CNTL_IN3 H6-1 Input control bit 3 CNTL_IN4 H6-3 Input control bit 4 CNTL_IN5 H6-5 Input control bit 5 CNTL_IN6 H6-7 Input control bit 6 CNTL_IN7 H6-9 Input control bit 7 CNTL_IN8 H6-11 Input control bit 8 Table 3. Input/Output Clock Locations SIGNAL DESIGNATION PCLK_IN H5-5 or P4 REFCLK H3-5 or P3 Detailed Description of Hardware The MAX9247/MAX9248 EV kit provides a proven design to evaluate the MAX9247 27-bit, 2.5MHz to 42MHz DC-balanced LVDS serializer and the MAX9248 27-bit, 2.5MHz to 42MHz DC-balanced LVDS deserializer. The MAX9247 serializes 27 bits of parallel input data, 18 bits of video, and 9 bits of control to a serial data stream. The MAX9248 deserializes the LVDS serial input, which converts to 18 bits of parallel video data and 9 bits of parallel control data. Input Signals The MAX9247 accepts 27-bit parallel data, 18 video data bits, and 9 control data bits. The 27-bit pattern is supplied to the EV kit by connecting a data generator to the four 20-pin headers (H6–H9), or by connecting selected pins of H6–H9 to high/low LVCMOS/LVTTL states. See Table 2 for input bit locations designated on H6–H9. Data-Enable Input (DE_IN) The MAX9247 DE_IN pin is accessible through header H6-13. Driving the pin high selects RGB_IN[17:0] to be latched. Driving the pin low selects CNTL_IN[8:0] to be latched. Input and Output Clocks The MAX9247 parallel input clock (PCLK_IN) is accessible through H5-5 or SMA connector P4 (see Table 3). Apply a clock frequency to the access points, which latches data and control inputs and provides the PLL clock. The MAX9248 reference clock (REFCLK) input is accessible through H3-5 or SMA connector P3 (see Table 3). Apply a reference clock to the access point that is within Q2% of the MAX9247 serializer PCLK_IN frequency. Output Signals The MAX9248 outputs 27-bit parallel data, 18 video data bits, and 9 control data bits at LVCMOS/LVTTL levels on the 40-pin headers (H1 and H2). To sample the 27-bit _______________________________________________________________________________________   5 Evaluates: MAX9247/MAX9248 Table 1. MAX9247/MAX9248 EV Kit Jumper Descriptions (JU1−JU21) (continued) Evaluates: MAX9247/MAX9248 MAX9247/MAX9248 Evaluation Kit pattern, connect a logic analyzer or data-acquisition system to H1 and H2. See Table 4 for the output bit locations on the H1 and H2 headers. Data-Enable Output (DE_OUT) The MAX9248 DE_OUT pin is accessible through header H2-21. A high output indicates that RGB_OUT[17:0] are active and a low output indicates that CNTL_OUT[8:0] are active. Rising and Falling Input Latch Edge (R/F) The MAX9248 has a selectable rising or falling output latch edge through logic setting on the R/F pin. Drive Table 4. Video and Control Data Outputs OUTPUT SIGNALS DESIGNATION DESCRIPTION CNTL_OUT0 H2-3 Output control bit 0 CNTL_OUT1 H2-5 Output control bit 1 CNTL_OUT2 H2-7 Output control bit 2 CNTL_OUT3 H2-9 Output control bit 3 CNTL_OUT4 H2-11 Output control bit 4 CNTL_OUT5 H2-13 Output control bit 5 CNTL_OUT6 H2-15 Output control bit 6 CNTL_OUT7 H2-17 Output control bit 7 CNTL_OUT8 H2-19 Output control bit 8 RGB_OUT0 H2-27 Output video bit 0 RGB_OUT1 H2-29 Output video bit 1 RGB_OUT2 H2-31 Output video bit 2 RGB_OUT3 H1-3 Output video bit 3 RGB_OUT4 H1-5 Output video bit 4 RGB_OUT5 H1-7 Output video bit 5 RGB_OUT6 H1-9 Output video bit 6 RGB_OUT7 H1-11 Output video bit 7 RGB_OUT8 H1-13 Output video bit 8 RGB_OUT9 H1-15 Output video bit 9 RGB_OUT10 H1-17 Output video bit 10 RGB_OUT11 H1-19 Output video bit 11 RGB_OUT12 H1-21 Output video bit 12 RGB_OUT13 H1-23 Output video bit 13 RGB_OUT14 H1-25 Output video bit 14 RGB_OUT15 H1-27 Output video bit 15 RGB_OUT16 H1-29 Output video bit 16 RGB_OUT17 H1-31 Output video bit 17 the R/F pin low by placing a shunt in the 1-2 position of jumper JU1 (see Table 1). Drive the R/F pin high by placing a shunt in the 1-4 position of JU1. Frequency Range Setting (RNG1 and RNG0) The parallel clock frequency range for the MAX9247 can be configured through jumpers JU14 and JU15. Place a shunt on JU14 and JU15 to drive RNG1 and RNG0 high, or leave JU14 and JU15 unconnected to drive RNG1 and RNG0 low. Refer to the MAX9247 IC data sheet for actual frequency settings. The operating frequency range for the MAX9248 can be configured through jumpers JU2 and JU3. Place a shunt in the 1-4 position of JU2 and JU3 to drive RNG1 and RNG0 high, or place a shunt in the 1-2 position of JU2 and JU3 to drive RNG1 and RNG0 low. Refer to the MAX9248 IC data sheet for actual frequency settings. Power-Down (PWRDWN) The power-down mode in the MAX9247 and MAX9248 puts the outputs in high impedance, stops the PLL, and reduces supply current to 50FA or less. The MAX9247 PWRDWN pin is accessible through header H6-15. Drive the pin high for normal operation of the MAX9247 or drive the pin low to power down the MAX9247. The MAX9248 PWRDWN pin is accessible through jumper JU4 (see Table 1). Drive the pin high by placing a shunt in the 1-4 position of JU4 for normal operation. Drive the pin low by placing a shunt in the 1-2 position of JU4 to power down the MAX9248. Spread-Spectrum Frequency (SS) The MAX9248 can set the frequency spread to ±4% or ±2% by moving the shunt of jumper JU5 to the appropriate position (see Table 1). Pseudo-Random Bit Sequence (PRBS) Mode The MAX9247/MAX9248 EV kit offers the user an internal test mode to quickly check full functionality and verify the quality of the SerDes link. This mode is called the pseudo-random bit sequence, or PRBS mode. The MAX9247 features an on-chip PRBS generator that can be utilized to generate a pseudo-random bit stream to evaluate the quality and performance by comparing the output of the serializer (prior to the link/cable) with the input of the deserializer (after the link/cable). 6   _______________________________________________________________________________________ MAX9247/MAX9248 Evaluation Kit To monitor the SerDes signal integrity, connect one channel of the digital oscilloscope with differential probe capabilities to OUT+ and OUT- signal lines from jumpers JU12 and JU13 (MAX9247). Repeat the same test for the deserializer (MAX9248) on signal lines IN+ and IN-, accessible through jumpers JU9 and JU10. Power Supplies The MAX9247 is powered by connecting PVCC1, LVCC1, IVCC, and DVCC1 to a DC power supply at 3.0V to 3.6V. The MAX9247 can be configured to reduce wiring to the supply and ground pads by placing shunts on jumpers JU19, JU20, and JU21. The MAX9248 is powered by applying 3.0V to 3.6V to the PVCC2, LVCC2, OVCC, and DVCC2 pads. The MAX9248 can be configured to reduce wiring to the supply and ground pads by placing shunts on jumpers JU16, JU17, and JU18. _______________________________________________________________________________________   7 Evaluates: MAX9247/MAX9248 To activate this feature, the MAX9247 must first enter power-down mode by driving H6-15 low. Place a shunt in the 2-3 position of JU7 and JU8. Activate the internal PRBS mode by applying a negative DC voltage (-1.0V to -3.0V) to the VNEG pad. 5 5 6 6 7 7 8 8 P1 1 1 2 2 3 3 4 4 H4-7 H4-9 H4-11 H4-13 H4-15 H4-17 H4-19 H4-8 H4-10 H4-12 H4-14 H4-16 H4-18 H4-20 H3-1 H3-3 H3-5 H3-7 H3-9 H3-11 H3-13 H3-15 H3-17 H3-19 H3-4 H3-6 H3-8 H3-10 H3-12 H3-14 H3-16 H3-18 H3-20 PVCC2 P3 REF R13 OPEN C19 10µF JU10 H3-2 H3 C24 0.1µF JU9 H4-5 H4-6 C23 0.1µF H4-3 H4-4 H4 C18 10µF H4-1 C17 10µF VTEST H4-2 DVCC2 C16 10µF JU17 LVCC2 JU18 OVCC JU11 REFCLK R4 82.5Ω R5 130Ω C20 10µF R8 49.9Ω 1% R14 82.5Ω R12 130Ω 3 3 3 3 3 2 4 2 4 2 4 2 4 2 4 R3 OPEN R6 OPEN 1 JU5 1 JU4 1 JU3 1 JU2 1 JU1 R9 OPEN R2 OPEN R1 OPEN C3 OPEN C45 0.1µF C43 0.1µF C44 0.001µF C42 0.001µF R/F RNG1 VCCLVDS IN+ INLVDSGND PLLGND VCCPLL RNG0 GND VCC REFCLK C47 0.1µF R11 OPEN R10 OPEN R7 OPEN 1 2 3 4 5 6 7 8 9 10 11 12 C2 OPEN C46 0.001µF C1 OPEN C4 OPEN C5 OPEN C6 OPEN MAX9248 U1 C34 OPEN C27 OPEN C35 OPEN C28 OPEN C8 OPEN C36 OPEN 36 35 34 33 32 31 30 29 28 27 26 25 C21 0.001µF RGB_OUT7 RGB_OUT6 RGB_OUT5 RGB_OUT4 RGB_OUT3 RGB_OUT2 RGB_OUT1 RGB_OUT0 PCLK_OUT LOCK VCCO VCCOGND C7 OPEN 48 47 46 45 44 43 42 41 40 39 38 37 RGB_OUT17 RGB_OUT16 RGB_OUT15 RGB_OUT14 RGB_OUT13 RGB_OUT12 RGB_OUT11 RGB_OUT10 RGB_OUT9 RGB_OUT8 VCCO VCCOGND PWRDWN SS CNTL_OUT0 CNTL_OUT1 CNTL_OUT2 CNTL_OUT3 CNTL_OUT4 CNTL_OUT5 CNTL_OUT6 CNTL_OUT7 CNTL_OUT8 DE_OUT 13 14 15 16 17 18 19 20 21 22 23 24 JU16 C29 OPEN C37 OPEN C22 0.1µF C9 OPEN C30 OPEN C10 OPEN C38 OPEN C11 OPEN C31 OPEN C25 0.001µF C12 OPEN C39 OPEN C13 OPEN C32 OPEN C26 0.1µF C40 OPEN C14 OPEN C33 OPEN C15 OPEN C41 OPEN H1-2 H1-1 H2-12 H2-10 H2-8 H2-6 H2-4 H2-2 H2-7 H2-5 H2-3 H2-1 H2-14 H2-9 H2-16 H2-13 H2-11 H2-18 H2-22 H2-19 H2-15 H2-24 H2-20 H2-21 H2-17 H2-26 H2-23 H2-28 H2-25 H2-30 H2-32 H2-31 H2-27 H2-34 H2-33 H2-29 H2-36 H2-35 H2-38 H1-4 H1-3 H2-40 H1-6 H1-5 H2-37 H1-8 H1-7 H2-39 H1-12 H1-9 H1-14 H1-10 H1-11 H1-16 H1-24 H1-23 H1-13 H1-26 H1-25 H1-18 H1-28 H1-27 H1-15 H1-30 H1-29 H1-17 H1-32 H1-31 H1-22 H1-34 H1-33 H1-20 H1-36 H1-35 H1-19 H1-38 H1-37 H1-21 H1-40 H1-39 H2 H1 Evaluates: MAX9247/MAX9248 MAX9247/MAX9248 Evaluation Kit Figure 1a. MAX9247/MAX9248 EV Kit Schematic (Sheet 1 of 2) 8   _______________________________________________________________________________________ GND2 _______________________________________________________________________________________   9 Figure 1b. MAX9247/MAX9248 EV Kit Schematic (Sheet 2 of 2) R19 49.9Ω 1% R40 OPEN R37 OPEN R35 OPEN R33 OPEN R31 OPEN R28 OPEN R26 OPEN R24 OPEN R22 OPEN R48 OPEN R46 OPEN R44 OPEN R36 OPEN R20 OPEN P4 PCLK R42 OPEN R41 OPEN R39 OPEN R36 OPEN R34 OPEN R32 OPEN R30 OPEN R27 OPEN R25 OPEN R23 OPEN R21 OPEN R47 OPEN R45 OPEN R43 OPEN R29 OPEN H5 H5-8 H5-7 H5-10 H5-9 H5-12 H5-11 H5-14 H5-13 H5-16 H5-15 H5-18 H5-17 H5-20 H5-19 H5-2 H5-1 H5-4 H5-3 H5-6 H5-5 H6 H6-8 H6-7 H6-10 H6-9 H6-12 H6-11 H6-14 H6-13 H6-16 H6-15 H6-18 H6-17 H6-20 H6-19 H6-2 H6-1 H6-4 H6-3 H6-6 H6-5 H7 H7-8 H7-7 H7-10 H7-9 H7-12 H7-11 H7-14 H7-13 H7-16 H7-15 H7-18 H7-17 H7-20 H7-19 H7-2 H7-1 H7-4 H7-3 H7-6 H7-5 C50 0.1µF Evaluates: MAX9247/MAX9248 H8 C51 0.001µF C56 0.1µF H8-8 H8-7 H8-10 H8-9 H8-12 H8-11 H8-14 H8-13 H8-16 H8-15 H8-18 H8-17 H8-20 H8-19 12 9 11 8 7 6 5 4 3 2 10 C57 0.001µF H8-2 H8-1 H8-4 H8-3 H8-6 H8-5 1 CNTL_IN1 CNTL_IN0 RGB_IN17 RGB_IN16 RGB_IN15 RGB_IN14 RGB_IN13 RGB_IN12 RGB_IN11 VCCIN RGB_IN10 GND RGB_IN5 CNTL_IN4 RGB_IN6 CNTL_IN3 RGB_IN7 CNTL_IN2 RGB_IN8 VCC RGB_IN9 GND RGB_IN4 U2 MAX9247 CNTL_IN5 CNTL_IN6 RGB_IN3 RGB_IN0 DE_IN RGB_IN1 CNTL_IN8 RGB_IN2 CNTL_IN7 GND I.C. VCC PCLK_IN H9 13 14 15 16 17 18 19 20 21 22 23 24 48 H9-19 47 H9-20 H9-17 46 H9-18 H9-15 45 H9-16 H9-13 44 H9-14 H9-11 43 H9-12 H9-9 42 H9-10 H9-7 41 H9-8 H9-5 40 H9-6 H9-3 39 H9-4 H9-1 38 H9-2 37 PRE VCCPLL PLLGND PWRDWN CMF LVDSGND OUT- OUT+ LVDSGND RNG1 RNG0 25 26 27 28 29 30 31 32 33 35 36 34 C62 0.001µF JU6 VCCLVDS 3 1 2 C53 0.1µF C58 10µF IVCC JU14 IVCC JU15 R17 1kΩ 1% C48 10µF C63 0.1µF R18 1kΩ 1% GND1 IVCC DVCC1 JU19 3 1 2 3 1 2 JU7 C54 0.001µF C60 10µF C64 0.001µF JU8 C59 10µF JU21 JU20 LVCC1 PVCC1 C55 0.1µF C65 0.1µF C61 10µF VNEG JU12 JU13 C52 0.1µF C49 0.1µF R16 OPEN R15 OPEN 4 4 3 3 2 2 1 1 P2 8 8 7 7 6 6 5 5 MAX9247/MAX9248 Evaluation Kit Evaluates: MAX9247/MAX9248 MAX9247/MAX9248 Evaluation Kit Figure 2. MAX9247/MAX9248 EV Kit Component Placement Guide—Component Side Figure 3. MAX9247/MAX9248 EV Kit PCB Layout—Component Side 10   ������������������������������������������������������������������������������������� MAX9247/MAX9248 Evaluation Kit Figure 5. MAX9247/MAX9248 EV Kit PCB Layout—Inner Layer 3 ______________________________________________________________________________________   11 Evaluates: MAX9247/MAX9248 Figure 4. MAX9247/MAX9248 EV Kit PCB Layout—Inner Layer 2 Evaluates: MAX9247/MAX9248 MAX9247/MAX9248 Evaluation Kit Figure 6. MAX9247/MAX9248 EV Kit PCB Layout—Solder Side Figure 7. MAX9247/MAX9248 EV Kit Component Placement Guide—Solder Side Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ©  2009 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX9248EVKIT+ 价格&库存

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