19-5138; Rev 4; 1/12
TION KIT
EVALUA BLE
AVAILA
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
The MAX9249 serializer with LVDS system interface
utilizes Maxim’s Gigabit multimedia serial link (GMSL)
technology. The MAX9249 serializer pairs with any
GMSL deserializer to form a complete digital serial link
for joint transmission of high-speed video, audio, and
control data.
The MAX9249 allows a maximum serial payload data rate
of 2.5Gbps for a 15m shielded twisted-pair (STP) cable.
The serializer operates up to a maximum clock rate of
104MHz (3-channel LVDS) or 78MHz (4-channel LVDS).
This serial link supports display panels from QVGA (320
x 240) to WXGA (1280 x 800) and higher with 24-bit color.
The 3-channel mode handles three lanes of LVDS data
(21 bits), UART control signals, and three audio signals.
The 4-channel mode handles four lanes of LVDS data
(28 bits), UART control signals, three audio signals,
and/or up to three auxiliary parallel inputs. The three
audio inputs form a standard I2S interface, supporting
sample rates from 8kHz to 192kHz and audio word
lengths of 4 to 32 bits. The embedded control channel forms a full-duplex, differential, 100kbps to 1Mbps
UART link between the serializer and deserializer. The
electronic control unit (ECU), or microcontroller (FC), can
be located on the MAX9249 side of the link (typical for
video display), on the deserializer side of the link (typical for image sensing), or on both sides. In addition, the
control channel enables ECU/FC control of peripherals
on the remote side, such as backlight control, grayscale
Gamma correction, camera module, and touch screen.
Base-mode communication with peripherals uses either
I2C or the GMSL UART format. A bypass mode enables
full-duplex communication using custom UART formats.
The MAX9249 serializer driver preemphasis, along with
the channel equalizer on the GMSL deserializer, extends
the link length and enhances the link reliability. Spread
spectrum is available on the MAX9249 to reduce EMI on
the serial link and the parallel output of the GMSL deserializer. The serial output complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
The core supply for the MAX9249 is 1.8V. The I/O supply
ranges from 1.8V to 3.3V. The MAX9249 is available in
a 48-pin TQFP package (7mm x 7mm) with an exposed
pad. Electrical performance is guaranteed over the
-40NC to +105NC automotive temperature range.
Features
S Pairs with Any GMSL Deserializer
S 2.5Gbps Payload Rate AC-Coupled Serial Link
with 8B/10B Line Coding
S Supports Up to WXGA (1280 x 800) with 24-Bit
Color
S 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz
to 78MHz (4-Channel LVDS) Input Clock
S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I2S
Audio Channel Supports High-Definition Audio
S Embedded Half-/Full-Duplex Bidirectional Control
Channel (100kbps to 1Mbps)
S Interrupt Supports Touch-Screen Functions for
Display Panels
S Remote-End I2C Master for Peripherals
S Preemphasis Line Driver
S Programmable Spread Spectrum on the Serial
Outputs for Reduced EMI
S Automatic Data-Rate Detection Allows “On-the-
Fly” Data-Rate Change
S Input Clock PLL Jitter Attenuator
S Built-In PRBS Generator for BER Testing of the
Serial Link
S Line-Fault Detector Detects Serial Link Shorts to
Ground, Battery, or Open Link
S ISO 10605 and IEC 61000-4-2 ESD Protection
S -40NC to +105NC Operating Temperature Range
S 1.8V to 3.3V I/O, 1.8V Core, and 3.3V LVDS
Supplies
S Patent Pending
Applications
High-Resolution Automotive Navigation
Rear-Seat Infotainment
Megapixel Camera Systems
Ordering Information
PART
TEMP RANGE
MAX9249GCM/V+
MAX9249GCM/V+T
-40NC to +105NC
-40NC to +105NC
PIN-PACKAGE
48 TQFP-EP*
48 TQFP-EP*
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX9249
General Description
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND.....................................................-0.5V to +1.9V
LVDSVDD to AGND...............................................-0.5V to +3.9V
DVDD to GND.......................................................-0.5V to +1.9V
IOVDD to GND......................................................-0.5V to +3.9V
Any Ground to Any Ground..................................-0.5V to +0.5V
RXIN_ _, RXCLKIN_ to AGND...............................-0.5V to +3.9V
OUT+, OUT- to AGND..........................................-0.5V to +1.9V
LMN_ to AGND (15mA current limit).....................-0.5V to +3.9V
All Other Pins to Any Ground............... -0.5V to (VIOVDD + 0.5V)
OUT+, OUT- Short Circuit to Ground or Supply........Continuous
Continuous Power Dissipation (TA = +70NC)
48-Pin TQFP (derate 36.2mW/NC above +70NC).....2898.6mW
ESD Protection
Human Body Model (RD = 1.5kω, CS = 100pF)
(RXIN_ _, RXCLKIN_, OUT+, OUT-) to AGND.................±8kV
All Other Pins to GND.......................................................±3kV
IEC 61000-4-2 (RD = 330ω, CS = 150pF)
Contact Discharge
(RXIN_ _, RXCLKIN_) to AGND........................................±4kV
(OUT+, OUT-) to AGND.................................................±10kV
Air Discharge
(RXIN_ _, RXCLKIN_) to AGND........................................±8kV
(OUT+, OUT-) to AGND.................................................±12kV
ISO 10605 (RD = 2kω, CS = 330pF)
Contact Discharge
(RXIN_ _, RXCLKIN_) to AGND........................................±6kV
(OUT+, OUT-) to AGND.................................................±10kV
Air Discharge
(RXIN_ _, RXCLKIN_) to AGND......................................±20kV
(OUT+, OUT-) to AGND.................................................±30kV
Operating Temperature Range......................... -40NC to +105NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
PACKAGE THERMAL CHARACTERISTICS (Note 1)
48 TQFP-EP
Junction-to-Ambient Thermal Resistance (θJA)........27.6NC/W
Junction-to-Case Thermal Resistance (θJC).................2NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I ±1% (differential), TA = -40NC to
+105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V
- |VID/2|. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (PWDN, SSEN, BWS, DRS, MS, CDS, AUTOS, SD/CNTL0, SCK, WS, CNTL_)
High-Level Input Voltage
PWDN, SSEN, BWS, DRS, MS, CDS, AUTOS
0.65 x
VIOVDD
SD/CNTL0, SCK, WS, CNTL_
0.7 x
VIOVDD
VIH1
Low-Level Input Voltage
VIL1
Input Current
IIN1
Input Clamp Voltage
VCL
VIN = 0 to VIOVDD
ICL = -18mA
V
-10
0.35 x
VIOVDD
V
+10
FA
-1.5
V
SINGLE-ENDED OUTPUT (INT)
High-Level Output Voltage
VOH1
IOH = -2mA
Low-Level Output Voltage
VOL1
IOL = 2mA
Output Short-Circuit Current
IOS
VO = 0V
VIOVDD 0.2
V
0.2
VIOVDD = 3.0V to 3.6V
16
35
64
VIOVDD = 1.7V to 1.9V
3
12
21
2 _______________________________________________________________________________________
V
mA
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
(VDVDD = VAVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I ±1% (differential), TA = -40NC to
+105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V
- |VID/2|. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
PARAMETER
I2C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AND UART I/O, OPEN-DRAIN OUTPUT (RX/SDA, TX/SCL, LFLT)
High-Level Input Voltage
VIH2
Low-Level Input Voltage
VIL2
Input Current
IIN2
Low-Level Open-Drain Output
Voltage
VOL2
0.7 x
VIOVDD
V
0.3 x
VIOVDD
V
+5
FA
VIN = 0 to VIOVDD (Note 2)
VIOVDD = 1.7V to 1.9V
IOL = 3mA
VIOVDD = 3.0V to 3.6V
-110
Preemphasis off (Figure 1)
300
3.3dB preemphasis setting, VOD(P)
(Figure 2)
350
610
3.3dB deemphasis setting, VOD(D)
(Figure 2)
240
425
0.4
0.3
V
DIFFERENTIAL OUTPUT (OUT+, OUT-)
Differential Output Voltage
Change in VOD Between
Complementary Output States
Output Offset Voltage
(VOUT+ + VOUT-)/2 = VOS
Change in VOS Between
Complementary Output States
Output Short-Circuit Current
VOD
400
DVOD
VOS
Preemphasis off
1.1
1.4
DVOS
IOS
Magnitude of Differential Output
Short-Circuit Current
IOSD
Output Termination Resistance
(Internal)
RO
VOUT+ or VOUT- = 0V
500
mV
15
mV
1.56
V
15
mV
-60
mA
VOUT+ or VOUT- = 1.9V
25
VOD = 0V
25
mA
63
I
27
mV
From OUT+, OUT- to VAVDD
45
54
REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)
High Switching Threshold
VCHR
Low Switching Threshold
VCLR
-27
mV
LINE-FAULT DETECTION INPUT (LMN_)
Short-to-GND Threshold
VTG
Figure 3
Normal Thresholds
VTN
Figure 3
0.3
V
0.57
1.07
V
V
Open Thresholds
VTO
Figure 3
1.45
VIO +
60mV
Open Input Voltage
VIO
Figure 3
1.47
1.75
V
Short-to-Battery Threshold
VTE
Figure 3
2.47
50
mV
LVDS INPUTS (RXIN_ _, RXCLKIN_)
Differential Input High Threshold
VTH
Differential Input Low Threshold
VTL
-50
mV
_______________________________________________________________________________________ 3
MAX9249
DC ELECTRICAL CHARACTERISTICS (continued)
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
DC ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VAVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I ±1% (differential), TA = -40NC to
+105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V
- |VID/2|. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
PARAMETER
Input Differential Termination
Resistance
Input Current
Power-Off Input Current
SYMBOL
CONDITIONS
RTERM
IIN+, IIN- PWDN = high or low, IN+ and IN- are shorted
IIN0+, IIN0- VAVDD = VDVDD = VIOVDD = 0V
MIN
TYP
MAX
UNITS
85
110
135
I
-25
+25
FA
-40
+40
FA
POWER SUPPLY
Worst-Case Supply Current
(Figure 4)
IWCS
BWS = GND
fRXCLKIN_ = 16.6MHz
125
165
fRXCLKIN_ = 33.3MHz
135
175
fRXCLKIN_ = 66.6MHz
150
190
fRXCLKIN_ = 104MHz
175
220
mA
Sleep-Mode Supply Current
ICCS
LVDS inputs are not driven
45
125
FA
Power-Down Supply Current
ICCZ
PWDN = GND, LVDS inputs are not driven
5
80
FA
AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I ±1% (differential), TA = -40NC to +105NC, unless otherwise
noted. Differential input voltage |VID| = 0.15V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|. Typical values are
at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUT (RXCLKIN_)
Clock Frequency
I2C/UART
fRXCLKIN_
BWS = GND, VDRS = VIOVDD
8.33
BWS = GND, DRS = GND
16.66
16.66
104
VBWS = VIOVDD, VDRS = VIOVDD
6.25
12.5
VBWS = VIOVDD, DRS = GND
12.5
78
MHz
PORT TIMING (Note 3)
Output Rise Time
tR
30% to 70%, CL = 10pF to 100pF,
1kI pullup to IOVDD
20
150
ns
Output Fall Time
tF
70% to 30%, CL = 10pF to 100pF,
1kI pullup to IOVDD
20
150
ns
Input Setup Time
tSET
I2C only (Figure 5)
100
ns
Input Hold Time
tHOLD
I2C only (Figure 5)
0
ns
SWITCHING CHARACTERISTICS (Note 3)
Differential Output Rise/Fall Time
tR, tF
20% to 80%, VOD ≥ 400mV, RL = 100I,
serial-bit rate = 3.125Gbps (Note 3)
Total Serial Output Jitter
tTSOJ1
3.125Gbps PRBS signal, measured at VOD
= 0V differential, preemphasis disabled
(Figure 6)
Deterministic Serial Output Jitter
tDSOJ2
3.125Gbps PRBS signal
90
0.25
0.15
150
ps
UI
UI
CNTL_ Input Setup Time
tSET
CNTL_ (Figure 7)
3
ns
CNTL_ Input Hold Time
tHOLD
CNTL_ (Figure 7)
1.5
ns
RXIN_ _ Skew Margin
tRSKM
Figure 8
0.3
UI
4 _______________________________________________________________________________________
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I ±1% (differential), TA = -40NC to +105NC, unless otherwise
noted. Differential input voltage |VID| = 0.15V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|. Typical values are
at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
PARAMETER
Serializer Delay (Note 4)
SYMBOL
CONDITIONS
MIN
TYP
MAX
Spread spectrum enabled
2950
Spread spectrum disabled
390
UNITS
tSD
Figure 9
Bits
Link Start Time
tLOCK
Figure 10
3.5
ms
Power-Up Time
tPU
Figure 11
3.5
ms
WS Frequency
fWS
Table 3
8
192
kHz
Sample Word Length
nWS
Table 3
4
32
Bits
I2S INPUT TIMING
SCK Frequency
fSCK
fSCK = fWS x nWS x 2
(8 x 4)
x2
(192 x 32)
x2
SCK Clock High Time (Note 3)
tHC
VSCK R VIH, tSCK = 1/fSCK
0.35 x
tSCK
ns
SCK Clock Low Time (Note 3)
tLC
VSCK ≤ VIL, tSCK = 1/fSCK
0.35 x
tSCK
ns
SD/CNTL0, WS Setup Time
tSET
Figure 12 (Note 3)
2
ns
SD/CNTL0, WS Hold Time
tHOLD
Figure 12 (Note 3)
2
ns
kHz
Note 2: Minimum IIN due to voltage drop across the internal pullup resistor.
Note 3: Not production tested.
1
1
=
(BWS
= 0),
=
(BWS
= VIOVDD )
Note 4: Bit time
30 × fRXCLKIN_
40 × fRXCLKIN_
_______________________________________________________________________________________ 5
MAX9249
AC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC, unless otherwise noted.)
TOTAL SUPPLY CURRENT
vs. RXCLKIN_ FREQUENCY
(3-CHANNEL MODE)
TOTAL SUPPLY CURRENT
vs. RXCLKIN_ FREQUENCY
(4-CHANNEL MODE)
PREEMP = 0x0B TO 0x0F
140
130
PREEMP = 0x01 TO 0x04
120
25
65
85
-60
-70
-80
2% SPREAD
-90
31.5
50
65
32.5
33.5
34.5
80
fRXCLKIN_ = 16.5MHz
-10
0.5% SPREAD
0% SPREAD
-20
-30
-40
-50
-60
-70
-80
2% SPREAD
4% SPREAD
-90
15.0
35.5
15.5
16.0
16.5
17.0
17.5
18.0
RXCLKIN FREQUENCY (MHz)
MAXIMUM PCLK FREQUENCY
vs. STP CABLE LENGTH (BER < 10-9)
MAXIMUM RXCLKIN_ FREQUENCY
vs. 10m STP CABLE CL (BER < 10-9)
MAX9249 toc05
80
OPTIMUM PE/EQ
SETTINGS
NO PE, EQS = LOW
NO PE, EQS = LOW
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 10m
0
35
RXCLKIN FREQUENCY (MHz)
100
0
20
0
4% SPREAD
120
20
PREEMP = 0x00
5
OUTPUT POWER SPECTRUM (dBm)
0.5% SPREAD
-50
40
PREEMP = 0x01 TO 0x04
OUTPUT POWER SPECTRUM
vs. RXCLKIN_ FREQUENCY
-40
60
130
OUTPUT POWER SPECTRUM
vs. RXCLKIN_ FREQUENCY
-30
30.5
135
RXCLKIN FREQUENCY (MHz)
0% SPREAD
-20
140
RXCLKIN FREQUENCY (MHz)
fRXCLKIN_ = 33MHz
-10
145
105
5
10
15
STP CABLE LENGTH (m)
120
MAXIMUM RXCLKIN FREQUENCY (MHz)
OUTPUT POWER SPECTRUM (dBm)
0
PREEMP = 0x0B TO 0x0F
150
120
45
MAX9249 toc03
5
155
125
PREEMP = 0x00
110
PRBS PATTERN
160
MAX9249 toc04
150
MAX9249 toc02
160
165
OPTIMUM PE/EQ SETTINGS
100
80
60
NO PE, EQS = LOW
40
NO PE, EQS = HIGH
20
BER CAN BE AS LOW AS 10-12 FOR
CL < 4pF FOR OPTIMUM PE/EQ SETTINGS
0
20
MAX9249 toc06
TOTAL SUPPLY CURRENT (mA)
PRBS PATTERN
TOTAL SUPPLY CURRENT (mA)
MAX9249 toc01
170
MAXIMUM PCLK FREQUENCY (MHz)
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
0
2
4
6
8
STP CABLE LOAD CAPACITANCE (pF)
6 _______________________________________________________________________________________
10
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
RX/SDA
LMN1
SSEN
TX/SCL
OUTAGND
OUT+
LFLT
LMN0
AVDD
DRS
INT
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25
IOVDD
GND
37
24
38
23
DVDD
N.C.
39
22
40
21
BWS
PWDN
CDS
MS
AUTOS
N.C.
AVDD
AGND
41
20
42
19
MAX9249
43
18
44
17
45
16
46
15
47
14
EP*
13
+
*EXPOSED PAD.
7
8
DVDD
AGND
CNTL2
CNTL1
WS
SCK
SD/CNTL0
AVDD
LVDSVDD
AGND
9 10 11 12
RXIN3+
6
RXCLKINRXCLKIN+
RXIN3-
5
AGND
4
RXIN2RXIN2+
3
LVDSVDD
2
RXIN0RXIN0+
1
RXIN1RXIN1+
48
IOVDD
GND
TQFP
Pin Description
PIN
NAME
1–4, 7, 8,
11, 12
RXIN_-,
RXIN_+
5, 14
LVDSVDD
6, 13, 21,
29, 48
AGND
9, 10
RXCLKIN-,
RXCLKIN+
15, 32, 47
AVDD
16
SD/CNTL0
17
SCK
I2S Serial-Clock Input with Internal Pulldown to GND
18
WS
I2S Word-Select Input with Internal Pulldown to GND
19
CNTL1
FUNCTION
Differential LVDS Data Inputs. Set BWS = low (3-channel mode) to use RXIN0_ to RXIN2_. Set
BWS = high (4-channel mode) to use RXIN0_ to RXIN3_.
3.3V LVDS Power Supply. Bypass LVDSVDD to AGND with 0.1FF and 0.001FF capacitors as close
as possible to the device with the smaller value capacitor closest to LVDSVDD.
Analog Ground
LVDS Input for the LVDS Clock
1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as close
as possible to the device with the smaller value capacitor closest to AVDD.
I2S Serial-Data Input with Internal Pulldown to GND. Disable I2S to use SD/CNTL0 as an additional
input.
Control Input 1 with Internal Pulldown to GND. Data is latched every RXCLKIN_ cycle (Figure 7).
CNTL1 is not available in 3-channel mode. Drive BWS high (4-channel mode) to use this input.
CNTL1 or RES (RES from VESA Standard Panel Specification) is mapped to DIN27 (see the
Reserved Bit (RES) section).
_______________________________________________________________________________________ 7
MAX9249
Pin Configuration
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Pin Description (continued)
PIN
NAME
FUNCTION
20
CNTL2
Control Input 2 with Internal Pulldown to GND. Data is latched every RXCLKIN_ cycle (Figure 7).
CNTL2 is not available in 3-channel mode. Drive BWS high (4-channel mode) to use this input.
CNTL2 is mapped to DIN28.
22, 39
DVDD
1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close as
possible to the device with the smaller value capacitor closest to DVDD.
23, 38
GND
Digital and I/O Ground
24, 37
IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with 0.1FF and
0.001FF capacitors as close as possible to the device with the smallest value capacitor closest to
IOVDD.
25
RX/SDA
Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to
IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9249’s UART. In I2C mode, RX/SDA is
the SDA input/output of the MAX9249’s I2C master.
26
TX/SCL
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD.
In UART mode, TX/SCL is the Tx output of the MAX9249’s UART. In I2C mode, TX/SCL is the SCL
output of the MAX9249’s I2C master.
27
SSEN
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external pulldown or
pullup resistors. The state of SSEN latches upon power-up or when resuming from power-down
mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on the serial link. Set SSEN =
low to use the serial link without spread spectrum.
28
LMN1
Line-Fault Monitor Input 1 (see Figure 3 for details)
30, 31
OUT-,
OUT+
Differential CML Output+/-. Differential outputs of the serial link.
33
LMN0
Line-Fault Monitor Input 0 (see Figure 3 for details)
34
LFLT
Line Fault. Active-low, open-drain line-fault output with a 60kI internal pullup resistor. LFLT = low
indicates a line fault. LFLT is high impedance when PWDN = low.
35
INT
Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when PWDN =
low. A transition on the INT input of the GMSL deserializer toggles the MAX9249’s INT output.
36
DRS
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistors.
Set DRS = high for RXCLKIN_ frequencies of 8.33MHz to 16.66MHz (3-channel mode) or 6.25MHz
to 12.5MHz (4-channel mode). Set DRS = low for RXCLKIN_ frequencies of 16.66MHz to 104MHz
(3-channel mode) or 12.5MHz to 78MHz (4-channel mode).
40, 46
N.C.
Internally Not Connected. Connect to GND or leave unconnected.
41
BWS
Bus-Width Select. Input width selection requires external pulldown or pullup resistors. Set BWS =
low for 3-channel mode. Set BWS = high for 4-channel mode.
42
PWDN
43
CDS
Control Direction Selection. Control link direction selection input requires external pulldown or
pullup resistors. Set CDS = low for FC use on the MAX9249 side of the serial link. Set CDS = high
for FC use on the GMSL deserializer side of the serial link.
44
MS
Mode Select. Control link mode-selection input requires external pulldown or pullup resistors. Set
MS = low to select base mode. Set MS = high to select the bypass mode.
Power-Down. Active-low power-down input requires external pulldown or pullup resistors.
8 _______________________________________________________________________________________
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
PIN
NAME
FUNCTION
45
AUTOS
Autostart Setting. Active-low power-up mode-selection input requires external pulldown or pullup
resistors. Set AUTOS = high to power up the device with no link active. Set AUTOS = low to have
the MAX9249 power up the serial link with autorange detection (see Tables 8 and 9).
—
EP
Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the AGND plane
for proper thermal and electrical performance.
Functional Diagram
LFLT
RXCLKIN+/-
7x PLL
DIVIDE BY 7
FILTER PLL
FIFO
CLKDIV
SPREAD PLL
LMN0
RXIN0+/-
S
P
DIN[6:0]
RXIN1+/-
S
P
DIN[13:7]
RXIN2+/-
S
P
DIN[20:14]
RXIN3+/-
S
P
DIN[26:21]
CNTL1
MUX
LMN1
MAX9249
8B/10B
ENCODE
PARITY
AUDIO FIFO
PRBS GEN
P
S
CML Tx
OUT+
DIN28
CNTL2
WS,
SD/CNTL0,
SCK
DIN27
LINE-FAULT DET
TERM
OUT-
ACB
UART/I2C
TX/SCL
RX/SDA
REV CH Rx
STP CABLE,
Z0 = 100I
(DIFF)
IN-
GMSL DESERIALIZER
IN+
_______________________________________________________________________________________ 9
MAX9249
Pin Description (continued)
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
RL/2
OUT+
VOD
VOS
OUT-
RL/2
GND
((OUT+) + (OUT-))/2
OUTVOS(+)
VOS(-)
VOS(-)
OUT+
DVOS = |VOS(+) - VOS(-)|
VOD(+)
VOD = 0V
VOD(-)
VOD(-)
DVOD = |VOD(+) - VOD(-)|
(OUT+) - (OUT-)
Figure 1. Serial-Output Parameters
OUT+
VOD(P)
VOS
VOD(D)
OUT-
SERIAL-BIT
TIME
Figure 2. Output Waveforms at OUT+ and OUT-
10
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
MAX9249
1.7V TO 1.9V
MAX9249
45kI*
45kI*
LMN0
LMN1
5kI*
OUTPUT
LOGIC
(OUT+)
5kI*
TWISTED PAIR
OUT+
OUT-
50kI*
50kI*
CONNECTORS
LFLT
REFERENCE
VOLTAGE
GENERATOR
OUTPUT
LOGIC
(OUT-)
*Q1% TOLERANCE
Figure 3. Line-Fault Detector Circuit
RXCLKIN+
RXCLKINRXIN0+ TO RXIN3+
RXIN0- TO RXIN3-
CNTL_
Figure 4. Worst-Case Pattern Input
______________________________________________________________________________________ 11
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
tF
tR
TX/
SCL
tHOLD
tSET
RX/
SDA
P
S
S
P
Figure 5. I2C Timing Parameters
800mVP-P
t TSOJ1
2
t TSOJ1
2
Figure 6. Differential Output Template
IDEAL SERIAL-BIT TIME
RXCLKINRXCLKIN+
RXIN_+/RXIN_-
tRSKM
tRSKM
tSET
tHOLD
VIHMIN
CNTL_
VILMAX
Figure 7. Input Setup-and-Hold Times
IDEAL
MIN
MAX
INTERNAL STROBE
Figure 8. LVDS Receiver Input Skew Margin
12
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
MAX9249
EXPANDED TIME SCALE
N-1
N
N+1
N+3
N+2
RXIN_+/RXIN_-
RXCLKIN+
RXCLKINN-1
N
OUT+/OUTFIRST BIT
LAST BIT
tSD
Figure 9. Serializer Delay
RXCLKINRXCLKIN+
tLOCK
350µs
SERIAL LINK INACTIVE
REVERSE CONTROL
CHANNEL ENABLED
SERIAL LINK ACTIVE
CHANNEL
DISABLED
REVERSE CONTROL
CHANNEL ENABLED
PWDN MUST BE HIGH
Figure 10. Link Startup Time
______________________________________________________________________________________ 13
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
RXCLKIN+
RXCLKIN-
VIH1
PWDN
tPU
POWERED UP, SERIAL
LINK INACTIVE
POWERED DOWN
POWERED UP, SERIAL LINK ACTIVE
350µs
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
Figure 11. Power-Up Delay
WS
tHOLD
tSCK
tSET
tLC
SCK
tHOLD
tSET
tHC
SD/CNTL0
Figure 12. Input I2S Timing Parameters
14
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
The MAX9249 serializer with LVDS system interface
utilizes Maxim’s GMSL technology. The MAX9249 serializer pairs with any GMSL deserializer to form a complete
digital serial link for joint transmission of high-speed
video, audio, and control data.
The MAX9249 allows a maximum serial payload data
rate of 2.5Gbps for a greater than 15m STP cable. The
serializer operates up to a maximum clock of 104MHz for
a 3-channel LVDS input or 78MHz for a 4-channel LVDS
input. This serial link supports display panels from QVGA
(320 x 240) up to WXGA (1280 x 800) with 24-bit color.
The 3-channel mode handles three lanes of LVDS data
(21 bits), UART control signals, and three audio signals.
The 4-channel mode handles four lanes of LVDS data
(28 bits), UART control signals, three audio signals, and/
or up to three auxiliary parallel inputs. The three audio
inputs form a standard I2S interface, supporting sample
rates from 8kHz to 192kHz and audio word lengths of
4 to 32 bits. The embedded control channel forms a
full-duplex, differential, 100kbps to 1Mbps UART link
between the serializer and deserializer. The ECU, or FC,
can be located on the MAX9249 side of the link (typical
for video display), on the deserializer side of the link (typical for image sensing), or on both sides. In addition, the
control channel enables ECU/FC control of peripherals
in the remote side, such as backlight control, grayscale
Gamma correction, camera module, and touch screen.
Base-mode communication with peripherals uses either
I2C or the GMSL UART format. A bypass mode enables
full-duplex communication using custom UART formats.
The MAX9249 serializer driver preemphasis, along with
the channel equalizer on the GMSL deserializer, extends
the link length and enhances the link reliability. Spread
spectrum is available on the MAX9249 to reduce EMI on
the serial link and the parallel output of the GMSL deserializer. The serial output complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
Register Mapping
The FC configures various operating conditions of the
MAX9249 and GMSL deserializer through internal registers. The default device addresses stored in the R0 and
R1 registers of both the MAX9249 and GSML deserializer are 0x80 and 0x90, respectively. Write to the R0/R1
registers in both devices to change the device address
of the MAX9249 or GMSL deserializer.
Table 1. Power-Up Default Register Map (see Table 12)
REGISTER
ADDRESS
(HEX)
POWER-UP
DEFAULT
(HEX)
0x00
0x80
SERID =1000000, serializer device address is 1000 000
RESERVED = 0
0x01
0x90
DESID =1001000, deserializer device address is 1001 000
RESERVED = 0
0x02
0x1F, 0x3F
0x03
0x00
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
SS = 000 (SSEN = low), SS = 001 (SSEN = high), spread-spectrum settings depend on
SSEN pin state at power-up
AUDIOEN = 1, I2S channel enabled
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
AUTOFM = 00, calibrate spread-modulation rate only once after locking
SDIV = 000000, autocalibrate sawtooth divider
______________________________________________________________________________________ 15
MAX9249
Detailed Description
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 1. Power-Up Default Register Map (see Table 12) (continued)
REGISTER
ADDRESS
(HEX)
0x04
POWER-UP
DEFAULT
(HEX)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x03, 0x13,
0x83 or 0x93
SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable default depends
on AUTOS pin state at power-up
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0 or 1, sleep-mode state depends on CDS and AUTOS pin state at power-up (see
the Link Startup Procedure section)
INTTYPE = 00, base mode uses I2C
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
0x05
0x70
I2CMETHOD = 0, I2C packets include register address
DISFPLL = 1, filter PLL disabled
CMLLVL = 11, 400mV CML signal level
PREEMP = 0000, preemphasis off
0x06
0x40
RESERVED = 01000000
0x07
0x22
RESERVED = 00100010
0x08
0x0A
(read only)
0x0C
0x70
RESERVED = 01110000
0x0D
0x0F
SETINT = 0, interrupt output set to low
RESERVED = 00
DISRES = 0, RES mapped to DIN27
SKEWADJ = 1111, no X7PLL clock skew adjustment
0x1E
0x03
(read only)
ID = 00000011, device ID is 0x03
0x1F
0x0X
(read only)
RESERVED = 0000
REVISION = XXXX, revision number
RESERVED = 0000
LFNEG = 10, no faults detected
LFPOS = 10, no faults detected
VESA Standard Panel Bitmapping
and Bus-Width Selection
The LVDS input has two selectable widths, 3-channel
and 4-channel. The MAX9249 accepts the VESA standard panel 3- or 4-channel LVDS (Table 2). Inputs on the
MAX9249 are mapped internally, according to Figures 13
and 14. In 3-channel mode, RXIN3_ and CNTL1/CNTL2
are not available. For both modes, the SD/CNTL0, SCK,
and WS pins are for I2S audio. The MAX9249 accepts
clock rates from 8.33MHz to 104MHz for 3-channel mode
and 6.25MHz to 78MHz for 4-channel mode.
Serial Link Signaling and Data Format
The MAX9249 high-speed data serial output uses
CML signaling with programmable preemphasis and
AC-coupling. The GMSL deserializer uses AC-coupling
and programmable channel equalization. When using
both the preemphasis and equalization, the MAX9249/
GMSL deserializer can operate up to 3.125Gbps over
STP cable lengths to 15m or more.
The MAX9249 serializer scrambles and encodes the
LVDS input data and sends the 8B/10B coded signal
through the serial link. The GMSL deserializer recovers
16
�������������������������������������������������������������������������������������
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
INPUT BITS
3-CHANNEL MODE
(BWS = LOW)
4-CHANNEL MODE
(BWS = HIGH)
VESA STANDARD
PANEL MAPPING
AUXILIARY SIGNALS
MAPPING
VESA STANDARD
PANEL MAPPING
AUXILIARY SIGNALS
MAPPING
DIN[0:5]
R[0:5]
DIN[6:11]
G[0:5]
—
R[0:5]
—
—
G[0:5]
—
DIN[12:17]
B[0:5]
DIN[18:20]
HS, VS, DE
—
B[0:5]
—
—
HS, VS, DE
DIN[21:22]
—
Not used
Not used
R6, R7
—
DIN[23:24]
Not used
Not used
G6, G7
—
DIN[25:26]
Not used
Not used
B6, B7
—
DIN27
Not used
Not used
RES*
CNTL1
DIN28
Not used
Not used
—
CNTL2
SD/CNTL0
—
SD/CNTL0
—
SD/CNTL0
*RES = Reserved (see the Reserved Bit (RES) section for details).
RXCLKINRXCLKIN+
CYCLE N-1
CYCLE N
RXIN0+/RXIN0-
DIN1
DIN0
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
RXIN1+/RXIN1-
DIN8
DIN7
DIN13
DIN12
DIN11
DIN10
DIN9
DIN8
DIN7
RXIN2+/RXIN2-
DIN15
DIN14
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
RXIN3+/RXIN3-
DIN22
DIN21
DIN27
DIN26
DIN25
DIN24
DIN23
DIN22
DIN21
CNTL1
DIN27
CNTL2
DIN28
SD/CNTL0*
SD*
*WITH I2S ENABLED; OTHERWISE CNTL0
Figure 13. LVDS Input Timing
______________________________________________________________________________________ 17
MAX9249
Table 2. Bus-Width Selection Using BWS
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
RXCLKINRXCLKIN+
CYCLE N-1
CYCLE N
RXIN0+/RXIN0-
R1
R0
G0
R5
R4
R3
R2
R1
R0
RXIN1+/RXIN1-
G2
G1
B1
B0
G5
G4
G3
G2
G1
RXIN2+/RXIN2-
B3
B2
DE
VS
HS
B5
B4
B3
B2
RXIN3+/RXIN3-
R7
R6
RES
B7
B6
G7
G6
R7
R6
Figure 14. VESA Standard Panel Clock and Bit Assignment
the embedded serial clock and then samples, decodes,
and descrambles before outputting the data. Figures
15 and 16 show the serial-data packet format before
scrambling and 8B/10B coding. In 3-channel or 4-channel mode, 21 or 28 bits come from the RXIN_ _ LVDS
inputs. Control bits can be mapped to DIN27 and DIN28
in 4-channel mode. The audio channel bit (ACB) contains an encoded audio signal derived from the three I2S
inputs (SD/CNTL0, SCK, and WS). The forward controlchannel (FCC) bit carries the forward control data. The
last bit (PCB) is the parity bit of the previous 23 or 31 bits.
24 BITS
DIN0
DIN1
R0
R1
DIN17 DIN18 DIN19 DIN20
B5
LVDS
DATA
(3 CHANNELS)
HS
VS
ACB
FCC
PCB
Reserved Bit (RES)
In 4-channel mode, the MAX9249 serializes all bits of all
four lanes including RES by default. Set DISRES (D4 of
Register 0x0D) to 1 to map CNTL1 to DIN27 instead of
RES.
Reverse Control Channel
The MAX9249 uses the reverse control channel to
receive I2C/UART and interrupt signals from the GMSL
deserializer in the opposite direction of the video stream.
The reverse control channel and forward video data
coexist on the same twisted pair forming a bidirectional
link. The reverse control channel operates independently
from the forward control channel. The reverse control
channel is available 500Fs after power-up. The MAX9249
temporarily disables the reverse control channel for
350Fs after starting/stopping the forward serial link.
Data-Rate Selection
DE
AUDIO
CHANNEL BIT
FORWARD
CONTROLCHANNEL BIT
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
SET ACCORDING TO VESA STANDARD PANEL BITMAP.
PACKET
PARITY
CHECK BIT
The MAX9249 uses the DRS input to set the RXCLKIN_
frequency. Set DRS high for an RXCLKIN_ frequency of
6.25MHz to 12.5MHz (4-channel mode) or 8.33MHz to
16.66MHz (3-channel mode). Set DRS low for normal
operation with an RXCLKIN_ frequency of 12.5MHz
to 78MHz (4-channel mode) or 16.66MHz to 104MHz
(3-channel mode).
Figure 15. 3-Channel Mode Serial Link Data Format
18
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
MAX9249
32 BITS
DIN0
DIN1
R0
R1
DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28
B5
HS
VS
R6
DE
R7
LVDS
DATA
(RXIN[2:0]_)
G6
G7
B6
B7
ACB
FCC
PCB
CNTL2
AUDIO
CHANNEL/CNTL0
BIT
LVDS
DATA
(RXIN3_)
RES/CNTL1
FORWARD
CONTROLCHANNEL BIT
NOTE: LOCATIONS OF THE LVDS RGB DATA AND CONTROL SIGNALS
ARE SET ACCORDING TO THE VESA STANDARD PANEL BITMAP.
PACKET
PARITY
CHECK BIT
*DIN27 FROM LVDS DATA (RXIN3_) OR EXTERNAL PIN (CNTL1).
Figure 16. 4-Channel Mode Serial Link Data Format
Table 3. Maximum Audio WS Frequency (kHz) for Various RXCLKIN_ Frequencies
RXCLKIN_ FREQUENCY
(DRS = LOW)
(MHz)
WORD LENGTH
(BITS)
RXCLKIN_ FREQUENCY
(DRS = HIGH)
(MHz)
12.5
15
16.6
> 20
6.25
7.5
8.33
> 10
8
> 192
> 192
> 192
> 192
> 192
> 192
> 192
> 192
16
> 192
> 192
> 192
> 192
> 192
> 192
> 192
> 192
18
185.5
> 192
> 192
> 192
185.5
> 192
> 192
> 192
20
174.6
> 192
> 192
> 192
174.6
> 192
> 192
> 192
24
152.2
182.7
> 192
> 192
152.2
182.7
> 192
> 192
32
123.7
148.4
164.3
> 192
123.7
148.4
164.3
> 192
Audio Channel
The I2S audio channel supports audio sampling rates
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not have to
be synchronized with RXCLKIN_. The MAX9249 automatically encodes audio data into a single bit stream
synchronous with RXCLKIN_. The GMSL deserializer
decodes the audio stream and stores audio words in a
FIFO. Audio rate detection uses an internal oscillator to
continuously determine the audio data rate and output
the audio in I2S format. The audio channel is enabled by
default. When the audio channel is disabled, the audio
data on the MAX9249 and GMSL deserializer is treated
as a control pin (CNTL0).
Low RXCLKIN_ frequencies limit the maximum audio
sampling rate. Table 3 lists the maximum audio sampling rate for various RXCLKIN_ frequencies. Spread-
spectrum settings do not affect the I2S data rate or WS
clock frequency.
Control Channel and Register Programming
The control channel is available for the FC to send
and receive control data over the serial link simultaneously with the high-speed data. Configuring the CDS pin
allows the FC to control the link from either the MAX9249
or the GMSL deserializer side to support video-display or
image-sensing applications.
The control channel between the FC and MAX9249 or
GMSL deserializer runs in base mode or bypass mode
according to the mode selection (MS) input of the device
connected to the FC. Base mode is a half-duplex control
channel and the bypass mode is a full-duplex control
channel. In base mode, the FC is the host and can
access the registers of both the MAX9249 and GMSL
deserializer from either side of the link by using the GMSL
______________________________________________________________________________________ 19
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
UART protocol. The FC can also program the peripherals on the remote side by sending the UART packets
to the MAX9249 or GMSL deserializer, with the UART
packets converted to I2C by the device on the remote
side of the link (GMSL deserializer for LCD or MAX9249
for image-sensing applications). The FC communicates
with a UART peripheral in base mode (through INTTYPE
register settings), using the half-duplex default GMSL
UART protocol of the MAX9249/GMSL deserializer. The
device addresses of the MAX9249 and GMSL deserializer in base mode are programmable. The default values
are 0x80 for the MAX9249 and 0x90 for the GMSL deserializer.
In base mode, when the peripheral interface uses
I2C (default), the MAX9249/GMSL deserializer convert
packets to I2C that have device addresses different
from those of the MAX9249 or GMSL deserializer. The
converted I2C bit rate is the same as the original UART
bit rate.
In bypass mode, the MAX9249/GMSL deserializer ignore
UART commands from the FC and the FC communicates with the peripherals directly using its own defined
UART protocol. The FC cannot access the MAX9249/
GMSL deserializer’s registers in this mode. Peripherals
accessed through the forward control channel using the
UART interface need to handle at least one RXCLKIN_
period of jitter due to the asynchronous sampling of the
UART signal by RXCLKIN_.
The MAX9249 embeds control signals going to the GMSL
deserializer in the high-speed forward link. Do not send
a logic-low value longer than 100Fs in either base or
bypass mode. The GMSL deserializer uses a proprietary
differential line coding to send signals back towards the
MAX9249. The speed of the control channel ranges from
100kbps to 1Mbps in both directions. The MAX9249/
GMSL deserializer automatically detect the control channel bit rate in base mode. Packet bit rates can vary up
to 3.5x from the previous bit rate (see the Changing the
Clock Frequency section). Figure 17 shows the UART
protocol for writing and reading in base mode between
the FC and the MAX9249/GMSL deserializer.
Figure 18 shows the UART data format. Even parity is
used. Figures 19 and 20 detail the formats of the SYNC
byte (0x79) and the ACK byte (0xC3). The FC and the
connected slave chip generate the SYNC byte and ACK
byte, respectively. Events such as device wake-up and
interrupt generate transitions on the control channel
that should be ignored by the FC. Data written to the
MAX9249/GMSL deserializer registers does not take
effect until after the acknowledge byte is sent. This
allows the FC to verify write commands received without
error, even if the result of the write command directly
affects the serial link. The slave uses the SYNC byte to
synchronize with the host UART data rate automatically.
If the INT or MS inputs of the GMSL deserializer toggles
while there is control-channel communication, the control-channel communication may be corrupted. In the
event of a missed acknowledge, the FC should assume
there was an error in the packet when the slave device
receives it, or that an error occurred during the response
from the slave device. In base mode, the FC must keep
the UART Tx/Rx lines high for 16 bit times before starting
to send a new packet.
As shown in Figure 21, the remote-side device converts
the packets going to or coming from the peripherals from
the UART format to the I2C format and vice versa. The
remote device removes the byte number count and adds
or receives the ACK between the data bytes of I2C. The
I2C’s data rate is the same as the UART data rate.
Interfacing Command-Byte-Only
I2C Devices
The MAX9249 and GMSL deserializer UART-to-I2C conversion interfaces with devices that do not require register addresses, such as the MAX7324 GPIO expander. In
this mode, the I2C master ignores the register address
byte and directly reads/writes the subsequent data bytes
(Figure 22). Change the communication method of the
I2C master using the I2CMETHOD bit. I2CMETHOD = 1
sets command-byte-only mode, while I2CMETHOD = 0
sets normal mode where the first byte in the data stream
is the register address.
Interrupt Control
The INT pin of the MAX9249 is the interrupt output and
the INT pin of the GMSL deserializer is the interrupt
input. The interrupt output on the MAX9249 follows the
transitions at the interrupt input. This interrupt function
supports remote-side functions such as touch-screen
peripherals, remote power-up, or remote monitoring.
Interrupts that occur during periods where the reverse
control channel is disabled, such as link startup/shutdown, are automatically resent once the reverse control
channel becomes available again. Bit D4 of register
0x06 in the GMSL deserializer also stores the interrupt
input state. The INT output of the MAX9249 is low after
power-up. In addition, the FC can set the INT output of
MAX9249 by writing to the SETINT register bit. In normal
operation, the state of the interrupt output changes when
the interrupt input on the GMSL deserializer toggles.
20
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
MAX9249
WRITE DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
BYTE 1
BYTE N
ACK
MASTER WRITES TO SLAVE
MASTER READS FROM SLAVE
READ DATA FRMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 17. GMSL UART Protocol for Base Mode
1 UART FRAME
START
D0
D1
D2
D3
FRAME 1
D4
D5
D6
D7
PARITY
STOP
FRAME 2
STOP
FRAME 3
START
STOP
START
Figure 18. GMSL UART Data Format for Base Mode
START
D0
D1
D2
D3
D4
D5
D6
D7
1
0
0
1
1
1
1
0
Figure 19. SYNC Byte (0x79)
PARITY STOP
START
D0
D1
D2
D3
D4
D5
D6
D7
1
1
0
0
0
0
1
1
PARITY STOP
Figure 20. ACK Byte (0xC3)
______________________________________________________________________________________ 21
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
FC
MAX9249/GMSL DESERIALIZER
11
SYNC FRAME
11
DEVICE ID + WR
MAX9249/GMSL DESERIALIZER
11
REGISTER ADDRESS
11
NUMBER OF BYTES
11
DATA 0
11
DATA N
11
ACK FRAME
PERIPHERAL
1
S
7
DEV ID
1 1
W A
8
REG ADDR
8
DATA 0
1
A
1
A
8
DATA N
1 1
A P
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)
FC
MAX9249/GMSL DESERIALIZER
11
SYNC FRAME
11
DEVICE ID + RD
MAX9249/GMSL DESERIALIZER
11
REGISTER ADDRESS
11
NUMBER OF BYTES
11
ACK FRAME
11
DATA 0
11
DATA N
PERIPHERAL
1
S
7
DEV ID
8
REG ADDR
1 1
W A
1 1
A S
: SLAVE TO MASTER
: MASTER TO SLAVE
7
DEV ID
1 1
R A
S: START
8
DATA 0
P: STOP
1
A
8
DATA N
1 1
A P
A: ACKNOWLEDGE
Figure 21. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
FC
11
SYNC FRAME
MAX9249/GMSL DESERIALIZER
11
11
DEVICE ID + WR
REGISTER ADDRESS
MAX9249/GMSL DESERIALIZER
FC
PERIPHERAL
1
7
S DEV ID
11
NUMBER OF BYTES
11
DATA N
1 1
W A
8
DATA 0
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)
MAX9249/GMSL DESERIALIZER
11
11
11
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS
MAX9249/GMSL DESERIALIZER
11
DATA 0
11
NUMBER OF BYTES
11
ACK FRAME
11
ACK FRAME
1
A
8
DATA N
11
DATA 0
11
DATA N
PERIPHERAL
1
S
: MASTER TO SLAVE
: SLAVE TO MASTER
7
DEV ID
S: START
1 1
R A
8
DATA 0
P: STOP
1
A
8
DATA N
1 1
A P
1 1
A P
A: ACKNOWLEDGE
Figure 22. Format Conversion Between UART and I2C in Command-Byte-Only Mode (I2CMETHOD = 1)
22
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
PREEMPHASIS LEVEL
(dB)*
PREEMPHASIS
SETTING
(0x05, D[3:0])
ICML
(mA)
IPRE
(mA)
-6.0
0100
12
-4.1
0011
-2.5
0010
-1.2
SINGLE-ENDED VOLTAGE SWING
MAX
(mV)
MIN
(mV)
4
400
200
13
3
400
250
14
2
400
300
0001
15
1
400
350
0
0000
16
0
400
400
1.1
1000
16
1
425
375
2.2
1001
16
2
450
350
3.3
1010
16
3
475
325
4.4
1011
16
4
500
300
6.0
1100
15
5
500
250
8.0
1101
14
6
500
200
10.5
1110
13
7
500
150
14.0
1111
12
8
500
100
*Negative preemphasis levels denote deemphasis.
Table 5. Serial Output Spread
SS
000
SPREAD (%)
No spread spectrum.
Power-up default when SSEN = low.
001
Q0.5% spread spectrum.
Power-up default when SSEN = high.
010
Q1.5% spread spectrum
011
Q2% spread spectrum
100
No spread spectrum
101
Q1% spread spectrum
110
Q3% spread spectrum
111
Q4% spread spectrum
Preemphasis Driver
The serial line driver in the MAX9249 employs current-mode logic (CML) signaling. The driver can be
programmed to generate a preemphasized waveform
according to the cable length and characteristics. There
are 13 preemphasis settings, as shown in Table 4.
Negative preemphasis levels are deemphasis levels in
which the swing is the same as normal, but the no-transition data is deemphasized. Program the preemphasis
levels through register 0x05 D[3:0] of the MAX9249. This
preemphasis function compensates the high-frequency
loss of the cable and enables reliable transmission over
longer link distances. Additionally, a lower power-drive
mode can be entered by programming CMLLVL bits
(0x05 D[5:4]) to reduce the driver strength down to
75% (CMLLVL = 10) or 50% (CMLLVL = 01) from 100%
(CMLLVL = 11, default).
Spread Spectrum
To reduce the EMI generated by the transitions on the
serial link and outputs of the GMSL deserializer, both
the MAX9249 and GMSL deserializer support spread
spectrum. Turning on spread spectrum on the MAX9249
spreads the serial data and the GMSL deserializer outputs. Do not enable spread for both the MAX9249 and
GMSL deserializer. The six selectable spread-spectrum
rates at the MAX9249 serial output are ±0.5%, ±1%,
±1.5%, ±2%, ±3%, and ±4% (Table 5). Some spreadspectrum rates can only be used at lower RXCLKIN_
frequencies (Table 6). There is no RXCLKIN_ frequency
limit for the 0.5% spread rate.
Set the MAX9249 SSEN input high to select 0.5% spread
at power-up and SSEN input low to select no spread at
power-up. The state of SSEN is latched upon power-up
or when resuming from power-down mode. Whenever
the MAX9249 spread spectrum is turned on or off, the
serial link automatically restarts and remains unavailable
while the GMSL deserializer relocks to the serial data.
Turning on spread spectrum on the MAX9249 or GMSL
deserializer does not affect the audio data stream.
Changes in the MAX9249 spread settings only affect
the GMSL deserializer MCLK output if it is derived from
RXCLKIN_ (MCLKSRC = 0).
______________________________________________________________________________________ 23
MAX9249
Table 4. CML Driver Strength (Default Level, CMLLVL = 11)
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 6. Spread-Spectrum Rate Limitations
3-CHANNEL MODE
RXCLKIN_ FREQUENCY
(MHz)
4-CHANNEL MODE
RXCLKIN_ FREQUENCY
(MHz)
SERIAL LINK BIT RATE
(Mbps)
AVAILABLE SPREAD
RATES
< 33.3
< 25
< 1000
All rates available
33.3 to < 66.7
20 to < 50
1000 to < 2000
1.5%, 1.0%, 0.5%
≥ 66.7
≥ 50
≥ 2000
0.5%
Table 7. Modulation Coefficients and Maximum SDIV Settings
BUS-WIDTH MODE
4-Channel
3-Channel
SPREAD-SPECTRUM
SETTING (%)
MODULATION COEFFICIENT
(DECIMAL)
SDIV UPPER LIMIT
(DECIMAL)
0.5
104
63
1
104
40
1.5
152
54
2
204
30
3
152
27
4
204
15
0.5
80
63
1
80
52
1.5
112
63
2
152
42
3
112
37
4
152
21
Both devices include a sawtooth divider to control the
spread-modulation rate. Autodetection or manual programming of the RXCLKIN_ operation range guarantees
a spread-spectrum modulation frequency within 20kHz
to 40kHz. Additionally, manual configuration of the
sawtooth divider (SDIV, 0x03 D[5:0]) allows the user to
set a modulation frequency according to the RXCLKIN_
frequency. Always keep the modulation frequency
between 20kHz to 40kHz to ensure proper operation.
Manual Programming of the
Spread-Spectrum Divider
The modulation rate for the MAX9249 relates to the
RXCLKIN_ frequency as follows:
fM=
where:
(1 + DRS)
fRXCLKIN_
MOD × SDIV
fM = Modulation frequency
DRS = DRS pin input value (0 or 1)
fRXCLKIN_ = LVDS clock frequency
MOD = Modulation coefficient given in Table 7
SDIV = 6-bit SDIV setting, manually programmed
by the FC
To program the SDIV setting, first look up the modulation
coefficient according to the part number and desired
bus-width and spread-spectrum settings. Solve the above
equation for SDIV using the desired pixel clock and modulation frequencies. If the calculated SDIV value is larger
than the maximum allowed SDIV value in Table 7, set SDIV
to the maximum value.
Sleep Mode
The MAX9249/GMSL deserializer include low-power
sleep mode to reduce power consumption on the device
not attached to the FC (the GMSL deserializer in LCD
applications and the MAX9249 in camera applications).
Set the corresponding remote IC’s SLEEP bit to 1 to initiate sleep mode. The MAX9249 sleeps immediately after
24
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
CASE
AUTOS
(MAX9249)
MAX9249
POWER-UP
STATE
MS
(GMSL
DESERIALIZER)
GMSL
DESERIALIZER
POWER-UP STATE
LINK STARTUP MODE
1
Low
Serialization
enabled
Low
Normal
(SLEEP = 0)
Both devices power up with serial link active
(autostart)
High
Sleep mode
(SLEEP = 1)
Serial link is disabled and the GMSL
deserializer powers up in sleep mode. Set
SEREN = 1 or CLINKEN = 1 in the MAX9249
to start the serial link and wake up the GMSL
deserializer.
Low
Normal
(SLEEP = 0)
Both devices power up in normal mode with
the serial link disabled. Set SEREN = 1 or
CLINKEN = 1 in the MAX9249 to start the
serial link.
High
Sleep mode
(SLEEP = 1)
GMSL deserializer starts in sleep mode.
Link autostarts upon MAX9249 power-up.
Use this case when the GMSL deserializer
powers up before the MAX9249.
2
3
4
High
Serialization
disabled
High
Serialization
disabled
Low
Serialization
enabled
setting its SLEEP = 1. The GMSL deserializer sleeps after
serial link inactivity or 8ms (whichever arrives first) after
setting its SLEEP = 1. See the Link Startup Procedure
section for details on waking up the device for different
FC and starting conditions.
The FC side device cannot enter into sleep mode. If an
attempt is made to program the FC side device for sleep,
the SLEEP bit remains 0. Use the PWDN input pin to
bring the FC side device into a low-power state.
Configuration Link Mode
The MAX9249 includes a low-speed configuration link to
allow control-data connection between the two devices
in the absence of a valid clock input. In either display or
camera applications, the configuration link can be used
to program equalizer/preemphasis or other registers
before establishing the video link. An internal oscillator
provides RXCLKIN_ for establishing the serial configuration link between the MAX9249 and GMSL deserializer.
Set CLINKEN = 1 on the MAX9249 to turn on the configuration link. The configuration link remains active as
long as the video link has not been enabled. The video
link overrides the configuration link and attempts to lock
when SEREN = 1.
Link Startup Procedure
Table 8 lists four startup cases for video-display applications. Table 9 lists two startup cases for image-sensing
applications. In either video-display or image-sensing
applications, the control link is always available after the
high-speed data link or the configuration link is established and the MAX9249/GMSL deserializer registers or
the peripherals are ready for programming.
Video-Display Applications
For the video-display application, with a remote display
unit, connect the FC to the serializer (MAX9249) and set
CDS = low for both the MAX9249 and GMSL deserializer.
Table 8 summarizes the four startup cases based on the
settings of AUTOS and MS.
Case 1: Autostart Mode
After power-up or when PWDN transitions from low to
high for both the serializer and deserializer, the serial
link establishes if a stable RXCLKIN_ is present. The
MAX9249 locks to RXCLKIN_ and sends the serial data
to the GMSL deserializer. The GMSL deserializer then
detects activity on the serial link and locks to the input
serial data.
______________________________________________________________________________________ 25
MAX9249
Table 8. Startup Selection for Video-Display Applications (CDS = Low)
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
AUTOS PIN
SETTING
LOW
HIGH
CLINKEN = 0 OR
SEREN = 1
SEREN BIT
POWER-UP VALUE
1
0
POWER-DOWN
OR POWER-OFF
CLINKEN = 0 OR
SEREN = 1
PWDN = HIGH,
POWER-ON
POWER-ON
IDLE
AUTOS = LOW
CLINKEN = 1
CONFIG
LINK STARTING
CONFIG LINK
UNLOCKED
CONFIG LINK
OPERATING
CONFIG LINK
PROGRAM
REGISTERS
LOCKED
PWDN = LOW OR
POWER-OFF
ALL STATES
SEREN = 0,
NO RXCLKIN_
SEREN = 1,
RXCLKIN_ RUNNING
PWDN = HIGH
POWER-ON,
AUTOS = LOW
SEREN = 0, OR
NO RXCLKIN_
VIDEO LINK
LOCKED
VIDEO
LINK LOCKING
PRBSEN = 0
VIDEO LINK
OPERATING
PRBSEN = 1
VIDEO LINK
PRBS TEST
VIDEO LINK
UNLOCKED
Figure 23. State Diagram, CDS = Low (LCD Application)
Table 9. Startup Selection for Image-Sensing Applications (CDS = High)
CASE
AUTOS
(MAX9249)
MAX9249 POWER-UP
STATE
GMSL DESERIALIZER
POWER-UP STATE
1
Low
Serialization enabled
Normal
(SLEEP = 0)
Autostart
2
High
Sleep mode
(SLEEP = 1)
Normal
(SLEEP = 0)
MAX9249 is in sleep mode. Wake up the
MAX9249 through the control channel (FC
attached to the GMSL deserializer).
Case 2: Standby Start Mode
After power-up or when PWDN transitions from low to
high for both the serializer and deserializer, the GMSL
deserializer starts up in sleep mode, and the MAX9249
stays in standby mode (does not send serial data). Use
the FC and program the MAX9249 to set SEREN = 1 to
establish a video link or CLINKEN = 1 to establish the
configuration link. After locking to a stable RXCLKIN_ (for
SEREN = 1) or the internal oscillator (for CLINKEN = 1),
the MAX9249 sends a wake-up signal to the deserializer.
The GMSL deserializer exits sleep mode after locking to
the serial data and sets SLEEP = 0. If after 8ms the deserializer does not lock to the input serial data, the GMSL
deserializer goes back to sleep, and the internal sleep bit
remains set (SLEEP = 1).
LINK STARTUP MODE
Case 3: Remote Side Autostart Mode
After power-up or when PWDN transitions from low
to high, the remote device (GMSL deserializer) starts
up and tries to lock to an incoming serial signal with
sufficient power. The host side (MAX9249) is in standby
mode and does not try to establish a link. Use the FC and
program the MAX9249 to set SEREN = 1 (and apply a
stable RXCLKIN_) to establish a video link or CLINKEN
= 1 to establish the configuration link. In this case, the
GMSL deserializer ignores the short wake-up signal sent
from MAX9249.
26
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
SLEEP = 1
FOR > 8ms
SLEEP
REVERSE LINK
CLINKEN = 0 OR
SEREN = 1
CLINKEN = 0 OR
SEREN = 1
WAKE-UP
SLEEP = 0,
SEREN = 0
POWER-ON
IDLE
CLINKEN = 1
CONFIG
LINK STARTED
WAKE-UP SIGNAL
PWDN = HIGH,
POWER-ON,
AUTOS = HIGH
SLEEP = 1
ALL STATES
PWDN = LOW OR
POWER-OFF
POWER-DOWN
OR
POWER-OFF
SLEEP = 0,
SLEEP = 1
PWDN = HIGH,
POWER-ON
AUTOS = LOW
SEREN = 1,
RXCLKIN_ RUNNING
CONFIG LINK
LOCKED
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
SEREN = 0 OR
NO RXCLKIN_
SEREN = 0 OR
NO RXCLKIN_
VIDEO
LINK LOCKING
CONFIG LINK
UNLOCKED
VIDEO LINK
LOCKED
PRBSEN = 0
VIDEO LINK
OPERATING
PRBSEN = 1
VIDEO LINK
PRBS TEST
VIDEO LINK
UNLOCKED
Figure 24. State Diagram, CDS = High (Camera Application)
Case 4: Remote Side in Sleep Mode
After power-up or when PWDN transitions from low to
high, the remote device (GMSL deserializer) starts up in
sleep mode. The high-speed link establishes automatically after MAX9249 powers up with a stable RXCLKIN_
and sends a wake-up signal to the GMSL deserializer.
Use this mode in applications where the GMSL deserializer powers up before the MAX9249.
Image-Sensing Applications
For image-sensing applications, connect the FC to the
GMSL deserializer and set CDS = high for both the
MAX9249 and GMSL deserializer. The GMSL deserializer powers up normally (SLEEP = 0) and continuously
tries to lock to a valid serial input. Table 9 summarizes
both startup cases, based on the state of the MAX9249
AUTOS pin.
Case 1: Autostart Mode
After power-up, or when PWDN transitions from low to
high, the MAX9249 locks to a stable RXCLKIN_ and
sends the high-speed data to the GMSL deserializer. The
GMSL deserializer locks to the serial data and outputs
the video data and clock.
Case 2: Sleep Mode
After power-up or when PWDN transitions from low to
high, the MAX9249 starts up in sleep mode. To wake up
the MAX9249, use the FC to send a GMSL protocol UART
frame containing at least three rising edges (e.g., 0x66),
at a bit rate no greater than 1Mbps. The low-power wakeup receiver of the MAX9249 detects the wake-up frame
over the reverse control channel and powers up. Reset
the sleep bit (SLEEP = 0) of the MAX9249 using a regular
control channel write packet to power up the device fully.
Send the sleep bit write packet at least 500Fs after the
wake-up frame. The MAX9249 goes back to sleep mode
if its sleep bit is not cleared within 5ms (min) after detecting a wake-up frame.
Applications Information
Self-PRBS Test
The MAX9249/GMSL deserializer link includes a PRBS
pattern generator and bit-error verification function. Set
PRBSEN =1 (0x04 D5) first in the MAX9249 and then the
GMSL deserializer to start the PRBS test. Set PRBSEN
=0 (0x04 D5) first in the GMSL deserializer and then the
MAX9249 to exit the PRBS self-test. The GMSL deserializer uses an 8-bit register (0x0E) to count the number of
detected errors. The control link also controls the start
and stop of the error counting. During PRBS mode, the
device does not count decoding errors and the GMSL
deserializer ERR output reflects PRBS errors only. Refer
to the respective GMSL deserializer data sheet for more
details.
______________________________________________________________________________________ 27
MAX9249
POWER-UP VALUE
SEREN
SLEEP
1
0
0
1
AUTOS PIN
SETTING
LOW
HIGH
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Microcontrollers on Both Sides of the
GMSL Link (Dual µC Control)
Usually the microcontroller is either on the serializer
(MAX9249) side for video-display applications or on the
deserializer side for image-sensing applications. For the
former case, both the CDS pins of the MAX9249/GMSL
deserializer are set to low, and for the latter case, the
CDS pins are set to high. However, if the CDS pin of the
MAX9249 is low and the same pin of the GMSL deserializer is high, then the MAX9249/GMSL deserializer
connect to both FCs simultaneously. In such a case, the
FCs on either side can communicate with the MAX9249/
GMSL deserializer.
Contentions of the control link can happen if the FCs
on both sides are using the link at the same time. The
MAX9249/GMSL deserializer do not provide the solution
for contention avoidance. The serializer/deserializer do
not send an acknowledge frame when communication
fails due to contention. Users can always implement a
higher layer protocol to avoid the contention. In addition, if UART communication across the serial link is not
required, the FCs can disable the forward and reverse
control channel through the REVCCEN and FWDCCEN
bits (0x04 D[1:0]) in the MAX9249/GMSL deserializer.
UART communication across the serial link is stopped
and contention between FCs no longer occurs. During
dual FCs operation, if one of the CDS pins on either side
changes state, the link resumes the corresponding state
described in the Link Startup Procedure section.
As an example of dual FC use in an image-sensing application, the MAX9249 can be in sleep mode and waiting
for wake-up by the GMSL deserializer. After wake-up, the
serializer-side FC sets the MAX9249 CDS pin low and
assumes master control of the MAX9249 registers.
Jitter-Filtering PLL
In some applications, the input clock to the MAX9249
(RXCLKIN_) includes jitter that reduces link reliability.
The MAX9249 has a programmable narrow-band jitterfiltering PLL to attenuate frequency components outside
the PLL’s bandwidth (< 100kHz, typ). Enable the jitterfiltering PLL by setting DISFPLL = 0 (0x05 D6).
Changing the Clock Frequency
Both the video clock rate (fRXCLKIN_) and the controlchannel clock rate (fUART) can be changed on-the-fly
to support applications with multiple clock speeds. It is
recommended to enable the serial link after RXCLKIN_
stabilizes. Stop RXCLKIN_ for 5Fs and restart the serial
link or toggle SEREN after each change in the RXCLKIN_
frequency to recalibrate any automatic settings if a clean
frequency change cannot be guaranteed. The reverse
control channel remains unavailable for 350Fs after serial
link start or stop. Limit on-the-fly changes in fUART to factors of less than 3.5 at a time to ensure that the device
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps and then at 100kbps to have
reduction ratios of 3 and 3.333, respectively.
LOCK Output Loopback
For quick loss-of-lock notification, the GMSL deserializer
can loop back its LOCK output to the MAX9249 using
the INT signal. Connect the LOCK output to the INT
input of the GMSL deserializer. The interrupt output on
the MAX9249 follows the transitions at the LOCK output
of the GMSL deserializer. Reverse control-channel communication does not require an active forward link to
operate and accurately tracks the LOCK status of the
video link. LOCK asserts for video link only and not for
the configuration link.
Line-Fault Detection
The line-fault detector in the MAX9249 monitors for line
failures such as short to ground, short to power supply,
and open link for system fault diagnosis. Figure 3 shows
the required external resistor connections. LFLT = low
when a line fault is detected and LFLT = high when the
line returns to normal. The line-fault type is stored in
0x08 D[3:0] of the MAX9249. The fault-detector threshold voltages are referenced to the MAX9249 ground.
Additional passive components set the DC level of the
cable (Figure 3). If the MAX9249 and GMSL deserializer
grounds are different, the link DC voltage during normal
operation can vary and cross one of the fault-detection
thresholds. For the fault-detection circuit, select the
resistor’s power rating to handle a short to the battery
and use surface-mount resistors with small case size to
minimize parasitic effects to the high-speed signal. Table
10 lists the mapping for line-fault types.
28
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
REGISTER
ADDRESS
BITS
D[3:2]
NAME
LFNEG
0x08
D[1:0]
LFPOS
VALUE
LINE-FAULT TYPE
00
Negative cable wire shorted to battery
01
Negative cable wire shorted to ground
10
Normal operation
11
Negative cable wire open
00
Positive cable wire shorted to battery
01
Positive cable wire shorted to ground
10
Normal operation
11
Positive cable wire open
Choosing I2C/UART Pullup Resistors
Both I2C/UART open-drain lines require pullup resistors to provide a logic-high level. There are trade-offs
between power dissipation and speed, and a compromise made in choosing pullup resistor values. Every
device connected to the bus introduces some capacitance even when the device is not in operation. I2C
specifies 300ns rise times to go from low to high (30% to
70%) for fast mode, which is defined for data rates up to
400kbps (see the I2C specifications in the AC Electrical
Characteristics section for details). To meet the fastmode rise-time requirement, choose the pullup resistors
so that rise time tR = 0.85 x RPULLUP x CBUS < 300ns.
The waveforms are not recognized if the transition time
becomes too slow. The MAX9249 supports I2C/UART
rates up to 1Mbps.
AC-Coupling
AC-coupling isolates the receiver from DC voltages up
to the voltage rating of the capacitor. Four capacitors—
two at the serializer output and two at the deserializer
input—are needed for proper link operation and to provide protection if either end of the cable is shorted to a
high voltage. AC-coupling blocks low-frequency ground
shifts and low-frequency common-mode noise.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition time
is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an
AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for an
AC-coupled link consists of the CML receiver termination
resistor (RTR), the CML driver termination resistor (RTD),
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
(RTD + RTR))/4. RTD and RTR are required to match the
transmission line impedance (usually 100I). This leaves
the capacitor selection to change the system time constant. Use at least 0.2FF high-frequency surface-mount
ceramic capacitors, with sufficient voltage rating to withstand a short to battery, to pass the lower speed reverse
control-channel signal. Use capacitors with a case size
less than 3.2mm x 1.6mm to have lower parasitic effects
to the high-speed signal.
Power-Supply Circuits and Bypassing
The MAX9249 uses a VAVDD and VDVDD of 1.7V to
1.9V, and a VLVDSVDD of 3.0V to 3.6V. All single-ended
inputs and outputs on the MAX9249 derive power from a
VIOVDD of 1.7V to 3.6V, which scale with IOVDD. Proper
voltage-supply bypassing is essential for high-frequency
circuit stability.
Cables and Connectors
Interconnect for CML typically has a differential impedance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables tend to generate less EMI due to magnetic-field
canceling effects. Balanced cables pick up noise as
common mode rejected by the CML receiver. Table 11
lists the suggested cables and connectors used in the
GMSL link.
______________________________________________________________________________________ 29
MAX9249
Table 10. Line-Fault Mapping
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 11. Suggested Connectors and Cables for GMSL
VENDOR
JAE Electronics, Inc.
Nissei Electric Co., Ltd.
Rosenberger Hochfrequenztechnik GmbH
CONNECTOR
CABLE
MX38-FF
A-BW-Lxxxxx
GT11L-2S
F-2WME AWG28
D4S10A-40ML5-Z
Dacar 538
Board Layout
Separate the digital signals and CML/LVDS high-speed
signals to prevent crosstalk. Use a four-layer PCB with
separate layers for power, ground, CML/LVDS, and
digital signals. Layout PCB traces close to each other
for a 100I differential characteristic impedance. The
trace dimensions depend on the type of trace used
(microstrip or stripline). Note that two 50I PCB traces
do not have 100I differential impedance when brought
close together—the impedance goes down when the
traces are brought closer.
Route the PCB traces for a CML/LVDS channel (there
are two conductors per CML/LVDS channel) in parallel to
maintain the differential characteristic impedance. Avoid
vias. Keep PCB traces that make up a differential pair
equal length to avoid skew within the differential pair.
ESD Protection
The MAX9249 ESD tolerance is rated for Human Body
Model, IEC 61000-4-2, and ISO 10605. The ISO 10605
and IEC 61000-4-2 standards specify ESD tolerance for
electronic systems. CML/LVDS I/O are tested for ISO
10605 ESD protection and IEC 61000-4-2 ESD protection. All pins are tested for the Human Body Model. The
Human Body Model discharge components are CS =
100pF and RD = 1.5kI (Figure 25). The IEC 61000-4-2
discharge components are CS = 150pF and RD = 330I
(Figure 26). The ISO 10605 discharge components are
CS = 330pF and RD = 2kI (Figure 27).
1MI
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
100pF
RD
1.5kI
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 25. Human Body Model ESD Test Circuit
RD
330I
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
150pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 26. IEC 61000-4-2 Contact Discharge ESD Test Circuit
RD
2kI
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
330pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 27. ISO 10605 Contact Discharge ESD Test Circuit
30
�������������������������������������������������������������������������������������
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
REGISTER
ADDRESS
0x00
0x01
BITS
NAME
VALUE
D[7:1]
SERID
XXXXXXX
D0
—
0
D[7:1]
DESID
XXXXXXX
D0
—
0
D[7:5]
SS
0x02
D4
D[3:2]
D[1:0]
D[7:6]
AUDIOEN
PRNG
SRNG
Reserved
Deserializer device address
Reserved
No spread spectrum. Power-up default when
SSEN = low.
001
Q0.5% spread spectrum. Power-up default when
SSEN = high.
010
Q1.5% spread spectrum
011
Q2% spread spectrum
100
No spread spectrum
101
Q1% spread spectrum
110
Q3% spread spectrum
111
Q4% spread spectrum
0
Disable I2S channel
1
Enable I2S channel
00
12.5MHz to 25MHz pixel clock
01
25MHz to 50MHz pixel clock
10
50MHz to 104MHz pixel clock
11
Automatically detect the pixel clock range
00
0.5 to 1Gbps serial-bit rate
01
1 to 2Gps serial-bit rate
10
2 to 3.125Gbps serial-bit rate
11
Automatically detect serial-bit rate
00
Calibrate spread-modulation rate only once after
locking
01
Calibrate spread-modulation rate every 2ms after
locking
10
Calibrate spread-modulation rate every 16ms after
locking
11
Calibrate spread-modulation rate every 256ms
after locking
AUTOFM
SDIV
Serializer device address
000
0x03
D[5:0]
FUNCTION
000000
Autocalibrate sawtooth divider
XXXXXX
Manual SDIV setting. See the Manual
Programming of the Spread-Spectrum Divider
section.
DEFAULT
VALUE
1000000
0
1001000
0
000, 001
1
11
11
00
000000
______________________________________________________________________________________ 31
MAX9249
Table 12. Register Table (See Table 1 for Default Value Details)
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 12. Register Table (See Table 1 for Default Value Details) (continued)
REGISTER
ADDRESS
BITS
D7
0x04
NAME
CLINKEN
D5
PRBSEN
D[3:2]
FUNCTION
0
Disable serial link. Power-up default when
AUTOS = high. Reverse control-channel communication remains unavailable for 350Fs after the
MAX9249 starts/stops the serial link.
1
Enable serial link. Power-up default when
AUTOS = low. Reverse control-channel communication remains unavailable for 350Fs after the
MAX9249 starts/stops the serial link.
0
Disable configuration link
1
Enable configuration link
0
Disable PRBS test
1
Enable PRBS test
0
Normal mode. Default value depends on CDS and
AUTOS pin values at power-up.
1
Activate sleep mode. Default value depends on
CDS and AUTOS pin values at power-up.
00
Base mode uses I2C peripheral interface
01
Base mode uses UART peripheral interface
SEREN
D6
D4
VALUE
SLEEP
INTTYPE
10, 11
D1
D0
Disable reverse control channel from deserializer
(receiving)
1
Enable reverse control channel from deserializer
(receiving)
0
Disable forward control channel to deserializer
(sending)
1
Enable forward control channel to deserializer
(sending)
FWDCCEN
0, 1
0
0
0, 1
00
Base mode peripheral interface disabled
0
REVCCEN
DEFAULT
VALUE
32
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1
1
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
REGISTER
ADDRESS
BITS
NAME
D7
I2CMETHOD
D6
DISFPLL
D[5:4]
CMLLVL
0x05
D[3:0]
PREEMP
VALUE
FUNCTION
0
I2C conversion sends the register address
1
Disable sending of I2C register address
(command-byte-only mode)
0
Filter PLL active
1
Filter PLL disabled
00
Do not use
01
200mV CML signal level
10
300mV CML signal level
11
400mV CML signal level
0000
Preemphasis off
0001
-1.2dB preemphasis
0010
-2.5dB preemphasis
0011
-4.1dB preemphasis
0100
-6.0dB preemphasis
0101
Do not use
0110
Do not use
0111
Do not use
1000
1.1dB preemphasis
1001
2.2dB preemphasis
1010
3.3dB preemphasis
1011
4.4dB preemphasis
1100
6.0dB preemphasis
1101
8.0dB preemphasis
1110
10.5dB preemphasis
1111
14.0dB preemphasis
DEFAULT
VALUE
0
1
11
0000
0x06
D[7:0]
—
01000000
Reserved
01000000
0x07
D[7:0]
—
00100010
Reserved
00100010
D[7:4]
—
0000
Reserved
0000
(read only)
D[3:2]
LFNEG
0x08
0x0C
D[1:0]
LFPOS
D[7:0]
—
00
Negative cable wire shorted to battery
01
Negative cable wire shorted to ground
10
Normal operation
11
Negative cable wire open
00
Positive cable wire shorted to battery
01
Positive cable wire shorted to ground
10
Normal operation
11
Positive cable wire open
01110000
Reserved
10
(read only)
10
(read only)
01110000
______________________________________________________________________________________ 33
MAX9249
Table 12. Register Table (See Table 1 for Default Value Details) (continued)
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 12. Register Table (See Table 1 for Default Value Details) (continued)
REGISTER
ADDRESS
BITS
NAME
D7
SETINT
D[6:5]
—
D4
DISRES
0x0D
D[3:0]
0x1E
0x1F
SKEWADJ
VALUE
FUNCTION
0
Set INT low when SETINT transitions from 1 to 0
1
Set INT high when SETINT transitions from 0 to 1
00
Reserved
0
RES (LVDS interface) mapped to DIN27
1
CNTL1 mapped to DIN27
0000
Adjust x7 PLL clock skew + 50ps
0001
Adjust x7 PLL clock skew + 100ps
0010
Adjust x7 PLL clock skew + 200ps
0011
Adjust x7 PLL clock skew + 250ps
0100
Adjust x7 PLL clock skew + 300ps
0101
Adjust x7 PLL clock skew + 350ps
0110
Adjust x7 PLL clock skew + 400ps
0111
Do not use
1000
Adjust x7 PLL clock skew - 50ps
1001
Adjust x7 PLL clock skew - 100ps
1010
Adjust x7 PLL clock skew - 200ps
1011
Adjust x7 PLL clock skew - 250ps
1100
Adjust x7 PLL clock skew - 300ps
1101
Adjust x7 PLL clock skew - 350ps
1110
Adjust x7 PLL clock skew - 400ps
1111
No x7PLL clock skew adjustment
DEFAULT
VALUE
0
00
0
1111
Device identifier
(MAX9249 = 0x03)
00000011
(read only)
0000
Reserved
0000
(read only)
XXXX
Device revision
(read only)
D[7:0]
ID
00000011
D[7:4]
—
D[3:0]
REVISION
X = Don’t care.
34
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Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
1.8V
TXCLK+/-
RXCLKIN+/-
TX0+/TO TX2+/-
RXIN0+/TO RXIN2+/CDS
AUTOS
GPU
PCLKOUT
45kI
45kI
PCLK
DOUT[20.0]
RGB
HSYNC
CDS
VSYNC
LMN1
DE
LMN0
MAX9260
ECU
5kI
5kI
DISPLAY
MAX9249
UART
Tx
RX/SDA
TX/SCL
Rx
IN+
OUT-
IN-
INT
RX/SDA
TX/SCL
OUT+
50kI
LFLT
INT
MS
LFLT
INT
MS
TO PERIPHERALS
50kI
SCL
SDA
WS
LOCK
WS
SCK
AUDIO
WS
SCK
SD
MAX9850
SD
WS
SCK
SD/CNTLO
SCK
SD
MCLK
MAX9491
X1
CLK_OUT
VIDEO-DISPLAY APPLICATION
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
48 TQFP-EP
C48E+8
21-0065
90-0138
______________________________________________________________________________________ 35
MAX9249
Typical Application Circuit
MAX9249
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Revision History
REVISION
NUMBER
REVISION
DATE
0
1/10
Initial release
1
3/10
Improved yield
2, 3
2
5/10
Added soldering temperature (reflow) to the Absolute Maximum Ratings section and
corrected spread-spectrum modulation settings in Table 7
2, 24
3
1/11
Added Patent Pending to Features
1
4
1/12
Corrected GND to AGND in Absolute Maximum Ratings
2
DESCRIPTION
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
36
©
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
Mouser Electronics
Authorized Distributor
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