19-4159; Rev 1; 10/08
KIT
ATION
EVALU
E
L
B
AVAILA
Low-Power Audio/Video Interface
for Single SCART Connectors
Features
The MAX9597 single SCART interface routes audio and
video signals between a set-top box decoder chip and
an external SCART connector under I 2 C control.
Operating from a 3.3V supply and a 12V supply, the
MAX9597 consumes 53mW during quiescent operation
and 254mW during average operation when driving
typical signals into typical loads.
The MAX9597 audio section contains left and right audio
paths with an independent operational amplifier at the
inputs. The DirectDrive ® output amplifiers create a
2VRMS full-scale audio signal biased around ground,
eliminating the need for bulky output capacitors and
reducing click-and-pop noise. The zero-cross detection
circuitry also further reduces clicks and pops by
enabling audio sources to switch only during a zerocrossing.
The MAX9597 video section contains 4 channels of
video filter amplifiers. The standard-definition video signals from the set-top box decoder chip are lowpass filtered to remove out-of-bandwidth artifacts. The
MAX9597 also supports slow-switching and fast-switching signals.
The MAX9597 is available in a compact 28-pin thin
QFN package and is specified over the 0°C to +70°C
commercial temperature range.
♦ 53mW Quiescent Power Consumption
♦ 5µW Shutdown Consumption
♦ Audio Operational Amplifiers to Create Input
Filters
♦ Clickless/Popless, DirectDrive Audio
♦ Video Reconstruction Filter with 10MHz Passband
and 43dB Attenuation at 27MHz
♦ 3.3V and 12V Supply Voltages
Ordering Information
PART
TEMP RANGE
MAX9597CTI+
0°C to +70°C
PIN-PACKAGE
28 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
Applications
Set-Top Boxes
TVs
AV Receivers
DVD Players
DirectDrive is a registered trademark of Maxim Integrated
Products, Inc.
System Block Diagram
V12
12V
VAUD
3.3V
MAX9597
STB CHIP
µC
VID
3.3V
I2C INTERFACE
AND REGISTERS
I2C
RGB, Y/C, CVBS
L/R AUDIO
VIDEO FILTERS
VIDEO
ENCODER
STEREO
AUDIO
DAC
TV
SCART
FAST AND SLOW SWITCHING
RGB, Y/C, CVBS
AUDIO
WITH DirectDrive
OUTPUTS
SINGLE OR
DIFFERENTIAL
STEREO AUDIO
SLOW SWITCHING
FAST SWITCHING
CHARGE PUMP
EP
GND
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX9597
General Description
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
VVID ..........................................................................-0.3V to +4V
V12 to EP ................................................................-0.3V to +14V
VAUD to EP ...............................................................-0.3V to +4V
EP to GND .............................................................-0.1V to +0.1V
All Video Inputs .......................................................-0.3V to +4V
All Audio Inputs to EP .............................(VEP - 1)V to (VEP + 1)V
SDA, SCL, DEV_ADDR ............................................-0.3V to +4V
TV_SS_OUT .................................................-0.3V to (V12 + 0.3V)
Current
All Video/Audio Inputs ..................................................±20mA
C1P, C1N, CPVSS ........................................................±50mA
Output Short-Circuit Current Duration
All Video Outputs, TV_FS_OUT to VVID, GND........Continuous
Audio Outputs to VAUD, EP ....................................Continuous
TV_SS_OUT to V12, EP...........................................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin Thin QFN
(derate 21.3mW/°C above +70°C) ...........................1702mW
Operating Temperature Range ..............................0°C to +70°C
Junction Temperature .....................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Video Supply Voltage Range
VVID
Inferred from video PSRR test at 3.0V and
3.6V
3.0
3.3
3.6
V
Audio Supply Voltage Range
VAUD
Inferred from audio PSRR tests at 3.0V and
3.6V
3.0
3.3
3.6
V
11.4
12
12.6
V
Slow-Switching Supply Voltage
Range
V12
Inferred from slow-switching levels
VVID Quiescent Supply Current
IVID_Q
Normal operation, all video output
amplifiers are enabled
13
20
mA
Shutdown
1
10
µA
VAUD Quiescent Supply Current
V12 Quiescent Supply Current
IAUD_Q
I12_Q
Normal operation
3
4.1
mA
Shutdown
0.01
10
µA
Normal operation
1.5
100
Shutdown
0.1
10
µA
VIDEO CHARACTERISTICS
DC-COUPLED INPUT
Input Voltage Range
VIN
Input Current
IIN
Input Resistance
RIN
RL = 75Ω to GND or
150Ω to VVID/2,
inferred from gain test
VVID = 3V
1.15
VVID = 3.135V
1.2
VVID = 3.3V
VP-P
1.3
VIN = GND
2
3
300
µA
kΩ
AC-COUPLED INPUT
Sync-Tip Clamp Level
VCLP
Sync-tip clamp
Sync Crush
Sync-tip clamp; percentage reduction in
sync pulse (0.3VP-P); guaranteed by input
clamping current measurement
Input Clamping Current
Sync-tip clamp
2
-5
0
2
_______________________________________________________________________________________
6.1
mV
2
%
3
µA
Low-Power Audio/Video Interface
for Single SCART Connectors
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
Max Input Source Resistance
Bias Voltage
TYP
MAX
VBIAS
Input Resistance
Bias circuit
0.57
Bias circuit
0.6
UNITS
Ω
300
0.63
10
V
kΩ
DC CHARACTERISTICS
VVID = 3V,
VIN = VCLP to
(VCLP + 1.15V)
DC Voltage Gain
AV
RL = 75Ω
to GND
or
RL = 150Ω
to VVID/2
VVID = 3.135V,
VIN = VCLP to
(VCLP + 1.2V)
Output Level
Output Voltage Swing
1.93
2
2.05
V/V
VVID = 3V,
VIN = (VBIAS - 0.575V)
to (VBIAS + 0.575V)
VVID = 3.135V
VIN = (VBIAS - 0.6V)
to (VBIAS + 0.6V)
DC Gain Mismatch
2
2
1.93
2
2.05
Guaranteed by DC voltage gain
-2
Sync-tip clamp
0.2
0.30
0.4
Bias circuit
1.38
1.5
1.62
Sync-tip clamp, measured at
output, VVID = 3V, VIN = VCLP
to (VCLP + 1.15V), RL = 75Ω
to GND or RL = 150Ω to
VVID/2
Measured at output, VVID =
3.135V, VIN = VCLP to (VCLP
+ 1.2V), RL = 75Ω to GND or
Guaranteed RL = 150Ω to VVID/2
by DC
Bias circuit, measured at
voltage gain output, VVID = 3V, VIN =
(VBIAS - 0.575V) to (VBIAS +
0.575V), RL = 75Ω to GND or
RL = 150Ω to VVID/2
Measured at output, VVID =
3.135V, VIN = (VBIAS - 0.6V)
to (VBIAS + 0.6V), RL = 75Ω
to GND or RL = 150Ω to
VVID/2
+2
2.316
2.4
2.46
VP-P
2.3
2.316
2.4
2.46
100
Output disabled
Power-Supply Rejection Ratio
3.0V ≤ VVID ≤ 3.6V
V
2.3
Output Short-Circuit Current
Output Leakage Current
%
0.02
50
75
mA
10
µA
dB
_______________________________________________________________________________________
3
MAX9597
ELECTRICAL CHARACTERISTICS (continued)
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS
Filter Passband Flatness
VOUT = 2VP-P, f = 100kHz to 10MHz
VOUT = 2VP-P,
attenuation is
referred to 100kHz
Filter Attenuation
1
f = 11MHz
3
f = 27MHz
43
f = 54MHz
dB
dB
63
Differential Gain
DG
5-step modulated staircase, f = 4.43MHz
0.2
%
Differential Phase
DP
5-step modulated staircase, f = 4.43MHz
0.3
Degrees
2T Pulse-to-Bar K Rating
2T = 200ns; bar time is 18µs; the beginning
2.5% and the ending 2.5% of the bar time is
ignored
0.5
K%
2T Pulse Response
2T = 200ns
0.5
K%
2T Bar Response
2T = 200ns; bar time is 18µs; the beginning
2.5% and the ending 2.5% of the bar time is
ignored
0.5
K%
Nonlinearity
5-step staircase
0.5
%
Group Delay Distortion
100kHz ≤ f ≤ 5MHz, outputs are 2VP-P
3.5
ns
Peak Signal to RMS Noise
100kHz ≤ f ≤ 5MHz
60
dB
Power-Supply Rejection Ratio
f = 100kHz, 100mVP-P
47
dB
Output Impedance
f = 5MHz
Video Crosstalk
f = 4.43MHz
5.5
Ω
-68.5
dB
AUDIO CHARACTERISTICS OUTPUT AMPLIFIER (Note 2)
Voltage Gain
3.95
Gain Mismatch
-1.5
4
4.05
+1.5
V/V
%
Flatness
f = 20Hz to 20kHz, 0.25VRMS input
0.01
dB
Frequency Bandwidth
0.25VRMS input, frequency where output is
-3dB referenced to 1kHz
205
kHz
Capacitive Drive
No sustained oscillations, 75Ω series
resistor on output
300
pF
Input Signal Amplitude
f = 1kHz, THD < 1%
0.5
VRMS
Output DC Level
Power-Supply Rejection Ratio
No input signal, VIN = 0V
-3
DC
75
f = 1kHz
+3
110
91
dB
Signal-to-Noise Ratio
f = 1kHz, 0.25VRMS input, 20Hz to 20kHz
Total Harmonic Distortion Plus
Noise
RL = 3.33kΩ,
f = 1kHz
Output Impedance
f = 1kHz
0.28
Ω
Mute Suppression
f = 1kHz, 0.25VRMS input
101
dB
Audio Crosstalk
f = 1kHz, 0.25VRMS input
100
dB
4
97
mV
0.25VRMS input
0.0011
0.5VRMS input
0.0021
_______________________________________________________________________________________
dB
%
Low-Power Audio/Video Interface
for Single SCART Connectors
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VIDEO TO AUDIO INTERACTION
Crosstalk
Video input: f = 15kHz, 1VP-P signal
100
Audio input: f = 15kHz, 0.1VRMS signal
102
dB
INPUT AMPLIFIER OPEN-LOOP CHARACTERISTICS
Input Offset Voltage
Input Bias Current
VOS
VCM = 0V
TA = +25°C
25
TA = 0°C to +70°C
100
225
µV
IB
VCM = 0V
100
550
nA
Input Offset Current
IOS
VCM = 0V
1.5
30
nA
Common-Mode Input Voltage
Range
VCM
Inferred from CMRR test
+0.707
V
Common-Mode Rejection Ratio
CMRR
Power-Supply Rejection Ratio
PSRR
Large-Signal Voltage Gain
AVOL
Output Voltage Swing
VOUT
Gain-Bandwidth Product
-0.707
80
100
dB
VCM = 0V
90
125
dB
VCM = 0V, -0.8V ≤ VOUT ≤ +0.8V
60
80
dB
RL = 124Ω, inferred from AVOL test
1.6
VP-P
GBWP
8.25
Slew Rate
SR
1.24
V/µs
Input Voltage-Noise Density
VN
f = 1kHz
13.5
nV/√Hz
Input Current-Noise Density
IN
f = 1kHz
0.2
pA/√Hz
AVCL = 1V/V, no sustained oscillation
20
pF
580
kHz
Capacitive Load Stability
MHz
CHARGE PUMP
Switching Frequency
FAST SWITCHING
Output Low Voltage
IOL = 0.5mA
Output High Voltage
IOH = 0.5mA
0.003
VVID 0.1
Output Resistance
0.1
V
VVID 0.003
V
5.5
Ω
Rise Time
RL = 143Ω to GND
2
ns
Fall Time
RL = 143Ω to GND
2
ns
SLOW SWITCHING
Output Low Voltage
10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V
Output Medium Voltage
10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V
5
Output High Voltage
10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V
10
Input Current
1.5
-1
6.5
V
V
V
+1
µA
DIGITAL INTERFACE (SDA, SCL)
Input High Voltage
VIH
0.7 x
VVID
V
_______________________________________________________________________________________
5
MAX9597
ELECTRICAL CHARACTERISTICS (continued)
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
Input Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
VIL
Input Hysteresis
VHYS
Input Leakage Current
IIH, IIL
MAX
UNITS
0.3 x
VVID
V
0.05 x
VVID
SCL and SDA have 40kΩ pullup resistors to
VVID
V
-1
Input Capacitance
+1
10
Input Current
VVIDMAX = 3.6V
0.1VVID < SDA < 0.9VVIDMAX
0.1VVID < SCL < 0.9VVIDMAX
I/O pins of fast-mode devices must not
obstruct the SDA and SCL lines if VVID is
switched off
ISINK = 6mA
µA
pF
-10
+10
µA
0.4
V
400
kHz
Output Low Voltage SDA
VOL
Serial-Clock Frequency
fSCL
0
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
µs
Hold Time, (REPEATED) START
Condition
tHD, STA
0.6
µs
Low Period of the SCL Clock
tLOW
1.3
µs
High Period of the SCL Clock
tHIGH
0.6
µs
Setup Time for a REPEATED
START Condition
tSU, STA
0.6
µs
Data Hold Time
tHD, DAT
Data Setup Time
tHD, DAT
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Pulse Width of Spike Suppressed
tF
A master device must provide a hold time of
at least 300ns for the SDA signal (referred
to VIL of the SCL signal) to bridge the
undefined region of SCL’s falling edge
0.9
100
CB = total capacitance of one bus line in pF
< 400pF; tR and tF measured between
0.3VVID and 0.7VVID (CB is in pF)
tSU, STO
tSP
0
ns
250
ns
0.6
Input filters on the SDA and SCL inputs
suppress noise spikes less than 50ns
µs
0
µs
50
ns
0.3 x
VVID
V
OTHER DIGITAL I/O
DEV_ADDR Low Level
DEV_ADDR High Level
DEV_ADDR Input Current
0.7 x
VVID
-1
V
+1
µA
Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by design for TA = 0°C to +70°C as specified.
Note 2: Input operational amplifier configured in voltage follower configuration, unless otherwise noted.
6
_______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
0
-3
-4
-5
-7
-8
1M
10M
FREQUENCY (Hz)
VIDEO LARGE-SIGNAL GAIN FLATNESS
vs. FREQUENCY
VIDEO CROSSTALK vs. FREQUENCY
2
VOUT = 2VP-P
1
0
100k
100M
0
VOUT = 2VP-P
-10
100k
100M
100
-3
-4
-5
-30
-40
-50
80
-7
-70
-8
-80
100k
1M
10M
FREQUENCY (Hz)
0
-20
-25
-30
-35
100M
100k
1M
10M
FREQUENCY (Hz)
3.5
MAX9597 toc08
2.02
100M
VIDEO OUTPUT VOLTAGE
vs. INPUT VOLTAGE
3.0
OUTPUT VOLTAGE (V)
-15
1M
10M
FREQUENCY (Hz)
2.03
VOLTAGE GAIN (V/V)
-10
40
VOLTAGE GAIN
vs. TEMPERATURE
MAX9597 toc07
0
50
10
VIDEO POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
-5
60
20
100k
100M
70
30
-60
-6
VOUT = 2VP-P
90
GROUP DELAY (ns)
CROSSTALK (dB)
-2
100M
VIDEO GROUP DELAY DISTORTION
vs. FREQUENCY
-20
-1
1M
10M
FREQUENCY (Hz)
2.01
2.00
1.99
MAX9597 toc09
10M
MAX9597 toc04
1M
MAX9597 toc05
FREQUENCY (Hz)
100k
-15
-20
-25
-30
-35
-40
-45
-50
-6
-45
-50
VOUT = 2VP-P
-10
-2
GAIN (dB)
GAIN (dB)
GAIN (dB)
-15
-20
-25
-30
-35
-40
PSRR (dB)
10
5
0
-5
-1
-10
GAIN (dB)
VOUT = 100mVP-P
1
MAX9597 toc03
2
MAX9597 toc02
VOUT = 100mVP-P
MAX9597 toc01
10
5
0
-5
VIDEO LARGE-SIGNAL GAIN
vs. FREQUENCY
VIDEO SMALL-SIGNAL GAIN FLATNESS
vs. FREQUENCY
MAX9597 toc06
VIDEO SMALL-SIGNAL GAIN
vs. FREQUENCY
2.5
2.0
1.5
1.0
0.5
-40
1.98
0
-45
-50
-0.5
1.97
100k
1M
10M
FREQUENCY (Hz)
100M
0
25
50
TEMPERATURE (°C)
75
-0.2
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
INPUT VOLTAGE (V)
_______________________________________________________________________________________
7
MAX9597
Typical Operating Characteristics
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, video load is 150Ω to GND, audio load is 10kΩ to GND, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, video load is 150Ω to GND, audio load is 10kΩ to GND, TA = +25°C, unless otherwise noted.)
0
1
2
3
4
12.5T RESPONSE
MAX9597 toc11
INPUT
200mV/div
INPUT
200mV/div
5
OUTPUT
400mV/div
1
2
3
4
100ns/div
400ns/div
VIDEO OUTPUT BIAS VOLTAGE
vs. TEMPERATURE
AUDIO LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
5
MAX9597 toc13
OUTPUT
1V/div
10
MAX9597 toc14
1.476
VIN = 0.25VRMS
RL = 10kΩ
5
0
GAIN (dB)
VIDEO OUTPUT BIAS VOLTAGE (V)
1.480
INPUT
0.5V/div
OUTPUT
400mV/div
1.472
1.468
-5
-10
1.464
-15
-20
1.460
10µs/div
0
25
50
10
75
100
RL = 3.3kΩ
0
MAX9597 toc17
-20
0.1
MAX9597 toc16
VIN = 0.25VRMS
RL = 10kΩ
PSRR (dB)
VIN = 0.25VRMS
0.001
-80
1M
VAUD = 3.3V + 100mVP-P
-40
THD+N (%)
-60
100k
-20
0.01
-40
10k
VAUD POWER-SUPPLY REJECTION RATIO
(INPUT REFERRED) vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
AUDIO CROSSTALK
vs. FREQUENCY
1k
FREQUENCY (Hz)
TEMPERATURE (°C)
0
MAX9597 toc15
0
PAL VIDEO TEST SIGNAL
-60
-80
VIN = 0.5VRMS
-100
-100
-120
0.0001
-120
100
1k
10k
FREQUENCY (Hz)
8
MAX9597 toc12
MAX9597 toc18
0.8
0.6
0.4
0.2
0
-0.2
-0.4
2T RESPONSE
MAX9597 toc10
DIFFERENTIAL GAIN (%)
DIFFERENTIAL PHASE (deg)
DIFFERENTIAL GAIN AND PHASE
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
CROSSTALK (dB)
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
FREQUENCY (Hz)
_______________________________________________________________________________________
10k
100k
Low-Power Audio/Video Interface
for Single SCART Connectors
VAUD QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
14.0
13.9
MAX9597 toc20
0.20
3.5
QUIESCENT SUPPLY CURRENT (µA)
14.1
3.6
QUIESCENT SUPPLY CURRENT (mA)
MAX9597 toc19
14.2
3.4
3.3
3.2
3.1
3.0
0.15
0.10
0.05
2.9
13.8
50
0
0
75
25
50
75
0
25
TEMPERATURE (°C)
TEMPERATURE (°C)
50
75
TEMPERATURE (°C)
INPUT-AMPLIFIER INPUT OFFSET
VOLTAGE vs. TEMPERATURE
INPUT-AMPLIFIER INPUT BIAS CURRENT
vs. TEMPERATURE
0.3
MAX9597 toc22
20
INPUT BIAS CURRENT (µA)
15
10
5
0
-5
MAX9597 toc23
25
INPUT OFFSET VOLTAGE (mV)
0.2
0.1
-10
0
-15
0
25
50
-50
75
25
50
75
TEMPERATURE (°C)
INPUT-AMPLIFIER GAIN AND PHASE
vs. FREQUENCY
INPUT-AMPLIFIER TOTAL HARMONIC
DISTORTION PLUS NOISE vs. FREQUENCY
PHASE MARGIN (CL = 0pF) = 60°
PHASE MARGIN (CL = 22pF) = 44°
40
180
MAX9597 toc24
60
0.1
UNITY GAIN
RL = OPEN
120
MAX9597 toc25
TEMPERATURE (°C)
GAIN
60
0
PHASE
CL = OpF
-20
AV = +100V/V
VIN = 10mVP-P
RLOAD = OPEN
CL = 0pF/22pF
-40
-60
10k
VIN = 0.25VRMS
0.001
-120
CL = 22pF
-180
-60
1k
0
0.01
THD+N (%)
20
PHASE (deg)
0
GAIN (dB)
QUIESCENT SUPPLY CURRENT (mA)
14.3
V12 QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
MAX9597 toc21
VVID QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
100k
1M
FREQUENCY (Hz)
10M
100M
VIN = 0.5VRMS
0.0001
10
100
1k
10k
100k
FREQUENCY (Hz)
_______________________________________________________________________________________
9
MAX9597
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, video load is 150Ω to GND, audio load is 10kΩ to GND, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, GND = EP = 0, video load is 150Ω to GND, audio load is 10kΩ to GND, TA = +25°C, unless otherwise noted.)
MAX9597 toc26
UNITY GAIN
RL = OPEN
UNITY GAIN
RL = 124Ω
0V
INPUT
50mV/div
0V
INPUT
50mV/div
0V
OUTPUT
50mV/div
0V
OUTPUT
50mV/div
200ns/div
200ns/div
UNITY GAIN
RL = OPEN
0V
INPUT
500mV/div
0V
OUTPUT
500mV/div
1µs/div
UNITY GAIN
RL = 124Ω
0V
MAX9597 toc29
INPUT-AMPLIFIER LARGE-SIGNAL
TRANSIENT RESPONSE
INPUT-AMPLIFIER LARGE-SIGNAL
TRANSIENT RESPONSE
10
MAX9597 toc27
INPUT-AMPLIFIER SMALL-SIGNAL
TRANSIENT RESPONSE
INPUT-AMPLIFIER SMALL-SIGNAL
TRANSIENT RESPONSE
MAX9597 toc28
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
INPUT
500mV/div
0V
OUTPUT
500mV/div
1µs/div
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
PIN
1
NAME
VAUD
FUNCTION
Audio Supply. Connect to a 3.3V supply. Bypass with a 10µF aluminum electrolytic capacitor in
parallel with a 0.1µF ceramic capacitor to EP.
2
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1µF capacitor from C1P to C1N.
3
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1µF capacitor from C1P to C1N.
4
CPVSS
Charge-Pump Negative Power Supply. Bypass with a 10µF aluminum electrolytic capacitor in
parallel with a 1µF ceramic capacitor to EP.
5
DEV_ADDR
6
SDA
Bidirectional, I2C Data I/O. Output is open drain and tolerates up to 3.6V.
7
SCL
I2C Clock Input
8
ENC_B_IN
9
ENC_G_IN
10
ENC_R/C_IN
11
ENC_CVBS_IN
12
TV_CVBS_OUT
13
VVID
14
TV_FS_OUT
15
GND
16
TV_R/C_OUT
17
TV_G_OUT
18
TV_B_OUT
19
V12
20
TV_SS_OUT
Device Address Set Input. Connect DEV_ADDR to GND, VVID, SDA, or SCL. See Table 3.
Encoder Blue Video Input
Encoder Green Video Input
Encoder Red/Chroma Video Input
Encoder Composite Video Input
TV SCART Composite Video Output. The sync tip is biased at 0.3V.
Video and Digital Supply. Connect to a +3.3V supply. Bypass with a parallel 1µF and 0.1µF
ceramic capacitor to GND. VVID also serves as a digital supply for the I2C interface.
TV SCART Fast-Switching Logic Output. This signal drives a back-terminated, 75Ω transmission
line.
Video Ground
TV SCART Red/Chroma Video Output. The black level of the red signal is set to 0.3V and the
blank level of the chroma signal is 1.5V.
TV SCART Green Video Output. The black level of the green signal is set to 0.3V.
TV SCART Blue Video Output. The black level of the blue signal is set to 0.3V.
+12V Supply. Bypass V12 with a 0.1µF capacitor to EP.
TV SCART Slow-Switch Signal Output
21
TV_OUTL
TV SCART Left-Channel Audio Output
22
ENC_INL+
Left Input-Amplifier Noninverting Terminal
23
ENC_INL-
Left Input-Amplifier Inverting Terminal
24
ENC_INLOUT
Left Input-Amplifier Output
25
ENC_INROUT
Right Input-Amplifier Output
26
ENC_INR-
27
ENC_INR+
Right Input-Amplifier Noninverting Terminal
28
TV_OUTR
TV SCART Right-Channel Audio Output
—
EP
Right Input-Amplifier Inverting Terminal
Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and charge pump.
A low-impedance connection to EP is required for proper isolation.
______________________________________________________________________________________
11
MAX9597
Pin Description
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
Detailed Description
The MAX9597 represents Maxim’s third generation of
SCART audio/video (A/V) switches. Under I2C control,
these devices route audio, video, and control information between the set-top box decoder chip and a
SCART connector. The audio signals are left audio and
right audio. The video signals are composite video with
blanking and sync (CVBS) and component video (red,
green, blue). S-video (Y/C) can be transported across
the SCART interface if CVBS is reassigned to luma (Y)
and red is reassigned to chroma (C). Support for
S-video is optional. The slow-switch signal and the fastswitch signal carry control information. The slow-switch
signal is a 12V, trilevel signal that indicates whether the
picture aspect ratio is 4:3, 16:9, or causes the television
to use an internal A/V source, such as an antenna. The
fast-switch signal indicates whether the television
should display CVBS or RGB signals.
CVBS, left audio, and right audio are full duplex. All the
other signals are half duplex. Therefore, one device on
the link must be designated as the transmitter, and the
other device must be designated as the receiver.
The low power consumption of the MAX9597 enables
the creation of lower power set-top boxes, televisions,
and DVD players. Unlike competing SCART ICs, the
audio and video circuits of the MAX9597 operate entirely
from 3.3V rather than from 5V and 12V. Only the slowswitch circuit of the MAX9597 requires a 12V supply.
The MAX9597 features DirectDrive audio circuitry to
eliminate click-and-pop noise. With DirectDrive, the DC
bias of the audio line outputs is always at ground when
the MAX9597 is being powered up or powered down.
Conventional audio line output drivers that operate from
a single supply require series AC-coupling capacitors.
During power-up, the DC bias on the AC-coupling
capacitor moves from ground to a positive voltage, and
during power-down, the opposite occurs. The changing
DC bias usually causes an audible transient.
Audio Section
The audio circuit consists of a left and right audio path,
each with an independent operational amplifier followed by a gain-of-4 amplifier. The encoder (stereo
audio DAC) is the input source, and the output goes to
the TV SCART connector. See Figure 1.
ENC_INR+
ENC_INR-
ZERO-CROSS
DETECTOR
INPUT
OP AMP
VAUD
EP
AV = 4V/V
TV_OUTR
ENC_INROUT
ENC_INL+
ENC_INL-
ZERO-CROSS
DETECTOR
INPUT
OP AMP
VAUD
EP
TV_OUTL
AV = 4V/V
ENC_INLOUT
VAUD
C1P
C1N
CHARGE
PUMP
CPVSS
EP
MAX9597
Figure 1. MAX9597 Audio Section Functional Diagram
12
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
MAX9597
The full-scale output of the independent operational
amplifiers is 0.5VRMS. The closed-loop gain of the operational amplifier circuit should be designed such that
the resulting full-scale output is 0.5VRMS. The fixed,
gain-of-4 amplifiers that follow the independent operational amplifiers amplify the 0.5VRMS to 2VRMS, which
complies with the SCART standard.
VDD
VOUT
VDD/2
An integrated charge pump inverts the +3.3V supply
(VAUD) to create a -3.3V supply (CPVSS), enabling the
audio circuit to operate from bipolar supplies. The
audio signal from the beginning to the end of the signal
path is always biased at ground.
GND
CONVENTIONAL DRIVER-BIASING SCHEME
Clickless Muting and Unmuting
The TV audio channel incorporates a zero-crossing
detect (ZCD) circuit that minimizes click noise due to
abrupt signal level changes that occur when entering
or coming out of a mute condition at an arbitrary
moment.
To implement the zero-crossing function when switching audio signals, set ZCD (register 00h, bit 6) high.
The MAX9597 switches the signal in or out of mute at
the next zero crossing after the mute or unmute request
occurs. See Table 8.
Audio Outputs
The MAX9597 audio output amplifiers feature Maxim’s
DirectDrive architecture, eliminating the need for outputcoupling capacitors required by conventional singlesupply audio line drivers. Conventional single-supply
audio line drivers have their outputs biased about a
nominal DC voltage (typically half the supply) for maximum dynamic range. Large coupling capacitors are
needed to block this DC bias. Clicks and pops are created when the coupling capacitors are charged during
power-up and discharged during power-down.
An internal charge pump inverts the positive supply
(VAUD), creating a negative supply (CPVSS). The audio
output amplifiers operate from the bipolar supplies with
the outputs biased about audio ground (Figure 2). The
benefit of this audio ground bias is that the amplifier
outputs do not have a DC component. The DC-blocking
capacitors required with conventional audio line drivers
are unnecessary, conserving board space, reducing
system cost, and improving frequency response.
The MAX9597 features a low-noise charge pump that
requires only two small ceramic capacitors. The
580kHz switching frequency is well beyond the audio
range and does not interfere with audio signals. The
switch drivers feature a controlled switching speed that
minimizes noise generated by turn-on and turn-off transients. The di/dt noise caused by the parasitic bond
+VDD
VOUT
GND
-VDD
DirectDrive BIASING SCHEME
Figure 2. Conventional Driver Output Waveform vs. MAX9597
Output Waveform
wire and trace inductance is minimized by limiting the
switching speed of the charge pump.
The SCART standard specifies 2VRMS as the full-scale
for audio signals. As the audio circuits process
0.5V RMS full-scale audio signals internal to the
MAX9597, the gain-of-4 output amplifiers restore the
audio signals to a full scale of 2VRMS.
Video Section
The video circuit routes different video formats between
the set-top box decoder and the TV SCART connector.
It also routes slow-switch and fast-switch control information as shown in Figure 3.
Video Inputs
Whether the incoming video input signal is AC-coupled
or DC-coupled into the MAX9597 depends upon the origin, format, and voltage range of the video signal. Table
1 below shows the recommended connections. Always
AC-couple an external video signal through a 0.1µF
capacitor because its voltage range is not well defined
(see the Typical Application Circuit). For example, the
______________________________________________________________________________________
13
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
CLAMP
LPF
AV = 2V/V
TV_CVBS_OUT
CLAMP/BIAS
LPF
AV = 2V/V
TV_R/C_OUT
ENC_G_IN
CLAMP
LPF
AV = 2V/V
TV_G_OUT
ENC_B_IN
CLAMP
LPF
AV = 2V/V
TV_B_OUT
AV = 1V/V
TV_FS_OUT
AV = 1V/V
TV_SS_OUT
ENC_CVBS_IN
ENC_R/C_IN
VVID
GND
V12
+6V
EP
MAX9597
Figure 3. MAX9597 Video Section Function Diagram
video transmitter circuit might have a different ground
than the video receiver, thereby level shifting the DC
bias. The 50Hz power line hum might cause the video
signal to change DC bias slowly.
Internal video signals that are between 0V and 1V can
be DC-coupled. Most video DACs generate video signals between 0V and 1V because the video DAC
sources current into a ground-referenced resistor. For
the minority of video DACs that generate video signals
between 2.3V and 3.3V because the video DAC sinks
current from a VDD-referenced resistor, AC-couple the
video signal to the MAX9597.
The MAX9597 restores the DC level of incoming,
AC-coupled video signals with either transparent synctip clamps or bias circuits. When using an AC-coupled
input, the transparent sync-tip clamp automatically
clamps the input signal minimum to ground, preventing it
14
from going lower. A small current of 2µA pulls down on
the input to prevent an AC-coupled signal from drifting
outside the input range of the part. The transparent synctip clamp is used with CVBS, RGB, and luma signals.
The transparent sync-tip clamp is transparent when the
incoming video signal is DC-coupled and at ground or
above. Under such conditions, the clamp never activates. Therefore, the outputs of video DACs that generate signals between 0V and 1V can be directly
connected to the MAX9597 inputs.
The bias circuit accepts AC-coupled chroma, which is
a subcarrier with the color information modulated onto
it. The bias voltage of the bias circuits is around
600mV.
ENC_R/C_IN can receive either a red video signal or a
chroma video signal. Set the input configuration by writing to bit 3 of register 08h. See Table 10.
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
MAX9597
Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit
Configuration**
VIDEO ORIGIN
FORMAT
VOLTAGE RANGE
(V)
COUPLING
INPUT CIRCUIT CONFIGURATION
External
CVBS
Unknown
AC
Transparent sync-tip clamp
External
RGB
Unknown
AC
Transparent sync-tip clamp
External
Y
Unknown
AC
Transparent sync-tip clamp
External
C
Unknown
AC
Bias circuit
Internal
CVBS
0 to 1
DC
Transparent sync-tip clamp
Internal
R, G, B
0 to 1
DC
Transparent sync-tip clamp
Internal
Y, C
0 to 1
DC
Transparent sync-tip clamp
Internal
Y, Pb, Pr
0 to 1
DC
Transparent sync-tip clamp
Internal
CVBS
2.3 to 3.3
AC
Transparent sync-tip clamp
Internal
R, G, B
2.3 to 3.3
AC
Transparent sync-tip clamp
Internal
Y
2.3 to 3.3
AC
Transparent sync-tip clamp
Internal
C
2.3 to 3.3
AC
Bias circuit
**Use a 0.1µF capacitor to AC-couple a video signal into the MAX9597.
Video Reconstruction Filter
The video DAC outputs of the set-top box decoder chip
need to be lowpass-filtered to reject the out-of-band
noise. The MAX9597 integrates sixth-order, Butterworth
filters. The filter passband (±1dB) is typically 10MHz,
and the attenuation at 27MHz is 43dB. The filters are
suited for standard-definition video.
Video Outputs
The video output amplifiers can both source and sink
load current, allowing output loads to be DC- or
AC-coupled. The amplifier output stage needs approximately 300mV of headroom from either supply rail.
If the supply voltage is greater than 3.135V (5% below
a 3.3V supply), each amplifier can drive two DC-coupled video loads to ground. If the supply is less than
3.135V, each amplifier can drive only one DC-coupled
or AC-coupled video load.
The SCART standard allows for video signals to have a
superimposed DC component within 0V and 2V.
Therefore, most video signals are DC-coupled at the output. In the unlikely event that the video signal needs to
be AC-coupled, the coupling capacitors should be
220µF or greater to keep the highpass filter formed by
the 37.5Ω equivalent resistance of the video transmission line to a corner frequency of 4.8Hz or below to keep
it well below the 25Hz frame rate of the PAL standard.
The video outputs can be enabled or disabled by bits 1
to 5 of register 0Dh. See Table 11.
Slow Switching
The MAX9597 supports the IEC 933-1, Amendment 1,
trilevel slow-switching standard that selects the aspect
ratio for the display (TV). Under I 2 C control, the
MAX9597 sets the slow-switching output voltage level.
Table 2 shows the valid input levels of the slow-switching signal and the corresponding operating modes of
the display device.
One port is available for slow-switching signals for the
TV. The slow-switching outputs can be set to a logic
level or high impedance by writing to bit 0 and 1 of register 07h. See Table 9.
Table 2. Slow-Switching Modes
SLOW-SWITCHING
SIGNAL VOLTAGE
(V)
0 to 2
MODE
Display device uses an internal
source such as a built-in tuner to
provide a video signal.
4.5 to 7.0
Display device uses a video signal
from the SCART connector and sets
the display to a 16:9 aspect ratio.
9.5 to 12.6
Display device uses a signal from the
SCART connector and sets the
display to a 4:3 aspect ratio.
______________________________________________________________________________________
15
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
Table 3. Slave Address
DEV_ADDR
B7
B6
B5
B4
B3
B2
B1
B0
GND
VVID
SCL
SDA
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
R/W
R/W
R/W
R/W
WRITE ADDRESS
(HEX)
94h
96h
98h
9Ah
READ ADDRESS
(HEX)
95h
97h
99h
9Bh
SDA
tSU, STA
tSU, DAT
tHD, DAT
tLOW
tBUF
tHD, STA
tSP
tSU, STO
SCL
tHIGH
tHD, STA
tR
tF
REPEATED
START CONDITION
START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 4. I2C Serial-Interface Timing Diagram
Fast Switching
The fast-switching signal was originally used to switch
between CVBS and RGB signals on a pixel-by-pixel
basis so that on-screen display (OSD) information
could be inserted. Since modern set-top box decoder
chips have integrated OSD circuitry, there is no need to
create OSD information using the older technique.
Now, the fast-switching signal is just used to switch
between CVBS and RGB signal sources.
Set the source of the fast-switching signal by writing to
bits 4 and 3 of register 07h. The fast-switching signal to
the TV SCART connector can be enabled or disabled
by bit 1 of register 0Dh. See Tables 9 and 11.
I2C Serial Interface
I2C/SMBus™-compatible,
The MAX9597 features an
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9597 and the master at clock rates up to 400kHz. Figure 4 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. A master
device writes data to the MAX9597 by transmitting a
START (S) condition, the proper slave address with the
R/W bit set to 0, followed by the register address and
then the data word. Each transmit sequence is framed
by a START and a STOP (P) condition. Each word transmitted to the MAX9597 is 8 bits long and is followed by
16
an acknowledge clock pulse. A master reads from the
MAX9597 by transmitting the slave address with the R/W
bit set to 0, the register address of the register to be
read, a REPEATED START (Sr) condition, the slave
address with the R/W bit set to 1, followed by a series of
SCL pulses. The MAX9597 transmits data on SDA in
sync with the master-generated SCL pulses. The master
acknowledges receipt of each byte of data. Each read
sequence is framed by a START or REPEATED START
condition, an acknowledge or a not acknowledge, and a
STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater
than 500Ω, is required on the SDA bus. SCL operates as
only an input. A pullup resistor, typically greater than
500Ω, is required on SCL if there are multiple masters on
the bus, or if the master in a single-master system has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the MAX9597 from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
SMBus is a trademark of Intel Corp.
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 5). A START
condition from the master signals the beginning of a
transmission to the MAX9597. The master terminates
transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9597 recognizes a STOP condition at any
point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
S
Sr
MAX9597
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
P
SCL
SDA
Figure 5. START, STOP, and REPEATED START Conditions
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
9
NOT ACKNOWLEDGE
Slave Address
The slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/W bit to 1 to configure the MAX9597 to read mode.
Set the R/W bit to 0 to configure the MAX9597 to write
mode. The slave address is always the first byte of
information sent to the MAX9597 after a START or a
REPEATED START condition. The MAX9597 slave
address is configurable with DEV_ADDR. Table 3
shows the possible slave addresses for the MAX9597.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9597 uses to handshake receipt of each byte of
data when in write mode (see Figure 6). The MAX9597
pulls down SDA during the entire master-generated
ninth clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication. The
master pulls down SDA during the ninth clock cycle to
acknowledge receipt of data when the MAX9597 is in
read mode. An acknowledge is sent by the master after
each read byte to allow data transfer to continue. A not
acknowledge is sent when the master reads the final
byte of data from the MAX9597, followed by a STOP
condition.
SDA
ACKNOWLEDGE
Figure 6. Acknowledge
Write Data Format
A write to the MAX9597 consists of transmitting a
START condition, the slave address with the R/W bit set
to 0, one data byte to configure the internal register
address pointer, one or more data bytes, and a STOP
condition. Figure 7 illustrates the proper frame format
for writing one byte of data to the MAX9597. Figure 8
illustrates the frame format for writing n-bytes of data to
the MAX9597.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9597.
The MAX9597 acknowledges receipt of the address
byte during the master-generated ninth SCL pulse.
The second byte transmitted from the master configures the MAX9597’s internal register address pointer.
The pointer tells the MAX9597 where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9597 upon receipt of the address pointer data.
The third byte sent to the MAX9597 contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX9597 signals receipt of the data
byte. The address pointer autoincrements to the next
______________________________________________________________________________________
17
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
ACKNOWLEDGE FROM MAX9597
B7
ACKNOWLEDGE FROM MAX9597
SLAVE ADDRESS
S
0
B6
B5
B4
B3
B2
B1
B0
ACKNOWLEDGE FROM MAX9597
A
REGISTER ADDRESS
A
DATA BYTE
A
R/W
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 7. Writing a Byte of Data to the MAX9597
ACKNOWLEDGE FROM MAX9597
ACKNOWLEDGE FROM MAX9597
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9597
ACKNOWLEDGE FROM MAX9597
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
A
R/W
DATA BYTE 1
A
DATA BYTE n
1 BYTE
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 8. Writing n-Bytes of Data to the MAX9597
register address after each received data byte. This
autoincrement feature allows a master to write to
sequential register address locations within one continuous frame. The master signals the end of transmission
by issuing a STOP condition.
Read Data Format
The master presets the address pointer by first sending
the MAX9597’s slave address with the R/W bit set to 0
followed by the register address after a START condition. The MAX9597 acknowledges receipt of its slave
address and the register address by pulling SDA low
during the ninth SCL clock pulse. A REPEATED START
condition is then sent followed by the slave address
with the R/W bit set to 1. The MAX9597 transmits the
contents of the specified register. Transmitted data is
valid on the rising edge of the master-generated serial
clock (SCL). The address pointer autoincrements after
each read data byte. This autoincrement feature allows
all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any
number of read data bytes. If a STOP condition is
issued followed by another read operation, the first
data byte to be read is from the register address location set by the previous transaction and not 00h and
subsequent reads autoincrement the address pointer
18
until the next STOP condition. Attempting to read from
register addresses higher than 01h results in repeated
reads from a dummy register containing FFh data. The
master acknowledges receipt of each read byte during
the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condition. Figures 9 and 10 illustrate the frame format for
reading data from the MAX9597.
Applications Information
Operating Modes
The MAX9597 has two operating modes: full power
and shutdown. The operations can be set by writing to
bit 7 of register 10h. See Table 12.
In shudown mode, all circuitry is shut down except for
the I2C interface, which is designed with static CMOS
logic. If the I2C bus is quiet, the I2C interface draws
only leakage current.
Power Consumption
With a low 3.3V supply, the quiescent power consumption and average power consumption of the MAX9597
is very low. Quiescent power consumption is defined
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
MAX9597
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MAX9597
ACKNOWLEDGE FROM MAX9597
S
SLAVE ADDRESS
0
A
R/W
ACKNOWLEDGE FROM MAX9597
A
REGISTER ADDRESS
Sr
SLAVE ADDRESS
REPEATED START
1
R/W
A
A
DATA BYTE
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 9. Reading One Indexed Byte of Data from the MAX9597
S
SLAVE ADDRESS
0
R/W
ACKNOWLEDGE FROM MAX9597
ACKNOWLEDGE FROM MAX9597
ACKNOWLEDGE FROM MAX9597
A
REGISTER ADDRESS
A
Sr
REPEATED START
SLAVE ADDRESS
1
A
R/W
A
DATA BYTE
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 10. Reading n-Bytes of Indexed Data from the MAX9597
when the MAX9597 is operating without loads and without any audio or video signals. Table 4 shows the quiescent power consumption in both operating modes.
Average power consumption is defined when the
MAX9597 drives typical signals into typical loads. Table 5
shows the average power consumption in full-power
mode, and Table 6 shows the input and output conditions.
Table 4. Quiescent Power Consumption
OPERATING MODE
POWER CONSUMPTION (mW)
Shutdown
0.005
Full power
53
Table 5. Average Power Consumption
Interfacing to an RF Modulator
If the set-top box modulates CVBS and mono audio
onto an RF carrier (for example, channel 3), a simple
application circuit can provide the needed signals (see
Figure 11). A 10kΩ resistor summer circuit between
TV_OUTR and TV_OUTL creates the mono audio signal. The resistor-divider to ground on TV_CVBS_OUT
creates a video signal with normal amplitude. The
unique feature of the MAX9597 that facilitates this
application circuit is that the audio and video output
amplifiers of the MAX9597 can drive multiple loads if
VAUD and VVID are both greater than 3.135V.
OPERATING MODE
POWER CONSUMPTION (mW)
Full power
254
Floating-Chassis Discharge Protection
and ESD
Some set-top boxes have a floating chassis problem in
which the chassis is not connected to earth ground. As
a result, the chassis can charge up to 500V. When a
SCART cable is connected to the SCART connector,
the charged chassis can discharge through a signal
pin. The equivalent circuit is a 2200pF capacitor
charged to 311V connected through less than 0.1Ω to a
signal pin. The MAX9597 is soldered on the PCB when
it experiences such a discharge. Therefore, the current
spike flows through both external and internal ESD protection devices and is absorbed by the supply bypass
capacitors, which have high capacitance and low ESR.
______________________________________________________________________________________
19
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
TV_OUTR
10kΩ
MAX9597
MONO AUDIO
10kΩ
TV_OUTL
75Ω
TV
SCART
TV_CVBS_OUT
75Ω OR GREATER
75Ω OR GREATER
RF
MODULATOR
Figure 11. Application Circuit to Connect CVBS and Mono Audio from TV SCART to RF Modulator
Table 6. Conditions for Average Power Consumption Measurement
PIN
NAME
TYPE
SIGNAL
LOAD
1
VAUD
8
ENC_B_IN
Supply
3.3V
N/A
Input
50% flat field
9
N/A
ENC_G_IN
Input
50% flat field
N/A
10
ENC_R/C_IN
Input
50% flat field
N/A
11
ENC_CVBS_IN
Input
50% flat field
N/A
12
TV_CVBS_OUT
Output
50% flat field
150Ω to ground
13
VVID
Supply
3.3V
N/A
14
TV_FS_OUT
Output
3.3V
150Ω to ground
15
GND
Supply
0
N/A
16
TV_R/C_OUT
Output
50% flat field
150Ω to ground
17
TV_G_OUT
Output
50% flat field
150Ω to ground
18
TV_B_OUT
Output
50% flat field
150Ω to ground
19
V12
Supply
12V
N/A
20
TV_SS_OUT
Output
12V
10kΩ to ground
21
TV_OUTL
Output
1VRMS, 1kHz
10kΩ to ground
22
ENC_INL+
Input
0.25VRMS, 1kHz
N/A
23
ENC_INL-
Input
N/A
N/A
24
ENC_INLOUT
Output
N/A
1kΩ to ground
25
ENC_INROUT
Output
N/A
1kΩ to ground
26
ENC_INR-
Input
N/A
N/A
27
ENC_INR+
Input
0.25VRMS, 1kHz
N/A
28
TV_OUTR
Output
1VRMS, 1kHz
10kΩ to ground
Note: Input operational amplifiers set to unity-gain configuration.
20
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
3.3V
3.3V
0.1µF
+3.3V
MAX9597
12V
0.1µF
0.1µF
VAUD
V12
STB CHIP
VVID
VAUD
300Ω
TV_OUTR
VAUD
SDA
µC
SCL
300Ω
MAX9597
TV_OUTL
CPVSS
V12
100Ω
CPVSS
TV_SS_OUT
VVID
75Ω
DEV_ADDR
TV_B_OUT
ENC_CVBS_IN
TV_G_OUT
VIDEO
ENCODER
EP
VVID
75Ω
75Ω
VVID
75Ω
TV_R/C_OUT
ENC_R/C_IN
GND
TV
SCART
GND
VVID
75Ω
GND
TV_FS_OUT
VVID
75Ω
75Ω
TV_CVBS_OUT
GND
ENC_G_IN
C1P
75Ω
ENC_B_IN
GND
C1N
CPVSS
75Ω
GND
ENC_INL+
EP
124Ω
15nF
ENC_INLSTEREO
AUDIO
DACS WITH
DIFFERENTIAL
OUTPUTS
124Ω
15nF
ENC_INLOUT
ENC_INR+
124Ω
15nF
ENC_INR124Ω
15nF
ENC_INROUT
NOTE: OPTIONAL RESISTOR CAN BE PLACED
FROM AUDIO DAC OUTPUTS TO GROUND TO
DECREASE SWING AT AUDIO DAC OUTPUTS.
:BAV99, SMALL-SIGNAL DIODE
Figure 12. Application Circuit to Connect Series Resistors and External ESD Protection Diodes at MAX9597 Outputs
______________________________________________________________________________________
21
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
PCM1742
DAC
MAX9597
3.01kΩ
ENC_INL+
10µF 604Ω
6.04kΩ
LEFT
ENC_INL1.2nF
3.01kΩ
390pF
ENC_INLOUT
3.01kΩ
ENC_INR+
10µF
604Ω
6.04kΩ
ENC_INR-
RIGHT
1.2nF
3.01kΩ
390pF
ENC_INROUT
NOTE: ALL RESISTORS ARE 1%.
Figure 13. Lowpass Filter Configuration for the Burr-Brown PCM1742
Lowpass Filter Configuration
for PCM1742 and CS4334
The lowpass filter configurations shown in Figures 13
and 15 are recommended when connecting a stereo
audio DAC to the audio preamplifier (input amplifier) of
the MAX9597. The filter configuration helps eliminate
the switching noise caused by the audio DAC. The corner frequency of the filter configuration should be set
above the maximum audio frequency (20kHz) and
below the sampling frequency of the DAC. The frequency response of the filter configurations is shown in
Figures 14 and 16.
Differential to Single-Ended Conversion
of Audio Signals
FILTER RESPONSE vs. FREQUENCY
PCM1742 APPLICATION CIRCUIT WITHOUT THE DAC
10
VIN = 0.25VRMS
5
0
GAIN (dB)
To better protect the MAX9597 against excess voltages
during the cable discharge condition or ESD events,
add series resistors to all inputs and outputs to the
SCART connector if series resistors are not already present in the application circuit. Also add external ESD
protection diodes (for example, BAV99) on all inputs
and output to the SCART connector.
-5
-10
-15
-20
-25
-30
1
10
100
1k
10k
100k
Figure 14. Filter Response of PCM1742 Filter Configuration
If the stereo audio DAC generates an analog, voltage
mode, differential audio signal, the circuit shown in Figure
17 can be used to convert the signal to single ended.
The gain of the circuit is represented by this equation:
⎛ R2 ⎞
GAIN = ⎜ ⎟ × 4
⎝ R1 ⎠
22
1M
FREQUENCY (Hz)
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
MAX9597
CS4334
DAC
MAX9597
3.57kΩ
ENC_INL+
10µF 1.21kΩ
4.64kΩ
1.21kΩ
LEFT
ENC_INL2.7nF
3.3nF
270kΩ
2.40kΩ
560pF
ENC_INLOUT
3.57kΩ
ENC_INR+
10µF
1.21kΩ
4.64kΩ
1.21kΩ
ENC_INR-
RIGHT
2.7nF
3.3nF
270kΩ
560pF
2.40kΩ
ENC_INROUT
NOTE: ALL RESISTORS ARE 1%.
Figure 15. Lowpass Filter Configuration for the Cirrus CS4334
Keep the full-scale audio output of the preamplifiers to
0.5VRMS. Capacitors C1 and C2 create a one-pole,
lowpass filter to attenuate any high-frequency noise
coming from the stereo audio DAC. The frequency of
the lowpass pole is represented by this equation:
1
1
or f−3dB =
⎛ R1 × R2 ⎞
⎛ R1 × R2 ⎞
2π ⎜
2π ⎜
C2
C1
⎝ R1 + R2 ⎟⎠
⎝ R1 + R2 ⎟⎠
If the stereo audio DAC generates an analog, current
mode, and differential audio signal, the Typical
Application Circuit can be used to convert the signal to
single ended. The transresistance of the circuit is represented by this equation:
VOUT = IDIFF x RF
Keep the full-scale audio output of the preamplifiers to
0.5VRMS. Capacitors C1 and C2 create a one-pole,
lowpass filter to attenuate any high-frequency noise
coming from the stereo audio DAC. The frequency of
the lowpass pole is represented by this equation:
f−3dB =
10
VIN = 0.25VRMS
0
-10
GAIN (dB)
f−3dB =
FILTER RESPONSE vs. FREQUENCY
CS4334 APPLICATION CIRCUIT WITHOUT THE DAC
-20
-30
-40
-50
-60
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 16. Filter Response of CS4334 Filter Configuration
1
1
or f−3dB =
2π(RF )C1
2π(RF )C2
______________________________________________________________________________________
23
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
STB CHIP
MAX9597
C1
R2
ENC_INL+
LEFT_P
R1
LEFT_N
ENC_INLR2
R2
C2
C1
R2
ENC_INLOUT
ENC_INR+
RIGHT_P
R1
ENC_INR-
RIGHT_N
R1
R2
C2
ENC_INROUT
Figure 17. Differential to Single-Ended Conversion Circuit for Voltage Mode, Differential Audio Signals
Stand-Alone Operational
Amplifier Applications
The input amplifier of the audio section can be utilized
for stand-alone operational amplifier applications by
configuring ENC_INR+ and ENC_INL+ input as the
noninverting input, ENC_INR- and ENC_INL- input as
the inverting input and ENC_INROUT and
ENC_INLOUT output as the output of the stand-alone
operational amplifier. The gain-bandwidth product of
the amplifier is 7MHz (typ).
Applications That Do Not Need
the Slow-Switch Signal
V12 should be left unconnected if the MAX9597 is used
in an application that does not require the slowswitch output signal. See Figure 18.
10µF electrolytic capacitor in parallel with a 0.1µF
ceramic capacitor to audio ground. Bypass VVID to
GND with a 0.1µF ceramic capacitor.
Using a Digital Supply
The MAX9597 was designed to operate from noisy digital supplies. The high video PSRR (47dB at 100kHz)
allows the MAX9597 to reject the noise from the digital
power supplies (see the Typical Operating Characteristics). If the digital power supply is very noisy and
stripes appear on the television screen, increase the
supply bypass capacitance. An additional, smaller
capacitor in parallel with the main bypass capacitor
can reduce digital supply noise because the smaller
capacitor has lower equivalent series resistance (ESR)
and equivalent series inductance (ESL).
Power-Supply Bypassing
Layout and Grounding
The MAX9597 features single 3.3V and 12V supply
operation and requires no negative supply. The 12V
supply V12 is for the SCART slow-switching function.
For pin V12, place a 0.1µF bypass capacitor as close to
it as possible. Connect VAUD to 3.3V and bypass with a
For optimal performance, use controlled-impedance
traces for video signal paths and place input termination resistors and output back-termination resistors
close to the MAX9597. Avoid routing video traces parallel to high-speed data lines.
24
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
VID
3.3V
MAX9597
V12
N.C.
VAUD
3.3V
MAX9597
STB CHIP
µC
I2C INTERFACE
AND REGISTERS
I2C
CVBS
VIDEO FILTERS
Y
VIDEO
ENCODER
CVBS, Y/C
4 3
C
STEREO
AUDIO
DAC
AUDIO
WITH DirectDrive
OUTPUTS
SINGLE OR
DIFFERENTIAL
STEREO AUDIO
2
1
LEFT AUDIO
RIGHT AUDIO
SLOW SWITCHING
FAST SWITCHING
CHARGE PUMP
EP
GND
Figure 18. Set-Top Box with CVBS Output, S-Video Output, and Stereo Audio Outputs
The MAX9597 provides separate ground connections
for video and audio supplies. For best performance,
use separate ground planes for each of the ground
returns and connect all ground planes together at a single point. Refer to the MAX9597 Evaluation Kit for a
proven circuit board layout example.
If the MAX9597 is mounted using flow soldering or
wave soldering, the ground via(s) for the exposed pad
should have a finished hole size of at least 14mil to
ensure adequate wicking of soldering onto the exposed
pad. If the MAX9597 is mounted using the solder mask
technique, the via requirement does not apply. In either
case, a good connection between the exposed pad
and ground is required to minimize noise from coupling
onto the outputs.
______________________________________________________________________________________
25
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
Register Tables
Table 7. Data Format for Write Mode
REGISTER
ADDRESS
(HEXADECIMAL)
BIT 7
BIT 6
0x00
Not used
ZCD
26
BIT 5
BIT 4
BIT 3
Not used
0x02
Not used
0x03
Not used
0x04
Not used
0x05
Not used
0x06
Not used
0x07
Not used
Not
used
Not used
0x08
Not used
Not
used
Not used
Set TV fast switching
Not used
TV_CVBS_OUT
TV_FS_OUT
Not
used
Not used
Not used
Not used
Not
used
0x0B
Not used
0x0C
Not used
Operating
mode
Not
used
Not used
Not used
Set TV slow switching
TV_B_OUT
Not used
TV_R/C_OUT TV_G_OUT
Not used
Not
used
Not used
0x10
TV audio
mute
Not used
0x09
Not
used
BIT 0
Not used
ENC_R/C_IN
clamp
0x0A
Not used
BIT 1
Not used
0x01
0x0D
BIT 2
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
MAX9597
Table 8. Register 00h: Audio Control
DESCRIPTION
TV audio mute
Zero-crossing detector
BIT
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
0
COMMENTS
Off
—
—
—
—
—
—
—
1
On (power-on default)
—
0
—
—
—
—
—
—
Off
—
1
—
—
—
—
—
—
On (power-on default)
Table 9. Register 07h: TV Video Output Control
DESCRIPTION
Set TV slow switching
Set TV fast switching
BIT
COMMENTS
7
6
5
4
3
2
1
0
—
—
—
—
—
—
0
0
Low (< 2V) internal source (power-on
default)
—
—
—
—
—
—
0
1
Medium (4.5V to 7V) external SCART
source with 16:9 aspect ratio
—
—
—
—
—
—
1
0
High impedance
—
—
—
—
—
—
1
1
High ( > 9.5V) external SCART source
with 4:3 aspect ratio
—
—
—
0
0
—
—
—
GND (power-on default)
—
—
—
0
1
—
—
—
Not used
—
—
—
1
0
—
—
—
Same level as VCR_FB_IN
—
—
—
1
1
—
—
—
VVID
Table 10. Register 08h: VCR Video Input Control
DESCRIPTION
ENC_R/C_IN clamp/bias
BIT
COMMENTS
7
6
5
4
3
2
1
0
—
—
—
—
0
—
—
—
DC restore clamp active at input
(power-on default)
—
—
—
—
1
—
—
—
Chrominance bias applied at input
______________________________________________________________________________________
27
Table 11. Register 0Dh: Output Enable
BIT
DESCRIPTION
TV_FS_OUT enable
TV_CVBS_OUT enable
TV_B_OUT enable
TV_G_OUT enable
TV_R/C_OUT enable
7
6
5
4
3
2
1
0
—
—
—
—
—
—
0
—
COMMENTS
Off (power-on default)
—
—
—
—
—
—
1
—
On
—
—
—
—
—
0
—
—
Off (power-on default)
—
—
—
—
—
1
—
—
On
—
—
—
—
0
—
—
—
Off (power-on default)
—
—
—
—
1
—
—
—
On
—
—
—
0
—
—
—
—
Off (power-on default)
—
—
—
1
—
—
—
—
On
—
—
0
—
—
—
—
—
Off (power-on default)
—
—
1
—
—
—
—
—
On
Table 12. Register 10h: Operating Modes
BIT
DESCRIPTION
Operating mode
6
5
4
3
2
1
0
0
—
—
—
—
—
—
—
Shutdown
1
—
—
—
—
—
—
—
Full-power mode (power-on default)
Chip Information
Pin Configuration
TV_SS_OUT
V12
TV_B_OUT
TV_G_OUT
TV_R/C_OUT
GND
PROCESS: BiCMOS
TV_OUTL
TOP VIEW
21
20
19
18
17
16
15
ENC_INL+ 22
14
TV_FS_OUT
ENC_INL- 23
13
VVID
ENC_INLOUT 24
12
TV_CVBS_OUT
ENC_INROUT 25
11
ENC_CVBS_IN
ENC_INR- 26
10
ENC_R/C_IN
ENC_INR+ 27
9
ENC_G_IN
8
ENC_B_IN
MAX9597
EP*
1
2
3
4
5
6
7
C1P
CPVSS
DEV_ADDR
SDA
SCL
+
C1N
TV_OUTR 28
COMMENTS
7
VAUD
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
*EXPOSED PAD. CONNECT EP TO AUDIO GROUND FOR
PROPER THERMAL AND ELECTRICAL PERFORMANCE
28
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
12V
0.1µF
+3.3V
V12
STB CHIP
3.3V
3.3V
0.1µF
VVID
0.1µF
VAUD
300Ω
TV_OUTR
SDA
µC
SCL
300Ω
MAX9597
TV_OUTL
100Ω
TV_SS_OUT
75Ω
DEV_ADDR
TV_B_OUT
ENC_CVBS_IN
TV_G_OUT
VIDEO
ENCODER
75Ω
75Ω
TV
SCART
75Ω
TV_R/C_OUT
ENC_R/C_IN
75Ω
TV_FS_OUT
75Ω
75Ω
TV_CVBS_OUT
ENC_G_IN
C1P
75Ω
ENC_B_IN
C1N
CPVSS
75Ω
GND
ENC_INL+
EP
124Ω
(RF)
15nF
(C1)
ENC_INLSTEREO
AUDIO
CURRENT
DACS WITH
DIFFERENTIAL
OUTPUTS
124Ω
(RF)
15nF
(C2)
ENC_INLOUT
ENC_INR+
124Ω
(RF)
15nF
(C1)
ENC_INR124Ω
(RF)
15nF
(C2)
ENC_INROUT
NOTE: OPTIONAL RESISTOR CAN BE PLACED
FROM AUDIO DAC OUTPUTS TO GROUND TO
DECREASE SWING AT AUDIO DAC OUTPUTS.
______________________________________________________________________________________
29
MAX9597
Typical Application Circuit
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
28 TQFN-EP
T2855-8
21-0140
QFN THIN.EPS
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
30
______________________________________________________________________________________
Low-Power Audio/Video Interface
for Single SCART Connectors
______________________________________________________________________________________
31
MAX9597
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
Revision History
REVISION
NUMBER
REVISION DATE
DESCRIPTION
PAGES CHANGED
0
6/08
Initial release
—
1
10/08
Corrected resistor value in Figure 13
22
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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