19-2744; Rev 0; 1/03
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Features
The MAX9760–MAX9763 family combines a stereo or
mono 3W bridge-tied load (BTL) audio power amplifier,
stereo single-ended headphone amplifier, headphone
sensing, and a 2:1 input multiplexer all in a tiny 28-pin
thin QFN package. These devices operate from a single 4.5V to 5.5V supply and feature an industry-leading
100dB PSRR, allowing these devices to operate from
noisy supplies without the addition of a linear regulator.
An ultra-low 0.002% THD+N ensures clean, low-distortion amplification of the audio signal. Click-and-pop
suppression eliminates audible transients on power and
shutdown cycles. Power-saving features include low
4mV V OS (minimizes DC current drain through the
speakers), low 13mA supply current, and a 10µA shutdown mode. A MUTE function allows the outputs to be
quickly enabled or disabled.
♦ Industry-Leading, Ultra-High 100dB PSRR
A headphone sense input detects the presence of a
headphone jack and automatically configures the
amplifiers for either speaker or headphone mode. In
speaker mode, the amplifiers can deliver up to 3W of
continuous average power into a 3Ω load. In headphone mode, the amplifier can deliver up to 200mW of
continuous average power into a 16Ω load. The gain of
the amplifiers is externally set, allowing maximum flexibility in optimizing output levels for a given load. The
amplifiers also feature a 2:1 input multiplexer, allowing
multiple audio sources to be selected. The multiplexer
can also be used to compensate for limitations in the
frequency response of the loud speakers by selecting
an external equalizer network. The various functions are
controlled by either an I2C-compatible or simple parallel
control interface.
The MAX9760–MAX9763 are available in either a thermally efficient 28-pin thin QFN package (5mm ✕ 5mm ✕
0.8mm) or a TSSOP-EP package. All devices have thermal overload protection (OVP) and are specified over
the extended -40°C to +85°C temperature range.
♦ Optional 2-Wire, I2C-Compatible or Parallel
Interface
Applications
♦ PC99/01 Compliant
♦ 3W BTL Stereo Speaker Amplifier
♦ 200mW Stereo Headphone Amplifier
♦ Low 0.002% THD+N
♦ Click-and-Pop Suppression
♦ ESD-Protected Outputs
♦ Low Quiescent Current: 13mA
♦ Low-Power Shutdown Mode: 10µA
♦ MUTE Function
♦ Headphone Sense Input
♦ Stereo 2:1 Input Multiplexer
♦ Tiny 28-Pin Thin QFN (5mm ✕ 5mm ✕ 0.8mm) and
TSSOP-EP Packages
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX9760ETI
PART
-40°C to +85°C
28 Thin QFN-EP*
MAX9760EUI
-40°C to +85°C
28 TSSOP-EP*
*EP = Exposed paddle.
Ordering Information continued at end of data sheet.
Simplified Block Diagram
SINGLE SUPPLY
4.5V TO 5.5V
LEFT IN1
LEFT IN2
Notebooks
SE/
BTL
Portable DVD Players
Tablet PCs
RIGHT IN1
PC Audio Peripherals
RIGHT IN2
Camcorders
CONTROL
Pin Configurations and Functional Diagrams appear at end
of data sheet.
I2CCOMPATIBLE
MAX9760
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9760–MAX9763
General Description
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................................+6V
SVDD to GND .........................................................................+6V
SVDD to VDD .........................................................................-0.3V
PVDD to VDD .......................................................................±0.3V
PGND to GND.....................................................................±0.3V
All Other Pins to GND.................................-0.3V to (VDD + 0.3V)
Continuous Input Current (into any pin except power-supply
and output pins) ...............................................................±20mA
Continuous Power Dissipation
28-Pin Thin QFN (derate 20.8mW/°C above +70°C) ....1667mW
28-Pin TSSOP-EP (derate 23.8mW/°C above +70°C) ..1905mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = PVDD = 5.0V, GND = PGND = 0V, SHDN = 5V, CBIAS = 1µF, RIN = RF = 15kΩ, RL = ∞. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Supply Voltage Range
Quiescent Supply Current
(IVDD + IPVDD)
Shutdown Current
Switching Time
Turn-On Time
SYMBOL
VDD/PVDD
IDD
I SHDN
tSW
tON
CONDITIONS
Inferred from PSRR test
MIN
TYP
4.5
MAX
UNITS
5.5
V
MAX9760/MAX9761
13
32
MAX9762/MAX9763
7
18
Single-ended mode, HPS = VDD
7
18
SHDN = GND
10
50
Gain or input switching
10
CBIAS = 1µF
300
CBIAS = 0.1µF
30
BTL mode,
HPS = 0V
mA
µA
µs
ms
Thermal Shutdown Threshold
160
o
C
Thermal Shutdown Hysteresis
15
o
C
OUTPUT AMPLIFIERS (SPEAKER MODE, HPS = GND)
Output Offset Voltage
VOS
VDD = 4.5V to 5.5V
Power-Supply Rejection Ratio
Output Power
Total Harmonic Distortion Plus
Noise
Signal-to-Noise Ratio
PSRR
POUT
THD+N
SNR
Slew Rate
SR
Maximum Capacitive Load Drive
CL
Crosstalk
2
±4
OUT_+ - OUT_-, AV = 1V/V
(Note 2)
75
82
f = 20kHz, VRIPPLE =
200mVP-P
70
fIN = 1kHz,
THD+N < 1%,
TA = +25°C
RL = 8Ω
fIN = 1kHz, BW =
22Hz to 22kHz
POUT = 1W, RL = 8Ω
0.005
POUT = 2W, RL = 4Ω
0.01
RL = 3Ω
RL = 8Ω, POUT = 1W, BW = 22Hz to 22kHz
1
mV
100
f = 1kHz, VRIPPLE =
200mVP-P
RL = 4Ω
±32
dB
1.4
2.6
W
3
%
95
dB
1.6
V/µs
No sustained oscillations
1
nF
fIN = 10kHz
73
dB
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
(VDD = PVDD = 5.0V, GND = PGND = 0V, SHDN = 5V, CBIAS = 1µF, RIN = RF = 15kΩ, RL = ∞. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
75
106
MAX
UNITS
OUTPUT AMPLIFIERS (HEADPHONE MODE, HPS = VDD)
VDD = 4.5V to 5.5V
Power-Supply Rejection Ratio
PSRR
Output Power
POUT
Total Harmonic Distortion Plus
Noise
THD+N
Signal-to-Noise Ratio
SNR
Slew Rate
SR
Maximum Capacitive Load Drive
CL
Crosstalk
(Note 2)
f = 1kHz, VRIPPLE =
200mVP-P
88
f = 20kHz, VRIPPLE =
200mVP-P
76
fIN = 1kHz, THD+N < RL = 32Ω
1%, TA = +25°C
RL = 16Ω
fIN = 1kHz, BW =
22Hz to 22kHz
dB
88
120
mW
200
POUT = 60mW,
RL = 32Ω
0.002
POUT = 125mW,
RL = 16Ω
0.002
%
RL = 32Ω, BW = 22Hz to 22kHz,
VOUT = 1VRMS
92
dB
1.8
V/µs
No sustained oscillations
2
nF
fIN = 10kHz
78
dB
VBIAS = 1.25V, VDD = 0V
425
STANDBY SUPPLY (SVDD) (Note 3)
SVDD Current
ISVDD
VBIAS = 2.5V, VDD = 5V
750
15
µA
BIAS VOLTAGE (BIAS)
BIAS Voltage
VBIAS
Output Resistance
RBIAS
2.35
2.5
2.65
50
V
kΩ
1/2)
DIGITAL INPUTS (MUTE, SHDN, HPS_EN, GAINA/B, IN1
Input Voltage High
VIH
Input Voltage Low
VIL
2
0.8
V
V
Input Leakage Current
IIN
±1
µA
HEADPHONE SENSE INPUT (HPS)
0.9 x
VDD
Input Voltage High
VIH
V
Input Voltage Low
VIL
0.7 x
VDD
V
Input Leakage Current
IIN
±1
µA
_______________________________________________________________________________________
3
MAX9760–MAX9763
ELECTRICAL CHARACTERISTICS (continued)
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ELECTRICAL CHARACTERISTICS (continued)
(VDD = PVDD = 5.0V, GND = PGND = 0V, SHDN = 5V, CBIAS = 1µF, RIN = RF = 15kΩ, RL = ∞. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
V
2-WIRE SERIAL INTERFACE (SCL, SDA, ADD, INT) (MAX9760/MAX9762)
Input Voltage High
VIH
Input Voltage Low
VIL
2.6
Input Hysteresis
V
0.2
V
Input High Leakage Current
IIH
VIN = 5V
±1
µA
Input Low Leakage Current
IIL
VIN = 0V
±1
µA
Input Capacitance
CIN
Output Voltage Low
VOL
IOL = 3mA
0.4
V
Output Current High
IOH
VOH = 5V
1
µA
400
kHz
10
pF
TIMING CHARACTERISTICS (MAX9760/MAX9762)
Serial Clock Frequency
fSCL
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
µs
START Condition Hold Time
tHD:STA
0.6
µs
START Condition Setup Time
tSU:STA
0.6
µs
tLOW
1.3
µs
µs
Clock Period Low
Clock Period High
tHIGH
0.6
Data Setup Time
tSU:DAT
100
Data Hold Time
tHD:DAT
(Note 4)
0
0.9
µs
Receive SCL/SDA Rise Time
tr
(Note 5)
20 +
0.1CB
300
ns
Receive SCL/SDA Fall Time
tf
(Note 5)
20 +
0.1CB
300
ns
Transmit SDA Fall Time
tf
(Note 5)
20 +
0.1CB
250
ns
tSP
(Note 6)
Pulse Width of Suppressed
Spike
ns
50
ns
All devices are 100% production tested at +25°C. All temperature limits are guaranteed by design.
PSRR is specified with the amplifier inputs connected to GND through RIN and CIN.
Refer to the SVDD section.
A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling
edge.
Note 5: CB = total capacitance of one of the bus lines in picofarads. Device tested with CB = 400pF. 1kΩ pullup resistors connected
from SDA/SCL to VDD.
Note 6: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.
Note 1:
Note 2:
Note 3:
Note 4:
4
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
RL = 3Ω
AV = 2V/V
RL = 3Ω
AV = 4V/V
1
RL = 4Ω
AV = 2V/V
0.01
THD+N (%)
POUT = 1W
POUT = 500mW
0.1
THD+N (%)
0.1
THD+N (%)
0.1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
MAX9760 toc02
1
MAX9760 toc01
1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
POUT = 500mW POUT = 1W
POUT = 250mW P
OUT = 500mW
0.01
POUT = 2W
0.01
POUT = 2.5W
POUT = 2W
POUT = 2.5W
0.001
100
1k
10k
100k
0.001
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
RL = 8Ω
AV = 2V/V
RL = 8Ω
AV = 4V/V
POUT = 250mW POUT = 500mW
0.01
THD+N (%)
0.1
THD+N (%)
0.1
THD+N (%)
0.1
1
POUT = 250mW P
OUT = 500mW
0.01
POUT = 250mW
POUT = 500mW
0.01
POUT = 2W
POUT = 1W
0.001
0.001
100
1k
10k
100k
POUT = 1.2W
POUT = 1W
POUT = 1W POUT = 1.2W
10
MAX9760 toc06
RL = 4Ω
AV = 4V/V
MAX9760 toc05
1
MAX9760 toc04
1
0.001
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
f = 10kHz
f = 20Hz
1
f = 10kHz
f = 1kHz
0.1
0.01
f = 1kHz
1
1
0.1
2
OUTPUT POWER (W)
3
4
f = 10kHz
f = 1kHz
0.01
f = 20Hz
0.001
0
10
f = 20Hz
0.001
MAX9760 toc09
10
AV = 2V/V
RL = 4Ω
THD+N (%)
1
0.01
AV = 4V/V
RL = 3Ω
THD+N (%)
10
100
MAX9760 toc08
AV = 2V/V
RL = 3Ω
0.1
100
MAX9760 toc07
100
THD+N (%)
POUT = 2W
POUT = 1W
0.001
10
MAX9760 toc03
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
0.001
0
1
2
OUTPUT POWER (W)
3
4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT POWER (W)
_______________________________________________________________________________________
5
MAX9760–MAX9763
Typical Operating Characteristics
(VDD = PVDD = 5V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25°C, unless otherwise noted.)
10
THD+N (%)
f = 10kHz
1
AV = 2V/V
RL = 8Ω
f = 1kHz
0.1
100
AV = 4V/V
RL = 8Ω
10
THD+N (%)
10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
MAX9760 toc11
AV = 4V/V
RL = 4Ω
THD+N (%)
100
MAX9760 toc10
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
1
f = 10kHz
0.1
MAX9760 toc12
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
1
f = 10kHz
0.1
f = 1kHz
f = 1kHz
0.01
0.01
0.01
f = 20Hz
f = 20Hz
f = 20Hz
0.001
0.001
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.001
0.5
0
1.0
1.5
2.0
1.0
OUTPUT POWER (W)
OUTPUT POWER vs. TEMPERATURE
(SPEAKER MODE)
OUTPUT POWER vs. TEMPERATURE
(SPEAKER MODE)
OUTPUT POWER vs. TEMPERATURE
(SPEAKER MODE)
THD+N = 1%
2
1
THD+N = 10%
3
THD+N = 1%
2
THD+N = 10%
OUTPUT POWER (W)
OUTPUT POWER (W)
3
2.0
1
THD+N = 1%
1.0
f = 1kHz
RL = 4Ω
f = 1kHz
RL = 8Ω
0
10
35
60
85
0
-40
TEMPERATURE (°C)
-15
10
35
85
60
-15
f = 1kHz
1.6
1.4
POWER DISSIPATION (W)
THD+N = 10%
35
60
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)
MAX9760 toc16
5
10
TEMPERATURE (°C)
OUTPUT POWER vs. LOAD RESISTANCE
(SPEAKER MODE)
4
-40
TEMPERATURE (°C)
3
THD+N = 1%
2
1
MAX9760 toc17
-15
OUTPUT POWER (W)
1.5
0.5
f = 1kHz
RL = 3Ω
0
1.2
1.0
0.8
0.6
0.4
RL = 4Ω
f = 1kHz
0.2
0
0
1
10
100
1k
LOAD RESISTANCE (Ω)
10k
2.0
MAX9760 toc15
4
MAX9760 toc13
THD+N = 10%
6
1.5
OUTPUT POWER (W)
4
-40
0.5
0
OUTPUT POWER (W)
MAX9760 toc14
0
OUTPUT POWER (W)
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
100k
0
0.5
1.0
1.5
2.0
OUTPUT POWER (W)
_______________________________________________________________________________________
2.5
85
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (SPEAKER MODE)
CROSSTALK vs. FREQUENCY
(SPEAKER MODE)
VRIPPLE = 200mVP-P
50
MAX9760 toc19
-40
MAX9760 toc18
40
VIN = 200mVP-P
RL = 8Ω
-50
-60
CROSSTALK (dB)
PSRR (dB)
60
70
80
-70
RIGHT TO LEFT
-80
-90
-100
LEFT TO RIGHT
90
-110
100
-120
10
100
1k
10k
100k
10
100
FREQUENCY (Hz)
1k
10k
100k
FREQUENCY (Hz)
ENTERING SHUTDOWN (SPEAKER MODE)
EXITING SHUTDOWN (SPEAKER MODE)
MAX9760 toc20
MAX9760 toc21
SHDN
2V/div
SHDN
2V/div
OUT_+
AND OUT_-
1V/div
OUT_+
AND OUT_-
1V/div
OUT_+
- OUT_-
200mV/div
OUT_+
- OUT_-
200mV/div
100ms/div
RL = 8Ω
INPUT AC-COUPLED TO GND
100ms/div
RL = 8Ω
INPUT AC-COUPLED TO GND
MAX9760 toc22
1
RL = 16Ω
AV = 1V/V
VDD
2V/div
1V/div
0.1
THD+N (%)
OUT_+
AND OUT_-
POUT = 25mW
0.01
0.001
OUT_+
- OUT_-
MAX9760 toc23
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
ENTERING POWER-DOWN
(SPEAKER MODE)
POUT = 50mW
POUT = 100mW
POUT = 150mW
200mV/div
0.0001
100ms/div
RL = 8Ω
INPUT AC-COUPLED TO GND
10
100
1k
10k
100k
FREQUENCY (Hz)
_______________________________________________________________________________________
7
MAX9760–MAX9763
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
0.1
1
RL = 32Ω
AV = 1V/V
0.1
1
MAX9760 toc26
RL = 16Ω
AV = 2V/V
MAX9760 toc24
1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
MAX9760 toc25
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
RL = 32Ω
AV = 2V/V
0.001
POUT = 100mW
POUT = 25mW
0.01
POUT = 50mW
0.001
POUT = 150mW
100
1k
100
1k
100k
10k
10
100
1k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
THD+N (%)
f = 20Hz
f = 10kHz
0.1
1
f = 10kHz
0.1
0.01
0.01
0.001
0.001
AV = 1V/V
RL = 32Ω
10
1
1
MAX9760 toc29
AV = 2V/V
RL = 16Ω
10
100
MAX9760 toc28
100
MAX9760 toc27
AV = 1V/V
RL = 16Ω
10
f = 20Hz
f = 10kHz
0.1
f = 20Hz
0.01
f = 1kHz
0.001
f = 1kHz
f = 1kHz
0.0001
0.0001
0
50
100
150
200
250
0.0001
0
300
50
100
150
200
250
300
0
25
50
75
100
125
OUTPUT POWER (mW)
OUTPUT POWER (mW)
OUTPUT POWER (mW)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
OUTPUT POWER vs. TEMPERATURE
(HEADPHONE MODE)
OUTPUT POWER vs. TEMPERATURE
(HEADPHONE MODE)
f = 10kHz
f = 20Hz
0.1
0.01
0.001
200
0.0001
150
100
25
50
75
OUTPUT POWER (mW)
100
125
100
THD+N = 1%
75
50
f = 1kHz
RL = 32Ω
0
0
0
THD+N = 10%
125
25
f = 1kHz
RL = 16Ω
MAX9760 toc332
MAX9760 toc31
THD+N = 1%
50
150
OUTPUT POWER (mW)
f = 1kHz
1
THD+N = 10%
250
OUTPUT POWER (mW)
AV = 2V/V
RL = 32Ω
10
300
MAX9760 toc30
100
8
10k
FREQUENCY (Hz)
100
THD+N (%)
0.0001
10
100k
10k
POUT = 150mW POUT = 100mW
POUT = 150mW
0.0001
10
POUT = 50mW
0.01
0.001
POUT = 100mW
0.0001
POUT = 25mW
THD+N (%)
POUT = 50mW
0.01
THD+N (%)
THD+N (%)
THD+N (%)
0.1
POUT = 25mW
THD+N (%)
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
300
THD+N = 1%
100
80
60
40
20
0
10
100
1k
50
40
30
20
10
RL = 16Ω
f = 1kHz
RL = 32Ω
f = 1kHz
0
0
1
60
POWER DISSIPATION (mW)
THD+N = 10%
200
100
POWER DISSIPATION (mW)
10k
0
50
100
150
0
200
20
40
60
80
100
LOAD RESISTANCE (Ω)
OUTPUT POWER (mW)
OUTPUT POWER (mW)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (HEADPHONE MODE)
CROSSTALK vs. FREQUENCY
(HEADPHONE MODE)
EXITING SHUTDOWN (HEADPHONE MODE)
VRIPPLE = 200mVP-P
50
MAX9760 toc38
-40
MAX9760 toc36
40
MAX9760 toc37
OUTPUT POWER (mW)
500
70
MAX9760 toc34
f = 1kHz
400
120
MAX9760 toc33
600
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)
MAX9760 toc35
OUTPUT POWER vs. LOAD RESISTANCE
(HEADPHONE MODE)
MAX9760–MAX9763
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25°C, unless otherwise noted.)
VIN = 200mVP-P
RL = 16Ω
-50
SHDN
2V/div
CROSSTALK (dB)
-60
PSRR (dB)
60
70
80
-70
-80
1V/div
RIGHT TO LEFT
OUT_+
-90
-100
90
-110
200mV/div
HP JACK
LEFT TO RIGHT
-120
100
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
100ms/div
RL = 16Ω
INPUT AC-COUPLED TO GND
EXITING POWER-DOWN
(HEADPHONE MODE)
ENTERING SHUTDOWN (HEADPHONE MODE)
MAX9760 toc39
MAX9760 toc40
2V/div
SHDN
2V/div
VDD
1V/div
OUT_+
OUT_+
1V/div
200mV/div
HP JACK
100ms/div
RL = 16Ω
INPUT AC-COUPLED TO GND
200mV/div
HP JACK
100ms/div
RL = 16Ω
INPUT AC-COUPLED TO GND
_______________________________________________________________________________________
9
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(SPEAKER MODE)
ENTERING POWER-DOWN
(HEADPHONE MODE)
MAX9760 toc41
MAX9760 toc42
25
TA = +85°C
2V/div
OUT_+
1V/div
20
SUPPLY CURRENT (mA)
VDD
TA = +25°C
15
10
TA = -40°C
5
HP JACK
200mV/div
0
4.50
100ms/div
RL = 16Ω
INPUT AC-COUPLED TO GND
5.00
5.50
5.25
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
10
TA = +85°C
SUPPLY CURRENT (µA)
TA = +85°C
8
6
TA = +25°C
4
TA = -40°C
MAX97960 toc44
20
MAX9760 toc43
12
SUPPLY CURRENT (mA)
4.75
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(HEADPHONE MODE)
TA = +25°C
15
10
TA = -40°C
5
2
0
0
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.50
5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)
EXITING POWER-DOWN
(SPEAKER MODE)
MAX9760 toc46
MAX9760 toc45
0.8
0.7
POWER DISSIPATION (W)
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
VDD
2V/div
OUT_+
AND OUT_-
1V/div
0.6
0.5
0.4
0.3
0.2
OUT_+
- OUT_-
RL = 8Ω
f = 1kHz
0.1
200mV/div
0
0
0.25
0.50
0.75
1.00
OUTPUT POWER (W)
10
1.25
1.50
100ms/div
RL = 8Ω
INPUT AC-COUPLED TO GND
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
PIN
MAX9760
MAX9761
MAX9762
MAX9763
NAME
FUNCTION
QFN
TSSOP
QFN
TSSOP
QFN
TSSOP
QFN
TSSOP
1
26
—
—
1
26
—
—
SDA
Bidirectional Serial Data I/O
2
27
—
—
2
27
—
—
INT
µC Interrupt Output
3
28
3
28
3
28
3
28
VDD
Power Supply
4
1
4
1
4
1
4
1
SVDD
Standby Power Supply. Connect
to a standby power supply that is
always on, or connect to VDD
through a Schottky diode and
bypass with 220µF capacitor to
GND. Short to VDD if clickless
operation is not essential.
5
2
5
2
5
2
5
2
INL1
Left-Channel Input 1
6
3
6
3
6
3
6
3
INL2
Left-Channel Input 2
7
4
7
4
7
4
7
4
GAINLA
Left-Channel Gain Set A
8
5
8
5
8
5
8
5
GAINLB
Left-Channel Gain Set B
9, 13,
23, 27
6, 10,
20, 24
9, 13,
23, 27
6, 10, 20,
24
9, 23,
27
6, 20, 24
9, 23, 27
6, 20, 24
PGND
Power Ground
10
7
10
7
10
7
10
7
OUTL+
Left-Channel Bridged Amplifier
Positive Output. OUTL+ also
serves as the left-channel
headphone amplifier output.
11, 25
8, 22
11, 25
8, 22
11, 25
8, 22
11, 25
8, 22
PVDD
Output Amplifier Power Supply
12
9
12
9
—
—
—
—
OUTL-
Left-Channel Bridged Amplifier
Negative Output
14
11
14
11
14
11
14
11
SHDN
Active-Low Shutdown. Connect
SHDN to VDD for normal operation.
15
12
—
—
15
12
—
—
ADD
Address Select. A logic high sets
the address LSB to 1, a logic low
sets the address LSB to zero.
HPS
Headphone Sense Input. A logic
high configures the device as a
single-ended headphone amp. A
logic low configures the device as
a BTL speaker amp.
16
13
16
13
16
13
16
13
17
14
17
14
17
14
17
14
BIAS
DC Bias Bypass. See BIAS
Capacitor Selection section for
capacitor selection. Connect
CBIAS from BIAS to GND.
18
15
18
15
13
10
13
10
GND
Ground
______________________________________________________________________________________
11
MAX9760–MAX9763
Pin Description
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
MAX9760–MAX9763
Pin Description (continued)
PIN
MAX9760
MAX9761
MAX9762
TSSOP
QFN
TSSOP
QFN
TSSOP
QFN
TSSOP
19
16
19
16
19
16
19
16
20
17
20
17
20
17
20
21
18
21
18
21
18
21
22
19
22
19
22
19
22
NAME
FUNCTION
INR1
Right-Channel Input 1
17
INR2
Right-Channel Input 2
18
GAINRA
Right-Channel Gain Set A
19
GAINRB
Right-Channel Gain Set B
24
21
24
21
24
21
24
21
OUTR+
Right-Channel Bridged Amplifier
Positive Output. OUTR+ also
serves as the right-channel
headphone amplifier output.
26
23
26
23
26
23
26
23
OUTR-
Right-Channel Bridged Amplifier
Negative Output
28
25
—
—
28
25
—
—
SCL
Serial Clock Line
—
—
—
—
12
9
12
9
N.C.
No Connection. Not internally
connected.
—
—
—
—
18
15
18
15
GAINM
Mono Gain Set
—
—
1
26
—
—
1
26
MUTE
Active-High Mute Input
—
—
2
27
—
—
2
27
HPS_EN
Headphone Enable. A logic high
enables HPS. A logic low disables
HPS and the device is always
configured as a BTL speaker amp.
—
—
15
12
—
—
15
12
GAINA/B
Gain Select. A logic low selects
the gain set by GAIN_A. A logic
high selects the gain set by
GAIN_B.
—
—
28
25
—
—
28
25
IN1/2
Input Select. A logic low selects
amplifier input 1. A logic high
selects amplifier input 2.
Detailed Description
The MAX9760–MAX9763 feature 3W BTL speaker
amplifiers, 200mW headphone amplifiers, input multiplexers, headphone sensing, and comprehensive clickand-pop suppression. The MAX9760/ MAX9761 are
stereo BTL/headphone amplifiers. The MAX9762/
MAX9763 are mono BTL/stereo headphone amplifiers.
The MAX9760/MAX9762 are controlled through an I2Ccompatible, 2-wire serial interface. The MAX9761/
MAX9763 are controlled through five logic inputs:
MUTE, SHDN, HPS_EN, GAINA/B, and IN1/2 (see
Selector Guide). The MAX9760–MAX9763 feature
exceptional PSRR (100dB at 1kHz), allowing these
12
MAX9763
QFN
devices to operate from noisy digital supplies without
the need for a linear regulator.
The speaker amplifiers use a BTL configuration. The
signal path is composed of an input amplifier and an
output amplifier. Resistor RIN sets the input amplifier’s
gain, and resistor RF sets the output amplifier’s gain.
The output of these two amplifiers serves as the input to
a slave amplifier configured as an inverting unity-gain
follower. This results in two outputs, identical in magnitude, but 180° out of phase. The overall gain of the
speaker amplifiers is twice the product of the two
amplifier gains (see Gain-Setting Resistor section). A
feature of this architecture is that there is no phase
inversion from input to output.
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
15kΩ
MAX9760
IN_1
AUDIO
INPUT
30kΩ
IN_2
Figure 1. Using the Input Multiplexer for Gain Setting
When configured as a headphone (single-ended) amplifier, the slave amplifier is disabled, muting the speaker
and the main amplifier drives the headphone. The
MAX9760–MAX9763 can deliver 3W of continuous average power into a 3Ω load with less than 1% THD+N in
speaker mode, and 200mW of continuous average
power into a 16Ω load with less than 1% THD+N in
headphone mode. These devices also feature thermal
overload protection.
Mono Mode
The MAX9762/MAX9763 are 3W mono speaker amplifiers, 200mW stereo headphone amplifiers, and a
mixer/attenuator (see the MAX9762/MAX9763 Functional
Diagram). In speaker (mono) mode, the mixer/attenuator
combines the two stereo inputs (INL_ and INR_) and
attenuates the resultant signal by a factor of 2. This
allows for full reproduction of a stereo signal through a
single speaker, while maintaining optimum headroom.
The resistor connected between GAINM and OUTR+,
sets the gain of the devices in speaker mode (see the
MAX9762 Functional Diagram). This allows the speaker
amplifier to have a different gain and feedback network
from the headphone amplifier.
BIAS
These devices operate from a single 5V supply, and
feature an internally generated, power-supply independent, common-mode bias voltage of 2.5V referenced to
GND. BIAS provides both click-and-pop suppression
and sets the DC bias level for the audio outputs. BIAS
is internally connected to the noninverting input of each
speaker amplifier (see Typical Application Circuit/
Functional Diagram). Choose the value of the bypass
capacitor as described in the BIAS Capacitor section.
No external load should be applied to BIAS. Any load
lowers the BIAS voltage, affecting the overall performance of the device.
The input multiplexer can also be used to further
expand the number of gain options available from the
MAX9760–MAX9763 family. Connecting the audio
source to the device through two different input resistors (Figure 1) increases the number of gain options
from two to four (MAX9760/MAX9761) and from three to
six (MAX9762/MAX9763). Additionally, the input multiplexer allows a speaker equalization network to be
switched into the speaker signal path. This is typically
useful in optimizing acoustic response from speakers
with small physical dimensions.
Headphone Sense Enable
The HPS pin is enabled by HPS_EN (MAX9762/
MAX9763) or the HPSD bit (MAX9760/MAX9761).
HPSD or HPS_EN determines whether the device is in
automatic detection mode or fixed mode operation (see
Tables 1a and 1b).
Headphone Sense Input (HPS)
A voltage on HPS less than 0.7 ✕ VDD sets the device
to speaker mode. A voltage greater than 0.9 ✕ VDD disables the inverting bridge amplifier (OUT_-), which
mutes the speaker amplifier and sets the device into
headphone mode.
For automatic headphone detection, connect HPS to the
control pin of a 3-wire headphone jack as shown in
Figure 2. With no headphone present, the resistive voltage-divider created by R1 and R2 sets the voltage on
HPS to be less than 0.7 ✕ VDD, setting the device to
speaker mode and the gain setting defaults to GAINA
(MAX9760/MAX9762). When a headphone plug is inserted into the jack, the control pin is disconnected from the
tip contact, and HPS is pulled to VDD through R1, setting
the device into headphone mode and the gain-setting
defaults to GAINB (MAX9760/MAX9762) (see Gain
Select section). Place a resistor in series with the control
pin and HPS (R3) to prevent any audio signal from coupling into HPS when the device is in speaker mode.
Shutdown
The MAX9760–MAX9763 feature a 10µA, low-power
shutdown mode that reduces quiescent current consumption and extends battery life. The drive amplifiers
and bias circuitry are disabled, the amplifier outputs
(OUT_) go high impedance, and BIAS is driven to
______________________________________________________________________________________
13
MAX9760–MAX9763
Input Multiplexer
Each amplifier features a 2:1 input multiplexer, allowing
input selection between two stereo sources. Both multiplexers are controlled by bit 1 in the control register
(MAX9760/MAX9762) or by the IN1/2 pin (MAX9761/
MAX9763). A logic low selects input IN_1 and a logic
high selects input IN_2.
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
GND. Driving SHDN low places the devices into shutdown mode, disables the interface, and resets the I2C
registers to a default state. A logic high on SHDN
enables the devices.
VDD
MAX9760–
MAX9763
HPS
MAX9760/MAX9762 Software Shutdown
A logic high on bit 0 of the SHDN register places the
MAX9760/MAX9762 in shutdown mode. A logic low
enables the device. The digital section of the
MAX9760/MAX9762 remains active when the device is
shut down through the interface. All devices feature a
logic low on the SHDN input.
MUTE
All devices feature a mute mode. When the device is
muted, the input is disconnected from the amplifiers.
MUTE does not shut down the device.
MAX9760/MAX9762 MUTE
The MAX9760/MAX9762 MUTE mode is selected by
writing to the MUTE register (see the Command Byte
Definitions section). The left and right channels can be
independently muted.
MAX9761/MAX9763 MUTE
The MAX9761/MAX9763 feature an active-high MUTE
input that mutes both channels.
Click-and-Pop Suppression
The MAX9760–MAX9763 feature Maxim’s comprehensive click-and-pop suppression. During startup and
shutdown, the common-mode bias voltage of the amplifiers is slowly ramped to and from the DC bias point
using an S-shaped waveform. In headphone mode, this
waveform shapes the frequency spectrum, minimizing
the amount of audible components present at the headphone. In speaker mode, the BTL amplifiers start up in
the same fashion as in headphone mode. When entering shutdown, both amplifier outputs ramp to GND
quickly and simultaneously. The MAX9760–
MAX9763 can also be connected to a standby power
source that ensures that the device undergoes its full
shutdown cycle even after power has been removed.
Standby Power Supply (SVDD)
The MAX9760–MAX9763 feature a system that provides
clickless power-down when power is inadvertently
removed from the device. SVDD is an optional secondary supply that powers the device through its shutdown cycle when VDD is removed. During this cycle,
the amplifier output DC level slowly ramps to GND,
ensuring clickless power-down. If clickless power-down
is required, connect SVDD to either a secondary power
supply that is always on, or connect a reservoir capacitor from SVDD to GND. SVDD does not need to be con14
R1
680kΩ
R3
47kΩ
OUTL+
OUTR+
R2
10kΩ
Figure 2. HPS Configuration Circuit
Table 1a. HPS Setting (MAX9760/MAX9761)
INPUTS
MODE
MAX9760
GAIN
PATH*
MAX9762
GAIN
PATH*
HPSD
HPS
SPKR/HP
0
0
X
BTL
A
M
0
1
X
SE
B
B
1
X
0
BTL
A or B
M
1
X
1
SE
A or B
A or B
*Note:
A – GAINA path selected
B – GAINB path selected
M – GAINM path selected
A or B – Gain path selected by GAINAB control bit in register
02h
Table 1b. HPS Setting (MAX9762/MAX9763)
INPUTS
MODE
MAX9761
GAIN PATH*
MAX9763
GAIN PATH*
M
HPSEN
HPS
0
X
BTL
A or B
1
0
BTL
A or B
M
1
1
SE
A or B
A or B
*Note:
A or B – Gain path selected by external GAINAB
M – GAINM path selected
nected to either a secondary power supply or reservoir
capacitor for normal device operation. If click-and-pop
suppression during power-down is not required, connect SVDD to VDD directly.
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
MAX9760–MAX9763
SDA
tBUF
tHD, STA
tSU, DAT
tHD, STA
tHD, DAT
tLOW
tSP
tSU, STO
SCL
tHIGH
tHD, STA
tR
tF
REPEATED
START
CONDITION
START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 3. 2-Wire Serial Interface Timing Diagram
The clickless power-down cycle only occurs when the
device is in headphone mode. The speaker mode is
inherently clickless, the differential architecture cancels
the DC shift across the speaker. The MAX9760–
MAX9763 BTL outputs are pulled to GND quickly and
simultaneously, resulting in no audible components. If
the MAX9760–MAX9763 are only used as speaker
amplifiers, then reservoir capacitors or secondary supplies are not necessary.
When using a reservoir capacitor, a 220µF capacitor
provides optimum charge storage for the shutdown
cycle for all conditions. If a smaller reservoir capacitor
is desired, decrease the size of CBIAS. A smaller CBIAS
causes the output DC level to decay at a faster rate,
increasing the audible content at the speaker, but
reducing the duration of the shutdown cycle.
Digital Interface
The MAX9760/MAX9762 feature an I2C/SMBus-compatible 2-wire serial interface consisting of a serial data
line (SDA) and a serial clock line (SCL). SDA and SCL
facilitate bidirectional communication between the
MAX9760/MAX9762 and the master at clock rates up to
400kHz. Figure 3 shows the 2-wire interface timing diagram. The MAX9760/MAX9762 are transmit/receive
slave-only devices, relying upon a master to generate a
clock signal. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to
permit that transfer.
A master device communicates to the MAX9760/
MAX9762 by transmitting the proper address followed
by a command and/or data words. Each transmit
sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted over the bus is 8 bits long and is
always followed by an acknowledge clock pulse.
S
Sr
P
SCL
SDA
Figure 4. START/STOP Conditions
The MAX9760/MAX9762 SDA and SCL amplifiers are
open-drain outputs requiring a pullup resistor (500Ω or
greater) to generate a logic high voltage. Series resistors in line with SDA and SCL are optional. These series
resistors protect the input stages of the devices from
high-voltage spikes on the bus lines, and minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions section). SDA and SCL idle high
when the I2C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 4). A START condition from the master signals
the beginning of a transmission to the MAX9760/
______________________________________________________________________________________
15
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always generates ACK. The MAX9760/MAX9762 generate an ACK
when receiving an address or data by pulling SDA low
during the night clock period. When transmitting data,
the MAX9760/MAX9762 wait for the receiving device to
generate an ACK. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful
data transfer, the bus master should reattempt communication at a later time.
SCL
SDA
STOP
START
LEGAL STOP CONDITION
SCL
Slave Address
The bus master initiates communication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9760/
MAX9762 wait for a START condition followed by its
slave address. The LSB of the address word is the
Read/Write (R/W) bit. R/W indicates whether the master
is writing to or reading from the MAX9760/MAX9762
(R/W = 0 selects the write condition, R/W = 1 selects
the read condition). After receiving the proper address,
the MAX9760/MAX9762 issue an ACK by pulling SDA
low for one clock cycle.
SDA
START
ILLEGAL
STOP
ILLEGAL EARLY STOP CONDITION
Figure 5. Early STOP Condition
S
A6
A5
A4
A3
A2
A1
A0
R/W
Figure 6. Slave Address Byte Definition
MAX9762. The master terminates transmission by issuing the STOP condition, this frees the bus. If a REPEATED START condition is generated instead of a STOP
condition, the bus remains active.
Early STOP Conditions
The MAX9760/MAX9762 recognize a STOP condition at
any point during the transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 5). This condition is not a legal I2C format,
at least one clock pulse must separate any START and
STOP conditions.
REPEATED START Conditions
A REPEATED START (S r ) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S r may also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX9760/
MAX9762 serial interface supports continuous write
operations with or without an Sr condition separating
them. Continuous read operations require Sr conditions
because of the change in direction of data flow.
16
The MAX9760/MAX9762 have a factory-/user-programmed address. Address bits A6–A2 are preset,
while A0 and A1 is set by ADD. Connect ADD to either
VDD, GND, SCL, or SDA to change the last 2 bits of the
slave address (Table 2).
Write Data Format
There are three registers that configure the
MAX9760/MAX9762: the MUTE register, SHDN register,
and control register. In write data mode (R/W = 0), the
register address and data byte follow the device
address (Figure 7).
MUTE Register
The MUTE register (01hex) is a read/write register that
sets the MUTE status of the device. Bit 3 (MUTEL) of
the MUTE register controls the left channel, bit 4
(MUTER) controls the right channel. A logic high mutes
the respective channel, a logic low brings the channel
out of mute.
SHDN Register
The SHDN register (02hex) is a read/write register that
controls the power-up state of the device. A logic high
in bit 0 of the SHDN register shuts down the device; a
logic low turns on the device. A logic high is required in
bits 2 to 7 to reset all registers to their default settings.
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ADDRESS
WR
ACK
COMMAND
7 BITS
I2C SLAVE ADDRESS.
SELECTS DEVICE.
S
ADDRESS
ACK
8 BITS
DATA
WR
ACK
COMMAND
ACK
REGISTER ADDRESS.
SELECTS REGISTER
TO BE READ.
SELECTS DEVICE.
1
REGISTER DATA
S
ADDRESS
8 BITS
I2C SLAVE ADDRESS.
P
8 BITS
REGISTER ADDRESS.
SELECTS REGISTER TO BE
WRITTEN TO.
7 BITS
ACK
MAX9760–MAX9763
S
WR
7 BITS
I2C SLAVE ADDRESS.
SELECTS DEVICE.
ACK
DATA
P
8 BITS
1
DATA FROM
SELECTED REGISTER
Figure 7. Write/Read Data Format Example
Table 2. I2C Slave Addresses
Table 4. SHDN Register Format
2
ADD CONNECTION
I C ADDRESS
GND
100 1000
VDD
100 1001
SDA
100 1010
SCL
100 1011
BIT
7
Table 3. MUTE Register Format
REGISTER
ADDRESS
REGISTER
ADDRESS
0000 0001
BIT
NAME
VALUE
DESCRIPTION
7
X
Don’t Care
—
6
X
Don’t Care
—
5
X
Don’t Care
—
4
MUTER
0*
Unmute right channel
1
Mute right channel
3
MUTEL
0*
Unmute left channel
1
Mute left channel
2
X
Don’t Care
—
1
X
Don’t Care
—
0
X
Don’t Care
—
*Default state.
Control Register
The control register (03hex) is a read/write register that
determines the device configuration. Bit 1 (IN1/IN2)
controls the input multiplexer, a logic high selects input
1, a logic low selects input 2. Bit 2 (HPS_D) controls the
headphone sensing. A logic low configures the device
NAME
RESET
6
RESET
5
RESET
4
RESET
3
RESET
2
RESET
1
X
0
SHDN
0000 0010
VALUE
DESCRIPTION
0*
—
1
Reset device
0*
—
1
Reset device
0*
—
1
Reset device
0*
—
1
Reset device
0*
—
1
Reset device
0*
—
1
Reset device
Don’t Care
—
0*
Normal operation
1
Shutdown
*Default state.
in automatic headphone detection mode. A logic high
disables the HPS input. Bit 3 (GAINA/B) controls the
gain-select multiplexer. A logic low selects GAINA. A
logic high selects GAINB. GAINA/B is ignored when
HPS_D = 0. Bit 4 (SPKR/HP) selects the amplifier operating mode when HPS_D = 1. A logic high selects
speaker mode and a logic low selects headphone
mode.
______________________________________________________________________________________
17
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Table 5. Control Register Format
REGISTER
ADDRESS
0000 0011
BIT
NAME
VALUE
DESCRIPTION
7
X
Don’t Care
—
6
X
Don’t Care
—
5
X
Don’t Care
—
0*
Speaker mode selected
1
Headphone mode
selected
0*
Gain-setting A selected
1
Gain-setting B selected
0*
Automatic headphone
detection enabled
1
Automatic headphone
detection disabled
(HPS ignored).
0*
Input 1 selected
1
Input 2 selected
4
SPKR/HP
3
GAINA/B
2
HPS_D
1
IN1/IN2
0
X
Don’t Care
—
Read Data Format
In read mode (R/W = 1), the MAX9760/MAX9762 write
the contents of the selected register to the bus. The
direction of the data flow reverses following the
address acknowledge by the MAX9760/MAX9761. The
master device reads the contents of all registers,
including the read-only status register. Table 6 shows
the status register format.
Interrupt Output (INT)
The MAX9760/MAX9762 include an interrupt output
(INT) that can indicate to a master device that an event
has occurred. INT is triggered when the state of HPS
changes. During normal operation, INT idles high. If a
headphone is inserted/removed from the jack and that
action is detected by HPS, INT pulls the line low. INT
remains low until a read data operation is executed.
I2C Compatibility
The MAX9760/MAX9762 are compatible with existing I2C
systems. SCL and SDA are high-impedance inputs; SDA
has an open drain that pulls the data line low during the
ninth clock pulse. The communication protocol supports
the standard I2C 8-bit communications. The general call
address is ignored. The MAX9760/MAX9762 addresses
are compatible with the 7-bit I2C addressing protocol
only. No 10-bit formats are supported.
18
VOUT(P-P)
+1
2 x VOUT(P-P)
VOUT(P-P)
-1
Figure 8. Bridge-Tied Load Configuration
Applications Information
BTL Speaker Amplifiers
The MAX9760–MAX9763 feature speaker amplifiers
designed to drive a load differentially, a configuration
referred to as bridge-tied load (BTL). The BTL configuration (Figure 8) offers advantages over the singleended configuration, where one side of the load is
connected to ground. Driving the load differentially
doubles the output voltage compared to a singleended amplifier under similar conditions. Thus, the
devices’ differential gain is twice the closed-loop gain
of the input amplifier. The effective gain is given by:
A VD = 2 ×
RF
RIN
Substituting 2 x VOUT(P-P) for VOUT(P-P) into the following equations yields four times the output power due to
doubling of the output voltage:
VRMS =
VOUT(P−P)
2 2
2
V
POUT = RMS
RL
Since the differential outputs are biased at midsupply,
there is no net DC voltage across the load. This eliminates the need for DC-blocking capacitors required for
single-ended amplifiers. These capacitors can be
large, expensive, consume board space, and degrade
low-frequency performance.
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
MAX9760–MAX9763
Table 6. Status Register Format
REGISTER ADDRESS
BIT
NAME
7
THRM
6
0000 0000
VALUE
0
AMPR-
5
AMPR+
4
AMPL-
DESCRIPTION
Device temperature below thermal limit
1
Device temperature exceeding thermal limit
0
OUTR- current below current limit
1
OUTR- current exceeding current limit
0
OUTR+ current below current limit
1
OUTR+ current exceeding current limit
0
OUTL- current below current limit
1
OUTL- current exceeding current limit
0
OUTL+ current below current limit
1
OUTL+ current exceeding current limit
0
Device in speaker mode
1
Device in headphone mode
3
AMPL+
2
HPSTS
1
X
Don’t Care
—
0
X
Don’t Care
—
When the MAX9760/MAX9762 are configured to automatically detect the presence of a headphone jack, the
device defaults to gain setting A when the device is in
speaker mode. When the MAX9762/MAX9763 are configured as speaker amplifiers, the gain setting defaults
to the mono setting (GAINM).
Single-Ended Headphone Amplifier
The MAX9760–MAX9763 can be configured as singleended headphone amplifiers through software or by
sensing the presence of a headphone plug (HPS). In
headphone mode, the inverting output of the BTL
amplifier is disabled, muting the speaker. The gain is
1/2 that of the device in speaker mode, and the output
power is reduced by a factor of 4.
In headphone mode, the load must be capacitively
coupled to the device, blocking the DC bias voltage
from the load (see Typical Application Circuit).
Power Dissipation and Heat Sinking
Under normal operating conditions, the MAX9760–
MAX9763 can dissipate a significant amount of power.
The maximum power dissipation for each package is
given in the Absolute Maximum Ratings section under
Continuous Power Dissipation or can be calculated by
the following equation:
PDISSPKG(MAX) =
TJ(MAX) − TA
where TJ(MAX) is +150°C, TA is the ambient temperature, and θJA is the reciprocal of the derating factor in
°C/W as specified in the Absolute Maximum Ratings
section. For example, θ JA of the QFN package is
+42°C/W.
The increase in power delivered by the BTL configuration directly results in an increase in internal power dissipation over the single-ended configuration. The
maximum power dissipation for a given VDD and load is
given by the following equation:
PDISS(MAX) =
2VDD2
π 2RL
If the power dissipation for a given application exceeds
the maximum allowed for a given package, either reduce
VDD, increase load impedance, decrease the ambient
temperature, or add heat sinking to the device. Large
output, supply, and ground PC board traces improve the
maximum power dissipation in the package.
Thermal overload protection limits total power dissipation in these devices. When the junction temperature
exceeds +160°C, the thermal protection circuitry disables the amplifier output stage. The amplifiers are
enabled once the junction temperature cools by 15°C.
This results in a pulsing output under continuous thermal-overload conditions as the device heats and cools.
θJA
______________________________________________________________________________________
19
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Component Selection
Gain-Setting Resistors
External feedback components set the gain of the
MAX9760–MAX9763. Resistor RIN sets the gain of the
input amplifier (AVIN) and resistor RF sets the gain of
the second stage amplifier (AVOUT):
10kΩ
RF
A VIN = −
, A VOUT = − 10kΩ
RIN
Combining AVIN and AVOUT, RIN and RF set the singleended gain of the device as follows:
RF
10kΩ
RF
A V = A VIN × A VOUT = −
× − 10kΩ = + R
IN
RIN
As shown, the two-stage amplifier architecture results
in a noninverting gain configuration, preserving
absolute phase through the MAX9760–MAX9763. The
gain of the device in BTL mode is twice that of the single-ended mode. Choose RIN between 10kΩ and 15kΩ
and RF between 15kΩ and 100kΩ.
Input Filter
The input capacitor (CIN), in conjunction with RIN, forms
a highpass filter that removes the DC bias from an
incoming signal. The AC-coupling capacitor allows the
amplifier to bias the signal to an optimum DC level.
Assuming zero-source impedance, the -3dB point of
the highpass filter is given by:
f−3dB =
1
2πRINCIN
Choose RIN according to the Gain-Setting Resistors
section. Choose the CIN such that f-3dB is well below
the lowest frequency of interest. Setting f-3dB too high
affects the amplifier’s low-frequency response. Use
capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic.
Capacitors with high-voltage coefficients, such as
ceramics, may result in an increased distortion at low
frequencies.
Other considerations when designing the input filter
include the constraints of the overall system,
the actual frequency band of interest, and click-andpop suppression.
20
Output-Coupling Capacitor
The MAX9760/MAX9763 require output-coupling
capacitors to operate in single-ended (headphone)
mode. The output-coupling capacitor blocks the DC
component of the amplifier output, preventing DC current from flowing to the load. The output capacitor and
the load impedance form a highpass filter with a -3dB
point determined by:
f−3dB =
1
2πRLCOUT
As with the input capacitor, choose COUT such that
f-3dB is well below the lowest frequency of interest.
Setting f-3dB too high affects the amplifier‘s low-frequency response.
Load impedance is a concern when choosing COUT.
Load impedance can vary, changing the -3dB point of
the output filter. A lower impedance increases the corner frequency, degrading low-frequency response.
Select COUT such that the worst-case load/COUT combination yields an adequate response. Select capacitors with low ESR to minimize resistive losses and
optimize power transfer to the load.
BIAS Capacitor
BIAS is the output of the internally generated 2.5VDC
bias voltage. The BIAS bypass capacitor, C BIAS ,
improves PSRR and THD+N by reducing power supply
and other noise sources at the common-mode bias
node, and also generates the clickless/popless, startup/shutdown DC bias waveforms for the speaker amplifiers. Bypass BIAS with a 1µF capacitor to GND.
Supply Bypassing
Proper power-supply bypassing ensures low-noise,
low-distortion performance. Place a 0.1µF ceramic
capacitor from V DD to GND. Add additional bulk
capacitance as required by the application, typically
100µF. Bypass PVDD with a 100µF capacitor to GND.
Locate bypass capacitors as close to the device as
possible.
Gain Select
The MAX9760–MAX9763 feature multiple gain settings
on each channel, making available different gain and
feedback configurations. The gain-setting resistor (RF)
is connected between the amplifier output (OUT_+)
and the gain setpoint (GAIN_). An internal multiplexer
switches between the different feedback resistors
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
RF2
RF1
GAIN
RF1
RIN
RIN
RF1 RF2
RIN
VBIAS
FREQUENCY
1
2π RF2 CF
Figure 9. Bass Boost Circuit
Figure 10. Bass Boost Response
depending on the status of the gain control input. The
stereo MAX9760/MAX9761 feature two gain options per
channel. The mono MAX9762/MAX9763 feature two
gain options per single-ended channel, and a single
gain option for the mono speaker amplifier (see Tables
1a and 1b for the gain-setting options).
The MAX9762 defaults to GAINM in speaker mode and
can switch between GAINA and GAINB in headphone
mode.
Assuming RF1 = RF2, then RF(EFF) at low frequencies is
twice that of RF(EFF) at high frequencies (Figure 10).
Thus, the amplifier has more gain at lower frequencies,
boosting the system’s bass response. Set the gain rolloff frequency based upon the response of the speaker
and enclosure.
Bass Boost Circuit
Headphones typically have a poor low-frequency
response due to speaker and enclosure size limitations.
A bass boost circuit compensates the poor low-frequency response (Figure 9). At low frequencies, the capacitor CF is an open circuit, and the effective impedance in
the feedback loop (RF(EFF)) is RF(EFF) = RF1.
At the frequency:
1
2πRF2CF
where the impedance, CF, begins to decrease, and at
high frequencies, the CF is a short circuit. Here the
impedance of the feedback loop is:
Layout and Grounding
Good PC board layout is essential for optimizing performance. Use large traces for the power-supply inputs
and amplifier outputs to minimize losses due to parasitic trace resistance, as well as route heat away from
the device. Good grounding improves audio performance, minimizes crosstalk between channels, and
prevents any digital switching noise from coupling into
the audio signal. If digital signal lines must cross over
or under audio signal lines, ensure that they cross perpendicular to each other.
The MAX9760–MAX9763 QFN and TSSOP-EP packages feature exposed thermal pads on their undersides. This pad lowers the package’s thermal
resistance by providing a direct heat conduction path
from the die to the printed circuit board. Connect the
pad to signal ground by using a large pad, or multiple
vias to the ground plane.
R × RF2
RF(EFF) = F1
RF1 + RF2
______________________________________________________________________________________
21
MAX9760–MAX9763
CF
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
MAX9760–MAX9763
Typical Application Circuit
VDD
0.1µF
VDD
BIAS
PVDD
0.047µF
SVDD
1µF
27.4kΩ
33.2kΩ
GAINLB
15kΩ
220µF
10kΩ
GAINLA
15kΩ
AUX_IN
OUT
0.68µF
BIAS
0.68µF
OUTL-
15kΩ
INL2
HPF
MAX4060
OUTL+
INL1
CODEC
0.68µF
MAX9760
15kΩ
INR1
IN+
IN-
OUTR-
0.68µF
15kΩ
INR2
HPF
OUTR+
VDD
15kΩ
220µF
VDD
GAINRA
33.2kΩ
1kΩ
1kΩ
10kΩ
GAINRB
27.4kΩ
10kΩ
SCL
0.047µF
SDA
MICROCONTROLLER
ADD
47kΩ
HPS
INT
SHDN
22
______________________________________________________________________________________
680kΩ
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
VDD
PVDD VDD
SVDD
GAIN
SET
MUX
10kΩ
AUDIO
INPUT
AUDIO
INPUT
INL1
INL2
BIAS
2:1
INPUT
MUX
GAINLB
GAINLA
10kΩ
OUTL+
10kΩ
BIAS
10kΩ
OUTL-
GAIN
SET
MUX
10kΩ
AUDIO
INPUT
AUDIO
INPUT
INR1
INR2
2:1
INPUT
MUX
GAINRB
GAINRA
10kΩ
OUTR+
10kΩ
SHDN
SCL
SDA
ADD
INT
10kΩ
OUTR-
LOGIC
HPS
MAX9760
HPS
GND
______________________________________________________________________________________
23
MAX9760–MAX9763
Functional Diagrams
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
MAX9760–MAX9763
Functional Diagrams (continued)
PVDD VDD
SVDD
GAIN
SET
MUX
10kΩ
INL1
INL2
BIAS
2:1
INPUT
MUX
GAINLB
GAINLA
10kΩ
OUTL+
10kΩ
BIAS
10kΩ
OUTL-
GAIN
SET
MUX
10kΩ
INR1
INR2
2:1
INPUT
MUX
GAINRB
GAINRA
10kΩ
OUTR+
10kΩ
SHDN
MUTE
HP_EN
GAINA/B
IN1/IN2
10kΩ
OUTRLOGIC
HPS
MAX9761
24
HPS
GND
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
PVDD VDD
SVDD
GAIN
SET
MUX
10kΩ
INR1
INR2
BIAS
2:1
INPUT
MUX
GAINRB
GAINRA
GAINM
10kΩ
MIXER
OUTR+
10kΩ
BIAS
10kΩ
OUTR-
GAIN
SET
MUX
10kΩ
INL1
INL2
SHDN
SCL
SDA
ADD
INT
2:1
INPUT
MUX
GAINLB
GAINLA
10kΩ
OUTL
LOGIC
HPS
MAX9762
HPS
GND
______________________________________________________________________________________
25
MAX9760–MAX9763
Functional Diagrams (continued)
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
MAX9760–MAX9763
Functional Diagrams (continued)
PVDD VDD
SVDD
GAIN
SET
MUX
10kΩ
INR1
INR2
BIAS
2:1
INPUT
MUX
GAINRB
GAINRA
GAINM
10kΩ
MIXER
OUTR+
10kΩ
BIAS
10kΩ
OUTR-
GAIN
SET
MUX
10kΩ
INL1
INL2
SHDN
HP_EN
MUTE
IN1/IN2
GAINA/B
2:1
INPUT
MUX
GAINLA
10kΩ
OUTL
LOGIC
MAX9763
26
GAINLB
HPS
HPS
GND
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
PVDD
OUTR+
PGND
GAINRB
25
24
23
22
GAINRB
22
OUTR-
PGND
23
26
OUTR+
24
PGND
PVDD
25
27
OUTR-
26
IN1/2
PGND
27
TOP VIEW
28
SCL
28
TOP VIEW
MUTE
1
21
GAINRA
INR2
HPS_EN
2
20
INR2
19
INR1
VDD
3
19
INR1
18
GND
SVDD
4
18
GND
5
17
BIAS
INL1
5
17
BIAS
INL2
6
16
HPS
INL2
6
16
HPS
GAINLA
7
15
ADD
GAINLA
7
15
GAINA/B
SDA
1
21
GAINRA
INT
2
20
VDD
3
SVDD
4
INL1
8
9
10
11
12
13
14
8
9
10
11
12
13
14
PGND
OUTL+
PVDD
OUTL-
PGND
SHDN
GAINLB
PGND
OUTL+
PVDD
OUTL-
PGND
SHDN
MAX9761
GAINLB
MAX9760
THIN QFN
THIN QFN
SVDD 1
28 VDD
SVDD 1
28 VDD
INL1 2
27 INT
INL1 2
27 HPS_EN
INL2 3
26 SDA
INL2 3
26 MUTE
25 SCL
GAINLA 4
25 IN/1V2
24 PGND
GAINLB 5
23 OUTR-
PGND 6
OUTL+ 7
22 PVDD
OUTL+ 7
22 PVDD
PVDD 8
21 OUTR+
PVDD 8
21 OUTR+
OUTL- 9
20 PGND
OUTL- 9
20 PGND
PGND 10
19 GAINRB
PGND 10
19 GAINRB
18 GAINRA
SHDN 11
18 GAINRA
GAINLA 4
GAINLB 5
PGND 6
MAX9760
SHDN 11
24 PGND
MAX9761
23 OUTR-
17 INR2
GAIN/AVB 12
17 INR2
HPS 13
16 INR1
HPS 13
16 INR1
BIAS 14
15 GND
BIAS 14
15 GND
ADD 12
TSSOP
TSSOP
______________________________________________________________________________________
27
MAX9760–MAX9763
Pin Configurations
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
20
VDD
3
SVDD
4
INL1
PVDD
OUTR+
PGND
GAINRB
25
24
23
22
GAINRB
22
2
OUTR-
PGND
23
INT
26
OUTR+
24
GAINRA
PGND
PVDD
25
21
27
OUTR-
26
1
IN1/2
PGND
27
SDA
MUTE
1
21
GAINRA
INR2
HPS_EN
2
20
INR2
19
INR1
VDD
3
19
INR1
18
GAINM
SVDD
4
18
GAINM
5
17
BIAS
INL1
5
17
BIAS
INL2
6
16
HPS
INL2
6
16
HPS
GAINLA
7
15
ADD
GAINLA
7
15
GAINA/B
9
10
11
12
13
14
8
9
10
11
12
13
14
PGND
OUTL+
PVDD
N.C.
GND
SHDN
GAINLB
PGND
OUTL+
PVDD
N.C.
GND
SHDN
MAX9763
8
MAX9762
THIN QFN
THIN QFN
SVDD 1
28 VDD
SVDD 1
28 VDD
INL1 2
27 INT
INL1 2
27 HPS_EN
INL2 3
26 SDA
INL2 3
26 MUTE
GAINLA 4
25 SCL
GAINLA 4
25 IN1/2
GAINLB 5
24 PGND
GAINLB 5
23 OUTR-
PGND 6
OUTL+ 7
22 PVDD
OUTL+ 7
22 PVDD
PVDD 8
21 OUTR+
PVDD 8
21 OUTR+
PGND 6
MAX9762
24 PGND
MAX9763
23 OUTR-
N.C. 9
20 PGND
N.C. 9
20 PGND
GND 10
19 GAINRB
GND 10
19 GAINRB
SHDN 11
18 GAINRA
SHDN 11
18 GAINRA
GAINA/B 12
17 INR2
16 INR1
HPS 13
16 INR1
15 GAINM
BIAS 14
15 GAINM
ADD 12
17 INR2
HPS 13
BIAS 14
TSSOP
28
TOP VIEW
28
SCL
28
TOP VIEW
GAINLB
MAX9760–MAX9763
Pin Configurations (continued)
TSSOP
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
TEMP RANGE
PIN-PACKAGE
MAX9761ETI
PART
-40°C to +85°C
28 Thin QFN-EP*
MAX9761EUI
-40°C to +85°C
28 TSSOP-EP*
MAX9762ETI
-40°C to +85°C
28 Thin QFN-EP*
MAX9762EUI
-40°C to +85°C
28 TSSOP-EP*
MAX9763ETI
-40°C to +85°C
28 Thin QFN-EP*
MAX9763EUI
-40°C to +85°C
28 TSSOP-EP*
Chip Information
MAX9760 TRANSISTOR COUNT: 5256
MAX9761 TRANSISTOR COUNT: 2715
MAX9762 TRANSISTOR COUNT: 5046
MAX9763 TRANSISTOR COUNT: 2505
PROCESS: BiCMOS
*EP = Exposed paddle.
Selector Guide
CONTROL INTERFACE
SPEAKER AMPLIFIER
HEADPHONE AMPLIFIER
INPUT MUX
MAX9760
PART
I2C Compatible
Stereo
Stereo
Yes
MAX9761
Parallel
Stereo
Stereo
Yes
2
MAX9762
I C Compatible
Mono
Stereo
Yes
MAX9763
Parallel
Mono
Stereo
Yes
______________________________________________________________________________________
29
MAX9760–MAX9763
Ordering Information (continued)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
0.15 C A
D
b
CL
0.10 M C A B
D2/2
D/2
PIN # 1
I.D.
QFN THIN.EPS
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
k
0.15 C B
PIN # 1 I.D.
0.35x45
E/2
E2/2
CL
(NE-1) X e
E
E2
k
L
DETAIL A
e
(ND-1) X e
CL
CL
L
L
e
e
0.10 C
A
C
0.08 C
A1 A3
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
COMMON DIMENSIONS
DOCUMENT CONTROL NO.
REV.
21-0140
C
1
2
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
30
DOCUMENT CONTROL NO.
REV.
21-0140
C
2
2
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
TSSOP, 4.0,EXP PADS.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX9760–MAX9763
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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