µ
19-0509; Rev 0; 4/06
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
The MAX9777/MAX9778 combine a stereo 3W bridgetied load (BTL) audio power amplifier, stereo singleended (SE) headphone amplifier, headphone sensing,
and a 2:1 input multiplexer all in a tiny 28-pin thin QFN
package. These devices operate from a single 4.5V to
5.5V supply and feature an industry-leading 100dB
PSRR, allowing these devices to operate from noisy
supplies without the addition of a linear regulator. An
ultra-low 0.002% THD+N ensures clean, low-distortion
amplification of the audio signal. Click-and-pop suppression minimizes audible transients on power and
shutdown cycles. Power-saving features include low
4mV V OS (minimizes DC current drain through the
speakers), low 13mA supply current, and a 10µA shutdown mode. A MUTE function allows the outputs to be
quickly enabled or disabled.
A headphone sense input detects the presence of a
headphone jack and automatically configures the
amplifiers for either speaker or headphone mode. In
speaker mode, the amplifiers can deliver up to 3W of
continuous average power into a 3Ω load. In headphone mode, the amplifier can deliver up to 200mW of
continuous average power into a 16Ω load. The gain of
the amplifiers is externally set, allowing maximum flexibility in optimizing output levels for a given load. The
amplifiers also feature a 2:1 input multiplexer, allowing
multiple audio sources to be selected. The multiplexer
can also be used to compensate for limitations in the
frequency response of the loud speakers by selecting
an external equalizer network. The various functions are
controlled by either an I2C-compatible (MAX9777) or
simple parallel control interface (MAX9778).
The MAX9777/MAX9778 are available in a thermally
efficient 28-pin thin QFN package (5mm x 5mm x
0.8mm). These devices have thermal-overload protection (OVP) and are specified over the extended -40°C
to +85°C temperature range.
Features
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Industry-Leading, Ultra-High 100dB PSRR
3W BTL Stereo Speaker Amplifier
200mW Stereo Headphone Amplifier
Low 0.002% THD+N
Click-and-Pop Suppression
ESD-Protected Outputs
Low Quiescent Current: 13mA
Low-Power Shutdown Mode: 10µA
MUTE Function
Headphone Sense Input
Stereo 2:1 Input Multiplexer
Optional 2-Wire, I2C-Compatible or Parallel
Interface
♦ Tiny 28-Pin Thin QFN (5mm x 5mm x 0.8mm)
Package
Ordering Information
PART
CONTROL
INTERFACE
PINPACKAGE
PKG
CODE
MAX9777ETI+
I2C Compatible
28 Thin QFN-EP* T2855-6
MAX9778ETI+
Parallel
28 Thin QFN-EP* T2855-6
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes lead-free package.
*EP = Exposed paddle.
Pin Configurations and Functional Diagrams appear at end
of data sheet.
Simplified Block Diagram
SINGLE SUPPLY
4.5V TO 5.5V
LEFT IN1
Applications
Notebooks
PC Audio Peripherals
Portable DVD Players
Camcorders
Tablet PCs
Multimedia Monitor
LEFT IN2
SE/
BTL
RIGHT IN1
RIGHT IN2
CONTROL
I2CCOMPATIBLE
MAX9777
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9777/MAX9778
General Description
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................................+6V
PVDD to VDD .......................................................................±0.3V
PGND to GND.....................................................................±0.3V
All Other Pins to GND.................................-0.3V to (VDD + 0.3V)
Continuous Input Current (into any pin except power-supply
and output pins) ...............................................................±20mA
OUT__ Short Circuit to GND, VDD ..........................................10s
Short Circuit Between OUT_+ and OUT_- .................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin TQFN, Multilayer Board
(derate 34.5mW/°C above +70°C) ..........................2758.6mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = PVDD = 5.0V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, RIN = RF = 15kΩ, RL = ∞. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Supply Voltage Range
Quiescent Supply Current
(IVDD + IPVDD)
Shutdown Current
Switching Time
Turn-On Time
SYMBOL
VDD/PVDD
IDD
I SHDN
tSW
tON
CONDITIONS
Inferred from PSRR test
MIN
TYP
4.5
MAX
UNITS
5.5
V
BTL mode, HPS = 0V, MAX9777/MAX9778
13
32
Single-ended mode, HPS = VDD
7
18
SHDN = GND
10
50
Gain or input switching
10
CBIAS = 1µF
300
CBIAS = 0.1µF
30
mA
µA
µs
ms
Thermal Shutdown Threshold
+160
o
C
Thermal Shutdown Hysteresis
15
o
C
OUTPUT AMPLIFIERS (SPEAKER MODE, HPS = GND)
Output Offset Voltage
Power-Supply Rejection Ratio
(Note 2)
Output Power
Total Harmonic Distortion Plus
Noise
Signal-to-Noise Ratio
VOS
VDD = 4.5V to 5.5V
PSRR
POUT
THD+N
SNR
Slew Rate
SR
Maximum Capacitive Load Drive
CL
Crosstalk
Click/Pop Level
2
±4
OUT_+ - OUT_-, AV = 1V/V
KCP
75
f = 1kHz, VRIPPLE = 200mVP-P
82
f = 20kHz, VRIPPLE = 200mVP-P
70
fIN = 1kHz,
THD+N < 1%,
TA = +25°C
RL = 8Ω
1.4
RL = 4Ω
2.6
RL = 3Ω
3
fIN = 1kHz, BW =
22Hz to 22kHz
POUT = 1W, RL = 8Ω
0.005
POUT = 2W, RL = 4Ω
0.01
RL = 8Ω, POUT = 1W, BW = 22Hz to 22kHz
±32
mV
100
dB
W
%
95
dB
1.6
V/µs
No sustained oscillations
1
nF
fIN = 10kHz
73
dB
Peak voltage, A-weighted,
32 samples per second
(Notes 2, 6)
Into shutdown
-50
Out of shutdown
-65
dBV
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
(VDD = PVDD = 5.0V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, RIN = RF = 15kΩ, RL = ∞. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
75
106
MAX
UNITS
OUTPUT AMPLIFIERS (HEADPHONE MODE, HPS = VDD)
Power-Supply Rejection Ratio
(Note 2)
Output Power
VDD = 4.5V to 5.5V
PSRR
POUT
Total Harmonic Distortion Plus
Noise
Signal-to-Noise Ratio
THD+N
SNR
Slew Rate
SR
Maximum Capacitive Load Drive
CL
Crosstalk
f = 1kHz, VRIPPLE = 200mVP-P
88
f = 20kHz, VRIPPLE = 200mVP-P
76
fIN = 1kHz, THD+N < RL = 32Ω
1%, TA = +25°C
RL = 16Ω
200
fIN = 1kHz,
BW = 22Hz to 22kHz
dB
88
POUT = 60mW,
RL = 32Ω
0.002
POUT = 125mW,
RL = 16Ω
0.002
mW
%
RL = 32Ω, BW = 22Hz to 22kHz,
VOUT = 1VRMS
92
dB
1.8
V/µs
No sustained oscillations
2
nF
fIN = 10kHz
78
dB
BIAS VOLTAGE (BIAS)
BIAS Voltage
VBIAS
Output Resistance
RBIAS
2.35
2.5
2.65
50
V
kΩ
1/2)
DIGITAL INPUTS (MUTE, SHDN, HPS_EN, GAINA/B, IN1
Input-Voltage High
VIH
Input-Voltage Low
VIL
2
0.8
V
V
Input Leakage Current
IIN
±1
µA
HEADPHONE SENSE INPUT (HPS)
0.9 x
VDD
Input-Voltage High
VIH
Input-Voltage Low
VIL
0.7 x
VDD
V
Input Leakage Current
IIN
±1
µA
Click/Pop Level
KCP
Peak voltage, A-weighted,
32 samples per second
(Notes 2, 4)
V
Into shutdown
-70
Out of shutdown
-52
dBV
_______________________________________________________________________________________
3
MAX9777/MAX9778
ELECTRICAL CHARACTERISTICS (continued)
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ELECTRICAL CHARACTERISTICS (continued)
(VDD = PVDD = 5.0V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, RIN = RF = 15kΩ, RL = ∞. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
V
±1
µA
±1
µA
2-WIRE SERIAL INTERFACE (SCL, SDA, ADD, INT) (MAX9777)
Input-Voltage High
VIH
Input-Voltage Low
VIL
2.6
Input Hysteresis
Input High Leakage Current
V
0.2
V
IIH
VIN = 5V
Input Low Leakage Current
IIL
VIN = 0V
Input Capacitance
CIN
Output-Voltage Low
VOL
IOL = 3mA
0.4
V
Output Current High
IOH
VOH = 5V
1
µA
400
kHz
10
pF
TIMING CHARACTERISTICS (MAX9777)
Serial Clock Frequency
fSCL
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
µs
START Condition Hold Time
tHD:STA
0.6
µs
START Condition Setup Time
tSU:STA
0.6
µs
Clock Period Low
tLOW
1.3
µs
Clock Period High
tHIGH
0.6
µs
Data Setup Time
tSU:DAT
100
Data Hold Time
tHD:DAT
(Note 3)
0
0.9
µs
Receive SCL/SDA Rise Time
tr
(Note 4)
20 +
0.1CB
300
ns
Receive SCL/SDA Fall Time
tf
(Note 4)
20 +
0.1CB
300
ns
Transmit SDA Fall Time
tf
(Note 4)
20 +
0.1CB
250
ns
tSP
(Note 5)
Pulse Width of Suppressed
Spike
ns
50
ns
Note 1: All devices are 100% production tested at +25°C. All temperature limits are guaranteed by design.
Note 2: Inputs AC-coupled to GND.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s
falling edge.
Note 4: CB = total capacitance of one of the bus lines in picofarads. Device tested with CB = 400pF. 1kΩ pullup resistors connected
from SDA/SCL to VDD.
Note 5: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.
Note 6: Headphone mode testing performed with 32Ω resistive load connected to GND. Speaker mode testing performed with 8Ω
resistive load connected to GND. Mode transitions are controlled by SHDN. KCP level is calculated as 20log[(peak voltage
during mode transition, no input signal)/1VRMS]. Units are expressed in dBV.
4
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
RL = 3Ω
AV = 4V/V
1
RL = 4Ω
AV = 2V/V
0.1
THD+N (%)
THD+N (%)
POUT = 1W
POUT = 500mW
THD+N (%)
0.1
0.1
POUT = 500mW POUT = 1W
POUT = 250mW P
OUT = 500mW
0.01
0.01
0.01
POUT = 2W
POUT = 2.5W
POUT = 2W
POUT = 2.5W
10
100
1k
10k
0.001
10
100k
100
1k
10k
10
100k
100
1k
100k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
RL = 8Ω
AV = 2V/V
1
RL = 8Ω
AV = 4V/V
0.1
POUT = 250mW POUT = 500mW
THD+N (%)
0.1
THD+N (%)
THD+N (%)
0.1
POUT = 250mW P
OUT = 500mW
0.01
0.01
POUT = 250mW
POUT = 500mW
0.01
POUT = 2W
POUT = 1W
0.001
0.001
100
1k
10k
0.001
10
100k
POUT = 1.2W
POUT = 1W
POUT = 1W POUT = 1.2W
10
MAX9777/78 toc06
RL = 4Ω
AV = 4V/V
MAX9777/78 toc05
1
MAX9777/78 toc04
1
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
f = 10kHz
f = 20Hz
1
f = 10kHz
f = 1kHz
0.1
0.1
2
OUTPUT POWER (W)
3
4
f = 10kHz
f = 1kHz
f = 20Hz
0.001
0.001
1
1
f = 20Hz
0.001
0
10
0.01
0.01
f = 1kHz
MAX9777/78 toc09
10
AV = 2V/V
RL = 4Ω
THD+N (%)
1
0.01
AV = 4V/V
RL = 3Ω
THD+N (%)
10
100
MAX9777/78 toc08
AV = 2V/V
RL = 3Ω
0.1
100
MAX9777/78 toc07
100
THD+N (%)
POUT = 2W
POUT = 1W
0.001
0.001
MAX9777/78 toc03
1
MAX9777/78 toc02
RL = 3Ω
AV = 2V/V
MAX9777/78 toc01
1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
0
1
2
OUTPUT POWER (W)
3
4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT POWER (W)
_______________________________________________________________________________________
5
MAX9777/MAX9778
Typical Operating Characteristics
(VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)
10
THD+N (%)
f = 10kHz
1
AV = 2V/V
RL = 8Ω
f = 1kHz
0.1
100
AV = 4V/V
RL = 8Ω
10
THD+N (%)
10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
MAX9777/78 toc11
AV = 4V/V
RL = 4Ω
1
f = 10kHz
0.1
1
f = 10kHz
0.1
f = 1kHz
f = 1kHz
0.01
0.01
0.01
f = 20Hz
f = 20Hz
f = 20Hz
0.001
0.001
0
0.5
1.0
1.5
2.0
2.5
3.0
0.001
3.5
0
0.5
1.0
1.5
2.0
0.5
0
1.0
1.5
OUTPUT POWER (W)
OUTPUT POWER vs. AMBIENT TEMPERATURE
(SPEAKER MODE)
OUTPUT POWER vs. AMBIENT TEMPERATURE
(SPEAKER MODE)
OUTPUT POWER vs. AMBIENT TEMPERATURE
(SPEAKER MODE)
4
4
THD+N = 1%
2
THD+N = 10%
3
THD+N = 1%
2
THD+N = 10%
OUTPUT POWER (W)
OUTPUT POWER (W)
3
2.0
MAX9777/78 toc14
MAX9777/78 toc13
OUTPUT POWER (W)
THD+N = 10%
1
1
1.0
f = 1kHz
RL = 8Ω
10
35
60
0
-40
85
-15
10
35
85
60
THD+N = 10%
35
3
THD+N = 1%
2
1.6
1.4
POWER DISSIPATION (W)
f = 1kHz
10
60
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)
MAX9777/78 toc16
5
-15
AMBIENT TEMPERATURE (°C)
OUTPUT POWER vs. LOAD RESISTANCE
(SPEAKER MODE)
4
-40
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
MAX9777/78 toc17
-15
OUTPUT POWER (W)
THD+N = 1%
0.5
0
0
-40
1.5
f = 1kHz
RL = 4Ω
f = 1kHz
RL = 3Ω
1.2
1.0
0.8
0.6
0.4
1
RL = 4Ω
f = 1kHz
0.2
0
0
1
10
100
1k
LOAD RESISTANCE (Ω)
6
2.0
OUTPUT POWER (W)
MAX9777/78 toc15
THD+N (%)
100
MAX9777/78 toc10
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
MAX9777/78 toc12
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
OUTPUT POWER (W)
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
10k
100k
0
0.5
1.0
1.5
2.0
OUTPUT POWER (W)
_______________________________________________________________________________________
2.5
85
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (SPEAKER MODE)
CROSSTALK vs. FREQUENCY
(SPEAKER MODE)
50
70
80
VIN = 200mVP-P
RL = 8Ω
-50
-60
CROSSTALK (dB)
60
MAX9777/78 toc19
VRIPPLE = 200mVP-P
PSRR (dB)
-40
MAX9777/78 toc18
40
-70
RIGHT TO LEFT
-80
-90
-100
LEFT TO RIGHT
90
-110
100
-120
10
100
1k
10k
100k
10
100
FREQUENCY (Hz)
1k
10k
EXITING SHUTDOWN (SPEAKER MODE)
ENTERING SHUTDOWN (SPEAKER MODE)
MAX9777/78 toc21
MAX9777/78 toc20
VDD
2V/div
SHDN
2V/div
OUT_+ AND OUT_1V/div
OUT_+ AND OUT_1V/div
OUT_+ - OUT_200mV/div
OUT_+ - OUT_500mV/div
100ms/div
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
POUT = 25mW
0.01
0.001
RL = 16Ω
AV = 2V/V
0.1
THD+N (%)
0.1
1
MAX9777/78 toc22
RL = 16Ω
AV = 1V/V
POUT = 50mW
POUT = 25mW
POUT = 50mW
0.01
POUT = 100mW
0.001
POUT = 100mW
MAX9777/78 toc23
400ms/div
1
THD+N (%)
100k
FREQUENCY (Hz)
POUT = 150mW
POUT = 150mW
0.0001
0.0001
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
_______________________________________________________________________________________
7
MAX9777/MAX9778
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)
0.1
POUT = 50mW
100
AV = 1V/V
RL = 16Ω
10
1
POUT = 25mW
THD+N (%)
POUT = 25mW
0.01
RL = 32Ω
AV = 2V/V
THD+N (%)
THD+N (%)
0.1
1
MAX9777/78 toc25
RL = 32Ω
AV = 1V/V
MAX9777/78 toc24
1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
MAX9777/78 toc26
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
POUT = 50mW
0.01
f = 20Hz
f = 10kHz
0.1
0.01
0.001
0.001
POUT = 100mW
POUT = 150mW POUT = 100mW
POUT = 150mW
0.001
f = 1kHz
0.0001
100
1k
10k
100k
10
100
1k
10k
50
100
150
200
250
300
FREQUENCY (Hz)
OUTPUT POWER (mW)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
1
f = 20Hz
0.01
f = 10kHz
0.1
f = 20Hz
f = 1kHz
0.001
0.001
f = 1kHz
0.0001
0.0001
0.0001
0
50
100
150
200
250
300
f = 10kHz
f = 20Hz
0.1
0.01
0.01
0.001
f = 1kHz
1
THD+N (%)
THD+N (%)
0.1
AV = 2V/V
RL = 32Ω
10
1
f = 10kHz
MAX9777/78 toc29
AV = 1V/V
RL = 32Ω
10
100
MAX9777/78 toc28
100
MAX9777/78 toc27
AV = 2V/V
RL = 16Ω
10
0
25
50
75
100
0
125
25
50
75
100
125
OUTPUT POWER (mW)
OUTPUT POWER (mW)
OUTPUT POWER vs. AMBIENT TEMPERATURE
(HEADPHONE MODE)
OUTPUT POWER vs. AMBIENT TEMPERATURE
(HEADPHONE MODE)
OUTPUT POWER vs. LOAD RESISTANCE
(HEADPHONE MODE)
150
100
50
100
THD+N = 1%
75
50
25
f = 1kHz
RL = 16Ω
-40
-15
10
35
60
AMBIENT TEMPERATURE (°C)
85
f = 1kHz
500
THD+N = 10%
400
300
200
THD+N = 1%
100
f = 1kHz
RL = 32Ω
0
0
600
OUTPUT POWER (mW)
THD+N = 1%
THD+N = 10%
125
OUTPUT POWER (mW)
200
MAX9777/78 toc331
MAX9777/78 toc30
THD+N = 10%
250
150
MAX9777/78 toc32
OUTPUT POWER (mW)
300
8
0
100k
FREQUENCY (Hz)
100
THD+N (%)
0.0001
0.0001
10
OUTPUT POWER (mW)
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
0
-40
-15
10
35
60
AMBIENT TEMPERATURE (°C)
85
1
10
100
1k
LOAD RESISTANCE (Ω)
_______________________________________________________________________________________
10k
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)
60
40
20
50
100
150
60
40
30
80
100
20
40
60
80
100
100
10
1k
OUTPUT POWER (mW)
OUTPUT POWER (mW)
10k
100k
FREQUENCY (Hz)
CROSSTALK vs. FREQUENCY
(HEADPHONE MODE)
EXITING SHUTDOWN (HEADPHONE MODE)
MAX9777/78 toc37
MAX9777/78 toc36
-40
VIN = 200mVP-P
RL = 16Ω
-50
-60
CROSSTALK (dB)
90
RL = 32Ω
f = 1kHz
0
200
70
20
0
0
0
50
10
RL = 16Ω
f = 1kHz
VRIPPLE = 200mVP-P
50
PSRR (dB)
80
40
MAX9777/78 toc34
60
POWER DISSIPATION (mW)
100
SHDN
2V/div
-70
-80
RIGHT TO LEFT
OUT_+
1V/div
-90
-100
-110
HP JACK
200mV/div
LEFT TO RIGHT
-120
100
1k
10k
100k
100ms/div
RL = 16Ω
INPUT AC-COUPLED TO GND
FREQUENCY (Hz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(SPEAKER MODE)
ENTERING SHUTDOWN (HEADPHONE MODE)
MAX9777/78 toc38
25
MAX9777/78 toc39
10
TA = +85°C
SHDN
2V/div
20
SUPPLY CURRENT (mA)
POWER DISSIPATION (mW)
70
MAX9777/78 toc33
120
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (HEADPHONE MODE)
MAX9777/78 toc35
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)
OUT_+
1V/div
TA = +25°C
15
10
TA = -40°C
5
HP JACK
100mV/div
0
100ms/div
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
MAX9777/MAX9778
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(HEADPHONE MODE)
TA = +85°C
8
6
TA = +25°C
4
TA = -40°C
2
MAX9777/78 toc40
12
10
SUPPLY CURRENT (mA)
10
SUPPLY CURRENT (mA)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(HEADPHONE MODE)
MAX9777/78 toc40
12
TA = +85°C
8
6
TA = +25°C
4
TA = -40°C
2
0
0
4.50
4.75
5.00
5.50
5.25
4.50
4.75
5.00
5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)
EXITING POWER-DOWN
(SPEAKER MODE)
MAX9777/78 toc42
0.7
0.6
VDD
2V/div
0.5
0.4
OUT_+ AND OUT_1V/div
0.3
0.2
RL = 8Ω
f = 1kHz
0.1
OUT_+ - OUT_1V/div
0
0
0.25
0.50
0.75
1.00
1.25
1.50
100ms/div
OUTPUT POWER (W)
10
5.50
MAX9777/78 toc43
0.8
POWER DISSIPATION (W)
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
PIN
MAX9777
MAX9778
1
—
NAME
SDA
FUNCTION
Serial Data I/O
2
—
INT
Interrupt Output
3, 4
3, 4
VDD
Power-Supply Input
5
5
INL1
Left-Channel Input 1
6
6
INL2
Left-Channel Input 2
7
7
GAINLA
Left-Channel Gain Set A
8
8
GAINLB
9, 13, 23, 27
9, 13, 23, 27
PGND
Power Ground. Connect to GND.
Left-Channel Gain Set B
10
10
OUTL+
Left-Channel Bridged Amplifier Positive Output. OUTL+ also serves as the
left-channel headphone amplifier output.
11, 25
11, 25
PVDD
Output Amplifier Power Supply
12
12
OUTL-
Left-Channel Bridged Amplifier Negative Output
14
14
SHDN
Active-Low Shutdown Input. Connect SHDN to VDD for normal operation.
15
—
ADD
Address Select. A logic-high sets the address LSB to 1, a logic-low sets the
address LSB to zero.
16
16
HPS
Headphone Sense Input. A logic-high configures the device as a singleended headphone amp. A logic-low configures the device as a BTL
speaker amp.
17
17
BIAS
DC Bias Bypass Terminal. See the BIAS Capacitor section for capacitor
selection. Connect CBIAS from BIAS to GND.
18
18
GND
Ground. Connect to PGND.
19
19
INR1
Right-Channel Input 1
20
20
INR2
Right-Channel Input 2
21
21
GAINRA
Right-Channel Gain Set A
22
22
GAINRB
Right-Channel Gain Set B
24
24
OUTR+
Right-Channel Bridged Amplifier Positive Output. OUTR+ also serves as the
right-channel headphone amplifier output.
26
26
OUTR-
Right-Channel Bridged Amplifier Negative Output
28
—
SCL
—
1
MUTE
Serial Clock Line
Active-High Mute Input
—
2
HPS_EN
Headphone Enable. A logic-high enables HPS. A logic-low disables HPS
and the device is always configured as a BTL speaker amplifier.
—
15
GAINA/B
Gain Select. A logic-low selects the gain set by GAIN_A. A logic-high
selects the gain set by GAIN_B.
—
28
IN1/2
Input Select. A logic-low selects amplifier input 1. A logic-high selects
amplifier input 2.
EP
EP
EP
Exposed Paddle. Connect to GND.
______________________________________________________________________________________
11
MAX9777/MAX9778
Pin Description
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Detailed Description
The MAX9777/MAX9778 feature 3W BTL speaker
amplifiers, 200mW headphone amplifiers, input multiplexers, headphone sensing, and comprehensive clickand-pop suppression. The MAX9777/MAX9778 are
stereo BTL/headphone amplifiers. The MAX9777 is
controlled through an I 2 C-compatible, 2-wire serial
interface. The MAX9778 is controlled through five logic
inputs: MUTE, SHDN, HPS_EN, GAINA/B, and IN1/2
(see the Selector Guide). The MAX9777/MAX97778 feature exceptional PSRR (100dB at 1kHz), allowing these
devices to operate from noisy digital supplies without
the need for a linear regulator.
The speaker amplifiers use a BTL configuration. The
signal path is composed of an input amplifier and an
output amplifier. Resistor RIN sets the input amplifier’s
gain, and resistor RF sets the output amplifier’s gain.
The output of these two amplifiers serves as the input to
a slave amplifier configured as an inverting unity-gain
follower. This results in two outputs, identical in magnitude, but 180° out of phase. The overall gain of the
speaker amplifiers is twice the product of the two
amplifier gains (see the Gain-Setting Resistors section).
A feature of this architecture is that there is no phase
inversion from input to output.
When configured as a headphone (single-ended) amplifier, the slave amplifier is disabled, muting the speaker
and the main amplifier drives the headphone. The
MAX9777/MAX9778 can deliver 3W of continuous power
into a 3Ω load with less than 1% THD+N in speaker
mode, and 200mW of continuous average power into a
16Ω load with less than 1% THD+N in headphone mode.
These devices also feature thermal-overload protection.
Input Multiplexer
Each amplifier features a 2:1 input multiplexer, allowing
input selection between two stereo sources. Both multiplexers are controlled by bit 1 in the control register
(MAX9777) or by the IN1/2 pin (MAX9778). A logic-low
selects input IN_1 and a logic-high selects input IN_2.
The input multiplexer can also be used to further
expand the number of gain options available from the
MAX9777/MAX9778 family. Connecting the audio
source to the device through two different input resistors (Figure 1) increases the number of gain options
from two to four. Additionally, the input multiplexer
allows a speaker equalization network to be switched
into the speaker signal path. This is typically useful in
optimizing acoustic response from speakers with small
physical dimensions.
Headphone Sense Enable
The HPS input is enabled by HPS_EN (MAX9778) or the
HPS_D bit (MAX9777). HPS_D or HPS_EN determines
whether the device is in automatic detection mode or
fixed-mode operation (see Tables 1a and 1b).
15kΩ
AUDIO
INPUT
MAX9777
MAX9778
IN_1
30kΩ
IN_2
Figure 1. Using the Input Multiplexer for Gain Setting
BIAS
These devices operate from a single 5V supply, and feature an internally generated, power-supply independent,
common-mode bias voltage of 2.5V referenced to GND.
BIAS provides both click-and-pop suppression and sets
the DC bias level for the audio outputs. BIAS is internally
connected to the noninverting input of each speaker
amplifier (see the Typical Application Circuits and
Functional Diagrams). Choose the value of the bypass
capacitor as described in the BIAS Capacitor section.
No external load should be applied to BIAS. Any load
lowers the BIAS voltage, affecting the overall performance of the device.
12
Table 1a. MAX9777 HPS Setting
INPUTS
HPS_D
BIT
HPS
SPKR/HP
BIT
MODE
GAIN
PATH*
0
0
X
BTL
A
0
1
X
SE
B
1
X
0
BTL
A or B
1
X
1
SE
A or B
*Note:
A—GAINA path selected
B—GAINB path selected
A or B—Gain path selected by GAINAB control bit in register
02h
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
INPUTS
VDD
MODE
GAIN PATH*
X
BTL
A or B
1
0
BTL
A or B
1
1
SE
A or B
HPS_EN
HPS
0
*Note:
A or B—Gain path selected by external GAINAB
R1
680kΩ
R3
47kΩ
MAX9777
MAX9778
HPS
OUTL+
OUTR+
R2
10kΩ
R2
10kΩ
Headphone Sense Input (HPS)
With headphone sense enabled, a voltage on HPS less
than 0.7 x VDD sets the device to speaker mode. A voltage greater than 0.9 x V DD disables the inverting
bridge amplifier (OUT_-), which mutes the speaker
amplifier and sets the device into headphone mode.
For automatic headphone detection, enable headphone
sense and connect HPS to the control pin of a 3-wire
headphone jack as shown in Figure 2. With no headphone present, the resistive voltage-divider created by
R1 and R2 sets the voltage on HPS to be less than 0.7 x
VDD, setting the device to speaker mode and the gain
setting defaults to GAINA (MAX9777). When a headphone plug is inserted into the jack, the control pin is disconnected from the tip contact, and HPS is pulled to VDD
through R1, setting the device into headphone mode and
the gain-setting defaults to GAINB (MAX9777) (see the
Gain Select section). Place a resistor in series with the
control pin and HPS (R3) to prevent any audio signal from
coupling into HPS when the device is in speaker mode.
Shutdown
The MAX9777/MAX9778 feature a 10µA, low-power
shutdown mode that reduces quiescent current consumption and extends battery life. The drive amplifiers
and bias circuitry are disabled, the amplifier outputs
(OUT_) go high impedance, and BIAS is driven to
GND. Driving SHDN low places the devices into shutdown mode, disables the interface, and resets the I2C
registers to a default state. A logic-high on SHDN
enables the devices.
MAX9777 Software Shutdown
A logic-high on bit 0 of the SHDN register places the
MAX9777 in shutdown mode. A logic-low enables the
Figure 2. HPS Configuration Circuit
device. The digital section of the MAX9777 remains
active when the device is shut down through the interface. All devices feature a logic-low on the SHDN input.
MUTE
The MAX9777/MAX9778 feature a mute mode. When
the device is muted, the input is disconnected from the
amplifiers. MUTE does not shut down the device.
MAX9777 MUTE
The MAX9777 MUTE mode is selected by writing to the
MUTE register (see the Mute Register section). The left
and right channels can be independently muted.
MAX9778 MUTE
The MAX9778 features an active-high MUTE input that
mutes all channels.
Click-and-Pop Suppression
The MAX9777/MAX9778 feature Maxim’s comprehensive click-and-pop suppression. When entering or exiting shutdown, the common-mode bias voltage of the
amplifiers is slowly ramped to and from the DC bias
point using an S-shaped waveform. In headphone
mode, this waveform shapes the frequency spectrum,
minimizing the amount of audible components present
at the headphone. In speaker mode, the BTL amplifiers
start up in the same fashion as in headphone mode.
When entering shutdown, both amplifier outputs ramp
to GND quickly and simultaneously. To maximize clickand-pop suppression, drive SHDN to 0V before powerup or power-down transitions.
______________________________________________________________________________________
13
MAX9777/MAX9778
Table 1b. MAX9778 HPS Setting
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Digital Interface
devices from high-voltage spikes on the bus lines, and
minimize crosstalk and undershoot of the bus signals.
The MAX9777 features an I2C/SMBus™-compatible 2wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the
MAX9777 and the master at clock rates up to 400kHz.
Figure 3 shows the 2-wire interface timing diagram. The
MAX9777 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). SDA and SCL idle high
when the I2C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 4). A START condition from the master signals
the beginning of a transmission to the MAX9777. The
master terminates transmission by issuing the STOP
condition; this frees the bus. If a REPEATED START
condition is generated instead of a STOP condition, the
bus remains active.
A master device communicates to the MAX9777 by
transmitting the proper address followed by a command and/or data words. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted
over the bus is 8 bits long and is always followed by an
acknowledge clock pulse.
SDA and SCL are open-drain outputs requiring a pullup
resistor (500Ω or greater) to generate a logic-high voltage. Series resistors in line with SDA and SCL are optional. These series resistors protect the input stages of the
SMBus is a trademark of Intel Corp.
SDA
tBUF
tHD, STA
tSU, DAT
tHD, STA
tSP
tHD, DAT
tLOW
tSU, STO
SCL
tHIGH
tHD, STA
tR
tF
REPEATED
START
CONDITION
START
CONDITION
STOP
CONDITION
Figure 3. 2-Wire Serial-Interface Timing Diagram
S
Sr
P
SCL
SDA
Figure 4. START/STOP Conditions
14
______________________________________________________________________________________
START
CONDITION
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
REPEATED START Conditions
A REPEATED START (S r ) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S r may also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX9777 serial interface supports continuous write operations with
or without an Sr condition separating them. Continuous
read operations require Sr conditions because of the
change in direction of data flow.
SCL
SDA
STOP
START
LEGAL STOP CONDITION
SCL
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always generates ACK. The MAX9777 generates an ACK when
receiving an address or data by pulling SDA low during
the night clock period. When transmitting data, the
MAX9777 waits for the receiving device to generate an
ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication at a later time.
Slave Address
The bus master initiates communication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9777
waits for a START condition followed by its slave
address. The LSB of the address word is the
Read/Write (R/W) bit. R/W indicates whether the master
is writing to or reading from the MAX9777 (R/W = 0
selects the write condition, R/W = 1 selects the read
condition). After receiving the proper address, the
MAX9777 issues an ACK by pulling SDA low for one
clock cycle.
The MAX9777 has a factory-/user-programmed
address. Address bits A6–A2 are preset, while A0 and
A1 is set by ADD. Connect ADD to either VDD, GND,
SCL, or SDA to change the last 2 bits of the slave
address (Table 2).
S
A6
A5
A4
A3
A2
A1
A0
R/W
Figure 6. Slave Address Byte Definition
SDA
Table 2. MAX9777 I2C Slave Addresses
START
ILLEGAL
STOP
ILLEGAL EARLY STOP CONDITION
Figure 5. Early STOP Condition
ADD CONNECTION
I2C ADDRESS
GND
100 1000
VDD
100 1001
SDA
100 1010
SCL
100 1011
______________________________________________________________________________________
15
MAX9777/MAX9778
Early STOP Conditions
The MAX9777 recognizes a STOP condition at any
point during the transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 5). This condition is not a legal I2C format;
at least one clock pulse must separate any START and
STOP condition.
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Write Data Format
There are three registers that configure the MAX9777:
the MUTE register, SHDN register, and control register.
In write data mode (R/W = 0), the register address and
data byte follow the device address (Figure 7).
in bit 0 of the SHDN register shuts down the device; a
logic-low turns on the device. A logic-high is required in
bits 2 to 7 to reset all registers to their default settings.
Control Register
The control register (03hex) is a read/write register that
determines the device configuration. Bit 1 (IN1/IN2) controls the input multiplexer, a logic-high selects input 1; a
logic-low selects input 2. Bit 2 (HPS_D) controls the
headphone sensing. A logic-low configures the device in
automatic headphone detection mode. A logic-high disables the HPS input. Bit 3 (GAINA/B) controls the gainselect multiplexer. A logic-low selects GAINA. A logichigh selects GAINB. GAINA/B is ignored when HPS_D =
0. Bit 4 (SPKR/HP) selects the amplifier operating mode
when HPS_D = 1. A logic-high selects speaker mode,
and a logic-low selects headphone mode.
MUTE Register
The MUTE register (01hex) is a read/write register that
sets the MUTE status of the device. Bit 3 (MUTEL) of
the MUTE register controls the left channel; bit 4
(MUTER) controls the right channel. A logic-high mutes
the respective channel; a logic-low brings the channel
out of mute.
SHDN Register
The SHDN register (02hex) is a read/write register that
controls the power-up state of the device. A logic-high
S
ADDRESS
WR
ACK
COMMAND
7 BITS
I2C SLAVE ADDRESS.
SELECTS DEVICE.
S
ADDRESS
ACK
8 BITS
DATA
REGISTER ADDRESS.
SELECTS REGISTER TO BE
WRITTEN TO.
WR
ACK
COMMAND
7 BITS
P
ACK
REGISTER ADDRESS.
SELECTS REGISTER
TO BE READ.
1
REGISTER DATA
S
ADDRESS
8 BITS
I2C SLAVE ADDRESS.
SELECTS DEVICE.
ACK
8 BITS
WR
ACK
7 BITS
I2C SLAVE ADDRESS.
SELECTS DEVICE.
DATA
P
8 BITS
1
DATA FROM
SELECTED REGISTER
Figure 7. Write/Read Data Format Example
Table 3. MAX9777 MUTE Register Format
REGISTER
ADDRESS
REGISTER ADDRESS
BIT
NAME
0000 0001
BIT
NAME
VALUE
DESCRIPTION
7
X
Don’t Care
—
6
X
Don’t Care
—
5
X
Don’t Care
—
4
MUTER
0*
Unmute right channel
1
Mute right channel
0*
Unmute left channel
3
MUTEL
1
Mute left channel
2
X
Don’t Care
—
1
X
Don’t Care
—
0
X
Don’t Care
—
*Default state.
Table 4. MAX9777 SHDN Register Format
7
RESET
6
RESET
5
RESET
4
RESET
3
RESET
2
RESET
1
X
0
SHDN
VALUE
0*
1
0*
1
0*
1
0*
1
0*
1
0*
1
Don’t Care
0*
1
0000 0010
DESCRIPTION
—
Reset device
—
Reset device
—
Reset device
—
Reset device
—
Reset device
—
Reset device
—
Normal operation
Shutdown
*Default state.
16
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
REGISTER ADDRESS
0000 0011
BIT
NAME
VALUE
DESCRIPTION
7
X
Don’t Care
—
6
X
Don’t Care
—
5
X
Don’t Care
—
0*
Speaker mode selected
1
Headphone mode
selected
0*
Gain-setting A selected
4
SPKR/HP
3
GAINA/B
2
1
Gain-setting B selected
0*
Automatic headphone
detection enabled
1
Automatic headphone
detection disabled
(HPS ignored)
0*
Input 1 selected
1
Input 2 selected
HPS_D
1
IN1/IN2
0
X
Don’t Care
—
Read Data Format
In read mode (R/W = 1), the MAX9777 writes the contents of the selected register to the bus. The direction of
the data flow reverses following the address acknowledge by the MAX9777. The master device reads the
contents of all registers, including the read-only status
register. Table 6 shows the status register format.
Interrupt Output (INT)
The MAX9777 includes an interrupt output (INT) that
can indicate to a master device that an event has
occurred. INT is triggered when the state of HPS
changes. During normal operation, INT idles high. If a
headphone is inserted/removed from the jack and that
action is detected by HPS, INT pulls the line low. INT
remains low until a read data operation is executed.
I2C Compatibility
The MAX9777 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The communication protocol supports the
standard I2C 8-bit communications. The general call
address is ignored. The MAX9777 slave addresses are
compatible with the 7-bit I2C addressing protocol only.
*Default
Table 6. MAX9777 Status Register Format
REGISTER ADDRESS
BIT
7
6
NAME
THRM
AMPR-
5
AMPR+
4
AMPL-
3
AMPL+
0000 0000
VALUE
0
DESCRIPTION
Device temperature below thermal limit
1
Device temperature exceeding thermal limit
0
OUTR- current below current limit
1
OUTR- current exceeding current limit
0
OUTR+ current below current limit
1
OUTR+ current exceeding current limit
0
OUTL- current below current limit
1
OUTL- current exceeding current limit
0
OUTL+ current below current limit
1
OUTL+ current exceeding current limit
0
Device in speaker mode
1
Device in headphone mode
2
HPSTS
1
X
Don’t Care
—
0
X
Don’t Care
—
______________________________________________________________________________________
17
MAX9777/MAX9778
Table 5. MAX9777 Control Register Format
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Applications Information
BTL Speaker Amplifiers
The MAX9777/MAX9778 feature speaker amplifiers
designed to drive a load differentially, a configuration
referred to as bridge-tied load (BTL). The BTL configuration (Figure 8) offers advantages over the singleended configuration, where one side of the load is
connected to ground. Driving the load differentially
doubles the output voltage compared to a singleended amplifier under similar conditions. Thus, the
devices’ differential gain is twice the closed-loop gain
of the input amplifier. The effective gain is given by:
A VD = 2 ×
RF
RIN
Substituting 2 x VOUT(P-P) for VOUT(P-P) into the following equations yields four times the output power due to
doubling of the output voltage:
VRMS =
2 2
2
V
POUT = RMS
RL
Since the differential outputs are biased at midsupply,
there is no net DC voltage across the load. This eliminates the need for DC-blocking capacitors required for
single-ended amplifiers. These capacitors can be large
and expensive, consume board space, and degrade
low-frequency performance.
When the MAX9777 is configured to automatically detect
the presence of a headphone jack, the device defaults to
gain setting A when the device is in speaker mode.
VOUT(P-P)
2 x VOUT(P-P)
-1
Power Dissipation and Heat Sinking
Under normal operating conditions, the MAX9777/
MAX9778 can dissipate a significant amount of power.
The maximum power dissipation for each package is
given in the Absolute Maximum Ratings section under
Continuous Power Dissipation or can be calculated by
the following equation:
PDISSPKG(MAX) =
VOUT(P−P)
+1
Single-Ended Headphone Amplifier
The MAX9777/MAX9778 can be configured as singleended headphone amplifiers through software or by
sensing the presence of a headphone plug (HPS). In
headphone mode, the inverting output of the BTL
amplifier is disabled, muting the speaker. The gain is
1/2 that of the device in speaker mode, and the output
power is reduced by a factor of 4.
In headphone mode, the load must be capacitively
coupled to the device, blocking the DC bias voltage
from the load (see the Typical Application Circuits).
VOUT(P-P)
TJ(MAX) − TA
θJA
where TJ(MAX) is +150°C, TA is the ambient temperature, and θJA is the reciprocal of the derating factor in
°C/W as specified in the Absolute Maximum Ratings
section. For example, θ JA of the TQFN package is
+29°C/W.
The increase in power delivered by the BTL configuration directly results in an increase in internal power dissipation over the single-ended configuration. The
maximum power dissipation for a given VDD and load is
given by the following equation:
PDISS(MAX) =
2VDD2
π 2RL
If the power dissipation for a given application exceeds
the maximum allowed for a given package, either reduce
VDD, increase load impedance, decrease the ambient
temperature, or add heatsinking to the device. Large
output, supply, and ground PC board traces improve the
maximum power dissipation in the package.
Thermal-overload protection limits total power dissipation in these devices. When the junction temperature
exceeds +160°C, the thermal-protection circuitry disables the amplifier output stage. The amplifiers are
enabled once the junction temperature cools by 15°C.
This results in a pulsing output under continuous thermal-overload conditions as the device heats and cools.
Figure 8. Bridge-Tied Load Configuration
18
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Gain-Setting Resistors
External feedback components set the gain of the
MAX9777/MAX9778. Resistor RIN sets the gain of the
input amplifier (AVIN), and resistor RF sets the gain of
the second stage amplifier (AVOUT):
⎛ 10kΩ ⎞
⎛ RF ⎞
A VIN = − ⎜
⎟ , A VOUT = − ⎜⎝ 10kΩ ⎟⎠
⎝ RIN ⎠
Combining AVIN and AVOUT, RIN and RF set the singleended gain of the device as follows:
⎛ 10kΩ ⎞
⎛ RF ⎞
⎛ RF ⎞
A V = A VIN × A VOUT = − ⎜
⎟ × − ⎜⎝ 10kΩ ⎟⎠ = +⎜ R ⎟
R
⎝ IN ⎠
⎝ IN ⎠
As shown, the two-stage amplifier architecture results
in a noninverting gain configuration, preserving
absolute phase through the MAX9777/MAX9778. The
gain of the device in BTL mode is twice that of the single-ended mode. Choose RIN between 10kΩ and 15kΩ
and RF between 15kΩ and 100kΩ.
Input Filter
The input capacitor (CIN), in conjunction with RIN, forms
a highpass filter that removes the DC bias from an
incoming signal. The AC-coupling capacitor allows the
amplifier to bias the signal to an optimum DC level.
Assuming zero-source impedance, the -3dB point of
the highpass filter is given by:
1
f−3dB =
2πRINCIN
Choose RIN according to the Gain-Setting Resistors section. Choose the CIN such that f-3dB is well below the
lowest frequency of interest. Setting f-3dB too high affects
the amplifier’s low-frequency response. Use capacitors
whose dielectrics have low-voltage coefficients, such as
tantalum or aluminum electrolytic. Capacitors with highvoltage coefficients, such as ceramics, may result in an
increased distortion at low frequencies.
Other considerations when designing the input filter
include the constraints of the overall system,
the actual frequency band of interest, and click-andpop suppression.
Output-Coupling Capacitor
The MAX9777/MAX9778 require output-coupling
capacitors to operate in single-ended (headphone)
mode. The output-coupling capacitor blocks the DC
component of the amplifier output, preventing DC current from flowing to the load. The output capacitor and
the load impedance form a highpass filter with a -3dB
point determined by:
f−3dB =
1
2πRLCOUT
As with the input capacitor, choose COUT such that
f-3dB is well below the lowest frequency of interest.
Setting f-3dB too high affects the amplifier‘s low-frequency response.
Load impedance is a concern when choosing COUT.
Load impedance can vary, changing the -3dB point of
the output filter. A lower impedance increases the corner frequency, degrading low-frequency response.
Select COUT such that the worst-case load/COUT combination yields an adequate response. Select capacitors with low ESR to minimize resistive losses and
optimize power transfer to the load.
If layout constraints require a physically smaller outputcoupling capacitor, decrease the value of COUT and add
series resistance to the output of the MAX9777/MAX9778
(see Figure 9). With the added series resistance at the
output, the cutoff frequency of the highpass filter is:
1
f−3dB =
2π(RL + RSERIES )COUT
Since the cutoff frequency of the output highpass filter
is inversely proportional to the product of the total load
resistance seen by the outputs (R L + RSERIES) and
C OUT , increase the total resistance seen by the
MAX9777/MAX9778 outputs by the same amount COUT
is decreased to maintain low-frequency performance.
Since the added series resistance forms a voltagedivider with the headphone speaker resistance for frequencies within the passband of the highpass filter,
there is a loss in voltage gain. To compensate for this
loss, increase the voltage gain setting by an amount
equal to the attenuation due to the added series resistance. Use the following equation to approximate the
required voltage gain compensation:
⎛ R + RSERIES ⎞
A V _ COMP = 20 log⎜ L
⎟
RL
⎝
⎠
COUT
RSERIES
OUT_+
RL
Figure 9. Reducing COUT by Adding RSERIES
______________________________________________________________________________________
19
MAX9777/MAX9778
Component Selection
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
BIAS Capacitor
BIAS is the output of the internally generated 2.5VDC
bias voltage. The BIAS bypass capacitor, C BIAS ,
improves PSRR and THD+N by reducing power supply
and other noise sources at the common-mode bias
node, and also generates the clickless/popless, startup/shutdown DC bias waveforms for the speaker amplifiers. Bypass BIAS with a 1µF capacitor to GND.
Supply Bypassing
Proper power-supply bypassing ensures low-noise, lowdistortion performance. Place a 0.1µF ceramic capacitor
from VDD to GND. Add additional bulk capacitance as
required by the application, typically 100µF. Bypass
PVDD with a 100µF capacitor to GND. Locate bypass
capacitors as close to the device as possible.
Gain Select
The MAX9777/MAX9778 feature multiple gain settings on
each channel, making available different gain and feedback configurations. The gain-setting resistor (RF) is connected between the amplifier output (OUT_+) and the
gain set point (GAIN_). An internal multiplexer switches
between the different feedback resistors depending on
the status of the gain control input. The stereo
MAX9777/MAX9778 feature two gain options per channel. See Tables 1a and 1b for the gain-setting options.
Bass Boost Circuit
Headphones typically have a poor low-frequency
response due to speaker and enclosure size limitations.
A bass boost circuit compensates the poor low-frequency response (Figure 10). At low frequencies, the capacitor CF is an open circuit, and the effective impedance in
the feedback loop (RF(EFF)) is RF(EFF) = RF1.
At the frequency:
1
2πRF2CF
where the impedance, CF, begins to decrease, and at
high frequencies, the CF is a short circuit. Here the
impedance of the feedback loop is:
R × RF2
RF(EFF) = F1
RF1 + RF2
Assuming RF1 = RF2, then RF(EFF) at low frequencies is
twice that of RF(EFF) at high frequencies (Figure 11).
Thus, the amplifier has more gain at lower frequencies,
boosting the system’s bass response. Set the gain rolloff frequency based upon the response of the speaker
and enclosure.
To minimize distortion at low frequencies, use capacitors with low-voltage coefficient dielectrics when selecting C F. Film or C0G dielectric capacitors are good
choices for CF. Capacitors with high-voltage coefficients, such as ceramics (non-C0G dielectrics), can
result in increased distortion at low frequencies.
Layout and Grounding
Good PC board layout is essential for optimizing performance. Use large traces for the power-supply inputs
and amplifier outputs to minimize losses due to parasitic trace resistance, as well as route heat away from
the device. Good grounding improves audio performance, minimizes crosstalk between channels, and
prevents any digital switching noise from coupling into
the audio signal. If digital signal lines must cross over
or under audio signal lines, ensure that they cross perpendicular to each other.
The MAX9777/MAX9778 TQFN package features an
exposed thermal pad. This pad lowers the package’s
thermal resistance by providing a direct heat conduction path from the die to the PC board. Connect the pad
to signal ground (0V) by using a large pad or multiple
vias to the ground plane.
GAIN
CF
RF2
RF1
RIN
RF1
RIN
RF1 RF2
RIN
VBIAS
Figure 10. Bass Boost Circuit
20
FREQUENCY
1
2π RF2 CF
Figure 11. Bass Boost Response
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
4.5V TO 5.5V
100µF
0.1µF
3, 4
17
11, 25
VDD
BIAS
PVDD
0.047µF
1µF
GAINLB
GAINLA
15kΩ
5
OUTL+
27.4kΩ
33.2kΩ
8
15kΩ
7
220µF
10kΩ
10
INL1
0.68µF
0.68µF
15kΩ
HPF
OUTL6
INL2
CODEC
0.68µF
0.68µF
15kΩ
MAX9777
19
INR1
OUTR-
15kΩ
HPF
20
OUTR+
GAINRA
1kΩ
10kΩ
GAINRB
28
1
MICROCONTROLLER
15
2
14
26
INR2
4.5V TO 5.5V
1kΩ
12
24
15kΩ
21
220µF
4.5V TO 5.5V
33.2kΩ
22
27.4kΩ
10kΩ
680kΩ
SCL
0.047µF
SDA
ADD
HPS
16
47kΩ
INT
SHDN
GND
18
PGND
9, 13, 23, 27
______________________________________________________________________________________
21
MAX9777/MAX9778
Typical Application Circuits
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
MAX9777/MAX9778
Typical Application Circuits (continued)
4.5V TO 5.5V
100µF
0.1µF
3, 4
17
11, 25
VDD
BIAS
PVDD
0.047µF
1µF
GAINLB
GAINLA
15kΩ
5
OUTL+
27.4kΩ
33.2kΩ
8
15kΩ
7
220µF
10kΩ
10
INL1
0.68µF
0.68µF
15kΩ
HPF
OUTL6
INL2
CODEC
0.68µF
0.68µF
HPF
15kΩ
MAX9778
19
INR1
OUTR-
15kΩ
20
GAINRA
GAINRB
28
1
15
2
14
24
15kΩ
21
220µF
4.5V TO 5.5V
33.2kΩ
22
27.4kΩ
10kΩ
IN1/2
0.047µF
MUTE
GAINA/B
HPS
16
47kΩ
HPS_EN
SHDN
GND
18
22
26
INR2
OUTR+
MICROCONTROLLER
12
PGND
9, 13, 23, 27
______________________________________________________________________________________
680kΩ
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
4.5V TO 5.5V
100µF
0.1µF
11, 25 3, 4
PVDD VDD
AUDIO
INPUT
AUDIO
INPUT
0.68µF
15kΩ
5 INL1
2:1
INPUT
MUX
6 INL2
0.68µF
15kΩ
10kΩ
33.2kΩ
10kΩ
220µF
10kΩ
BIAS
10kΩ
OUTL- 12
GAIN
SET
MUX
10kΩ
0.68µF
15kΩ
27.4kΩ
OUTL+ 10
1µF
19 INR1
2:1
INPUT
MUX
20 INR2
0.68µF
0.047µF
GAINLA 7
15kΩ
17 BIAS
AUDIO
INPUT
AUDIO
INPUT
GAINLB 8
GAIN
SET
MUX
10kΩ
GAINRB 22
0.047µF
GAINRA 21
33.2kΩ
15kΩ
10kΩ
27.4kΩ
10kΩ
OUTR+ 24
15kΩ
220µF
4.5V TO 5.5V
10kΩ
10kΩ
TO
µCONTROLLER
1kΩ
10kΩ
1kΩ
14
28
1
15
2
SHDN
SCL
SDA
ADD
INT
OUTR- 26
LOGIC
MAX9777
HPS
GND
18
HPS 16
PGND
9, 13, 23, 27
______________________________________________________________________________________
23
MAX9777/MAX9778
Functional Diagrams
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
MAX9777/MAX9778
Functional Diagrams (continued)
4.5V TO 5.5V
100µF
0.1µF
11, 25 3, 4
PVDD VDD
AUDIO
INPUT
AUDIO
INPUT
0.68µF
15kΩ
5 INL1
6 INL2
0.68µF
2:1
INPUT
MUX
15kΩ
10kΩ
33.2kΩ
10kΩ
220µF
10kΩ
BIAS
10kΩ
OUTL- 12
GAIN
SET
MUX
10kΩ
0.68µF
15kΩ
27.4kΩ
OUTL+ 10
1µF
19 INR1
20 INR2
0.68µF
0.047µF
GAINLA 7
15kΩ
17 BIAS
AUDIO
INPUT
AUDIO
INPUT
GAINLB 8
GAIN
SET
MUX
10kΩ
2:1
INPUT
MUX
GAINRB 22
0.047µF
GAINRA 21
33.2kΩ
15kΩ
10kΩ
27.4kΩ
10kΩ
OUTR+ 24
15kΩ
220µF
4.5V TO 5.5V
10kΩ
10kΩ
TO
µCONTROLLER
1kΩ
10kΩ
1kΩ
14
28
1
15
2
MAX9778
24
OUTR- 26
SHDN
IN1/2
MUTE
LOGIC
GAINA/B
HPS_EN
HPS
GND
18
HPS 16
PGND
9, 13, 23, 27
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ADD
GAINRA
INR2
17
16
15
21
20
GAINA/B
HPS
18
HPS
BIAS
19
BIAS
GND
20
INR1
INR1
21
GND
INR2
TOP VIEW
GAINRA
TOP VIEW
19
18
17
16
15
GAINRB 22
14
SHDN
GAINRB 22
14
SHDN
PGND 23
13
PGND
PGND 23
13
PGND
OUTR+ 24
12
OUTL-
OUTR+ 24
12
OUTL-
PVDD 25
11
PVDD
PVDD 25
11
PVDD
OUTR- 26
10
OUTL+
OUTR- 26
10
OUTL+
PGND 27
9
PGND
PGND 27
9
PGND
8
GAINLB
6
7
1
2
INL2
GAINLA
MUTE
HPS_EN
THIN QFN
3
4
5
6
7
GAINLA
5
INL2
4
INL1
3
INL1
IN1/2 28
VDD
2
GAINLB
VDD
1
INT
8
SDA
SCL 28
+
VDD
+
MAX9778
VDD
MAX9777
THIN QFN
______________________________________________________________________________________
25
MAX9777/MAX9778
Pin Configurations
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
26
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX9777/MAX9778
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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