EVALUATION KIT AVAILABLE
The MAX98371 is a high-efficiency, mono Class D audio
amplifier featuring dynamic headroom tracking (DHT).
DHT automatically optimizes the headroom available to
the Class D amplifier as the power supply voltage varies, due to sudden transients and declining battery life to
maintain a consistent listening experience. A wide 5.5V
to 18V supply range allows the device to reach 19W into
an 8Ω load.
The MAX98371’s flexible digital audio interface (DAI)
supports I2S, left-justified, and TDM formats. The digital
audio interface accepts 32kHz, 44.1kHz, 48kHz, 88.2kHz,
and 96kHz sample rates with 16-/24-/32-bit data supported for all data formats. In TDM mode, the device can
support up to 16 channels of audio data. A unique clocking structure eliminates the need for an external MCLK
signal that is typically needed for PCM communication.
This reduces pin count and simplifies board layout.
Active emissions limiting with edge rate control minimizes
EMI, and eliminates the need for output filtering found in
traditional Class D devices.
An 8-bit PVDD supply voltage ADC enables the Dynamic
Headroom Tracking circuit. DHT optimizes audio program
peak behavior as the supply voltage varies and provides
flexible user-defined parameters.
Thermal foldback protection ensures robust behavior
when the thermal limits of the device are exercised. The
circuit can be enabled to automatically reduce the output
power above a user specified temperature. This allows for
uninterrupted music playback even at high ambient temperatures. Traditional thermal protection is also available
in addition to robust overcurrent protection.
All MAX98371 control is performed using a standard
2-wire, I2C interface. One of sixteen slave addresses can
be selected through two, four-level address pins. The IC
is available in a 0.4mm pitch, 30-bump WLP package. It is
specified over the extended, -40°C to +85°C temperature
range.
Applications
●● Tablets
●● Notebook Computers
●● Soundbars
19-7537; Rev 0; 3/15
Benefits and Features
●● Wide Supply Range (5.5V to 18V)
●● Dynamic Headroom Tracking Maintains a Consistent
Listening Experience
●● Integrated Thermal Foldback Allows Robust
Operation in a WLP Package
●● Remote Output Sensing Allows Up to 20dB THD+N
Improvement When Ferrites Are Used
●● Class D Edge Rate Control Enables Filterless
Operation
●● 110dB A-Weighted Dynamic Range
●● Output Power at 1% THD+N:
• 15.7W into 8Ω, VPVDD = 17V
• 13.2W into 4Ω, VPVDD = 12V
●● Output Power at 10% THD+N
• 19W into 8Ω, VPVDD = 17V
• 15.8W into 4Ω, VPVDD = 12V
●● Speaker Amplifier Efficiency
• 91% at 10W into 8Ω, VPVDD = 12V
• 81% at 15W into 4Ω, VPVDD = 12V
●● Extensive Click-and-Pop Suppression
●● Space Saving, 30-Bump WLP Package (2.1mm x
2.6mm x 0.6mm, 0.4mm Pitch)
Simplified Block Diagram
DVDD
PVDD
MAX98371
THERMAL
FOLDBACK
DHT
I 2C
DSP
General Description
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
DIGITAL
AUDIO INTERFACE
MAX98371
D
V
O
L
DAC
P
G
A
CLASS D
Ordering Information appears at end of data sheet.
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Detailed Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Interface Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Configuring the DAI Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Configuring the Digital Audio Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Digital Passband Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Biquad Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Signal Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PVDD ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Digital Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Output Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Dynamic Headroom Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DHT Ballistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Maxim Integrated │ 2
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
TABLE OF CONTENTS (continued)
Thermal ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Thermal Foldback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DOUT Operation and Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Interchip Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Multiamplifier Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Double Data Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Class D Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Ultra-Low EMI Filterless Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
VDVDD and VPVDD UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Click-and-Pop Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Amplifier Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Thermal Shutdown Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output Sensing When Using Ferrites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clocking Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Early Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I2C Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Layout and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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Maxim Integrated │ 3
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
LIST OF FIGURES
Figure 1. I2S Audio Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2. Left-Justified Audio Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3.TDM Audio Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. I2C Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. I2S Digital Audio Format Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 6. Left-Justified Digital Audio Format Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 7. TDM Digital Audio Format Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 8. Example of Dynamic Headroom Tracking in Mode 1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 9. Example of Dynamic Headroom Tracking in Mode 2 Operation with a High RP . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. Example of Dynamic Headroom Tracking in Mode 2 Operation with a Low RP . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. Example of Dynamic Headroom Tracking in Mode 3a Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 12. Example of Dynamic Headroom Tracking in Mode 3b Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 13. Example of Dynamic Headroom Tracking in Mode 3b with Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 14. Dynamic Headroom Tracking Attack functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 15. Thermal Foldback performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 16. DOUT data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 17. Single Data Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 18. Double Data Drive illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 19. Typical Application Circuit with Ferrites Beads Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 20 .THD Performance Improvement Enabled by Remote Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 21. START, STOP, and REPEATED START Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 22. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 23. Writing One Byte of Data to the MAX98371 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 24. n-Bytes of Data to the MAX98371 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 25. Reading One Byte of Data from the MAX98371 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 26. Reading n-Bytes of Data from the MAX98371 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 27. MAX98371+ WLP Ball Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
LIST OF TABLES
Table 1. MAX98371 Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 3. Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 4. Supported Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5. Supported BCLK Rates in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. Configuration for Digital Audio Interface Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Maxim Integrated │ 4
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
LIST OF TABLES (CONTINUED)
Table 7. Configuration for Digital Audio Interface Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8. TDM Channel Selection for Mono Replay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 9. Digital Highpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 10. Biquad Filter Coefficient Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 11. Signal Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 12. PVDD Measurement ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 13. Digital Volume Ramping and Digital Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 14. Digital Gain Settings and Output Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15. Speaker Gain Minimum Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 16. Dynamic Headroom Tracking Attack Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 17. Dynamic Headroom Tracking Release Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 18. Dynamic Gain Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 19. Limiter Threshold Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 20. Manual Limiter Threshold Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 21. Limiter Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 22. Limiter Attack and Release Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 23. Thermal ADC Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 24. Thermal Foldback Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 25. Thermal Foldback Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 26. DHT INFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 28. Thermal and DHT Link Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 27. THERM INFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 29. InterChip Communication Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 30. DOUT Double Data Drive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 31. DOUT DHT Receive Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 32. DOUT Thermal Foldback Receive Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 33. DOUT Thermal Foldback Receive Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 34. Extra BCLK Cycle Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 35. Manual HIZ Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 36. Speaker Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 37. Clock Monitor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 38. Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 39. Global Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 40. ADDR I2C Address Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 41. Recommended External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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Maxim Integrated │ 5
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Detailed Functional Diagram
IRQ
INTERRUPT
DISPATCHER
DVDD
UVLO
ADDR1
ADDR0
SCL
LINEAR
REGULATOR
MAX98371
I2C
CONTROL
REGISTERS
LPF
PVDD
VREFC
DVDD
DECIMATION
FILTER
PVDD
ADC
THERMAL
FOLDBACK
TEMPERATURE
MONITOR
PVDD
UVLO
SDA
DSP
RESET
CLOCK
MONITOR
DYNAMIC
HEADROOM
TRACKING
MDLL
DOUT
OUTP SNS
DIN
LRCLK
OUTP
DIGITAL AUDIO
INTERFACE
BIQUAD
MIXER
VOL
INTERPOLATION
FILTER
DAC
SPEAKER AMPLIFIER
OUTN
OUTN SNS
BCLK
DGND
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AGND
PGND
Maxim Integrated │ 6
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Absolute Maximum Ratings
PVDD to PGND........................................................-0.3V to 20V
OUT_ to PGND..................................... -0.3V to (VPVDD + 0.3V)
VREFC to AGND......................................................-0.3V to 2.2V
DVDD to DGND.......................................................-0.3V to 2.2V
SDA, SCL, ADDR_, IRQ to DGND..........................-0.3V to 2.2V
BCLK, LRCLK, DIN,
RESET to DGND ...............................-0.3V to (VDVDD + 0.3V)
AGND, DGND to PGND .........................................-0.1V to 0.1V
Short-Circuit Duration
Between OUTP, OUTN and PGND or PVDD.........Continuous
Between OUTP and OUTN ...................................Continuous
Continuous Power Dissipation (TA = +70°C) for Multilayer Board
(derate 27mW/°C above +70°C)......................................1.9W
Junction Temperature......................................................... 150°C
Operating Temperature Range...............................-40°C to 85°C
Storage Temperature Range................................-65°C to 150°C
Soldering Temperature (reflow).......................................... 260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
Junction-to-Ambient Thermal Resistance (θJA).............. 37°C/W
Junction-to-Board Thermal Resistance (θJB)................33.4°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VPVDD = 12V, VDVDD = RESET = 1.8V, VGND = 0V, CPVDD = 1x 220µF, 2x 10µF, 2x 0.1µF, CREFC = 1µF, CDVDD = 1µF, ZSPK = open,
AC measurement bandwidth 20Hz to 22kHz, fS = 48kHz, 24-bit data, TA = TMIN to TMAX, unless, otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
Power Supply Voltage
Range
VPVDD
5.5
18
VDVDD
1.14
1.98
VREFC Regulator Output
VREFC
PVDD Under Voltage
Lockout
PVDD
UVLO
DVDD Under Voltage
Lockout
DVDD
UVLO
Quiescent Current
IQ_PVDD
Quiescent Current
IQ_DVDD
2.0
3.65
4.3
4.75
472kHz
8.4
SPK_SWCLK = 1
330kHz
7
12
10
2.5
Software Shutdown Supply
Current
ISHDN_SW
All DAI pins pulled low,
TA = +25°C
IPVDD
IDVDD
10
Hardware Shutdown
Supply Current
ISHDN_HW
RESET =0V,
TA = +25°C
IPVDD
5
IDVDD
1
Turn-On Time
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tON
Volume ramping
disabled
10
Volume ramping
enabled
30
V
V
SPK_SWCLK = 0
From SW_EN bit set to full
operation
V
V
0.75
1.5
UNITS
mA
mA
µA
µA
ms
Maxim Integrated │ 7
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Electrical Characteristics (continued)
(VPVDD = 12V, VDVDD = VRESET = 1.8V, VGND = 0V, CPVDD = 1x 220µF, 2x 10µF, 2x 0.1µF, CREFC = 1µF, CDVDD = 1µF, ZSPK = open,
AC measurement bandwidth 20Hz to 22kHz, fS = 48kHz, 24-bit data, TA = TMIN to TMAX, unless, otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Turn-Off Time
tOFF
CONDITION
From SW_EN bit cleared
to shutdown
MIN
TYP
Volume ramping
disabled
10
Volume ramping
enabled
30
MAX
UNITS
ms
DIGITAL FILTER CHARACTERISICS (LRCLK < 50kHz) (Note 5)
Passband Cutoff
fPLP
Passband Ripple
Stopband Cutoff
Ripple limit cutoff
0.43 x fS
-3dB cutoff
0.47 x fS
-6.02dB cutoff
0.5 x fS
f < fPLP
Hz
-0.1
fSLP
Stopband Attenuation
f > fSLP
+0.1
dB
0.58 x fS
Hz
60
dB
DIGITAL FILTER CHARACTERISICS (LRCLK > 50kHz) (Note 5)
Passband Cutoff
fPLP
Passband Ripple
Stopband Cutoff
Ripple limit cutoff
0.24 x fS
-3dB cutoff
0.31 x fS
Hz
f < fPLP
-0.1
f > fSLP
60
dB
80
dB
fSLP
Stopband Attenuation
+0.1
dB
0.417 x fS
Hz
DIGITAL HIGHPASS FILTER CHARACTERISTICS
DC Attenuation (Note 5)
DC Blocking Cutoff
Frequency (Note 5)
Across all sample rates
Highpass Cutoff
Frequency
Across all sample rates
DACHPF = 0x1
2
DACHPF = 0x2
50
DACHPF = 0x3
100
DACHPF = 0x4
200
DACHPF = 0x5
400
DACHPF = 0x6
800
Hz
Hz
SPEAKER AMPLIFIER ELECTRICAL CHARACTERISTICS
DIGITAL VOLUME CONTROL
Digital Volume (max)
DVOL[6:0] = 0x00
0
dB
Digital Volume (min)
DVOL[6:0] = 0x7E
-63
dB
0.5
dB
Volume Control Step Size
Output Offset Voltage
Click-and-Pop Level
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VOS
TA = +25°C
KCP
Peak voltage, TA = +25°C,
A-weighted,
32 samples per second,
digital audio inputs have
zero-code input
±1
Into shutdown
±5
mV
-66
dBV
Out of shutdown
-60
Maxim Integrated │ 8
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Electrical Characteristics (continued)
(VPVDD = 12V, VDVDD = VRESET = 1.8V, VGND = 0V, CPVDD = 1x 220µF, 2x 10µF, 2x 0.1µF, CREFC = 1µF, CDVDD = 1µF, ZSPK = open,
AC measurement bandwidth 20Hz to 22kHz, fS = 48kHz, 24-bit data, TA = TMIN to TMAX, unless, otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITION
Dynamic Range
DR
VPVDD = 17V, ZL = 8Ω +
33µH, measured using the
EIAJ method,
-60dBFS 1kHz output
signal, referenced to 1%
output power
Integrated Output Noise
eN
ZL = 8Ω + 33µH
THD+N ≤ 1%, f = 1kHz
Output Power
POUT
THD+N ≤ 10%, f = 1kHz
Efficiency
ηSPK
f = 1kHz
f = 1kHz
Total Harmonic Distortion
+ Noise
THD+N
f = Up to 6kHz
Maximum Frequency
Response Deviation
Gain Error
Maximum Channel-toChannel Phase Error
(Note 3)
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MIN
A-weighted
110
A-weighted
35
Unweighted
72
ZL = 8Ω + 33µH
8.2
ZL = 8Ω + 33µH,
VPVDD = 17V
15.7
ZL = 4Ω + 33µH
13.2
ZL = 8Ω + 33µH
10.2
ZL = 8Ω + 33µH,
VPVDD = 17V
19
ZL = 4Ω + 33µH
15.8
POUT = 10W,
ZL = 8Ω + 33µH
91
POUT = 15W,
ZL = 4Ω + 33µH
81
POUT = 4W,
ZL = 8Ω + 33µH
0.02
POUT = 8W,
ZL = 4Ω + 33µH
0.03
POUT = 4W,
ZL = 8Ω + 33µH
0.1
POUT = 8W,
ZL = 4Ω + 33µH
0.2
f =1kHz, VO = 2.828VRMS
Output phase shift
between multiple devices
from 20Hz to 20kHz,
across all sample rates
and DAI operating modes
MAX
UNITS
dB
µVRMS
W
%
%
Maximum deviation above
and below 1kHz reference
AVERROR
TYP
0.2
-0.5
dB
+0.5
1
dB
deg
Maxim Integrated │ 9
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Electrical Characteristics (continued)
(VPVDD = 12V, VDVDD = VRESET = 1.8V, VGND = 0V, CPVDD = 1x 220µF, 2x 10µF, 2x 0.1µF, CREFC = 1µF, CDVDD = 1µF, ZSPK = open,
AC measurement bandwidth 20Hz to 22kHz, fS = 48kHz, 24-bit data, TA = TMIN to TMAX, unless, otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
PVDD Power Supply
Rejection Ratio
DVDD Power Supply
Rejection Ratio
Output Switching
Frequency
SYMBOL
CONDITION
PSRR
PSRR
fS
Constant across all
sample rates
MIN
TYP
MAX
UNITS
VPVDD = 5.5V to
18V
85
f = 20Hz to
10kHz, VRIPPLE =
100mVP-P
75
f = 10kHz to
20kHz, VRIPPLE =
100mVP-P
60
f = 1kHz,
VRIPPLE =
50mVP-P
100
SPK_SWCLK = 0
472
kHz
SPK_SWCLK = 1
330
kHz
0.425
Ω
6.0
A
10
µs
Output Stage
On-Resistance
RON
PMOS + NMOS
Current Limit
ILIM
ZL = 8Ω + 33µH or ZL = 4Ω + 33µH
4.5
dB
THERMAL FOLDBACK
Attack Time
Attenuation Slope
THRM_SLOPE[1:0] = 0x0
0.5
THRM_SLOPE[1:0] = 0x1
1
THRM_SLOPE[1:0] = 0x2
2
Maximum Attenuation
Release Time
dB/°C
12
THRM_REL[1:0] = 0x0
3
THRM_REL[1:0] = 0x3
300
dB
ms/dB
THERMAL SHUTDOWN
Trigger Point
(Note 3)
140
Hysteresis
150
160
20
°C
°C
PVDD ADC ELECTRICAL CHARACTERISTICS
Resolution
Absolute Error
ADC Voltage Range
ADC Lowpass Filter
Cutoff Frequency
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8
Bits
1.2
LSB
5.35
-3dB limit
18.15
0.0875
x fS
V
Hz
Maxim Integrated │ 10
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Electrical Characteristics (continued)
(VPVDD = 12V, VDVDD = VRESET = 1.8V, VGND = 0V, CPVDD = 1x 220µF, 2x 10µF, 2x 0.1µF, CREFC = 1µF, CDVDD = 1µF, ZSPK = open,
AC measurement bandwidth 20Hz to 22kHz, fS = 48kHz, 24-bit data, TA = TMIN to TMAX, unless, otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
ADC Lowpass Filter
Stopband Frequency
CONDITION
MIN
MAX
0.167
x fS
-40dB limit
ADC Programmable
Lowpass Filter
TYP
PVDD_ADC_BW[1:0] = 0x1
2
PVDD_ADC_BW[1:0] = 0x2
20
PVDD_ADC_BW[1:0] = 0x3
200
UNITS
Hz
Hz
DIGITAL I/O CHARACTERISTICS
DIN, BCLK, LRCLK, ADDR_, RESET
Input Voltage High
VIH
Input Voltage Low
VIL
Input Leakage Current
Input Capacitance
0.7 x
VDVDD
IIH, IIL
V
-1
CIN
0.3 x
VDVDD
V
+1
µA
3
pF
INPUT (SDA, SCL)
Input Voltage High
VIH
Input Voltage Low
VIL
Input Hysteresis
Input Capacitance
Input Leakage Current
OUTPUT (SDA, IRQ)
0.7 x
VDVDD
V
0.3 x
VDVDD
V
VHYS
200
mV
CIN
3
pF
IIH, IIL
Output Low Voltage
VOL
Output Current
IOL
TA = +25°C, input high
-1
ISINK = 3mA
+1
µA
0.4
V
13
mA
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS
GLOBAL
LRCLK Frequency Range
fLRCLK
All DAI operating modes
32
96
kHz
16
Word Length
All DAI operating modes
24
bits
32
BCLK Duty Cycle
Maximum BCLK/LRCLK
Input Jitter
www.maximintegrated.com
45
Maximum jitter with
minimal performance
degradation
55
RMS jitter below 40kHz
0.5
RMS jitter above 40kHz
0.9
%
ns
Maxim Integrated │ 11
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Electrical Characteristics (continued)
(VPVDD = 12V, VDVDD = VRESET = 1.8V, VGND = 0V, CPVDD = 1x 220µF, 2x 10µF, 2x 0.1µF, CREFC = 1µF, CDVDD = 1µF, ZSPK = open,
AC measurement bandwidth 20Hz to 22kHz, fS = 48kHz, 24-bit data, TA = TMIN to TMAX, unless, otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
PCM MODE
(I2S,
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
55
%
LEFT-JUSTIFIED)
LRCLK Duty Cycle
45
LRCLK to BCLK Active
Edge Setup Time
tSYNCSET
10
ns
LRCLK to BCLK Active
Edge Hold Time
tSYNCHOLD
10
ns
DIN to BCLK Active Edge
Setup Time
tSETUP
10
ns
DIN to BCLK Active Edge
Hold Time
tHOLD
10
ns
BCLK Period (Note 3)
tBCLK
160
ns
6.25
BCLK Frequency
(Note 3)
fS x 32
fBCLK
MHz
fS x 48
fS x 64
TDM MODE
LRCLK Pulse Width
PWLRCLK
DIN Frame Delay after
LRCLK Edge
Measured in number of BCLK cycles
BCLK Period (Note 3)
tBCLK
BCLK Frequency
(Note 3)
fBCLK
www.maximintegrated.com
Measured in number of BCLK cycles
0
511
cycles
2
cycles
20
All TDM operating modes
ns
50
MHz
Maxim Integrated │ 12
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
tBCLK
tBCLKH
BCLK (INPUT)
VIH
VIL
VIL
VIH
VIH tBCLKL
VIL
tSYNCHOLD
tSYNCSET
VIH
LRCLK (INPUT)
VIL
tSETUP
DIN (INPUT)
VIL
VIH
tHOLD
RIGHT MSB
LEFT MSB
Figure 1. I2S Audio Interface Timing Diagram
tBCLK
tBCLKH
BCLK (INPUT)
VIH
VIL
VIL
VIH tBCLKL
VIL
VIH
tSYNCHOLD
tSYNCSET
LRCLK (INPUT)
VIH
VIL
tSETUP
DIN (INPUT)
LEFT MSB VIL
tHOLD
VIH
RIGHT MSB
Figure 2. Left-Justified Audio Interface Timing Diagram
tBCLK
BCLK (INPUT)
VIL
tSYNCSET
VIH
tBCLKH tBCLKL
VIH
VIL
tSYNCHOLD
LRCLK (INPUT)
VIL
VIH
tSETUP
DIN (INPUT)
MSB VIL
tHOLD
VIH
Figure 3.TDM Audio Interface Timing Diagrams
www.maximintegrated.com
Maxim Integrated │ 13
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
I2C Timing Characteristics
(VPVDD = 12V, VDVDD = VRESET = 1.8V, VGND = 0V, CPVDD = 1x 220µF, 2x 10µF, 2x 0.1µF, CVREFC = 1µF, CDVDD = 1µF, ZSPK = open,
AC measurement bandwidth 20Hz to 22kHz, fS = 48kHz, 24-bit data, TA = TMIN to TMAX, unless, otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
I2C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
TIMING CHARACTERISTICS
Serial Clock Frequency
fSCL
0
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
µs
Hold Time (Repeated) START
Condition
tHD,STA
0.6
µs
SCL Pulse-Width Low
tLOW
1.3
µs
SCL Pulse-Width High
tHIGH
0.6
µs
Setup Time for a Repeated
START Condition
tSU,STA
0.6
µs
Data Hold Time
tHD,DAT
0
Data Setup Time
tSU,DAT
100
SDA and SCL Receiving Rise
Time (Note 4)
tR
20 +
0.1CB
300
ns
SDA and SCL Receiving Fall
Time (Note 4)
tF
20 +
0.1CB
300
ns
SDA Transmitting Fall Time
tF
20
250
ns
tSU,STO
0.6
Bus Capacitance
CB
400
pF
Pulse Width of Suppressed
Spike
tSP
0
50
ns
Setup Time for STOP
Condition
900
ns
ns
µs
SDA
tSU,STA
tSU,DAT
tLOW
tBUF
tHD,STA
tHD,DAT
tSP
tSU,STO
SCL
tHIGH
tHD,STA
tR
tF
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 4. I2C Interface Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 14
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Power Consumption
(VPVDD = 12V, VDVDD = VRESET = 1.8V, VGND = 0V, CPVDD = 1x 220µF, 2x 10µF, 2x 0.1µF, CVREFC = 1µF, CDVDD = 1µF, ZSPK = open,
AC measurement bandwidth 20Hz to 22kHz, fS = 48kHz, 24-bit data, TA = TMIN to TMAX, unless, otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
IPVDD
(mA)
PPVDD
(mW)
IDVDD
(mA)
PDVDD
(mW)
PTOTAL
(mW)
PCM to SPK
7.0
84.0
1.3
2.3
86.3
PCM to SPK, DHT
7.3
88.0
1.8
3.3
91.3
PCM to SPK, LMTR
7.0
84.0
1.8
3.2
87.2
PCM to SPK,
8.4
100.8
1.3
2.3
103.1
PCM to SPK, DHT
8.8
105.6
1.8
3.3
108.9
PCM to SPK, LMTR
8.5
101.5
1.8
3.2
104.7
PCM to SPK
9.3
157.7
1.3
2.3
160.0
PCM to SPK, DHT
6.6
163.0
1.8
3.3
166.6
PCM to SPK, LMTR
6.0
157.1
1.8
3.2
160.3
CONDITION
fSPK = 330kHz
fSPK = 472kHz
fSPK = 472kHz AND PVDD = 17V
Note 2: 100% production tested at TA = +25C. Specifications over temperature limits are guaranteed by design. Typical values are
based on 1 sigma characterization data, unless otherwise noted.
Note 3: Minimums and/or maximum limits shown are design targets and not 100% production tested. Characterization data is
provided to validate device performance.
Note 4: CB in pF.
Note 5: Digital filter performance is invariant over temperature and production tested at TA = +25C.
www.maximintegrated.com
Maxim Integrated │ 15
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Typical Operating Characteristics
(VPVDD = 12V, VDVDD = 1.8V, VGND = 0V, SPK_GAIN_MAX = 0x0B (20.5dB), fBCLK = 3.072MHz, fLRCLK = 48kHz, speaker loads
(ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25˚C.)
DVDD QUIESCENT CURRENT
vs. DVDD VOLTAGE
ZSPK = ∞
toc01
1.2
1.0
0.8
0.6
0.4
0.2
0.8
1.0
1.2
1.4
1.6
1.8
fSPK = 472kHz
8
7
fSPK = 330kHz
6
5
4
3
2
1
0
2.0
5
10
DVDD SOFTWARE SHUTDOWN
CURRENT vs. DVDD VOLTAGE
toc03
ZSPK = ∞
DAI PINS = GND
2.5
2.0
1.5
1.0
0.5
0.0
0.8
1.0
1.2
1.4
1.6
1.8
2.0
DVDD HARDWARE SHUTDOWN
CURRENT vs. DVDD VOLTAGE
ZSPK = ∞
RST = 0V
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.8
1.3
DVDD VOLTAGE (V)
www.maximintegrated.com
20
ZSPK = ∞
toc04
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
10
15
20
PVDD VOLTAGE (V)
toc05
PVDD HARDWARE SHUTDOWN CURRENT (μA)
DVDD HARDWARE SHUTDOWN CURRENT (μA)
0.35
PVDD SOFTWARE SHUTDOWN
CURRENT vs. PVDD VOLTAGE
0.8
DVDD VOLTAGE (V)
0.40
15
PVDD SUPPLY VOLTAGE (V)
PVDD SOFTWARE SHUTDOWN CURRENT (µA)
DVDD SOFTWARE SHUTDOWN CURRENT (μA)
DVDD SUPPLY VOLTAGE (V)
3.0
toc02
ZSPK = ∞
9
1.4
0.0
PVDD QUIESCENT CURRENT
vs. PVDD VOLTAGE
10
PVDD QUIESCENT CURRENT (mA)
DVDD QUIESCENT CURRENT (mA)
1.6
1.8
0.8
0.7
PVDD HARDWARE SHUTDOWN
CURRENT vs. PVDD VOLTAGE
toc06
ZSPK = ∞
VRST = 0V
0.6
0.5
0.4
0.3
0.2
0.1
0.0
5
10
15
20
PVDD VOLTAGE (V)
Maxim Integrated │ 16
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDVDD = 1.8V, VGND = 0V, SPK_GAIN_MAX = 0x0B (20.5dB), fBCLK = 3.072MHz, fLRCLK = 48kHz, speaker loads
(ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25˚C.)
TOTAL HARMONIC DISTORTION +
NOISE vs. OUTPUT POWER
0
-20
-20
-50
f=6kHz
-60
f=1kHz
-70
-80
-30
THD+N RATIO (dB)
-40
-40
-50
0.01
0.1
f = 6kHz
-60
f = 1kHz
-70
-80
f=100Hz
-90
f = 100Hz
-90
1
-100
0.001
10
0.01
OUTPUT POWER (W)
-10
toc09
0
ZSPK = 8Ω + 68µH
VPVDD = 17V
-10
-20
-30
THD+N RATIO (dB)
THD+N RATIO (dB)
-20
-40
-50
f = 6kHz
-60
f = 1kHz
-70
-80
-100
0.001
0.01
0.1
1
10
TOTAL HARMONIC DISTORTION +
NOISE vs. OUTPUT POWER
0
-20
-40
-50
f = 6kHz
-60
f = 1kHz
-70
-100
0.001
100
0.01
0.1
1
toc12
0
-20
-50
POUT = 0.1W
10
100
f = 6kHz
-60
-70
f = 1kHz
f=100Hz
0.01
0.1
TOTAL HARMONIC DISTORTION +
NOISE vs. FREQUENCY
1
10
100
toc13
VPVDD = 12V
ZSPK = 8Ω + 68µH
-30
-40
-50
-60
POUT = 4W
-70
POUT = 1W
-90
1000
FREQUENCY (Hz)
www.maximintegrated.com
-50
-80
POUT = 1W
-90
-40
OUTPUT POWER (W)
-10
-40
-80
-30
-100
0.001
10
toc11
ZSPK = 4Ω + 33µH
VPVDD = 12V
-90
VPVDD = 5.5V
ZSPK = 8Ω + 68µH
-70
100
TOTAL HARMONIC DISTORTION +
NOISE vs. OUTPUT POWER
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION +
NOISE vs. FREQUENCY
-60
10
-80
f = 100Hz
-90
-30
-100
-10
THD+N RATIO (dB)
THD+N RATIO (dB)
-20
1
0
-30
OUTPUT POWER (W)
-10
toc10
ZSPK = 4Ω + 33µH
VPVDD = 5.5V
-80
f = 100Hz
-90
0.1
OUTPUT POWER (W)
THD+N RATIO (dB)
0
TOTAL HARMONIC DISTORTION +
NOISE vs. OUTPUT POWER
toc08
ZSPK = 8Ω + 68µH
VPVDD = 12V
-10
-30
-100
0.001
TOTAL HARMONIC DISTORTION +
NOISE vs. OUTPUT POWER
0
ZSPK = 8Ω + 68µH
VPVDD = 5.5V
-10
THD+N RATIO (dB)
toc07
10000
100000
-100
10
100
1000
10000
100000
FREQUENCY (Hz)
Maxim Integrated │ 17
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDVDD = 1.8V, VGND = 0V, SPK_GAIN_MAX = 0x0B (20.5dB), fBCLK = 3.072MHz, fLRCLK = 48kHz, speaker loads
(ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25˚C.)
0
-10
-20
-30
-40
-50
-60
POUT = 4W
-80
10
100
10000
100000
-50
-60
POUT = 0.1W
-70
10
5.0
16
3.5
14
3.0
THD+N = 10%
2.0
THD+N = 1%
1.5
100
0
100
toc20
1
15
10% THD+N
1% THD+N
5
10
toc21
PVDD SUPPLY VOLTAGE (V)
www.maximintegrated.com
20
10000
OUTPUT POWER vs.
LOAD RESISTANCE
100000
toc19
VPVDD = 17V
THD+N = 10%
10
0.5
0.4
THD+N = 1%
1
10
100
NORMALIZED GAIN vs. FREQUENCY
toc22
NORMALIZED TO 1kHz
ZSPK = 8Ω + 68µH
0.3
14
12
10
10% THD+N
8
1% THD+N
6
0
1000
LOAD RESISTANCE (Ω)
0.2
0.1
fS = 32kHz
0
fS = 44.1kHz
-0.1
fS = 48kHz
fS = 96kHz
-0.2
-0.3
2
15
100
15
0
100
4
10
10
5
16
5
POUT = 1W
25
ZSPK = 4Ω + 33µH
18
OUTPUT POWER (W)
OUTPUT POWER (W)
toc18
OUTPUT POWER vs.
PVDD SUPPLY VOLTAGE
20
20
0
POUT = 8W
-70
LOAD RESISTANCE (Ω)
ZSPK = 8Ω + 68µH
10
-60
FREQUENCY (Hz)
THD+N = 1%
LOAD RESISTANCE (Ω)
25
100000
THD+N = 10%
6
2
OUTPUT POWER vs.
PVDD SUPPLY VOLTAGE
-50
20
8
0.5
10
10000
10
4
1
1000
12
1.0
0.0
-40
-100
VPVDD = 12V
18
4.0
2.5
-30
-90
OUTPUT POWER vs.
LOAD RESISTANCE
20
OUTPUT POWER (W)
OUTPUT POWER (W)
toc17
toc16
VPVDD = 12V
ZSPK = 4Ω + 33µH
FREQUENCY (Hz)
VPVDD = 5.5V
4.5
TOTAL HARMONIC DISTORTION +
NOISE vs. FREQUENCY
-80
POUT = 1W
FREQUENCY (Hz)
OUTPUT POWER vs.
LOAD RESISTANCE
-20
-40
-90
1000
-10
-30
-100
0
VPVDD = 5.5V
ZSPK = 4Ω + 33µH
-80
POUT = 1W
-90
-100
toc15
OUTPUT POWER (W)
-70
TOTAL HARMONIC DISTORTION +
NOISE vs. FREQUENCY
THD+N RATIO (dB)
VPVDD = 17V
ZSPK = 8Ω + 68µH
THD+N RATIO (dB)
THD+N RATIO (dB)
-20
toc14
NORMALIZED GAIN (dB)
0
-10
TOTAL HARMONIC DISTORTION +
NOISE vs. FREQUENCY
-0.4
5
7
9
11
PVDD SUPPLY VOLTAGE (V)
13
-0.5
20
200
2000
20000
FREQUENCY (Hz)
Maxim Integrated │ 18
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDVDD = 1.8V, VGND = 0V, SPK_GAIN_MAX = 0x0B (20.5dB), fBCLK = 3.072MHz, fLRCLK = 48kHz, speaker loads
(ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25˚C.)
EFFICIENCY vs. OUTPUT POWER
70
80
EFFICIENCY (%)
50
40
30
20
VPVDD = 12V
ZSPK = 4Ω + 33μH
0
100
5
10
40
fSPK = 330kHz
30
fSPK = 472kHz
15
0
0.001
20
0.01
100
fSPK = 330kHz
90
80
fSPK = 472kHz
EFFICIENCY (%)
60
50
40
30
10
toc27
5
10
15
fSPK = 330kHz
50
40
30
0.01
100
toc29
fSPK = 330kHz
90
80
90
80
fSPK = 472kHz
EFFICIENCY (%)
70
60
50
40
30
0.1
1
10
VPVDD = 12V
ZSPK = 8Ω + 68μH
10
0
2
4
6
8
OUTPUT POWER (W)
www.maximintegrated.com
10
12
fSPK = 472kHz
fSPK = 330kHz
0.01
0.1
1
toc30
1
fSPK = 472kHz
0.5
1.0
70
60
fSPK = 472k
fSPK = 330kHz
30
fSPK = 330kHz
0.01
0.1
1
10
100
POWER DISSIPATION vs.
OUTPUT POWER
toc31
VPVDD = 12V
ZSPK = 8Ω + 68μH
0.8
0.6
fSPK = 472kHz
0.4
fSPK = 330kHz
0.2
10
0
0.001
toc28
VPVDD = 17V
ZSPK = 8Ω + 68μH
1.5
1.2
VPVDD = 12V
ZSPK = 8Ω + 68μH
40
100
OUTPUT POWER (W)
EFFICIENCY vs. OUTPUT POWER
50
10
POWER DISSIPATION vs.
OUTPUT POWER
0
0.001
100
20
20
1.0
OUTPUT POWER (W)
OUTPUT POWER (W)
100
1.5
2
fSPK = 472kHz
60
0
0.001
20
EFFICIENCY vs. OUTPUT POWER
2.0
2.5
POWER DISSIPATION (W)
0
2.5
10
VPVDD = 17V
ZSPK = 8Ω + 68μH
10
3.0
OUTPUT POWER (W)
VPVDD = 17V
ZSPK = 8Ω + 68μH
70
toc25
VPVDD = 12V
ZSPK = 4Ω + 33μH
0.0
0.001
100
20
20
EFFICIENCY (%)
1
EFFICIENCY vs. OUTPUT POWER
70
0
0.1
EFFICIENCY vs. OUTPUT POWER
toc26
POWER DISSIPATION vs.
OUTPUT POWER
0.5
10
OUTPUT POWER (W)
80
EFFICIENCY (%)
50
OUTPUT POWER (W)
90
0
3.5
60
20
10
4.0
VPVDD = 12V
ZSPK = 4Ω + 33μH
70
fSPK = 472kHz
60
0
toc24
POWER DISSIPATION (W)
80
EFFICIENCY (%)
90
fSPK = 330kHz
EFFICIENCY vs. OUTPUT POWER
POWER DISSIPATION (W)
90
toc23
0.01
0.1
1
OUTPUT POWER (W)
10
100
0.0
0.001
0.01
0.1
1
10
100
OUTPUT POWER (W)
Maxim Integrated │ 19
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDVDD = 1.8V, VGND = 0V, SPK_GAIN_MAX = 0x0B (20.5dB), fBCLK = 3.072MHz, fLRCLK = 48kHz, speaker loads
(ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25˚C.)
PVDD POWER SUPPLY REJECTION
RATIO vs. FREQUENCY
toc32
80
80
70
70
60
60
50
40
20
20
10
10
0
0
100
1000
10000
100000
FREQUENCY (Hz)
140
120
5
7
9
11
13
15
17
19
21
VRIPPLE = 100mVP-P
fS = 1kHz
0
10
100
1000
10000
100000
FREQUENCY (Hz)
SOFTWARE ENABLE
TURN-ON RESPONSE
VOLUME RAMPING DISABLED
toc36
100
PSRR(dB)
60
20
SOFTWARE ENABLE
TURN-ON RESPONSE
VOLUME RAMPING ENABLED
toc35
80
40
PVDD SUPPLY VOLTAGE (V)
POWER SUPPLY REJECTION RATIO vs.
DVDD SUPPLY VOLTAGE
toc34
VRIPPLE = 100mVP-P
100
40
30
DVDD POWER SUPPLY REJECTION
RATIO vs. FREQUENCY
120
50
30
10
140
VRIPPLE = 100mVP-P
fs = 1kHz
90
PSRR (dB)
PSRR (dB)
100
VRIPPLE = 100mVP-P
ZSPK = ∞
90
toc33
PSRR (dB)
100
POWER SUPPLY REJECTION RATIO vs.
PVDD SUPPLY VOLTAGE
80
toc37
SCL
1V/div
SCL
1V/div
SPKOUT
5V/div
SPKOUT
5V/div
60
40
20
0
1.0
1.2
1.4
1.6
1.8
2.0
DVDD SUPPLY VOLTAGE (V)
SOFTWARE DISABLE
TURN OFF RESPONSE
VOLUME RAMPING ENABLED
4ms/div
www.maximintegrated.com
4ms/div
SOFTWARE DISABLE
TURN OFF RESPONSE
VOLUME RAMPING DISABLED
toc38
2ms/div
HARDWARE RESET
TURN-OFF RESPONSE
toc39
toc40
SCL
1V/div
SCL
1V/div
RST
1V/div
SPKOUT
5V/div
SPKOUT
5V/div
SPKOUT
5V/div
2ms/div
800µs/div
Maxim Integrated │ 20
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDVDD = 1.8V, VGND = 0V, SPK_GAIN_MAX = 0x0B (20.5dB), fBCLK = 3.072MHz, fLRCLK = 48kHz, speaker loads
(ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25˚C.)
BCLK REMOVAL
TURN-OFF RESPONSE
INBAND OUTPUT SPECTRUM
40
toc41
20
SPKOUT
5V/div
0
-20
-20
-60
-80
INBAND OUTPUT SPECTRUM
toc44
-120
-120
0
5000
10000
15000
-140
20000
ZSPK = 8Ω + 68µH
fS = 32kHz
ZSPK = 8Ω + 68µH
fS = 44.1kHz
20
-20
-20
-60
-80
AMPLITUDE (dBV)
0
-20
-40
-40
-60
-80
-100
-120
-120
-140
20000
FREQUENCY (Hz)
toc47
10000
15000
INBAND OUTPUT SPECTRUM
40
ZSPK = 8Ω + 68µH
fS = 44.1kHz
20
5000
20000
toc48
20
-80
AMPLITUDE (dBV)
-20
AMPLITUDE (dBV)
0
-20
-60
-40
-60
-80
-80
-100
-120
-120
-120
-140
-140
FREQUENCY (Hz)
www.maximintegrated.com
20000
0
5000
10000
FREQUENCY (Hz)
15000
20000
toc49
-60
-100
15000
20000
-40
-100
10000
15000
ZSPK = 8Ω + 68µH
fS = 48kHz
20
-20
-40
10000
INBAND OUTPUT SPECTRUM
40
ZSPK = 8Ω + 68µH
fS = 48kHz
0
5000
5000
FREQUENCY (Hz)
0
0
0
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
40
-140
0
toc46
ZSPK = 8Ω + 68µH
fS = 44.1kHz
-80
-120
15000
20000
-60
-100
10000
15000
-40
-100
5000
10000
20
0
0
5000
INBAND OUTPUT SPECTRUM
40
toc45
0
-140
0
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
40
AMPLITUDE (dBV)
AMPLITUDE (dBV)
-80
FREQUENCY (Hz)
20
AMPLITUDE (dBV)
-60
-100
2ms/div
40
-40
-100
-140
toc43
ZSPK = 8Ω + 68µH
fS = 32kHz
20
0
-40
INBAND OUTPUT SPECTRUM
40
AMPLITUDE (dBV)
LRCLK
1V/div
AMPLITUDE (dBV)
BCLK
2V/div
toc42
ZSPK = 8Ω + 68µH
fS = 32kHz
-140
0
5000
10000
15000
20000
FREQUENCY (Hz)
Maxim Integrated │ 21
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDVDD = 1.8V, VGND = 0V, SPK_GAIN_MAX = 0x0B (20.5dB), fBCLK = 3.072MHz, fLRCLK = 48kHz, speaker loads
(ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25˚C.)
INBAND OUTPUT SPECTRUM
40
20
INBAND OUTPUT SPECTRUM
40
toc51
20
-20
-20
-60
-80
AMPLITUDE (dBV)
0
-20
-40
-60
-80
-40
-60
-80
-100
-100
-100
-120
-120
-120
-140
-140
0
5000
10000
15000
20000
0
5000
FREQUENCY (Hz)
toc53
AMPLITUDE (dBV)
0
-20
-40
-60
-80
-120
15000
-140
20000
0
5000
FREQUENCY (Hz)
0
-20
-40
-60
-80
-80
-120
-120
FREQUENCY (Hz)
www.maximintegrated.com
15000
20000
toc56
-60
-100
10000
20000
-40
-100
5000
15000
ZSPK = 8Ω + 68µH
fS = 96kHz
20
-20
0
10000
INBAND OUTPUT SPECTRUM
40
AMPLITUDE (dBV)
AMPLITUDE (dBV)
toc55
ZSPK = 8Ω + 68µH
fS = 96kHz
0
-140
toc54
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
20
20000
-80
-120
10000
15000
-60
-100
5000
10000
-40
-100
40
5000
ZSPK = 8Ω + 68µH
fS = 96kHz
20
-20
0
0
INBAND OUTPUT SPECTRUM
40
0
-140
-140
20000
FREQUENCY (Hz)
ZSPK = 8Ω + 68µH
fS = 88.2kHz
20
AMPLITUDE (dBV)
15000
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
40
10000
toc52
ZSPK = 8Ω + 68µH
fS = 88.2kHz
20
0
-40
INBAND OUTPUT SPECTRUM
40
ZSPK = 8Ω + 68µH
fS = 88.2kHz
0
AMPLITUDE (dBV)
AMPLITUDE (dBV)
toc50
ZSPK = 8Ω + 68µH
fS = 48kHz
-140
0
5000
10000
15000
20000
FREQUENCY (Hz)
Maxim Integrated │ 22
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Pin Configuration
TOP VIEW (BUMP SIDE DOWN)
1
2
3
4
5
A
OUTNSNS
PVDD
PVDD
DVDD
ADDR1
SCL
B
OUTN
OUTN
PGND
DGND
ADDR0
SDA
PGND
PGND
PGND
AGND
DOUT
LRCLK
D
OUTP
OUTP
PGND
AGND
IRQ
DIN
E
OUTPSNS
PVDD
PVDD
VREFC
RESET
6
+
C
DIGITAL
www.maximintegrated.com
ANALOG
BCLK
HIGH POWER
Maxim Integrated │ 23
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Pin Description
BUMP
NAME
SUPPLY RAIL
A1
OUTNSNS
PVDD
A2, A3
E2, E3
PVDD
—
Speaker Amplifier Power Supply. Bypass each bump pair to PGND with a 10µF
and a 0.1µF, and a single 220µF per device.
A4
DVDD
—
Digital Core, Digital Audio Interface, and I2C Control Power Supply. Bypass to
DGND with a 1µF.
A5
ADDR1
DVDD
Four-Level I2C Slave Address Select Input. See the Slave Address Selection
section for additional information (Table 40).
A6
SCL
DVDD
I2C Control Clock Input
B1, B2
OUTN
PVDD
Negative Speaker Amplifier Output
B3,C1–C3,
D3
PGND
—
Speaker Amplifier Ground
B4
DGND
—
Digital Ground
B5
ADDR0
DVDD
Four-Level I2C Slave Address Select Input. See the Slave Address Selection
section for additional information (Table 40).
B6
SDA
DVDD
I2C Control Data Input/Output
C4, D4
AGND
—
C5
DOUT
DVDD
Bidirectional ICC Link Data
C6
LRCLK
DVDD
DAI Left/Right Clock Input. LRCLK is the audio sample rate clock and determines
whether audio data is routed to the left or right channel. In TDM mode, LRCLK is
a frame sync pulse with programmable width.
D1, D2
OUTP
PVDD
Positive Speaker Amplifier Output
D5
IRQ
DVDD
Hardware Interrupt Output. IRQ can be programmed to pull low
when individual bits in the flag registers change value. Connect a 10kΩ pullup
resistor for full output swing.
D6
DIN
DVDD
DAI Audio Data Input
E1
OUTPSNS
PVDD
Positive Speaker Amplifier Output Sense. If not used, connect to OUTP.
E4
VREFC
PVDD
Internal Regulator Decoupling Point. Bypass to AGND with a 1µF.
E5
RESET
DVDD
Active-Low Hardware Reset. Drive low to place the device into low power reset
mode and reset the device registers to their power-on-reset (POR) states.
E6
BCLK
DVDD
DAI Bit Clock Input
www.maximintegrated.com
FUNCTION
Negative Speaker Amplifier Output Sense. If not used, connect to OUTN.
Analog Ground
Maxim Integrated │ 24
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Detailed Description
The DAI supports I2S, left-justified, and TDM formatted
data at the following sample rates: 32kHz, 44.1kHz,
48kHz, 88.2kHz, and 96kHz. Audio bit depths of 16, 24,
and 32 bits are supported for input data. The DAI operates
from BCLK to allow the device to function without MCLK.
The MAX98371 can operate over a wide range of supply
voltage (PVDD), and has extensive on-board digital signal
processing to enable dynamic headroom tracking (DHT).
This feature automatically adjusts the output signal to fit
into the available supply voltage range. The DHT can be
completely bypassed for operation with fixed, regulated
supply voltages.
Thermal foldback allows the device to smoothly attenuate
the audio output in an effort to prevent destructive thermal
behavior. Above a set threshold, the gain of the replay path
reduces at a (user programmable) dB/°C rate to a 12dB
maximum attenuation. Thermal monitoring capabilities
alert the host when die temperature has triggered the
thermal foldback circuit, or is approaching the maximum
operating temperature. If maximum die temperature is
exceeded, the device shuts down to protect itself. Shortcircuit protection ensures that accidental shorts or highcurrent events do not cause damage to the IC.
The MAX98371 is a high-efficiency mono Class D audio
amplifier that features thermal foldback protection and
ADCs for sensing battery supply voltage and onboard
temperature.
Active emissions limiting edge rate and overshoot control
circuitry, together with Class D modulation minimize the
electromagnetic interference (EMI) traditionally associated
with Class D amplifiers. In systems that use less than 18
inches of speaker cable, an output filter is unnecessary to
meet standard EMI limits.
Two ADCs monitor PVDD supply voltage and die
temperature. The PVDD supply voltage value can be
read using the I2C interface. The temperature ADC can
be read back through I2C, however, accurate readings
only occur after the die temperature exceeds +100°C.
Device status is communicated to the host through a
hardware interrupt (IRQ) and status registers accessible
through the I2C interface.
The MAX98371 is fully programmable through the I2C
interface. ADDR0, ADDR1 connections select one of
sixteen I2C slave addresses. Shutdown mode is directly
controlled through the I2C interface, or a hardware
shutdown can be asserted through the RESET pin.
Table 1. MAX98371 Control Register Map
REGISTER DESCRIPTION
ADDR
NAME
REGISTER CONTENTS
R/W
BIT 7
BIT 6
R
—
—
BIT 5
BIT 4
BIT 3
—
WRN_
BIT2
BIT1
—
SHDN_
BIT 0
POR
STATE
—
0x00
INTERRUPTS
0x01
0x02
0x03
0x04
0x05
INTERRUPT
STATUS 0
INTERRUPT
STATUS 1
INTERRUPT
STATE 0
INTERRUPT
STATE 1
INTERRUPT
FLAG 0
www.maximintegrated.com
R
R
R
R/W
—
—
—
—
THRMFB_
STATUS
ICCOVC_
LMTRACT_
STATUS
STATUS
—
THRM
STATUS
INVAL
SLOT_
STATUS
DHTACT_
STATUS
STATUS
SPK
PVDD
PVDD
CURNT_
OVFL_
UVLO_
STATUS
STATUS
STATUS
THRM
THRM
THRMFB_
THRMFB_
THRM
THRM
END_
BGN_
WRN_END
WRN_BGN
STATE
STATE
_STATE
_STATE
ICCOVC_
LMTRACT_
STATE
STATE
—
THRM
THRMFB_
END_ FLAG
INVAL
SLOT_
STATE
DHTACT_
STATE
SHDN_END SHDN_BGN
_STATE
0x00
0x00
_STATE
SPK
PVDD
PVDD
CURNT_
OVFL_
UVLO_
STATE
STATE
STATE
THRMFB_
THRM
THRM
THRM
THRM
BGN_
WRN_END_
WRN_BGN
SHDN_
SHDN_
FLAG
FLAG
_FLAG
0x00
0x00
END_ FLAG BGN_ FLAG
Maxim Integrated │ 25
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 1. MAX98371 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR
0x06
0x07
0x08
0x09
0x0A
NAME
INTERRUPT
FLAG 1
INTERRUPT
ENABLES 0
INTERRUPT
ENABLES 1
INTERRUPT
CLEARS 0
INTERRUPT
CLEARS 1
REGISTER CONTENTS
R/W
BIT 7
R/W
—
R/W
—
R/W
—
W
BIT 5
ICCOVC_
LMTRACT_
FLAG
FLAG
INVAL
SLOT_
FLAG
BIT 3
BIT2
DHTACT_
FLAG
0x11
0x14
0x15
0x16
0x18
0x19
PCM CLOCK
SETUP
PCM SAMPLE
RATE SETUP
PCM MODE
CONFIG
PCM RX
ENABLES A
PCM RX
ENABLES B
MONOMIX
CHANNEL SOURCE
MONOMIX
CHANNEL SOURCE
SPK
PVDD
CURNT_
OVFL_
FLAG
FLAG
BIT 0
PVDD
UVLO_ FLAG
THRMFB_
THRM
THRM
THRM
THRM
BGN_
WRN_
WRN_
SHDN_
SHDN_
EN
EN
END_ EN
BGN_ EN
END_ EN
BGN_ EN
ICCOVC_
LMTRACT_
INVAL
EN
EN
SLOT_ EN
DHTACT_ EN
CURNT_
THRMFB_
THRMFB_
END_CLR
BGN_ CLR
ICCOVC_
LMTRACT_
INVAL
DHTACT_
CLR
CLR
SLOT_ CLR
CLR
SPK
EN
PVDD
PVDD
OVFL_ EN
UVLO_ EN
THRM
THRM
THRM
THRM
WRN_
WRN_
SHDN_
SHDN_
END_ CLR
BGN_ CLR
END_ CLR
BGN_ CLR
SPK
CURNT_
CLR
PCM CONFIGURATION
0x10
BIT1
END_
—
—
BIT 4
THRMFB_
—
—
W
BIT 6
PVDD
PVDD
OVFL_CLR
UVLO_ CLR
POR
STATE
0x00
0x00
0x00
0x00
0x00
R/W
—
—
—
—
BSEL[3:0]
0x06
R/W
—
—
—
—
SPK_SR[3:0]
0x08
R/W
CHANSZ[1:0]
R/W
R/W
FORMAT[2:0]
BCLEDGE
CHANSEL
—
RX_
RX_
RX_
RX_
RX_
RX_
RX_
RX_
CH7_EN
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
RX_
RX_
RX_
RX_
RX_
RX_
RX_
RX_
CH15_EN
CH14_EN
CH13_EN
CH12_EN
CH11_EN
CH10_EN
CH9_EN
CH8_EN
R/W
DMONOMIX_CH1_SOURCE[3:0]
R/W
—
—
—
DMONOMIX_CH0_SOURCE[3:0]
—
—
—
DMONOMIX_CFG[1:0]
0x80
0x00
0x00
0x00
0x00
DIGITAL FILTER PARAMETERS
0x1C
DIGITAL FILTER
0x1D
0x1E
DAC BQ B0
R/W
0x20
DAC BQ B1
R/W
R/W
0x22
R/W
0x23
0x24
R/W
R/W
R/W
0x1F
0x21
R/W
DAC BQ B2
0x25
www.maximintegrated.com
R/W
R/W
PVDD_FILT PVDD_FILT
_TO_LMTR
_TO_DHT
PVDD_ADC_BW[1:0]
—
DACHPF[2:0]
0x00
DAC_BQ_B0[23:16]
0x00
DAC_BQ_B0[15:8]
0x00
DAC_BQ_B0[7:0]
0x00
0x00
DAC_BQ_B1[23:16]
DAC_BQ_B1[15:8]
DAC_BQ_B1[7:0]
DAC_BQ_B2[23:16]
DAC_BQ_B2[15:8]
DAC_BQ_B2[7:0]
0x00
0x00
0x00
0x00
0x00
Maxim Integrated │ 26
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 1. MAX98371 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR
NAME
0x26
0x27
DAC BQ A0
DAC BQ A1
BIT 5
DIGITAL VOLUME
CONTROL
PATH GAIN
BIT 3
BIT2
BIT1
BIT 0
0x00
DAC_BQ_A1[23:16]
0x00
DAC_BQ_A1[15:8]
0x00
DAC_BQ_A1[7:0]
DVOL_
R/W
0x00
0x00
DAC_BQ_A0[7:0]
DVOL[6:0]
RAMP_BYP
POR
STATE
0x00
DAC_BQ_A0[15:8]
R/W
R/W
BIT 4
DAC_BQ_A0[23:16]
R/W
R/W
0x2B
0x2E
R/W
BIT 6
R/W
0x29
0x2D
BIT 7
R/W
0x28
0x2A
REGISTER CONTENTS
R/W
0x00
DPGA_CLIP[3:0]
SPK_GAIN_MAX[3:0]
0x0B
SPK_GAIN_MIN[3:0]
DHT_VROT_PNT[3:0]
0x00
DYNAMIC GAIN PARAMETERS
0x31
DHT ROTATION
POINT
R/W
0x32
DHT ATTACK
R/W
—
—
—
DHT_ATK_STEP[1:0]
DHT_ATK_RATE[2:0]
0x18
0x33
DHT RELEASE
R/W
—
—
—
DHT_REL_STEP[1:0]
DHT_REL_RATE[2:0]
0x00
0x34
0x36
0x37
PVDD ADC
MEASUREMENT
THERMAL
FOLDBACK
THERMAL ADC
MEASUREMENT
R
R/W
PVDD_ADC[7:0]
THRM_HOLD[1:0]
—
—
0x00
THRM_REL[1:0]
THRM_SLOPE[1:0]
0x00
R
—
—
THRM_ADC_MEAS[5:0]
0x00
R/W
—
—
THRM_MIN_TEMP[5:0]
0x00
R/W
—
—
—
—
—
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
CH7_EN
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
THERMAL
0x38
FOLDBACK MIN
TEMP
THERMAL
0x39
FOLDBACK LOW
THRM_FILT_SEL[2:0]
0x00
PASS FILTER
0x3A
0x3B
0x3C
0x3D
0x3E
PCM2 RXDHT
ENABLES A
PCM2 RXDHT
ENABLES B
PCM2 RXTHM
ENABLES A
PCM2 RXTHM
ENABLES B
PCM2 TX/
ENABLES A
www.maximintegrated.com
R/W
R/W
R/W
R/W
R/W
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
CH15_EN
CH14_EN
CH13_EN
CH12_EN
CH11_EN
CH10_EN
CH9_EN
CH8_EN
RXTHM_
RXTHM_
RXTHM_
RXTHM_
RXTHM_
RXTHM_
RXTHM_
RXTHM_
CH7_EN
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
RXTHM_
RXTHM_
RXTHM_
RXTHM_
RXTHM_
RXTHM_
RXTHM_
RXTHM_
CH15_EN
CH14_EN
CH13_EN
CH12_EN
CH11_EN
CH10_EN
CH9_EN
CH8_EN
TX_
TX_
TX_
TX_
TX_
TX_
TX_
TX_
CH7_EN
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
0x00
0x00
0x00
0x00
0x00
Maxim Integrated │ 27
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 1. MAX98371 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR
NAME
PCM2 TX
0x3F
0x40
0x41
ENABLES A
PCM2 DATA
ORDER SELECT
PCM2 HiZ
MANUAL MODE
PCM2 TX HiZ
0x42
ENABLES A
PCM2 TX HiZ
0x43
ENABLES B
R/W
REGISTER CONTENTS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT1
BIT 0
POR
STATE
TX_
TX_
TX_
TX_
TX_
TX_
TX_
TX_
CH15_EN
CH14_EN
CH13_EN
CH12_EN
CH11_EN
CH10_EN
CH9_EN
CH8_EN
R/W
—
—
—
—
—
—
—
0x00
R/W
—
—
—
—
—
EXTRA_
—
0x00
R/W
DRIVE_
MODE
0x00
TX_
—
HIZ
R/W
R/W
TX_
TX_
TX_
TX_
TX_
TX_
TX_
TX_
CH7_HIZ
CH6_HIZ
CH5_HIZ
CH4_HIZ
CH3_HIZ
CH2_HIZ
CH1_HIZ
CH0_HIZ
0x00
TX_
TX_
TX_
TX_
TX_
TX_
TX_
TX_
CH15_HIZ
CH14_HIZ
CH13_HIZ
CH12_HIZ
CH11_HIZ
CH10_HIZ
CH9_HIZ
CH8_HIZ
—
—
—
SPK_EDGE[1:0]
—
SPK_EN
0x00
DHT_EN
0x00
0x00
ENABLES
0x4A
0x4B
0x4C
SPEAKER
ENABLE
DYNAMIC GAIN
R/W
SPK_
SWCLK
R/W
—
—
—
—
—
PVADC_EN
LMTR_EN
R/W
—
—
—
—
—
—
—
RESTART BEHAVIOR R/W
—
—
—
—
CMON_
OVC_
ENA
SEL
ENABLES
THERMAL
FOLDBACK ENABLE
CMON_
0x4D
AUTO_
RESTART
TSHDN_
AUTO_
0x00
RESTART
DHT_
LINK_EN
—
—
EN
0x00
—
—
RST
0x00
R/W
—
—
—
—
—
—
0x50
GLOBAL ENABLE
R/W
—
—
—
—
—
0x51
SOFTWARE RESET
W
—
—
—
—
—
R/W
—
—
R/W
—
—
—
R/W
—
—
—
R/W
—
AND RELEASE
0x00
THM_
ICC LINK ENABLE
0x55
FB_EN
LINK_EN
0x4E
LIMITER ATTACK
THERM_
LMTR_REL_RATE[2:0]
LMTR_ATK_RATE[2:0]
0x00
0x00
LIMITER
0x58
THRESHOLD
—
—
—
LMTR_TH_SEL[1:0]
0x00
SELECT
0x59
0x5C
0xFF
LIMITER MANUAL
THRESHOLD
ICC PAD
CONTROL
REV ID
www.maximintegrated.com
R
ICC_OC_
ENA
LMTR_THC[4:0]
ICC_
ICC_
DOUTEN_
DOUT_
EXTFF
EXTFF
REVID[7:0]
0x00
ICC_PAD_CTRL[3:0]
0x00
0x43
Maxim Integrated │ 28
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Interrupts
Flag
The MAX98371 supports programmable interrupts for
sending feedback to the host about events that have
occurred on-chip. Table 2 lists the available interrupt
sources. Interrupts are output on IRQ, an active low opendrain output.
Status
Each interrupt source has one bit to indicate the real-time
STATUS of the source. This bit is read-only.
State
Each interrupt source has a STATE bit that is set whenever a rising edge occurs on the associated STATUS bit
regardless of the state of the associated ENABLE bit. This
bit is read-only.
Each interrupt source has a FLAG bit to indicate that a rising edge has occurred on the associated STATUS bit and
the associated ENABLE bit is set. This bit is read-only.
Enable
Each interrupt source has an ENABLE bit to indicate that
the associated FLAG bit is set whenever the STATE bit is
set. This bit is read/write.
Clear
Each interrupt has a CLEAR bit that clears the associated
STATE and FLAG bits when a 1 is written. Writing a 0 has
no effect. This bit is write-only.
Table 2. Interrupt Sources
NAME
Overtemperature Begin Event
Overtemperature End Event
Thermal Warning Begin Event
Thermal Warning End Event
Speaker Current Event
Invalid Slot Event
Thermal Foldback Event
Thermal Foldback End Event
VPVDD Overflow Event
PVDD UVLO Event
DHT Active Event
Limiter Active Event
ICC Overcurrent Event
www.maximintegrated.com
DESCRIPTION
Indicates when the die overtemperature threshold has been exceeded.
Indicates when the die overtemperature threshold is no longer exceeded including 20°C of
hysteresis.
Indicates when the thermal warning threshold has been exceeded.
Indicates that the die temperature was previously above the thermal warning threshold and has
now dropped below the threshold.
Indicates when the speaker amplifier current limit has been exceeded.
Indicates that a slot has been selected that is not available due to one or more of the following
reasons:
The (number of bits per channel) x (channels per frame) does not allow for the selected slot
(I2S mode only).
The number of BCLK cycles per frame does not allow for the selected slot (TDM mode only).
Indicates that the Thermal Foldback Limiter is operating in the attack or release phase.
Indicates that the die temperature was previously above the thermal threshold and has now
dropped below the threshold.
Indicates that the VPVDD supply voltage has reached the VPVDD ADC’s maximum input level.
Indicates that PVDD has dropped below the minimum allowed voltage.
Indicates that the DHT circuit is applying compression to the signal.
Indicates that the limiter circuit is applying a hard limit (infinite compression) to the signal.
Indicates that an overcurrent event is in progress on DOUT.
Maxim Integrated │ 29
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers
Interrupt Status0
Interrupt Status bits reflect real-time fault conditions. If the fault condition is less than 3-4 LRCLK cycles, the Live Status bit holds
high for 3–4 LRCLK cycles.
ADDRESS
0x01
BIT
NAME
7
0
Unused: Readback is 0.
6
0
Unused: Readback is 0.
5
THERMFB_STATUS
4
0
3
THERMWRN_STATUS
2
0
1
THERMSHDN_STATUS
0
0
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DESCRIPTION
Die Thermal Foldback Status
0: The die temperature is below the thermal warning threshold.
1: The die temperature is above the thermal warning threshold and the
signal is being dynamically attenuated.
Unused: Readback is 0.
Die Overtemperature Warning Status
0: The die temperature is below the thermal warning threshold.
1: The die temperature is above the thermal warning threshold.
Unused: Readback is 0.
Die Overtemperature Status
0: The die temperature is below the maximum die temperature.
1: The die temperature exceeds the maximum die temperature.
Unused: Readback is 0.
Maxim Integrated │ 30
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers (continued)
Interrupt Status1
Interrupt Status bits reflect real-time fault conditions. If the fault condition is less than 3–4 LRCLK cycles, the Live Status bit holds
high for 3–4 LRCLK cycles.
ADDRESS
BIT
NAME
7
0
6
ICCOVC_STATUS
5
LMTRACT_STATUS
DESCRIPTION
Unused: Readback is 0.
ICC Overcurrent Status
0: No overcurrent event on the DOUT is in progress.
1: Overcurrent event on the DOUT is in progress.
Limiter Active Status
0: Limiter is not active.
1: Limiter is active.
Invalid Slot Status
0: Slot is valid.
1: Slot is invalid, one or more possible error conditions apply:
a. The (number of bits per channel) x (channels per frame)
does not allow for the selected slot (I2S mode only)
b. The number of BCLK cycles per frame does not allow for the
selected slot (TDM mode only).
4
INVALSLOT_STATUS
3
DHTACT_STATUS
2
SPKCURNT_STATUS
Speaker Overcurrent Status
0: Speaker current is below the current limit.
1: Speaker current is above the current limit.
PVDDOVFL_STATUS
PVDD Supply Voltage Monitor Overflow Status
0: The PVDD supply voltage is below the PVDD ADC’s maximum
input level.
1: The PVDD supply voltage has exceeded the PVDD ADC’s
maximum input level
PVDDUVLO_STATUS
PVDD Supply Voltage Undervoltage Status
0: The PVDD supply voltage is above the PVDD UVLO level.
1: The PVDD supply voltage is below the PVDD UVLO threshold,
and the speaker outputs are disabled.
0x02
1
0
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DHT Active Status
0: Dynamic headroom tracking is not attacking or releasing.
1: Dynamic headroom tracking is active and is attacking or releasing.
Maxim Integrated │ 31
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers (continued)
Interrupt State 0
ADDRESS
BIT
NAME
7
0
Unused: Readback is 0.
6
0
Unused: Readback is 0.
5
4
0x03
3
2
1
0
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DESCRIPTION
THERMFB_END_STATE
Die Thermal Foldback State End Event
0: No falling edge on thermal foldback status is detected.
1: A falling edge on thermal foldback status is detected.
Note: Write a 1 to THERMFB_END_CLR to reset
THERMFB_BGN_STATE
Die Thermal Foldback State End Event
0: No rising edge on thermal foldback status is detected.
1: A rising edge on thermal foldback status is detected.
Note: Write a 1 to THERMFB_BGN_CLR to reset.
THERMWRN_END_STATE
Thermal Warning Status End Event
0: No falling edge on THERMWRN_STATUS is detected.
1: A falling edge on THERMWRN_STATUS is detected.
Note: Write a 1 to THERMWRN_END_CLR to reset.
THERMWRN_BGN_STATE
Thermal Warning Status Begin Event
0: No rising edge on THERMWRN_ STATUS is detected.
1: A rising edge on THERMWRN_STATUS is detected.
Note: Write a 1 to THERMWRN_BGN_CLR to reset.
THERMSHDN_END_STATE
Thermal Shutdown End Event
0: No falling edge on THERMSHDN_STATUS is detected.
1: A falling edge on THERMSHDN_STATUS is detected.
Note: Write a 1 to THERMSHDN_END_CLR to reset.
THERMSHDN_BGN_STATE
Thermal Shutdown Begin Event
0: No rising edge on THERMSHDN_STATUS is detected.
1: A rising edge on THERMSHDN_STATUS is detected.
Note: Write a 1 to THERMSHDN_BGN_CLR to reset.
Maxim Integrated │ 32
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers (continued)
Interrupt State 1
ADDRESS
BIT
NAME
7
0
6
5
4
0x04
3
2
1
0
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ICCOVC_STATE
LMTRACT_STATE
INVALSLOT_STATE
DHTACT_STATE
SPKCURNT_STATE
PVDDOVFL_STATE
PVDDUVLO_STATE
DESCRIPTION
Unused: Readback is 0.
ICC Overcurrent Event
0: No rising edge on ICCOVC_STATUS is detected.
1: A rising edge on ICCOVC_STATUS is detected.
Note: Write a 1 to ICCOVC_CLR to reset.
Limiter Active Event
0: No rising edge on LMTRACT_STATUS is detected.
1: A rising edge on LMTRACT_STATUS is detected.
Note: Write a 1 to LMTRACT_CLR to reset.
Invalid Slot Event
0: No rising edge on INVALSLOT_STATUS is detected.
1: A rising edge on INVALSLOT_STATUS is detected.
Note: Write a 1 to INVALSLOT_CLR to reset.
DHT Active Event
0: No rising edge on DHTACT_STATUS is detected.
1: A rising edge on DHTACT_STATUS is detected.
Note: Write a 1 to DHTACT_STATUS to reset.
Speaker Overcurrent Event
0: No rising edge on SPKCURNT_STATUS is detected.
1: A rising edge on SPKCURNT_STATUS is detected.
Note: Write a 1 to SPKCURNT_CLR to reset.
PVDD ADC Overflow Event
0: No rising edge on PVDDOVFL_STATUS is detected.
1: A rising edge on PVDDOVFL_STATUS is detected.
Note: Write a 1 to PVDDOVFL_CLR to reset.
PVDD Supply Voltage Undervoltage Lockout Event
0: No rising edge on PVDDUVLO_STATUS is detected.
1: A rising edge on PVDDUVLO_STATUS is detected.
Note: Write a 1 to PVDDOVFL_CLR to reset.
Maxim Integrated │ 33
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers (continued)
Interrupt Flag 0
ADDRESS
0x05
BIT
NAME
7
0
Unused: Readback is 0.
6
0
Unused: Readback is 0.
5
THERMFB_END_FLAG
Die Thermal Foldback End Flag
0: No thermal foldback end interrupt is generated.
1: Thermal foldback end interrupt is generated.
4
THERMFB_BGN_FLAG
Die Thermal Foldback Begin Flag
0: No thermal foldback begin interrupt is generated.
1: Thermal foldback begin interrupt is generated.
3
THERMWRN_END_FLAG
Thermal Warning End Flag
0: No thermal warning end is interrupt generated.
1: Thermal warning end interrupt is generated.
2
THERMWRN_BGN_FLAG
Thermal Warning Begin Flag
0: No thermal warning begin interrupt is generated.
1: Thermal warning begin interrupt is generated.
1
THERMSHDN_END_FLAG
Thermal Shutdown End Flag
0: No thermal shutdown end interrupt is generated.
1: Thermal shutdown end interrupt is generated.
0
THERMSHDN_BGN_FLAG
Thermal Shutdown Begin Flag
0: No thermal shutdown begin interrupt is generated.
1: Thermal shutdown begin interrupt is generated.
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DESCRIPTION
Maxim Integrated │ 34
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers (continued)
Interrupt Flag 1
ADDRESS
0x06
BIT
NAME
7
0
6
ICCOVC_FLAG
5
LMTRACT_FLAG
4
INVALSLOT_FLAG
3
DHTACT_FLAG
2
SPKCURNT_FLAG
Speaker Overcurrent Flag
0: No speaker overcurrent interrupt is generated.
1: Speaker overcurrent interrupt is generated.
1
PVDDOVFL_FLAG
PVDD ADC Overflow Flag
0: No PVDD ADC overflow interrupt is generated.
1: PVDD ADC overflow interrupt is generated.
0
PVDDUVLO_FLAG
PVDD Supply Voltage Undervoltage Lockout Flag
0: No PVDD UVLO Interrupt is generated.
1: PVDD UVLO Interrupt is generated.
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DESCRIPTION
Unused: Readback is 0.
ICC Overcurrent Flag
0: No ICC overcurrent interrupt is generated.
1: ICC overcurrent interrupt is generated.
Limiter Active Flag
0: No limiter active interrupt is generated.
1: Limiter active interrupt is generated.
Invalid Slot Flag
0: No invalid slot interrupt is generated.
1: Invalid slot interrupt is generated.
DHT Active Flag
0: No Dynamic Headroom Tracking active slot interrupt is generated.
1: Dynamic Headroom Tracking active slot interrupt is generated.
Maxim Integrated │ 35
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers (continued)
Interrupt Enable 0
ADDRESS
BIT
NAME
7
0
Unused: Readback is 0.
6
0
Unused: Readback is 0.
5
4
0x07
3
2
1
0
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DESCRIPTION
THERMFB_END_EN
Die Thermal Foldback End Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when THERMFB_END_FLAG
transitions from 0 to 1.
THERMFB_BGN_EN
Die Thermal Foldback Begin Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when THERMFB_END_FLAG
transitions from 0 to 1.
THERMWRN_END_ EN
Thermal Warning End Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when
THERMWRN_END_FLAG transitions from 0 to 1.
THERMWRN_BGN_ EN
Thermal Warning Begin Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when
THERMWRN_BGN_FLAG transitions from 0 to 1.
THERMSHDN_END_ EN
Thermal Shutdown End Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when
THERMSHDN_END_FLAG transitions from 0 to 1.
THERMSHDN_BGN_ EN
Thermal Shutdown Begin Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when
THERMSHDN_BGN_FLAG transitions from 0 to 1.
Maxim Integrated │ 36
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers (continued)
Interrupt Enable 1
ADDRESS
BIT
NAME
7
0
6
5
4
0x08
3
2
1
0
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ICCOVC_EN
DESCRIPTION
Unused: Readback is 0.
ICC Overcurrent Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when ICCOVC_FLAG
transitions from 0 to 1.
LMTRACT_EN
Limiter Active Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when LMTRACT_FLAG
transitions from 0 to 1.
INVALSLOT_EN
Invalid Slot Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt enabled. IRQ is pulled low when INVALSLOT_FLAG
transitions from 0 to 1.
DHTACT_EN
DHT Active Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when DHTACT_FLAG
transitions from 0 to 1.
SPKCURNT_EN
Speaker Overcurrent Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when SPKCURNT_FLAG
transitions from 0 to 1.
PVDDOVFL_EN
PVDD ADC Overflow Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when PVDDOVFL_FLAG
transitions from 0 to 1.
PVDDUVLO_EN
PVDD Supply Voltage Undervoltage Lockout Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when PVDDUVLO_FLAG
transitions from 0 to 1.
Maxim Integrated │ 37
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers (continued)
Interrupt Clear 0
ADDRESS
BIT
NAME
7
0
Unused: Readback is 0.
6
0
Unused: Readback is 0.
5
THERMFB_END_CLR
Die Thermal Foldback End Interrupt Clear
0: No effect.
1: Clears the THERMFB_END_STATE and THERMFB_END_FLAG.
4
THERMFB_BGN_CLR
Die Thermal Foldback Begin Interrupt Clear
0: No effect.
1: Clears the THERMFB_BGN_STATE and THERMFB_BGN_FLAG.
3
THERMWRN_END_CLR
Thermal Warning End Interrupt Clear
0: No effect.
1: Clears the THERMWRN_END_STATE and
THERMWRN_END_FLAG.
THERMWRN_BGN_CLR
Thermal Warning Begin Interrupt Clear
0: No effect.
1: Clears the THERMWRN_BGN_STATE and
THERMWRN_BGN_FLAG.
THERMSHDN_END_CLR
Thermal Shutdown End Interrupt Clear
0: No effect.
1: Clears the THERMSHDN_END_STATE and
THERMSHDN_END_FLAG.
THERMSHDN_BGN_CLR
Thermal Shutdown Begin Interrupt Clear
0: No effect.
1: Clears the THERMSHDN_BGN_STATE and
THERMSHDN_BGN_FLAG.
0x09
2
1
0
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DESCRIPTION
Maxim Integrated │ 38
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 3. Interrupt Registers (continued)
Interrupt Clear 1
ADDRESS
0x0A
BIT
NAME
7
0
6
ICCOVC_CLR
5
LMTRACT_CLR
4
INVALSLOT_CLR
3
DHTACT_CLR
2
SPKCURNT_CLR
Speaker Overcurrent Interrupt Clear
0: No effect.
1: Clears the SPKCURNT_STATE and SPKCURNT_FLAG.
1
PVDDOVFL_CLR
PVDD ADC Overflow Interrupt Clear
0: No effect.
1: Clears the PVDDOVFL_STATE and PVDDOVFL_FLAG.
0
PVDDUVLO_CLR
PVDD Supply Voltage Undervoltage Lockout Interrupt Clear
0: No effect.
1: Clears the PVDDUVLO_STATE and PVDDUVLO_FLAG.
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DESCRIPTION
Unused: Readback is 0.
ICC Overcurrent Clear
0: No effect.
1: Clears the ICCOVC_STATE and ICCOVC_FLAG.
Limiter Active Interrupt Clear
0: No effect.
1: Clears the LMTRACT_STATE and LMTRACT_FLAG.
Invalid Slot Interrupt Clear
0: No effect.
1: Clears the INVALSLOT_STATE and INVALSLOT_FLAG.
DHT Active Interrupt Clear
0: No effect.
1: Clears the DHTACT_STATE and DHTACT_FLAG.
Maxim Integrated │ 39
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Digital Audio Interface
Operating in slave mode only, the MAX98371 eliminates
the need for the external MCLK signal that is typically
used in I2S applications by generating MCLK internally.
This reduces EMI and improves the RF immunity of the
IC. Table 5 lists the supported BCLK frequencies when
operating in this mode.
The digital audio interface (DAI) is highly flexible,
supporting common sample rates (Table 4) with 16/24/
32-bit depth for I2S/left-justified data as well as up to 16
slots in a time division multiplexed (TDM) format.
Table 4. Supported Sample Rates
ADDRESS
BIT
NAME
3
2
0x11
SPK_SR[3:0]
1
0
DESCRIPTION
Speaker Path Sample Rate Select
0000–0101: Reserved
0110: 32kHz
0111: 44.1kHz
1000: 48kHz
1001: Reserved
1010: 88.2kHz
1011: 96kHz
1100–1111: Reserved
Table 5. Supported BCLK Rates in Slave Mode
ADDRESS
BIT
NAME
3
2
0x10
1
0
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BSEL[3:0]
DESCRIPTION
Selects the Number of BCLKs/LRCLK
0000: Not supported
0001: Not supported
0010: 32 BCLKs
0011: 48 BCLKs
0100: 64 BCLKs
0101: 96 BCLKs
0110: 128 BCLKs
0111: 192 BCLKs
1000: 256 BCLKs
1001: 384 BCLKs
1010: 512 BCLKs
1011–1111: Not supported
Maxim Integrated │ 40
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Interface Format
TDM mode (Figure 7) uses a frame sync pulse instead
of a 50% duty cycle frame clock. The frame sync pulse
(applied to the LRCLK pin) is equal to one BCLK period
as a minimum, although the interface operates with longer
periods; the rising edge of LRCLK is used to indicate
the start of a new frame. The falling edge can occur at
any time as long as it does not violate the setup time
requirements of the LRCLK rising edge. In TDM, latch the
MSB of the first audio word on the first or second active
BCLK edge after an LRCLK rising edge.
The MAX98371 supports standard I2S, left-justified, and
TDM data formats. I2S and Left-Justified formats support
two audio channels of 16, 24 or 32-bit depth. TDM
supports up to 16 audio channels of 16-, 24-, or 32-bit
depth. The IC supports slave operation only, and the
LRCLK and BCLK pins operate as inputs.
I2S (Figure 5) and left-justified (Figure 6) modes configure
the LRCLK signal to transition before each channel. With
the default I2S settings LRCLK low indicates left channel
while LRCLK high indicates the right channel. The MSB
of the audio word is latched on the second active BCLK
edge after an LRCLK transition. In left-justified mode, the
MSB of the audio word is latched on the first active BCLK
edge after an LRCLK transition.
Configuring the DAI Format
Specify the format by configuring the LRCLK invert, BCLK
active edge, data delay, and TDM mode configuration bits
(Table 6).
Table 6. Configuration for Digital Audio Interface Format
ADDRESS
BIT
7
6
NAME
CHANSZ[1:0]
Configures Channel Word Length
00: 8 bits
10: 24 bits
01: 16 bits
11: 32 bits
FORMAT[2:0]
PCM Format Select
000: I2S mode
001: Left-justified
010: Right-justified
011: TDM mode 1
100: TDM mode 2
101–111: Reserved
5
4
DESCRIPTION
3
0x14
BCLEDGE
Active BCLK Edge Select
0: Data captured and valid on rising edge of BCLK
1: Data captured and valid on the falling edge of BCLK
1
CHANSEL
Non-TDM LRCLK Starting Edge
0: Falling LRCLK indicates the start of a stereo pair. Channel 0 when
LRCLK is low, Channel 1 when LRCLK is high.
1: Rising LRCLK indicates the start of a stereo pair. Channel 0 when
LRCLK is high, Channel 1 when LRCLK is low.
0
0
2
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0
Maxim Integrated │ 41
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Configuring the Digital Audio Input
Route mono data directly to the speaker amplifier. If the
input is stereo, input the right channel to the device and
mix with the left channel if desired. Sum left and right
channels with the amplitude divided by 2 to reduce the
DAC input and avoid saturation. Stereo summing and L or
R choices are limited to 2 adjacent slots on the TDM bus.
The DAI may be configured to accept a mono PCM input,
placed from anywhere from slots 1 to 16 of digital audio in
TDM mode. In I2S and left-justified modes, two channels
are available.
Table 7. Configuration for Digital Audio Interface Format
ADDRESS
BIT
NAME
7
RX_CH7_EN
Receive Channel Enable
0: Receive channel 7 is disabled.
1: Receive channel 7 is enabled.
6
RX_CH6_EN
Receive Channel Enable
0: Receive channel 6 is disabled.
1: Receive channel 6 is enabled.
5
RX_CH5_EN
Receive Channel Enable
0: Receive channel 5 is disabled.
1: Receive channel 5 is enabled.
4
RX_CH4_EN
Receive Channel Enable
0: Receive channel 4 is disabled.
1: Receive channel 4 is enabled.
3
RX_CH3_EN
Receive Channel Enable
0: Receive channel 3 is disabled.
1: Receive channel 3 is enabled.
2
RX_CH2_EN
Receive Channel Enable
0: Receive channel 2 is disabled.
1: Receive channel 2 is enabled.
1
RX_CH1_EN
Receive Channel Enable
0: Receive channel 1 is disabled.
1: Receive channel 1 is enabled.
0
RX_CH0_EN
Receive Channel Enable
0: Receive channel 0 is disabled.
1: Receive channel 0 is enabled.
0x15
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DESCRIPTION
Maxim Integrated │ 42
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 7. Configuration for Digital Audio Interface Format (continued)
ADDRESS
BIT
NAME
7
RX_CH15_EN
Receive Channel Enable
0: Receive channel 15 is disabled.
1: Receive channel 15 is enabled.
6
RX_CH14_EN
Receive Channel Enable
0: Receive channel 14 is disabled.
1: Receive channel 14 is enabled.
5
RX_CH13_EN
Receive Channel Enable
0: Receive channel 13 is disabled.
1: Receive channel 13 is enabled.
4
RX_CH12_EN
Receive Channel Enable
0: Receive channel 12 is disabled.
1: Receive channel 12 is enabled.
3
RX_CH11_EN
Receive Channel Enable
0: Receive channel 11 is disabled.
1: Receive channel 11 is enabled.
2
RX_CH10_EN
Receive Channel Enable
0: Receive channel 10 is disabled.
1: Receive channel 10 is enabled.
1
RX_CH9_EN
Receive Channel Enable
0: Receive channel 9 is disabled.
1: Receive channel 9 is enabled.
0
RX_CH8_EN
Receive Channel Enable
0: Receive channel 8 is disabled.
1: Receive channel 8 is enabled.
0x16
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DESCRIPTION
Maxim Integrated │ 43
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 8. TDM Channel Selection for Mono Replay
ADDRESS
BIT
NAME
DMONOMIX_CH1_SOURCE[3:0]
Digital Monomix Source Selection
0000: Channel 1 gets PCM RX channel 0.
0001: Channel 1 gets PCM RX channel 1.
0010: Channel 1 gets PCM RX channel 2.
0011: Channel 1 gets PCM RX channel 3.
…
1111: Channel 1 gets PCM RX channel 15.
DMONOMIX_CH0_SOURCE[3:0]
Digital Monomix Source Selection
0000: Channel 0 gets PCM RX channel 0.
0001: Channel 0 gets PCM RX channel 1.
0010: Channel 0 gets PCM RX channel 2.
0011: Channel 0 gets PCM RX channel 3.
…
1111: Channel 0 gets PCM RX channel 15.
7
6
5
0x18
4
3
2
1
0
1
0x19
DESCRIPTION
DMONOMIX_CFG[1:0]
0
Monomix Configuration
00: Output of Monomix is channel 0.
01: Output of Monomix is channel 1.
10: Output of Monomix is (channel 0 + channel 1)/2.
11: Reserved
Figure 5. I2S Digital Audio Format Examples
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Maxim Integrated │ 44
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
LEFT-JUSTIFIED MODE (STANDARD)
DOUT
CH1
CH0
LRCLK
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6
D5 D4 D3 D2
D1 D0
D15 D14 D13 D12 D11 D10 D9
D8
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6
D5 D4 D3 D2
D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6
D5 D4 D3 D2
D1 D0
BCLK
DIN
D7 D6 D5 D4 D3 D2 D1 D0
LEFT-JUSTIFIED MODE (BCLK INVERTED)
CH0
LRCLK
DOUT
CH1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0
BCLK
DIN
Figure 6. Left-Justified Digital Audio Format Examples
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Maxim Integrated │ 45
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
TDM MODE 1, 16 32-BIT CHANNELS LATCHED ON FALLING EDGE OF BCLK, PCM_BCLEDGE = 1,
PCM_FORMAT = 011
LRCLK
DOUT
HIZ
D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
HIZ
BCLK
DIN
TDM MODE 1, 16 32-BIT CHANNELS LATCHED ON RISING EDGE OF BCLK, PCM_BCLEDGE = 0,
PCM_FORMAT = 011
LRCLK
DOUT
HIZ
D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
HIZ
BCLK
DIN
TDM MODE 2, 16 32-BIT CHANNELS LATCHED ON FALLING EDGE OF BCLK, PCM_BCLEDGE = 1,
PCM_FORMAT = 100
LRCLK
DOUT
HIZ
D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
HIZ
BCLK
DIN
TDM MODE 2, 16 32-BIT CHANNELS LATCHED ON FALLING EDGE OF BCLK, PCM_BCLEDGE = 0,
PCM_FORMAT = 100
LRCLK
DOUT
HIZ
D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
HIZ
BCLK
DIN
Figure 7. TDM Digital Audio Format Examples
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Maxim Integrated │ 46
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Digital Passband Filtering
through the biquad filter coefficients by setting the
DACHPF[2:0] bits to 111. See the Biquad Filter section.
The MAX98371 features an optional highpass filter with
selectable corner frequency (50Hz, 100Hz, 200Hz, 400Hz,
and 800Hz), or a DC blocking filter with a cutoff frequency
of 2Hz (80dB attenuation). The MAX98371 supports 5
sample rates: 32kHz, 44.1kHz, 48kHz, 88.2kHz or 96KHz.
For 32kHz, 44.1kHz and 48kHz, a linear phase, halfband filter effectively defines the response. For 96kHz
operation, a different filter characteristic is employed with
a smooth roll off above 20kHz. Set the digital highpass
filter corner frequency though the DACHPF bits in control
register 0x1C (Table 9). Create user-programmed filtering
The MAX98371 also features a configurable PVDD ADC
filter. This cutoff frequency of this filter can be adjusted by
setting the PVDD_ADC_BW bits in register 0x1C. These
filtered PVDD ADC measurements can be fed to the DHT
or limiter. Filtered or unfiltered PVDD ADC readings can
be sent to the DHT and limiter. To send filtered data to the
limiter or DHT, set the PVDD_FILT_TO_LMTR or PVDD_
FILT_TO_DHT bits, respectively. See Table 9.
Table 9. Digital Highpass Filter
ADDRESS
BIT
NAME
7
PVDD_FILT_TO_LMTR
6
PVDD_FILT_TO_DHT
0: Unfiltered PVDD ADC measurements are sent to DHT.
1: Lowpass filtered PVDD ADC measurements are sent to DHT.
PVDD_ADC_BW[1:0]
PVDD ADC Lowpass Filter Selection
00: Pass through, filter off
01: 2Hz cutoff
10: 20Hz cutoff
11: 200Hz cutoff
5
4
0x1C
3
0
2
1
0
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DACHPF[2:0]
DESCRIPTION
0: Unfiltered PVDD ADC measurements are sent to the limiter.
1: Lowpass filtered PVDD ADC measurements are sent to limiter.
0
Digital Highpass Filter
000: Pass through, filter off
001: DC blocker is enabled.
010: 50Hz HPF is enabled.
011: 100Hz HPF is enabled.
100: 200Hz HPF is enabled.
101: 400Hz HPF is enabled.
110: 800Hz HPF is enabled.
111: User programmable using DAC_BQ_B[0–2] and DAC_BQ_A[1–2]
registers
Maxim Integrated │ 47
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Biquad Filter
The digital biquad coefficients are uninitialized at powerup, and if the filter is going to be used, the coefficients
must be programmed before the device and biquad filter
are enabled. The transfer function is:
The digital biquad filter has five user-programmable
coefficients (B0, B1, B2, A1, and A2), and each individual
coefficient is 3 bytes (24 bits) long (A0 is fixed at 1). They
occupy 15 consecutive registers (Table 10) and each set
of three registers (per coefficient) must be programmed
consecutively for the settings to take effect. The coeffi
cients are stored using a two’s complement format where
the first 4 bits are the integer portion and the last 20 bits
are the decimal portion that results in an approximate +8
to -8 range for each coefficient.
H(z) =
B 0 + B 1 * Z -1 + B 2 * Z -2
1 + A 1 * Z -1 + A 2 * Z -2
Signal Path Delay
Delay through the signal path is minimized by use of
efficient signal processing and hardware DSP. Delay is
affected by the configuration of various blocks and filters
in the signal path. Typical delay, listed in number of audio
samples, is shown in Table 11.
Table 10. Biquad Filter Coefficient Registers
REG
REG NAME
0x1D
Biquad
Coefficient B0
0x1E
0x1F
0x20
Biquad
Coefficient B1
0x21
0x22
0x23
Biquad
Coefficient B2
0x24
0x25
0x26
Biquad
Coefficient A1
0x27
0x28
0x29
Biquad
Coefficient A2
0x2A
0x2B
R/W
BIT NAME
VALUE
R/W
B0[23:16]
0x00
R/W
B0[15:8]
0x00
R/W
B0[7:0]
0x00
R/W
B1[23:16]
0x00
R/W
B1[15:8]
0x00
R/W
B1[7:0]
0x00
R/W
B2[23:16]
0x00
R/W
B2[15:8]
0x00
R/W
B2[7:0]
0x00
R/W
A1[23:16]
0x00
R/W
A1[15:8]
0x00
R/W
A1[7:0]
0x00
R/W
A2[23:16]
0x00
R/W
A2[15:8]
0x00
R/W
A2[7:0]
0x00
Table 11. Signal Path Delay
SAMPLE RATE
DELAY (SAMPLES)
32k
19
44.1k
19
48k
18
88.2k
15
96k
14
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Maxim Integrated │ 48
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
PVDD ADC
The PVDD ADC readback is real time and is dependant
on the PVDD_ADC_BW register setting in register 0x1C.
The PVDD ADC has an effective 8kHz sample rate, 8-bit
resolution and full scale input of 18V. The bandwidth
of the output is user programmable to reject both high
frequency and audio band noise from the supply, and to
tradeoff reaction time to follow the supply accurately. The
PVDD_ADC values are used to by the DHT and Limiter
circuits. These values can be read back over I2C through
the PVDD_ADC Register located at 0x34. See Table 12.
Digital Volume Control
A user-controlled digital volume control with an attenuation
range of 0dB to -63dB in 0.5dB steps, as well as a mute
setting is available. Volume ramping is available and
configurable with through the DVOL_RAMP_BYP bit in
the digital volume control register. See Table 13.
Table 12. PVDD Measurement ADC
ADDRESS
BIT
NAME
DESCRIPTION
7
6
5
0x34
4
3
PVDD_ADC[7:0]
2
1
0: 5.35V
1: 5.40V
2: 5.45V
3: 5.50V
…
253: 18.05V
254: 18.10V
255: 18.15V
0
Table 13. Digital Volume Ramping and Digital Volume
ADDRESS
BIT
NAME
7
DVOL_RAMP_BYP
6
0x2D
5
4
3
2
1
0
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DVOL[6:0]
DESCRIPTION
Digital Volume Ramp Bypass
0: Ramping is enabled at startup, shutdown and all volume changes.
1: All volume ramping is disabled.
Digital Volume Control
0: 0dB
1: -0.5dB
2: -1.0dB
3: -1.5dB
…
125: -62.5dB
126: -63.0dB
127: Digital mute
Maxim Integrated │ 49
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Output Voltage Scaling
The DPGA and SPK_GAIN_MAX register settings are
shown in Table 14.
The MAX98371 operates over a large supply voltage
range. As a result, the part must be configured to scale
the output signals across possible PVDD supply range.
SPK_GAIN_MAX applies gain after the DAC to achieve
this voltage scaling.
Digital gain can be applied before the DAC by using the
DPGA_CLIP register. In conjunction with the SPK_GAIN_MAX
setting, the overall full-scale behavior of the device is set.
Gain through the signal path is referenced to the full-scale
output of the DAC, which is 2.1dBV. The MAX98371 output
level can be calculated based on the digital input signal
level and selected amplifier gain.
Output signal level (dBV) = input signal level (dBFS) +
2.1dBV + SPK_GAIN_MAX (dB)
where 0dBFS is referenced to 0dBV.
Table 14. Digital Gain Settings and Output Voltage Scaling
ADDRESS
BIT
NAME
7
6
5
DPGA_CLIP[3:0]
4
3
0x2E
2
SPK_GAIN_MAX[3:0]
1
0
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DESCRIPTION
Digital Gain Settings (dB)
0000: 0
0110: 3.0
0001: 0.5
0111: 3.5
0010: 1.0
1000: 4.0
0011: 1.5
1001: 5.0
0100: 2.0
1010: 6.0
0101: 2.5
1011–1111: 0
Speaker No-Load Output Voltage Maximum
Sets the output voltage level (VP) of 0dBFS.
0000: 5.37 (9.5dB)
Guaranteed no clipping
0001: 6.03 (10.5dB)
Best near 5.5V (min) operating
0010: 6.77 (11.5dB)
0011: 7.59 (12.5dB)
0100: 8.52 (13.5dB)
2-cell Li-ion operation
0101: 9.56 (14.5dB)
0110: 10.72 (15.5dB)
0111: 12.03 (16.5dB)
12V nominal
1000: 13.5 (17.5dB)
3-cell Li-ion operation
1001: 15.15 (18.5dB)
1010: 16.99 (19.5dB)
Optimum for 16.5V PVDD operation
1011: 19.07 (20.5dB)
1100–1111:
Reserved
Maxim Integrated │ 50
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Dynamic Headroom Tracking
A key element in tracking available headroom is the
PVDD ADC. The output of the ADC feeds the DHT circuitry with the necessary inputs to calculate the amount of
compression (if any) applied to signal peaks. Filtering can
be applied to the PVDD ADC readings used by the DHT
by using the PVDD_FILT_TO_DHT bit (Table 9).
The dynamic headroom tracking function relies heavily on two parameters to be effective. The first is the
SPK_GAIN_MAX setting explained in the Output Voltage
Scaling section. This sets the maximum no-load peak
output voltage (VMPO) that the Class D amplifier reproduces when fed with a full-scale (0dBFS) signal. The
second parameter is the rotation point (RP). The rotation
point sets the level in dBFS above which compression
is applied to the output signal, if the PVDD voltage level
drops below VMPO.
DHT uses a parameter called SPK_GAIN_MIN to control
the maximum compression ratio. This parameter can
enable the addition of a second inflection point on the
transfer function.
PVDD > VMPO
VMPO
VEXP_RP
OUTPUT VOLTAGE LEVEL (VP)
The MAX98371 features dynamic headroom tracking
(DHT) to preserve consistent dynamic range in the presence of a varying supply. DHT maintains consistent volume and listening levels up to a predefined point, below
full scale. DHT maintains the headroom of the amplifier at
signal peaks that occur above this level (referred to as the
rotation point or RP) up to full scale to ensure consistent,
smooth compression of these signals in the presence of
supply variations.
ROTATION POINT (RP)
SET BY USER
INPUT SIGNAL LEVEL (dBFS)
-6
0
Figure 8. Example of Dynamic Headroom Tracking in Mode 1
Operation
MODE 1: PVDD voltage is greater than maximum peak
output voltage. If VPVDD is greater than VMPO then there
is no action taken by the DHT block. There is sufficient
headroom for the amplifier to linearly represent any signal
up to and including 0dBFS; the signal transfer function is
unaffected.
The behavior of DHT has 3 modes, depending on the
measured value of VPVDD by the PVDD ADC:
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Maxim Integrated │ 51
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
MODE 2: VPVDD is less than VMPO, and greater than the
output voltage as set by the Rotation Point register setting (VEXP_RP). For example, if the RP is set for -6dBFS,
then the peak voltage on the output (VEXP_RP) would
be VMPO/2). If this is the case, the transfer function for
signals below the RP is reproduced exactly as in Mode 1.
Any signals between RP and 0dBFS are now subject to
an audio compression function, acting in the DSP block
of the MAX98371. This acts with appropriate attenuation
for peaks over the RP in magnitude with programmable
attack and release times. See the DHT Ballistics section.
Figure 9 and Figure 10 show the effect on the transfer
function.
VMPO
DECREASING PVDD
MAX98371
SPK_GAIN_MAX
PVDD < VMPO
PEAK OUTPUT SCALED TO
FIT AVAILABLE PVDD
OUTPUT VOLTAGE LEVEL (VP)
VEXP_RP
RP SET BY USER
COMPRESSION RATIO IS SCALED TO
FIT TRANSFER FUNCTION
AUTOMATICALLY BETWEEN
ROTATION POINT AND THEORETICAL
PEAK OUTPUT VOLTAGE (AS
DETERMINED BY PVDD ADC BLOCK)
INPUT SIGNAL LEVEL (dBFS)
-6
0
INPUT (dBFS)
Figure 9. Example of Dynamic Headroom Tracking in Mode 2 Operation with a High RP
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Maxim Integrated │ 52
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
OUTPUT VOLTAGE LEVEL (VP)
VMPO
DECREASING PVDD
MAX98371
SPK_GAIN_MAX
PVDD < VMPO
PEAK OUTPUT SCALED TO
FIT AVAILABLE PVDD
SPK_GAIN_MIN
COMPRESSION RATIO IS SCALED TO
FIT TRANSFER FUNCTION
AUTOMATICALLY BETWEEN
ROTATION POINT AND THEORETICAL
PEAK OUTPUT VOLTAGE (AS
DETERMINED BY PVDD ADC BLOCK)
RP SET BY USER
VEXP_RP
-30
INPUT SIGNAL LEVEL (dBFS)
0
Figure 10. Example of Dynamic Headroom Tracking in Mode 2 Operation with a Low RP
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Maxim Integrated │ 53
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
The compression ratios in Mode 2 are effectively defined
by the combination of: PVDD, RP, SPK_GAIN_MAX, and
SPK_GAIN_MIN settings. The ballistics of the compressor
(in both Mode 2 and Mode 3) are set by the parameters
in Table 16 and Table 17.
Table 15. Speaker Gain Minimum Voltage
ADDRESS
BIT
NAME
SPK_GAIN_MIN[3:0]
Speaker Gain Min (VP):
0000: 5.37 (9.5dB)
0001: 6.03 (10.5dB)
0010: 6.77 (11.5dB)
0011: 7.59 (12.5dB)
0100: 8.52 (13.5dB)
0101: 9.56 (14.5dB)
0110: 10.72 (15.5dB)
DHT_VROT_PNT[3:0]
DHT Rotation Point (dBFS)
0000: -0.5
1000: -10
0001: -1
1001: -12
0010: -2
1010: -15
0011: -3
1011: -18
0100: -4
1100: -20
0101: -5
1101: -22
0110: -6
1110: -25
0111: -8
1111: -30
7
6
5
4
0x31
3
2
1
0
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DESCRIPTION
0111: 12.03 (16.5dB)
1000: 13.5 (17.5dB)
1001: 15.15 (18.5dB)
1010: 16.99 (19.5dB)
1011: 18.0 (20.0dB)
1100–1111: Reserved
Maxim Integrated │ 54
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
MODE 3a: PVDD voltage is less than the rotation points
maximum output voltage, VEXP_RP. When the rotation
point is set to a high value (for example -6dBFS) this
mode applies. If VPVDD is less than VEXP_RP, then
hard limiting is applied to peaks and the effective RP is
now set by the need to fit peak signals into the available
PVDD range. The MAX98371 automatically determines
a new RP based on the PVDD ADC. Normally, RP is set
so that this mode is never used, and the VEXP_RP as
set by the RP and SPK_GAIN_MAX combination should
reflect the lowest PVDD value expected. In this Mode the
SPK_GAIN_MAX
PVDD < VEXP_RP
WHEN PVDD < VEXP_RP A NEW
ROTATION POINT IS
AUTOMATICALLY DETERMINED AND
INFINITE COMPRESSION IS APPLIED.
RP SET BY USER
OUTPUT VOLTAGE LEVEL (VP)
VEXP_RP
DECREASING PVDD
VMPO
INPUT SIGNAL LEVEL (dBFS)
-6
0
Figure 11. Example of Dynamic Headroom Tracking in Mode 3a Operation
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Maxim Integrated │ 55
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
SPK_GAIN_MIN parameter is set to be well below the
VEXP_RP.
MIN, the output signal starts to clip. This clipping can be
eliminated if the limiter is enabled in addition to the DHT.
MODE 3b: PVDD voltage is less than the speaker gain
minimum output voltage. When the Rotation Point is set
to a low value (for example -30dBFS), this mode applies.
If VPVDD is less than SPK_GAIN_MIN, the DHT cannot
compress the signal any further. So the compression ratio
stays fixed, and as PVDD decreases below SPK_GAIN_
Figure 10 and Figure 12 show an additional parameter, SPK_GAIN_MIN, on the transfer function plots.
This parameter is useful when a lower RP is selected.
SPK_GAIN_MIN provides a means to create a maximum
compression ratio. When the input signal reaches the
maximum output voltage that PVDD can provide, the
OUTPUT VOLTAGE LEVEL (VP)
SPK_GAIN_MIN
DECREASING PVDD
SPK_GAIN_MAX
VMPO
PVDD < SPK_GAIN_MIN
CLIPPING
COMPRESSION
RP SET BY USER
VEXP_RP
-30
INPUT SIGNAL LEVEL (dBFS)
0
Figure 12. Example of Dynamic Headroom Tracking in Mode 3b Operation
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Maxim Integrated │ 56
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
output signal starts to clip (Figure 12). This behavior may
not be desirable, but the clipping can be eliminated by
enabling the limiter. See Figure 13.
The transfer function shown in Figure 13 is typically
preferable to the transfer function shown in Figure 12.
When DHT and the limiter are used together, it allows
for creation of a second inflection point on the transfer
SPK_GAIN_MAX
DECREASING PVDD
OUTPUT VOLTAGE LEVEL (VP)
VMPO
SPK_GAIN_MIN
PVDD < SPK_GAIN_MIN
LIMITING
COMPRESSION
THE PERFORMANCE SHOWN
IN THIS FIGURE IS THE
RESULT OF THE DHT AND
THE LIMITER WORKING IN
CONCERT
RP SET BY USER
VEXP_RP
-30
INPUT SIGNAL LEVEL (dBFS)
0
Figure 13. Example of Dynamic Headroom Tracking in Mode 3b with Limiter.
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Maxim Integrated │ 57
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
function. This second inflection point reduces the transition
from compression to limiting and minimizes the audible
impact of signal manipulation by the DHT.
full attack time has completed there should be no clipping.
Hard clipping can also be prevented by using the limiter.
See the Limiter section.
DHT Ballistics
Observing the output waveform, the amount of attenuation applied increases up to when VIN(dBFS) = PVDD
(dBFS). Once VIN(dBFS) is greater than PVDD(dBFS) the
amount of attenuation observed in the output waveform
appears to decrease. This is a result of the output clipping
against the PVDD voltage level. The DHT still takes the
same amount of time to apply the compression as though
it had the headroom to reproduce the signal.
When an input signal exceeds the rotation point, DHT
will apply attenuation to the signal over some amount of
time (this is configurable by through the DHT_ATK_RATE
register 0x32). The instant that the large signal is input to
the MAX98371, the output tries to reproduce that signal
without any attenuation from the DHT. Over time, the
DHT applies compression to ensure that the signal can
fit within the available PVDD voltage. If a large enough
input signal is applied there can be hard clipping on the
output for a short time. See Figure 14. However, after the
The amount of compression applied by DHT depends on
a few parameters: SPK_GAIN_MAX, PVDD, input signal
amplitude, and the rotation point.
SPK_GAIN_MAX
VMPO
OUTPUT VOLTAGE LEVEL (VP)
-3 dB
VPVDD = 8.4V
ATTACK
THE ATTACK ARROW
DEMOSTRATES THE TRANSISTION
FROM AN UNATTENUATED SIGNAL
TO THE COMPRESSED SIGNAL
THAT OCCURS OVER THE TOTAL
ATTACK TIME.
RP SET BY USER
VEXP_RP
-10
INPUT SIGNAL LEVEL (dBFS)
-3
0
INPUT (dBFS)
Figure 14. Dynamic Headroom Tracking Attack Functionality
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Maxim Integrated │ 58
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
To establish where PVDD is relative to speaker gain max,
use Equation 1:
Equation 1:
PVDD(V)
PVDD(dBFS) = 20log
VMPO
where VPVDD is the voltage readback from the PVDD
ADC, and VMPO is the maximum peak output voltage. See
Table 14. For example, if VPVDD = 12V and VMPO = 12V
then PVDD(dBFS) = 0dBFS. It should be noted that 0dBFS
is the maximum value for PVDD(dBFS). If solving Equation
1 returns a value greater than 0 then 0dBFS should be
used for further calculations. This is important as DHT only
ever applies attenuation and never positive gain.
If VPVDD = 8.4V and SPK_GAIN_MAX = 12V, then solving Equation 1 gives -3.098dBFS. This is PVDD’s level
relative to SPK_GAIN_MAX in dB. To find the expected
compressed output voltage, use Equation 2:
Equation 2:
-PVDD(dBFS)
ATTENUATION(dB) = PVDD(dBFS) + Input(dBFS) ×
VRP (dBFS)
when PVDD(dBFS) = 0, PVDD and the fraction term dropout that gives attenuation equals zero. This makes sense
because when PVDD(dBFS) = 0, there is sufficient headroom to playback any signal input into the MAX98371 and
no compression is applied.
A non-trivial case might be If VPVDD = 8.4V, VMPO =
12V, rotation point = -10dBFS and the input signal level is
-5dBFS. Next, solve Equation 2 with these values:
-PVDD(dBFS)
= PVDD(dBFS) + Input(dBFS) ×
VRP (dBFS)
3.098dBFS
= -3.098dBFS + -5dBFS ×
-10dBFS
= -1.54dBFS
For this example, the total amount of compression applied
by DHT 1.54dB. DHT attack rate and DHT attack step can
be configured to apply the 1.54dB of attenuation of over a
programmable amount of time.
As a rule of thumb, attack times (product of attack rate,
attack step, and number of steps) faster than 600µs are
not achievable. This is independent of sample rate. Input
data is rectified, filtered, and converted to the log domain.
The DSP compares the input data with filtered data from
the PVDD ADC, then compression is applied within the
DSP. The compressed data must be converted back to linear scale and then output. The large number of complex
computations required in the DSP requires a fixed 600µs
to complete the compression algorithm. As a result, attack
times faster than 600µs are not possible. See Table 16.
Continuing the same example when the input signal size
decreases below the rotation point, DHT releases the 1.54dB
of attenuation it applied to the signal. The release time for
DHT is configurable through Register 0x33. See Table 17.
Limiter
The MAX98371 features a programmable limiter that is
used to compress large near full-scale signals. The input
signal level where the attenuation is applied varies based
on how the Limiter Threshold Select register is set.
Table 16. Dynamic Headroom Tracking Attack Settings
ADDRESS
BIT
NAME
DHT_ATK_STEP[1:0]
DHT Attack Step Size
00: 0.25dB
01: 0.5 dB
10: 1.0dB
11: 2.0dB (default)
DHT_ATK_RATE[2:0]
DHT Compressor Attack Rate
All attack times in µs/step
000: 17.5 (default)
001: 35
010: 70
011: 140
100: 280
101: 560
110: 1120
111: 2240
4
3
0x32
2
1
0
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DESCRIPTION
Maxim Integrated │ 59
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 17. Dynamic Headroom Tracking Release Settings
ADDRESS
BIT
NAME
DHT_REL_STEP[1:0]
DHT_REL_RATE[2:0]
DHT Compressor Release Rate
All release times in ms/step
000: 45 (default)
001: 225
010: 450
011: 1150
100: 2250
101: 3100
110: 4500
111: 6750
4
3
0x33
2
1
DESCRIPTION
DHT Release Step Size
00: 0.25dB
01: 0.5dB
10: 1.0dB
11: 2.0dB (default)
0
Table 18. Dynamic Gain Enables
ADDRESS
0x4B
BIT
NAME
2
PVADC_EN
1
LMTR_EN
0
DHT_EN
DESCRIPTION
0: PVDD ADC is disabled.
1: PVDD ADC is enabled.
0: Limiter is disabled.
1: Limiter is enabled.
0: Dynamic headroom tracking is disabled.
1: Dynamic headroom tracking is enabled.
Table 19. Limiter Threshold Select
ADDRESS
BIT
NAME
1
0x58
0
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LMTR_TH_SEL[1:0]
DESCRIPTION
Limiter Threshold Select
00: User-programmable threshold (contents of register 0x59).
01: Threshold is set by SPK_GAIN_MAX.
10–11: Threshold is set by PVDD level.
Maxim Integrated │ 60
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 20. Manual Limiter Threshold Settings
ADDRESS
BIT
NAME
4
3
0x59
2
1
0
LMTR_THC[4:0]
DESCRIPTION
Manual Limiter Threshold Setting (Input Referred)
00000: 0dBFS
00001: -1dBFS
00010: -2dBFS
00011: -3dBFS
…
11101: -29dBFS
11110: -30dBFS
11111: -31dBFS
When LMTR_TH_SEL is set to 00, the limiter threshold
is user configurable through register LMTR_THC. See
Table 20.
Table 21. Limiter Threshold
SPK_GAIN_MAX SETTING
LMTR_THRESHOLD (dB)
When LMTR_TH_SEL is set to 01, the threshold is
determined by SPK_GAIN_MAX. Table 21 provides the
threshold values.
0x0B
0
0x0A
-1
0x09
-2
When LMTR_TH_SEL is set to 10 or 11, the part looks
at the PVDD ADC and the SPK_GAIN_MAX setting and
determines the maximum output swing that the part can
deliver without clipping. Input signals that require more
voltage than is available on PVDD are limited to prevent
clipping. Filtering can be applied to the PVDD ADC readings used by the limiter with the PVDD_FILT_TO_LMTR
bit (Table 9).
0x08
-3
The limiter attack and release rates are measured in
absolute time and are independent of sample rate. The
limiter has its own set of configurable ballistics (Table 22).
Thermal ADC
The MAX98371 features a die temperature monitoring
ADC. This 6-bit ADC with a 100kHz sample rate reports
the die temperature from +100°C to +163°C. THRM_
MIN_TEMP sets the temperature at which the thermal
foldback circuit initially activates. The measurements from
the thermal ADC can be filtered before they are used by
the thermal foldback circuit, or the values can pass directly
without being filtered. THRM_FILT_SEL controls the filter
selection.
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…
…
0x01
-10
0x00
-11
Thermal Protection
The MAX98371 continuously monitors die temperature to
ensure that the temperature does not exceed the maximum of +150°C (typ). The device can warn the host if die
temperature is approaching the limit and shuts down if the
limit is exceeded. As the overtemperature limit varies from
part to part, the thermal warning thresholds are defined as
percentages of the overtemperature limit. Once the device
shuts down, it resets all register values except those
related to thermal warning and overtemperature interrupt
handling. The interrupt registers are maintained to ensure
that host is alerted of the overtemperature event. Other
registers can become corrupted by the overtemperature
event and are reset to prevent unwanted behavior. Once
the die temperature drops below +140°C (typ), the device
alerts the host through an interrupt, indicating that it is safe
to reprogram the device and resume audio playback.
Maxim Integrated │ 61
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 22. Limiter Attack and Release Settings
ADDRESS
BIT
NAME
LMTR_REL_RATE[2:0]
Limiter Release Time
Total time required for limiter to fully release
000: 15ms
001: 40ms
010: 70ms
011: 160ms
100: 300ms
101: 450ms
110: 600ms
111: 850ms
LMTR_ATK_RATE[2:0]
Limiter Attack Time
Total time required for limiter to fully attack
000 - 100: 160µs
101: 320µs
110: 640µs
111: 1280µs
5
4
0x55
3
2
1
DESCRIPTION
0
Table 23. Thermal ADC Measurements
ADDRESS
BIT
NAME
5
4
0x37
3
2
THRM_ADC_MEAS[7:0]
1
0
5
4
0x38
3
2
THRM_MIN_TEMP[6:0]
1
0
2
0x39
1
0
Thermal Foldback
THRM_FILT_SEL[2:0]
DESCRIPTION
0: 100°C
1: 101°C
…
62: 162°C
63: 163°C
0: 100°C
1: 101°C
…
20: 120°C (default)
…
39: 139°C
40-63: 140°C
000: THRM ADC LPF filter on fC = 0.55kHz
001: THRM ADC LPF filter on fC = 2.15kHz
010: THRM ADC LPF filter on fC = 4.55kHz
011: Bypass filter (default)
100: THRM ADC peak detect filter on fC = 0.55kHz
101: THRM ADC peak detect filter on fC = 2.15kHz
110: THRM ADC peak detect filter on fC = 4.55kHz
111: Bypass filter
To allow a smoother audio response to high temperature
events the MAX97805B features a thermal foldback loop.
As the die temperature rises above a threshold of set by
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THRM_MIN_TEMP register (+120°C by default), the
audio path is subjected to increasing attenuation, up to a
maximum of -12dB. See Table 23.
Maxim Integrated │ 62
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
The thermal foldback feature can be turned on through the
THRM_FB_EN bit, default is off (Table 25). The release rate
of the attenuation and the slope of the effect can be set by
the user (Table 24), the attack time is fixed at 10µs/dB.
the DIN pin. The DOUT pin only drives out during the slot
assigned to the amplifier by TX_CH#_EN bit. At all other
times, the pin is an input (to allow other devices to drive
the DOUT signal).
Regardless of whether the thermal foldback feature is
enabled, the thermal warning bit in the interrupt registers
assert and generate an interrupt through the Interrupt
Mask register when the +125°C (typ) temperature
threshold is crossed.
DOUT Operation and Data format
The MAX98371 features a bidirectional DOUT pin to
provide feedback data to the applications processor and
other MAX98371s. The data output from DOUT shares
the status of amplifier DHT and thermal foldback adjustments. The data format used to frame the data carried on
DOUT is the same as the data format of the input data on
THERMAL FOLDBACK
ATTENUTATION vs. TEMERATURE
2
THERMAL FOLDBACK ATTENUATION(dB)
THRM_HOLD controls how long the temperature must
stay on one side of the hysteresis threshold. THRM_REL
controls the release rate of the attenuation applied by
the thermal foldback circuit. THRM_SLOPE controls the
amount of attenuation per °C. See Table 24.
0
-2
THERM_SLOPE = 00
-4
-6
-8
-10
-12
-14
THERM_SLOPE = 01 THERM_SLOPE =10
100
110
120
130
140
150
TEMPERATURE (°C)
Figure 15. Thermal Foldback Performance
Table 24. Thermal Foldback Settings
ADDRESS
BIT
NAME
7
THRM_HOLD[1:0]
6
0x36
DESCRIPTION
Thermal Foldback Hold Settings
00: 0ms
01: 20ms
10: 40ms
11: 80ms (default)
5
0
—
4
0
—
THRM_REL[1:0]
Thermal Foldback Release Times
00: 3ms/dB
01: 10ms/dB
10: 100ms/dB
11: 300ms/dB
THRM_SLOPE[1:0]
Thermal Foldback Slope Settings
00: 0.5dB/°C
01: 1.0dB/°C
10: 2.0dB/°C
11: Reserved
3
2
1
0
Table 25. Thermal Foldback Enable
ADDRESS
0x4C
BIT
0
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NAME
THRM_FB_EN
DESCRIPTION
Thermal Foldback Enable
0: Thermal foldback disabled
1: Thermal foldback enabled
Maxim Integrated │ 63
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
The data output on the DOUT pin is structured as shown
in Figure 16.
The THRM_LINK_EN and DHT_LINK_EN are intended
to be used as the global enables of receive data function
of the ICC. It should also be noted that for the ICC to
function properly ICC_OC_ENA bit in register 0x5C must
be set to 1 so that the overcurrent protection on DOUT is
enabled.
Where DHT_INFO[7:0] contains the DHT attenuation
(in dB) and THERM_INFO [5:0] contains the attenuation thermal foldback attenuation broadcast out to
other amplifiers on the same bus. It is decoded as
shown in Figure 16.
Table 26. DHT Information
Table 27. THERM Information
VALUE
DECODE (dB)
VALUE
DECODE (°C)
0
-95.625
0
No thermal adjustment needed
1
-95.25
1
+1
2
-94.875
2
+2
…
0.375 (steps)
…
1 (steps)
253
-0.750
61
+61
254
-0.375
62
+62
0
63
+63
255
Note: XX are padding bits and zeros that make up the remaining bits in the rest of the frame.
SLOT 1
SLOT 2
DHT_INFO[7:0]
SLOT 3
THERM_INFO[5:0]
SLOT 4
XX
Figure 16. DOUT Data Structure
Table 28. Thermal and DHT Link Enables
ADDRESS
BIT
NAME
1
THRM_LINK_EN
0
DHT_LINK_EN
0x4E
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DESCRIPTION
0: Disable THRM link.
1: Enable THRM link.
0: Disable DHT link.
1: Enable DHT link.
Maxim Integrated │ 64
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Interchip Communication
enable to listen to both slots 0 and 2, so both amplifiers
would have RX_DHT_CH0_EN and RX_DHT_CH2_EN
enabled. While this configuration groups the amplifier in
the same DHT group, there is another set of grouping registers for thermal foldback. These registers can be configured identically or differently to accommodate the desired
behavior. To configure the second group, set amplifier 2 to
broadcast on slot 1 through TX_CH1_EN and set amplifier 4 to broadcast on slot 3 through TX_CH3_EN. Then
configure both amplifiers to enable RX enable to listen to
both slots 1 and 3, so both amps would have RX_DHT_
CH1_EN and RX_DHT_CH3_EN enabled.
The MAX98371 features an interchip communication
(ICC) bus that facilitates synchronized gain adjustments
between groups of MAX98371 amplifiers.
Multiamplifier Grouping
By setting registers 0x3A through register 0x3F, it is possible to group MAX98371 amplifiers so that any gain
adjustments due to DHT and/or thermal foldback are
synchronized.
Each amplifier is configured by a register setting to monitor DOUT during certain slots. The slots selected define
to which group each amplifier belongs. Therefore, each
amplifier in a group must have the same settings for RX
enables. Each individual amplifier must also have only
one TX_CH# enable set as well as the corresponding
RX_CH# enable.
For example, if we have four amplifiers and we want two
groups, then one configuration may be that amplifiers 1
and 3 would belong to one group and amplifiers 2 and
4 belong to another. Assign amplifier 1 to broadcast on
Slot 0 through the TX_CH0_EN bit enable and amplifier
3 to broadcast on slot 2 through the TX_CH2_EN bit.
We would then configure both amplifiers to enable RX
By definition, the minimum size of a group is two amplifiers, so the maximum number of groups that is supported
is eight. A group can contain as many as 16 amplifiers,
but then only one group is supported.
It is a requirement of the host processor to ensure that
the RX register bits are set to the same values across all
amplifiers intended to be used in a group. Devices in the
same DHT group must also be configured with the same
DHT parameters (SPK_GAIN_MAX, RP, and Ballistics)
to achieve a balanced response across the group. The
same is true of the THERM group.
Table 29. Interchip Communication Configuration
ADDRESS
0x5C
BIT
NAME
6
ICC_OC_ENA
5
ICC_DOUTEN_EXTFF
0: Disable faster drive enable of the DOUT.
1: Enable faster drive enable of the DOUT for the ICC with BCLK rate
greater than 12.288MHz.
4
ICC_DOUT_EXTFF
0: Disable faster drive of the DOUT.
1: Enable faster drive of the DOUT for the ICC with BCLK rate greater
than 12.288MHz.
ICC_PAD_CTRL[3:0]
DOUT Drive Strength Control
0000: 1 (default)
0001 and 0010: 7/8
0011 and 0100: 3/4
0101 and 0110: 5/8
0111 and 1000: 1/2
1001 and 1010: 3/8
1011 and 1100: 1/4
1101: 1/8
1110: 1/8 with Miller slew rate reduction (improves EMI)
1111: off
3
2
1
0
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DESCRIPTION
0: Disable overcurrent protection on DOUT.
1: Enable overcurrent protection on DOUT.
Maxim Integrated │ 65
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Double Data Drive
In this way, the DOUT data transfer rate is effectively
half of the BCLK speed. This is accomplished by setting
DRIVE_MODE = 1.
If the shared DOUT trace has a high capacitance that
needs to be driven at high speed then the double-data
drive feature can be used. This gives a longer drive time
for each device.
This has implications for the supported slot lengths. When
double-data drive is enabled, only 32-bit slot lengths are
permitted.
When the BCLK is less than or equal to 25MHz, DOUT
can be clocked with standard clocking: data changes on
the falling edge and is valid on the rising edge of each
BCLK (Table 30).
Additional MAX98371 devices correctly interpret the
double-data drive format (if enabled). Any other attached
hardware, such as an applications processor, which is
expecting standard timing, needs to ensure that it omits
away the information captured on the nonvalid rising edge
each time and reconstruct the samples accordingly.
When the BCLK is greater than 25MHz, DOUT should be
clocked using a double-data drive method: data changes
on the falling edge and is valid on the second rising edge.
Table 30. DOUT Double Data Drive Mode
ADDRESS
BIT
NAME
DESCRIPTION
0x40
3
DRIVE_MODE
0: Single data drive (default)
1: Double data drive
31
30
29
28
27
26
25
24
23
22
21
20
19
18
DHT
[7]
DHT
[6]
DHT
[5]
DHT
[4]
DHT
[3]
DHT
[2]
DHT
[1]
DHT
[0]
THM
[5]
THM
[4]
THM
[3]
THM
[2]
THM
[1]
THM
[0]
DRIVE DATA ON
FALLING EDGE
17
THREE-STATE DATA AT
END OF SLOT
RECEIVE DATA ON
RISING EDGE
Figure 17. Single Data Drive
31
30
DHT [7]
29
28
DHT [6]
27
26
DHT [5]
25
24
DHT [4]
tDRIVE
Figure 18. Double Data Drive illustration
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Maxim Integrated │ 66
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 31. DOUT DHT Receive Channel Configuration
ADDRESS
BIT
NAME
DESCRIPTION
7
RXDHT_CH7_EN
0: DHT receive channel 7 is disabled.
1: DHT receive channel 7 is enabled.
6
RXDHT_CH6_EN
0: DHT receive channel 6 is disabled.
1: DHT receive channel 6 is enabled.
5
RXDHT_CH5_EN
0: DHT receive channel 5 is disabled.
1: DHT receive channel 5 is enabled.
4
RXDHT_CH4_EN
0: DHT receive channel 4 is disabled.
1: DHT receive channel 4 is enabled.
3
RXDHT_CH3_EN
0: DHT receive channel 3 is disabled.
1: DHT receive channel 3 is enabled.
2
RXDHT_CH2_EN
0: DHT receive channel 2 is disabled.
1: DHT receive channel 2 is enabled.
1
RXDHT_CH1_EN
0: DHT receive channel 1 is disabled.
1: DHT receive channel 1 is enabled.
0
RXDHT_CH0_EN
0: DHT receive channel 0 is disabled.
1: DHT receive channel 0 is enabled.
7
RXDHT_CH15_EN
0: DHT receive channel 15 is disabled.
1: DHT receive channel 15 is enabled.
6
RXDHT_CH14_EN
0: DHT receive channel 14 is disabled.
1: DHT receive channel 14 is enabled.
5
RXDHT_CH13_EN
0: DHT receive channel 13 is disabled.
1: DHT receive channel 13 is enabled.
4
RXDHT_CH12_EN
0: DHT receive channel 12 is disabled.
1: DHT receive channel 12 is enabled.
3
RXDHT_CH11_EN
0: DHT receive channel 11 is disabled.
1: DHT receive channel 11 is enabled.
2
RXDHT_CH10_EN
0: DHT receive channel 10 is disabled.
1: DHT receive channel 10 is enabled.
1
RXDHT_CH9_EN
0: DHT receive channel 9 is disabled.
1: DHT receive channel 9 is enabled.
0
RXDHT_CH8_EN
0: DHT receive channel 8 is disabled.
1: DHT receive channel 8 is enabled.
0x3A
0x3B
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Maxim Integrated │ 67
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 32. DOUT Thermal Foldback Receive Channel Configuration
ADDRESS
BIT
NAME
7
RXTHM_CH7_EN
0: THRM FB receive channel 7 is disabled.
1: THRM FB receive channel 7 is enabled.
6
RXTHM_CH6_EN
0: THRM FB receive channel 6 is disabled.
1: THRM FB receive channel 6 is enabled.
5
RXTHM_CH5_EN
0: THRM FB receive channel 5 is disabled.
1: THRM FB receive channel 5 is enabled.
4
RXTHM_CH4_EN
0: THRM FB receive channel 4 is disabled.
1: THRM FB receive channel 4 is enabled.
3
RXTHM_CH3_EN
0: THRM FB receive channel 3 is disabled.
1: THRM FB receive channel 3 is enabled.
2
RXTHM_CH2_EN
0: THRM FB receive channel 2 is disabled.
1: THRM FB receive channel 2 is enabled.
1
RXTHM_CH1_EN
0: THRM FB receive channel 1 is disabled.
1: THRM FB receive channel 1 is enabled.
0
RXTHM_CH0_EN
0: THRM FB receive channel 0 is disabled.
1: THRM FB receive channel 0 is enabled.
7
RXTHM_CH15_EN
0: THRM FB receive channel 15 is disabled.
1: THRM FB receive channel 15 is enabled.
6
RXTHM_CH14_EN
0: THRM FB receive channel 14 is disabled.
1: THRM FB receive channel 14 is enabled.
5
RXTHM_CH13_EN
0: THRM FB receive channel 13 is disabled.
1: THRM FB receive channel 13 is enabled.
4
RXTHM_CH12_EN
0: THRM FB receive channel 12 is disabled.
1: THRM FB receive channel 12 is enabled.
3
RXTHM_CH11_EN
0: THRM FB receive channel 11 is disabled.
1: THRM FB receive channel 11 is enabled.
2
RXTHM_CH10_EN
0: THRM FB receive channel 10 is disabled.
1: THRM FB receive channel 10 is enabled.
1
RXTHM_CH9_EN
0: THRM FB receive channel 9 is disabled.
1: THRM FB receive channel 9 is enabled.
0
RXTHM_CH8_EN
0: THRM FB receive channel 8 is disabled.
1: THRM FB receive channel 8 is enabled.
0x3C
0x3D
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DESCRIPTION
Maxim Integrated │ 68
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 33. DOUT Thermal Foldback Receive Channel Configuration
ADDRESS
BIT
NAME
7
TX_CH7_EN
0: Transmit channel 7 is disabled.
1: Transmit channel 7 is enabled.
6
TX_CH6_EN
0: Transmit channel 6 is disabled.
1: Transmit channel 6 is enabled.
5
TX_CH5_EN
0: Transmit channel 5 is disabled.
1: Transmit channel 5 is enabled.
4
TX_CH4_EN
0: Transmit channel 4 is disabled.
1: Transmit channel 4 is enabled.
3
TX_CH3_EN
0: Transmit channel 3 is disabled.
1: Transmit channel 3 is enabled.
2
TX_CH2_EN
0: Transmit channel 2 is disabled.
1: Transmit channel 2 is enabled.
1
TX_CH1_EN
0: Transmit channel 1 is disabled.
1: Transmit channel 1 is enabled.
0
TX_CH0_EN
0: Transmit channel 0 is disabled.
1: Transmit channel 0 is enabled.
7
TX_CH15_EN
0: Transmit channel 15 is disabled.
1: Transmit channel 15 is enabled.
6
TX_CH14_EN
0: Transmit channel 14 is disabled.
1: Transmit channel 14 is enabled.
5
TX_CH13_EN
0: Transmit channel 13 is disabled.
1: Transmit channel 13 is enabled.
4
TX_CH12_EN
0: Transmit channel 12 is disabled.
1: Transmit channel 12 is enabled.
3
TX_CH11_EN
0: Transmit channel 11 is disabled.
1: Transmit channel 11 is enabled.
2
TX_CH10_EN
0: Transmit channel 10 is disabled.
1: Transmit channel 10 is enabled.
1
TX_CH9_EN
0: Transmit channel 9 is disabled.
1: Transmit channel 9 is enabled.
0
TX_CH8_EN
0: Transmit channel 8 is disabled.
1: Transmit channel 8 is enabled.
0x3E
0x3F
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DESCRIPTION
Maxim Integrated │ 69
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 34. Extra BCLK Cycle Configuration
ADDRESS
0x41
BIT
1
NAME
TX_EXTRA_HIZ
DESCRIPTION
0: Extra BCLK cycles are driven to zero.
1: Extra BCLK cycles are driven to high impedance.
Table 35. Manual HIZ Mode Configuration
ADDRESS
BIT
NAME
DESCRIPTION
7
TX_CH7_HIZ
0: Transmit Channel 7 outputs data/zeros.
1: Transmit Channel 7 outputs high impedance.
6
TX_CH6_HIZ
0: Transmit Channel 6 outputs data/zeros.
1: Transmit Channel 6 outputs high impedance.
5
TX_CH5_HIZ
0: Transmit Channel 5 outputs data/zeros.
1: Transmit Channel 5 outputs high impedance.
4
TX_CH4_HIZ
0: Transmit Channel 4 outputs data/zeros.
1: Transmit Channel 4 is enabled.
3
TX_CH3_HIZ
0: Transmit Channel 3 outputs data/zeros.
1: Transmit Channel 3 outputs high impedance.
2
TX_CH2_HIZ
0: Transmit Channel 2 outputs data/zeros.
1: Transmit Channel 2 outputs high impedance.
1
TX_CH1_HIZ
0: Transmit Channel 1 outputs data/zeros.
1: Transmit Channel 1 outputs high impedance.
0
TX_CH0_HIZ
0: Transmit Channel 0 outputs data/zeros.
1: Transmit Channel 0 outputs high impedance.
7
TX_CH15_HIZ
0: Transmit Channel 15 outputs data/zeros.
1: Transmit Channel 15 outputs high impedance.
6
TX_CH14_HIZ
0: Transmit Channel 14 outputs data/zeros.
1: Transmit Channel 14 outputs high impedance.
5
TX_CH13_HIZ
0: Transmit Channel 13 outputs data/zeros.
1: Transmit Channel 13 outputs high impedance.
4
TX_CH12_HIZ
0: Transmit Channel 12 outputs data/zeros.
1: Transmit Channel 12 outputs high impedance.
3
TX_CH11_HIZ
0: Transmit Channel 11 outputs data/zeros.
1: Transmit Channel 11 outputs high impedance.
2
TX_CH10_HIZ
0: Transmit Channel 10 outputs data/zeros.
1: Transmit Channel 10 outputs high impedance.
1
TX_CH9_HIZ
0: Transmit Channel 9 outputs data/zeros.
1: Transmit Channel 9 outputs high impedance.
0
TX_CH8_HIZ
0: Transmit Channel 8 outputs data/zeros.
1: Transmit Channel 8 outputs high impedance.
0x42
0x43
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Maxim Integrated │ 70
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Table 36. Speaker Configuration
ADDRESS
0x4A
BIT
NAME
DESCRIPTION
Class D output Switching Frequency Select
0: Speaker switching frequency is set to 472kHz.
1: Speaker switching frequency is set to 330kHz.
7
SPK_SWCLK
6
—
—
5
—
—
4
—
—
3
SPK_EDGE[1:0]
2
1
—
0
SPK_EN
Programmable Speaker Edge Rate Control
00: Nominal edge rate
01: +15% faster edge rate
10: -40% slower edge rate
11: -20% slower edge rate
—
Speaker amplifier Enable
0: Speaker amplifier is disabled (default).
1: Enable
Class D Output Stage
VDVDD and VPVDD UVLO
The default Class D output switching frequency is 472kHz
for the best THD performance. To trade off THD performance for higher efficiency the output switching frequency
can be set to 330kHz by setting SPK_SWCLK to 1.
If the voltage PVDD drops below the PVDD-UVLO threshold, the audio output is muted to prevent the PVDD supply
from being used by the amplifier. If the voltage on PVDD
later exceeds the VPVDD-UVLO threshold, the device can
be commanded to unmute through the I2C command.
The MAX98371 Class D output stage with active emissions limiting provides optimum suppression and control
of output switching harmonics that most directly contribute
to EMI and radiated emissions. Programmable speaker
edge rate control is available to help tweak EMI performance. As the edge rate increases, the efficiency goes
up slightly, and as the edge rate slows the efficiency goes
down. Set the speaker edge rate with bits SPK_EDGE
bits in register 0x4A.
To achieve the lower power consumption, the output
switching of the Class D amplifier the part can be disabled through the SPK_EN bit. See Table 36 for the
speaker configuration.
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters, or shielding, to meet electromagnetic-interference (EMI) regulation standards. The active emissions
limiting edge-rate control circuitry reduce EMI emissions
so that with 18in of speaker cable the MAX98371 passes
the EN55022B standard without the need for external
filtering components.
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The MAX98371 monitors both DVDD and PVDD for low voltage conditions that would prevent the speaker amplifier from
operating normally. If the voltage on DVDD drops below the
DVDD-UVLO threshold (VDVDD-UVLO), the device is placed
in hardware shutdown. All the I2C internal registers reset to
their default values. The device can be commanded to leave
this state through the I2C command if the voltage on DVDD
later exceeds the VDVDD-UVLO threshold.
Click-and-Pop Suppression
The MAX98371 speaker amplifier features Maxim’s comprehensive click-and-pop suppression. During power-up
and power-down, the click-and-pop suppression circuitry
reduces any audible transient sources internal to the device.
At startup, the PGA gain is automatically ramped from
mute to the desired setting at a rate of 200µs/dB.
Similarly, the gain is ramped down to mute at shutdown
at the same rate. For faster startup and shutdown, disable
gain ramping.
During normal operation, any requested gain changes are
ramped from the old value to the new value at a value
determined by the ballistics within the volume control block.
Maxim Integrated │ 71
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Amplifier Current Limit
The MAX98371 features current limit protection that protects the device against shorts. If the output current of
the speaker amplifier exceeds the current limit (6A typ)
the IC disables the outputs for approximately 100µs. After
100ms, the outputs are reenabled. If the fault condition
still exists, the IC continues to disable and re-enable the
outputs until the fault condition is removed. Set OVC_SEL
low to disable this behavior. See Table 37. The current limit
protects against both high-current and short-circuit events.
MAX98371
OUTP SNS
OUTP
FB
SPEAKER AMPLIFIER
OUTN
FB
Thermal Shutdown Recovery
When the temperate of the die exceeds +150°C, the
part enters thermal shutdown. However, the MAX98371
features a configurable thermal shutdown autorecovery mode. When the die temperate has decreased by
30°C from the thermal shutdown event, the MAX98371
attempts to resume the previous operating state. Set
TSHDN_AUTO_RESTART high to enable autorecovery
mode. See Table 37.
OUTN SNS
Figure 19. Typical Application Circuit with Ferrite Beads Used
Output Sensing When Using Ferrites
However, in many applications, there might not be a need
to filter the output with a ferrite bead.
Clocking Architecture
The MAX98371 includes a flexible clocking architecture
and operation with no MCLK input.
0
-10
-20
THD+N RATIO (dB)
The MAX98371 features two remote sensing pins OUTN_
SNS and OUTP_SNS. Remotely sensing the voltage at
the load provides a THD+N advantage over sensing at
the DUT output when ferrite beads are used. See Figure
20. The remote sense lines connect the output signal
at the load to the inverting terminal of the internal error
amplifier of the Class D. See Figure 19. Ferrites are highly
nonlinear so sensing at the load versus at the output pins
ensures that any signal degradation caused by the filtering components is appropriately compensated.
TOTAL HARMONIC DISTORTION +
NOISE vs. OUTPUT POWER
ZL = 8Ω + 33µH
VPVDD = 17V
fS = 48kHz
-30
-40
SENSE AT OUTPUT
-50
-60
-70
-80
SENSE AT LOAD
-90
-100
0.001
0.01
0.1
1
10
100
OUTPUT POWER (W)
Figure 20. THD Performance Improvement Enabled by Remote
Sensing
A configurable internal clock monitor circuit monitors the
internal clock source (BCLK) and automatically places
the device in software shutdown if the clock source is
removed. Set CMON_ENA high to enable the clock
monitor. This prevents unwanted signals from being
applied to the speaker during a fault condition. When
CMON_AUTO_RESTART is high the device automatically returns to normal operation when the clock source
is subsequently reapplied. See Table 37.
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Digital Input Class D Speaker Amplifier
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Reset
Software Reset
The MAX98371 features an active-low hardware reset.
When the voltage-on reset is pulled low, the part enters
global shutdown. To reenable the part the reset pin must
be pulled high and a global enable I2C command must
be issued.
Hardware Reset
When the reset pin is pulled low, the device is in its lowest
power-down state and communication over I2C is not
possible. After exiting reset mode, all registers are set to
their default POR values.
Write 1 to bit 0 of register 0x51 to trigger a software reset.
Software reset is used to return most registers to their default
(POR) states. Biquad equalizer coefficients are not reset.
The software reset register is a write only register. As a
result, a read of this register always returns 0x00. Writing
logic-high to RST triggers a software register reset, while
writing a logic-low to RST has no effect.
Also if PVDD is removed while DVDD is still applied the
device goes into software shutdown mode where all
blocks are disabled except I2C control block.
Also, if DVDD is removed while PVDD is still applied,
the device goes into a hardware shutdown mode and
communication through I2C is not possible.
Table 37. Clock Monitor Configuration
ADDRESS
BIT
NAME
3
CMON_AUTO_RESTART
2
CMON_ENA
1
OVC_SEL
0
TSDHN_AUTO_RESTART
0x4D
DESCRIPTION
0: Device does not restart after a clock monitor event.
1: Device restarts automatically when BCLK is restarted.
0: Clock monitor is disabled (default).
1: Clock monitor is enabled.
0: Current limit recovery is in manual mode.
1: Current limit recovery is in autorecovery mode.
0: Thermal protection recovery is in manual mode.
1: Thermal protection recovery is in autorecovery mode.
Table 38. Reset Register
ADDRESS
BIT
NAME
0x51
0
RST
DESCRIPTION
Reset
0: No action is taken.
1: Reset. All registers return to their POR (default) values.
Table 39. Global Enable Register
ADDRESS
0x50
BIT
0
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NAME
EN
DESCRIPTION
Global Enable:
0: Disabled
1: Enabled
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MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
I2C Serial Interface
Bit Transfer
The MAX98371 features an I2C 2-wire serial interface
consisting of a serial data line (SDA) and a serial clock line
(SCL). SDA and SCL facilitate communication between the
IC and the master at clock rates up to 400kHz. Figure 21
shows the 2-wire interface timing diagram. The master
generates SCL and initiates data transfer on the bus. The
master device writes data to the IC by transmitting the
proper slave address followed by the register address and
then the data word. Each transmit sequence is framed by
a START (S) or REPEATED START (Sr) condition and a
STOP (P) condition. Each word transmitted to the IC is 8
bits long and is followed by an acknowledge clock pulse.
A master reading data from the IC transmits the proper
slave address followed by a series of nine SCL pulses.
The IC transmits data on SDA in sync with the mastergenerated SCL pulses. The master acknowledges receipt
of each byte of data. Each read sequence is framed by
a START (S) or REPEATED START (Sr) condition, a
not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup
resistor, typically greater than 500Ω, is required on SDA.
SCL operates only as an input. A pullup resistor, typically
greater than 500Ω, is required on SCL if there are multiple masters on the bus, or if the single master has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the IC from high voltage spikes on the bus lines,
and minimize crosstalk and undershoot of the bus signals.
S
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are control signals. See the START and STOP Conditions section.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition on
SDA while SCL is high (Figure 21). A START condition
from the master signals the beginning of a transmission to
the IC. The master terminates transmission, and frees the
bus, by issuing a STOP condition. The bus remains active
if a REPEATED START condition is generated instead of
a STOP condition.
Early Stop Conditions
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the same
SCL high pulse as the START condition.
Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the IC
the seven most significant bits are programmable through
the ADDR1 and ADDR0 bumps. Setting the read/write bit
to 1 configures the IC for read mode. Setting the read/
write bit to 0 configures the IC for write mode. The slave
address is the first byte of information sent to the IC after
the START condition.
Sr
P
SCL
SDA
Figure 21. START, STOP, and REPEATED START Conditions
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Digital Input Class D Speaker Amplifier
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Acknowledge
An acknowledge is sent by the master after each read
byte to allow data transfer to continue. A not-acknowledge
is sent when the master reads the final byte of data from
the IC, followed by a STOP condition.
The acknowledge bit (ACK) is a clocked 9th bit that the
IC uses to handshake receipt each byte of data when in
write mode (Figure 22). The IC pulls down SDA during the
entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful
data transfer, the bus master reattempts communication.
The master pulls down SDA during the 9th clock cycle to
acknowledge receipt of data when the IC is in read mode.
Write Data Format
A write to the IC includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of
data to configure the internal register address pointer, one
or more bytes of data, and a STOP condition. Figure 23
illustrates the proper frame format for writing one byte of
data to the IC. Figure 24 illustrates the frame format for
writing n-bytes of data to the IC.
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 22. Acknowledge
ACKNOWLEDGE FROM SLAVE
B7
SLAVE ADDRESS
S
O
B6
B5
B4
B3
B2
B1
B0
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
A
A
REGISTER ADDRESS
DATA BYTE
A
P
1 BYTE
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 23. Writing One Byte of Data to the MAX98371
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
S
SLAVE ADDRESS
O
A
REGISTER ADDRESS
R/W
A
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
DATA BYTE 1
1 BYTE
A
DATA BYTE n
A
P
1 BYTE
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 24. n-Bytes of Data to the MAX98371
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Maxim Integrated │ 75
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the IC. The IC
acknowledges receipt of the address byte during the
master-generated 9th SCL pulse.
The first byte transmitted from the IC is the content of
register 0x00. Transmitted data is valid on the rising edge
of SCL. The address pointer autoincrements after each
read data byte. This autoincrement feature allows all
registers to be read sequentially within one continuous
frame. A STOP condition can be issued after any number
of read data bytes. If a STOP condition is issued followed
by another read operation, the first data byte to be read is
from register 0x00.
The second byte transmitted from the master configures
the IC’s internal register address pointer. The pointer tells
the IC where to write the next byte of data. An acknowledge pulse is sent by the IC upon receipt of the address
pointer data.
The third byte sent to the IC contains the data that is written to the chosen register. An acknowledge pulse from the
IC signals receipt of the data byte. The address pointer
autoincrements to the next register address after each
received data byte. This autoincrement feature allows a
master to write to sequential registers within one continuous frame. The master signals the end of transmission by
issuing a STOP condition.
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate
a read operation. The IC acknowledges receipt of its slave
address by pulling SDA low during the 9th SCL clock
pulse. A START command followed by a read command
resets the address pointer to register 0x00.
ACKNOWLEDGE FROM SLAVE
S
ACKNOWLEDGE FROM SLAVE
O
SLAVE ADDRESS
A
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not acknowledge
from the master and then a STOP condition. Figure 25
illustrates the frame format for reading one byte from
the IC. Figure 26 illustrates the frame format for reading
multiple bytes from the IC.
ACKNOWLEDGE FROM SLAVE
A Sr
REGISTER ADDRESS
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the IC’s slave address
with the R/W bit set to 0 followed by the register address. A
REPEATED START condition is then sent followed by the
slave address with the R/W bit set to 1. The IC then transmits the contents of the specified register. The address
pointer autoincrements after transmitting the first byte.
A
R/W
REPEATED START
R/W
1
SLAVE ADDRESS
NOT ACKNOWLEDGE FROM MASTER
DATA BYTE
A
P
1 BYTE
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 25. Reading One Byte of Data from the MAX98371
ACKNOWLEDGE FROM SLAVE
S
SLAVE ADDRESS
R/W
O
ACKNOWLEDGE FROM SLAVE
A
REGISTER ADDRESS
ACKNOWLEDGE FROM SLAVE
A Sr
REPEATED START
SLAVE ADDRESS
1
R/W
A
DATA BYTE
A
1 BYTE
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 26. Reading n-Bytes of Data from the MAX98371
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Maxim Integrated │ 76
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
I2C Slave Addresses
must be kept short and should have minimum trace length
and loop area to ensure optimumal performance.
The addresses effectively allow unique audio endpoint destinations in systems that use multiples of the device. The
IC uses hardware select slave addresses determined by
the configuration of ADDR0, ADDR1 as shown in Table 40.
See the I2C Serial Interface section for a complete interface description.
Use wide, low-resistance output, supply and ground
traces. As load impedance decreases, the current drawn
from the device outputs increase. At higher current, the
resistance of the output traces decreases the power
delivered to the load. For example, if 2W is delivered
from the speaker output to a 4Ω load through a 100mΩ
trace, 49mW is consumed in the trace. If power is delivered through a 10mΩ trace, only 5mW is consumed in
the trace. Wide output, supply, and ground traces also
improve the power dissipation of the device.
The MAX98371 is configured using the I2C control bus.
Applications Information
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Use at least 4 PCB layers, and add thermal
vias to the ground/power plane close to the MAX98371
to ensure good thermal performance and high-end output power. Good grounding improves audio performance
and prevents switching noise from coupling into the
audio signal. Ground the power signals and the analog
signals of the IC separately at the system ground plane,
to prevent switching interference from corrupting sensitive analog signals.
Place the recommended supply decoupling capacitors as
close as possible to the IC. The PVDD to PGND connection
The MAX98371 is inherently designed for excellent RF
immunity. For best performance, add ground fills around
all signal traces on the top and bottom PCB planes.
It is generally advisable to follow the layout of the
MAX98371 evaluation kit as closely as is practical in the
application.
Thermal and performance measurements shown in this
data sheet were measured with a 6 layer board with 2
signal layers and 4 ground layers. As a result, the EV kit
performance is likely better than what can be achieved
with a JEDEC standard board.
Table 40. ADDR I2C Address Select
ADDR1
ADDR0
I2C WRITE ADDRESS SELECT
ADDR1 connected to DVDD
ADDR0 connected to DGND
0x62
ADDR1 connected to DGND
ADDR0 connected to DGND
0x64
ADDR1 connected to SDA
ADDR0 connected to DGND
0x66
ADDR1 connected to SCL
ADDR0 connected to DGND
0x68
ADDR1 connected to DVDD
ADDR0 connected to SDA
0x6A
ADDR1 connected to DGND
ADDR0 connected to SDA
0x6C
ADDR1 connected to SDA
ADDR0 connected to SDA
0x6E
ADDR1 connected to SCL
ADDR0 connected to SDA
0x70
ADDR1 connected to DVDD
ADDR0 connected to DVDD
0x72
ADDR1 connected to DGND
ADDR0 connected to DVDD
0x74
ADDR1 connected to SDA
ADDR0 connected to DVDD
0x76
ADDR1 connected to SCL
ADDR0 connected to DVDD
0x78
ADDR1 connected to DVDD
ADDR0 connected to SCL
0x7A
ADDR1 connected to DGND
ADDR0 connected to SCL
0x7C
ADDR1 connected to SDA
ADDR0 connected to SCL
0x7E
ADDR1 connected to SCL
ADDR0 connected to SCL
0x80
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Digital Input Class D Speaker Amplifier
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Table 41. Recommended External Components
BUMP
VALUE (µF)
SIZE
VOLTAGE RATING
(V)
DIELECTRIC
PVDD
10
0603
50
X5R
PVDD
10
0603
50
X5R
PVDD
0.1
0402
25
X5R
PVDD
0.1
0402
25
X5R
PVDD
220
—
35
Alum-Elec
VREFC
1
0201
6.3
X5R
DVDD
1
0201
6.3
X5R
IRQ
10
0201
—
—
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: Wafer-Level
Packaging (WLP) and Its Applications. See Figure 27 for
the recommended PCB footprint of the MAX98371.
MAX98731
UBM
0.26mm
0.31mm
PCB PAD
0.21mm
PRINTED CIRCUIT BOARD
Figure 27. MAX98371+ WLP Ball Dimensions
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Maxim Integrated │ 78
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Typical Application Circuit
1.14V TO 1.98V
1μF
10kΩ
10kΩ
5.5V TO 18V
1μF
10μF
220μF
10μF
0.1μF
0.1μF
10kΩ
DVDD
VREFC
PVDD
SDA
SCL
CONTROL
INTERFACE
OUTP SNS
IRQ
ADDR1
SEE THE
APPLICATIONS
INFORMATION
SECTION
OUTP
ADDR2
MAX98371
RESET
OUTN
BCLK
LRCLK
DIGITAL
AUDIO
INTERFACE
OUTN SNS
DIN
DOUT
AGND
DGND
Ordering Information
PART
Package Information
TEMP RANGE
PIN-PACKAGE
MAX98371EWV+T
-40°C to +85°C
30 WLP
MAX98371EWV+
-40°C to +85°C
30 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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PGND
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
30 WLP
W302E2+1
21-0016
Refer to
Application
Note 1891
Maxim Integrated │ 79
MAX98371
Digital Input Class D Speaker Amplifier
with Dynamic Headroom Tracking
Revision History
REVISION
NUMBER
REVISION
DATE
0
3/15
DESCRIPTION
Initial release
PAGES
CHANGED
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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