Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MMA8450Q
Rev. 9.1, 04/2012
An Energy Efficient Solution by Freescale
3-Axis, 8-bit/12-bit
MMA8450Q
Digital Accelerometer
The MMA8450Q is a smart low-power, three-axis, capacitive micromachined
accelerometer featuring 12 bits of resolution. This accelerometer is packed with
embedded functions with flexible user programmable options, configurable to
two interrupt pins. Embedded interrupt functions allow for overall power savings
relieving the host processor from continuously polling data. The MMA8450Q’s
Embedded FIFO buffer can be configured to log up to 32 samples of X,Y and
Z-axis 12-bit (or 8-bit for faster download) data. The FIFO enables a more
efficient analysis of gestures and user programmable algorithms, ensuring no
loss of data on a shared I2C bus, and enables system level power saving (up to
96% of the total power consumption savings) by allowing the applications
processor to sleep while data is logged. There is access to both low pass
filtered data as well as high pass filtered data, which minimizes the data
analysis required for jolt detection and faster transitions. The MMA8450Q has
user selectable full scales of ±2g/±4g/±8g. The device can be configured to
generate inertial wakeup interrupt signals from any combination of the
configurable embedded functions allowing the MMA8450Q to monitor events
and remain in a low power mode during periods of inactivity.
16 PIN QFN
3 mm x 3 mm x 1 mm
CASE 2077-02
NC
NC
VDD
Top View
16
15
14
1
13
NC
BYP
2
12
GND
NC
3
11
INT1
SCL
4
10
GND
GND
5
9
INT2
7
8
EN
6
SA0
VDDIO
SDA
Features
• 1.71V to 1.89V supply voltage
• ±2g/±4g/±8g dynamically selectable full-scale
• Output Data Rate (ODR) from 400 Hz to 1.563 Hz
• 375 μg/√Hz noise at normal mode ODR = 400 Hz
• 12-bit digital output
• I2C digital output interface (operates up to 400 kHz Fast Mode)
• Programmable two interrupt pins for eight interrupt sources
• Embedded four channels of motion detection
– Freefall or motion detection: 2 channels
– Pulse Detection: 1 channel
– Transient (Jolt) Detection: 1 channel
• Orientation (Portrait/Landscape) detection with hysteresis compensation
• Automatic ODR change for auto-wake and return-to-sleep
• 32 sample FIFO
• Self-Test
• 10,000g high shock survivability
• RoHS compliant
Top and Bottom View
Pin Connections
Typical Applications
• Static orientation detection (portrait/landscape, up/down, left/right, back/front position identification)
• Real-time orientation detection (virtual reality and gaming 3D user position feedback)
• Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup)
• Motion detection for portable product power saving (auto-sleep and auto-wake for cell phone, PDA, GPS, gaming)
• Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)
• User interface (menu scrolling by orientation change, tap detection for button replacement
ORDERING INFORMATION
Part Number
Temperature Range
Package Description
MMA8450QT
-40°C to +85°C
QFN-16
Tray
MMA8450QR1
-40°C to +85°C
QFN-16
Tape and Reel
© 2010-2012 Freescale Semiconductor, Inc. All rights reserved.
Shipping
Contents
1
2
3
4
5
6
Block Diagram and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Mechanical and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 I2C Interface Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Zero-g Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Device Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 8-bit or 12-bit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Internal FIFO Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5 Auto-Wake/Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6 Freefall and Motion Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Transient Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.8 Orientation Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.9 Interrupt Register Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.10 Serial I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 32 Sample FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3 Portrait/ Landscape Embedded Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 Freefall & Motion Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5 Transient Detection Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.6 Tap Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.7 Auto-Sleep Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.8 User Offset Correction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Related Documentation
The MMA8450Q device features and operations are described in a variety of reference manuals, user guides, and application
notes. To find the most-current versions of these documents:
1.
Go to the Freescale homepage at:
http://www.freescale.com/
2.
3.
In the Keyword search box at the top of the page, enter the device number MMA8450Q.
In the Refine Your Result pane on the left, click on the Documentation link.
MMA8450Q
2
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1
Block Diagram and Pin Description
1.1
Block Diagram
VDD
VSS
Internal
OSC
X-axis
Transducer
Clock
GEN
Embedded
DSP
Functions
12-bit
ADC
C to V
Converter
Y-axis
Transducer
SDA
I2 C
SCL
Z-axis
Transducer
32 Data Point
Configurable
FIFO Buffer
with Watermark
Freefall
and Motion
Detection
(2 channels)
Transient
Detection
(i.e., fast motion,
jolt)
Enhanced
Orientation with
Hysteresis
and Z-lockout
Shake Detection
through
Motion
Threshold
Tap and
Double Tap
Detection
Auto-Wake/Auto-Sleep Configurable with debounce counter and multiple motion interrupts for control
Normal
Mode
Active Mode
SLEEP Mode
Auto-Wake
Low Power
Mode
(Reduced
Sampling Rate)
Auto-Sleep
Figure 1. Block Diagram
1.2
Pin Description
Z
X
1
Y
(TOP VIEW)
DIRECTION OF THE
DETECTABLE ACCELERATIONS
13
1
9
5
(BOTTOM VIEW)
Figure 2. Direction of the Detectable Accelerations
MMA8450Q
Sensors
Freescale Semiconductor, Inc.
3
Figure 3 shows the device configuration in the 6 different orientation modes. These orientations are defined as the following:
PU = Portrait Up, LR = Landscape Right, PD = Portrait Down, LL = Landscape Left, Back and Front. There are several registers
to configure the orientation detection and are described in detail in the register setting section.
Top View
PU
Pin 1
Earth Gravity
Side View
LL
LR
Xout @ 0g
Yout @ -1g
Zout @ 0g
BACK
Xout @ 0g
Yout @ 0g
Zout @ -1g
PD
Xout @ -1g
Yout @ 0g
Zout @ 0g
Xout @ 1g
Yout @ 0g
Zout @ 0g
FRONT
Xout @ 0g
Yout @ 0g
Zout @ 1g
Xout @ 0g
Yout @ 1g
Zout @ 0g
Figure 3. Landscape/Portrait Orientation
1.8V
4.7μF
1.8V
0.1μF
4.7kΩ
NC
4
SCL
5
GND
VDD
3
NC
NC
MMA8450Q
EN
4.7kΩ
SCL
2
14
SA0
1.8V
VDD
15
SDA
SDA
1
NC
16
6
7
8
GND 13
GND
12
INT1
11
GND
10
INT2
9
INT1
INT2
EN
SA0
Figure 4. Application Diagram
MMA8450Q
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Freescale Semiconductor, Inc.
Table 1. Pin Description
Pin #
Pin Name
1
VDD
2
Description
Pin Status
Power Supply (1.8 V only)
Input
NC/GND
Connect to Ground or Non Connection
Input
3
NC/GND
Connect to Ground or Non Connection
4
SCL
I2C Serial Clock
5
GND
Connect to Ground
SDA
I2
7
SA0
I2C Least Significant Bit of the Device Address
(0: $1C 1: $1D)
8
EN
6
C Serial Data
Device Enable
(1: I2C Bus Enabled; 0: Shutdown Mode)
Input
Open Drain
Input
Open Drain
Input
Input
9
INT2
Inertial Interrupt 2
10
GND
Connect to Ground
Output
11
INT1
Inertial Interrupt 1
12
GND
Connect to Ground
Input
13
GND
Connect to Ground
Input
14
VDD
Power Supply (1.8 V only)
Input
15
NC
Internally not connected
Input
16
NC
Internally not connected
Input
Input
Output
When using MMA8450Q in applications, it is recommended that pin 1 and pin 14 (the VDD pins) be tied together. Power supply
decoupling capacitors (100 nF ceramic plus 4.7 µF bulk, or a single 4.7 µF ceramic) should be placed as near as possible to the
pins 1 and 5 of the device. The SDA and SCL I2C connections are open drain and therefore require a pullup resistor as shown
in Figure 4
Note: The above application diagram presents the recommended configuration for the MMA8450Q. For information on future
products of this product family please review Freescale application note, AN3923, Design Checklist and Board Mounting
Guidelines of the MMA8450Q.This application note details the small modifications between the MMA8450Q and the next
generation products.
1.3
Soldering Information
The QFN package is compliant with the RoHS standard. Please refer to AN4077.
MMA8450Q
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5
2
Mechanical and Electrical Specifications
2.1
Mechanical Characteristics
Table 2. Mechanical Characteristics @ VDD = 1.8 V, T = 25°C unless otherwise noted.
Parameter
Test Conditions
Full Scale Measurement Range
FS[1:0] set to 01
Min
Typ
Max
±1.8
±2
±2.2
±3.6
±4
±4.4
FS[1:0] set to 11
±7.2
±8
±8.8
FS[1:0] set to 01
0.878
0.976
1.074
1.758
1.953
2.148
3.515
3.906
4.296
FS[1:0] set to 10
Sensitivity
FS[1:0] set to 10
Symbol
FS
So
FS[1:0] set to 11
Sensitivity Change vs. Temperature(1)
FS[1:0] set to 01
Typical Zero-g Level Offset (2)
FS[1:0] set to 01
FS[1:0] set to 10
Unit
g
mg/digit
TCSo
±0.05
%/°C
0g-Off
±40
mg
0g-OffBM
±50
mg
TCOff
±0.5
mg/°C
FS[1:0] set to 11
Typical Zero-g Offset Post Board Mount (2), (3)
FS[1:0] set to 01
FS[1:0] set to 10
FS[1:0] set to 11
Typical Zero-g Offset Change vs. Temperature
Non Linearity
Best Fit Straight Line
(2)
FS[1:0] set to 01
FS[1:0] set to 10
(4)
Self-test Output Change
±0.25
NL
±0.5
FS[1:0] set to 11
±1
FS[1:0] set to 01, X-axis
-195
FS[1:0] set to 01, Y-axis
Vst
-195
FS[1:0] set to 01, Z-axis
Output Noise
Operating Temperature Range
1.
2.
3.
4.
Normal Mode ODR = 400 Hz
% FS
LSB
+945
Noise
Top
μg/√Hz
375
-40
+85
°C
Before board mount.
See appendix for distribution graphs.
Post board mount offset specification are based on an 8 layer PCB.
Self-test in one direction only. These are approximate values and can change by ±100 counts.
MMA8450Q
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2.2
Electrical Characteristics
Table 3. Electrical Characteristics @ VDD = 1.8 V, T = 25°C unless otherwise noted.(1)
Parameter
Test Conditions
Supply Voltage
Low Power Mode
$39 CTRL_REG2: MOD[0]=1
Symbol
Min
Typ
Max
Unit
VDD
1.71
1.8
1.89
V
EN = 1, ODR = 1.563 Hz
27
EN = 1, ODR = 12.5 Hz
27
EN = 1, ODR = 50 Hz
EN = 1, ODR = 100 Hz
Normal Mode
$39 CTRL_REG2: MOD[0]=0
27
IddLP
EN = 1, ODR = 200 Hz
72
EN = 1, ODR = 400 Hz
120
EN = 1, ODR = 1.563 Hz
42
EN = 1, ODR = 12.5 Hz
42
EN = 1, ODR = 50 Hz
EN = 1, ODR = 100 Hz
Current Consumption in Shutdown Mode
Supply Current Drain in Standby Mode
μA
42
42
Idd
μA
72
EN = 1, ODR = 200 Hz
132
EN = 1, ODR = 400 Hz
225
EN = 0
IddSdn
280°
Z > 100° and Z < 260°
01
Z < 75° or Z > 285°
Z > 105° and Z < 255°
10
Z < 70° or Z > 290°
Z > 110° and Z < 250°
11
Z < 65° or Z > 295°
Z > 115° and Z < 245°
0x1D - 0x1F: PL_P_L_THS_REG1, 2, 3 Portrait-to-Landscape Threshold Registers
The following registers represent the Portrait-to-Landscape trip threshold registers. These registers are used to set the trip
angle for the image transition from the Portrait orientation to the Landscape orientation. The angle can be selected from Table 28
and the corresponding values for that angle should be written into the three PL_P_L_THS Registers.
0x1D PL_P_L_THS_REG1 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P_L_THS[7]
P_L_THS[6]
P_L_THS[5]
P_L_THS[4]
P_L_THS[3]
P_L_THS[2]
P_L_THS[1]
P_L_THS[0]
Table 25. PL_P_L_THS_REG1 Description
P_L_THS
Portrait-to-Landscape Threshold Register 1. Default value: 30° → 0001_1010.
0x1E PL_P_L_THS_REG2 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P_L_THS[7]
P_L_THS[6]
P_L_THS[5]
P_L_THS[4]
P_L_THS[3]
P_L_THS[2]
P_L_THS[1]
P_L_THS[0]
Table 26. PL_P_L_THS_REG2 Description
P_L_THS
Portrait-to-Landscape Threshold Register 2. Default value: 30° → 0010_0010.
0x1F PL_P_L_THS_REG3 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P_L_THS[7]
P_L_THS[6]
P_L_THS[5]
P_L_THS[4]
P_L_THS[3]
P_L_THS[2]
P_L_THS[1]
P_L_THS[0]
MMA8450Q
28
Sensors
Freescale Semiconductor, Inc.
Table 27. PL_P_L_THS_REG3 Description
P_L_THS
Portrait-to-Landscape Threshold Register 3. Default value: 30°→ 1101_0100.
Table 28. Portrait-to-Landscape Trip Angle Thresholds Lookup Table
Portrait-to-Landscape
Trip Angle
PL_P_L_THS_REG1
PL_P_L_THS_REG2
PL_P_L_THS_REG3
15
0x17
0x75
0x77
20
0x18
0x14
0x23
25
0x18
0xF3
0x59
30
0x1A
0x32
0xD5
35
0x1B
0x92
0x77
40
0x1D
0x92
0x33
45
0x20
0x00
0x00
50
0x23
0x31
0xD9
55
0x27
0x71
0xB9
60
0x2D
0x41
0xA2
0x20 - 0x22 PL_L_P_THS_REG1, 2, 3 Landscape-to-Portrait Threshold Registers
The following registers represent the Landscape-to-Portrait trip threshold registers. These registers are used to set the trip
angle for the image transition from the Landscape orientation to the Portrait orientation. The angle can be selected from Table 32
and the corresponding values for that angle should be written into the three PL_L_P_THS Registers.
0x20 PL_L_P_THS_REG1 Register (Read/Write)
Bit 7
L_P_THS[7]
Bit 6
L_P_THS[6]
Bit 5
L_P_THS[5]
Bit 4
L_P_THS[4]
Bit 3
L_P_THS[3]
Bit 2
L_P_THS[2]
Bit 1
L_P_THS[1]
Bit 0
L_P_THS[0]
Table 29. PL_L_P_THS_REG1 Description
L_P_THS
Landscape-to-Portrait Threshold Register 1. Default value: 60° → 0010_1101.
0x21 PL_L_P_THS_REG2 Register (Read/Write)
Bit 7
L_P_THS[7]
Bit 6
L_P_THS[6]
Bit 5
L_P_THS[5]
Bit 4
L_P_THS[4]
Bit 3
L_P_THS[3]
Bit 2
L_P_THS[2]
Bit 1
L_P_THS[1]
Bit 0
L_P_THS[0]
Bit 1
L_P_THS[1]
Bit 0
L_P_THS[0]
Table 30. PL_L_P_THS_REG2 Description
L_P_THS
Landscape-to-Portrait Threshold Register 2. Default value: 60° → 0100_0001.
0x22 PL_L_P_THS_REG3 Register (Read/Write)
Bit 7
L_P_THS[7]
Bit 6
L_P_THS[6]
Bit 5
L_P_THS[5]
Bit 4
L_P_THS[4]
Bit 3
L_P_THS[3]
Bit 2
L_P_THS[2]
Table 31. PL_L_P_THS_REG3 Description
L_P_THS
Landscape-to-Portrait Threshold Register 3. Default value: 60° → 1010_0010.
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Table 32. Landscape-to-Portrait Trip Angle Thresholds Lookup Table
Landscape-to-Portrait
Trip Angle
PL_L_P_THS_REG1
PL_L_P_THS_REG2
PL_L_P_THS_REG3
30
0x1A
0x22
0xD4
35
0x1B
0x92
0x77
40
0x1D
0x92
0x33
45
0x20
0x00
0x00
50
0x23
0x31
0xD9
55
0x27
0x71
0xB9
60
0x2D
0x41
0xA2
65
0x35
0x91
0x8F
70
0x42
0x31
0x81
75
0x57
0x71
0x77
6.4
Freefall & Motion Detection Registers
For details on how to configure the device for Freefall and/or Motion detection and for sample code, refer to application note
AN3917.
Note: There are two Freefall and Motion Detection Functions. The registers from 0x27 - 0x2A have the same descriptions as
registers 0x23 - 0x26.
0x23: FF_MT_CFG_1 Freefall and Motion Configuration Register 1
0x23 FF_MT_CFG_1 Register (Read/Write)
Bit 7
ELE
Bit 6
OAE
Bit 5
ZHEFE
Bit 4
ZLEFE
Bit 3
YHEFE
Bit 2
YLEFE
Bit 1
XHEFE
Bit 0
XLEFE
Table 33. FF_MT_CFG_1 Description
ELE
OAE
ZHEFE
ZLEFE
YHEFE
YLEFE
XHEFE
XLEFE
Event Latch Enable: Event flag is latched into FF_MT_SRC_1 register. Reading of the FF_MT_SRC_1 register clears the EA
event flag. Default value: 0.
0: Event flag latch disabled; 1: Event flag latch enabled
Logical Or/And combination of events flags. Default value: 0.
0: Logical AND combination of events flags; 1: Logical OR combination of events flags
Event flag enable on Z High event. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
Event flag enable on Z Low event. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
Event flag enable on Y High event. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
Event flag enable on Y Low event. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
Event flag enable on X High event. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
Event flag enable on X Low event. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
OAE bit allows the selection between Motion (logical OR combination of X, Y, Z-axis event flags) and Freefall (logical AND
combination of X, Y, Z-axis event flags) detection.
ELE denotes whether the enabled event flag will be latched in the FF_MT_SRC_1 register or the event flag status in the
FF_MT_SRC_1 will indicate the real-time status of the event. If ELE bit is set to a logic 1, then the event active “EA” flag is cleared
by reading the FF_MT_SRC_1 source register.
ZHEFE, YHEFE, XHEFE enables the detection of a high g event when the measured acceleration data on X, Y, or Z-axis is
higher than the threshold set in FF_MT_THS_1 register.
ZLEFE, YLEFE, XLEFE enables the detection of a low g event when the measured acceleration data on X, Y, or Z-axis is lower
than the threshold set in FF_MT_THS_1 register.
FF_MT_THS_1 is the threshold register used by the Freefall/Motion function to detect Freefall or Motion events. The unsigned
7-bit FF_MT_THS_1 threshold register holds the threshold for the low g event detection where the magnitude of the X and Y and
Z acceleration values are lower than the threshold value. Conversely the FF_MT_THS_1 also holds the threshold for the high g
event detection where the magnitude of the X, or Y, or Z-axis acceleration values is higher than the threshold value.
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0x24 FF_MT_SRC_1 Register
0x24: FF_MT_SRC_ Freefall and Motion Source Register (0x24) (Read Only)
Bit 7
—
Bit 6
EA
Bit 5
ZHE
Bit 4
ZLE
Bit 3
YHE
Bit 2
YLE
Bit 1
XHE
Bit 0
XLE
Table 34. FF_MT_SRC_1 Description
EA
Event Active Flag. Default value: 0.
0: No event flag has been asserted; 1: one or more event flags have been asserted.
ZHE
Z High Event Flag. Default value: 0.
0: No Z High event detected, 1: Z High event has been detected
ZLE
Z Low Event Flag. Default value: 0.
0: No Z Low event detected, 1: Z Low event has been detected
YHE
Y High Event Flag. Default value: 0.
0: No Y High event detected, 1: Y High event has been detected
YLE
Y Low Event Flag. Default value: 0.
0: No Y Low event detected, 1: Y Low event has been detected
XHE
X High Event Flag. Default value: 0.
0: No X High event detected, 1: X High event has been detected
XLE
X Low Event Flag. Default value: 0.
0: No X Low event detected, 1: X Low event has been detected
This register keeps track of the acceleration event which is triggering (or has triggered, in case of ELE bit in FF_MT_CFG_1
register being set to 1) the event flag. In particular EA is set to a logic 1 when the logical combination of acceleration events flags
specified in FF_MT_CFG_1 register is true. This bit is used in combination with the values in INT_EN_FF_MT_1 and
INT_CFG_FF_MT_1 register to generate the Freefall/Motion interrupts.
An X,Y, or Z high or an X,Y, and Z high event is true when the acceleration value of the X or Y or Z axes is higher than the
preset threshold value defined in the FF_MT_THS_1 register.
Conversely X,Y, or Z high or an X,Y, and Z low event is true when the acceleration value of the X and Y and Z axes are lower
than the preset threshold value defined in the FF_MT_THS_1 register.
When the ELE bit is set, only the EA bit is latched. The other bits are not latched. To see the events that have been detected,
the register must be read immediately. The EA bit will remain high until the source register is read.
0x25: FF_MT_THS_1 Freefall and Motion Threshold 1 Register
0x25 FF_MT_THS_1 Register (Read/Write)
Bit 7
DBCNTM
Bit 6
THS6
Bit 5
THS5
Bit 4
THS4
Bit 3
THS3
Bit 2
THS2
Bit 1
THS1
Bit 0
THS0
Table 35. FF_MT_THS_1 Description
DBCNTM
Debounce counter mode selection. Default value: 0.
0: increments or decrements debounce, 1: increments or clears counter.
THS[6:0]
Freefall /Motion Threshold: Default value: 000 0000
The minimum threshold resolution is dependent on the selected acceleration g range and the threshold register has a range
of 0 to 127.
Therefore:
• If the selected acceleration g range is 8g mode (FS = 11), the minimum threshold resolution is 0.063g/LSB. The maximum
value is 8g.
• If the selected acceleration g range is 4g mode (FS = 10), the minimum threshold resolution is 0.0315g/LSB. The
maximum value is 4g.
• If the selected acceleration g range is 2g mode (FS = 01), the minimum threshold resolution is 0.01575g/LSB. The
maximum value is 2g.
When DBCNTM bit is a logic ‘1’, the debounce counter is cleared to 0 whenever the event of interest is no longer true (Figure
12 part b) while if the DBCNTM bit is set a logic ‘0’ the debounce counter is decremented by 1 whenever the event of interest is
no longer true (Figure 12 part c) until the debounce counter reaches 0 or the event of interest becomes active.
Decrementing of the debounce counter acts as a median filter enabling the system to filter out irregular spurious events which
might impede the detection of the event.
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Low g Event on
all 3-axis
(Freefall)
Count Threshold
(a)
FF_MT
Counter
Value
EA FF
Low g Event on
all 3-axis
(Freefall)
DBCNTM = 1
Count Threshold
FF_MT
Counter
Value
(b)
EA FF
Low g Event on
all 3-axis
(Freefall)
DBCNTM = 0
Count Threshold
FF_MT
Counter
Value
(c)
EA FF
Figure 12. DBCNTM Bit Function
0x26: FF_MT_COUNT_1 Freefall Motion Count 1 Register
This register sets the number of debounce sample counts for the event trigger.
0x26 FF_MT_COUNT_1 Register (Read/Write)
Bit 7
D7
Bit 6
D6
Bit 5
D5
Bit 4
D4
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
Table 36. FF_MT_COUNT_1 Description
D[7-0]
Count value. Default value: 0000_0000.
D7 - D0 define the number of debounce sample counts for the event trigger. When the debounce counter exceeds the
FF_MT_COUNT_1 value, a Freefall/Motion event flag is set. The time step used for the debounce sample count depends on the
ODR chosen (Table 37).
Table 37. FF_MT_COUNT_1 and FF_MT_COUNT_2 Relationship with the ODR
Output Data Rate (Hz)
Step
Duration Range
400
2.5 ms
2.5 ms – 0.63s
200
5 ms
5 ms – 1.275s
100
10 ms
10 ms – 2.55s
50
20 ms
20 ms – 5.1s
12.5
80 ms
80 ms – 20.4s
1.56
640 ms
640 ms – 163s
An ODR of 100 Hz and a FF_MT_COUNT_1 value of 15 would result in a debounce response time of 150 ms.
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0x27: FF_MT_CFG_2 Freefall and Motion Configuration 2 Register
These registers all have the same descriptions as above for Registers 0x23 - 0x26.
0x27 FF_MT_CFG_2 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ELE
OAE
ZHEFE
ZLEFE
YHEFE
YLEFE
XHEFE
XLEFE
0x28: FF_MT_SRC_2 Freefall and Motion Source 2 Register
0x28 FF_MT_SRC_2 Register (Read Only)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
EA
ZHE
ZLE
YHE
YLE
XHE
XLE
0x29: FF_MT_THS_2 Freefall and Motion Threshold 2 Register
0x29 FF_MT_THS_2 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DBCNTM
THS6
THS5
THS4
THS3
THS2
THS1
THS0
0x2A: FF_MT_COUNT_2 Freefall and Motion Debounce 2 Register
0x2A FF_MT_COUNT_2 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
6.5
Transient Detection Registers
For more information on the uses of the transient function and sample code, refer to application note AN3918.
0x2B: TRANSIENT_CFG Transient Configuration Register
The transient detection mechanism can be configured to raise an interrupt when the magnitude of the high pass filtered data
is greater than a user definable threshold. The TRANSIENT_CFG register is used to enable the transient interrupt generation
mechanism for each of the 3 axes (X, Y, Z) of acceleration.
0x2B TRANSIENT_ CFG Register (Read/Write)
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
ELE
Bit 2
ZTEFE
Bit 1
YTEFE
Bit 0
XTEFE
Table 38. TRANSIENT_ CFG Description
ELE
Transient event flag is latched into the TRANSIENT_SRC register. Reading of the TRANSIENT_SRC register clears the event
flag. Default value: 0.
0: event flag latch disabled; 1: Event flag latch enabled
ZTEFE
Event flag enable on Z-axis. Default value: 0.
0: Event detection disabled; 1: Event detection Enabled
YTEFE
Event flag enable on Y-axis. Default value: 0.
0: Event detection disabled; 1: Event detection Enabled
XTEFE
Event flag enable on X-axis. Default value: 0.
0: Event detection disabled; 1: Event detection Enabled
0x2C: TRANSIENT_SRC Transient Source Register
The transient source register is read to determine the source of an interrupt. When the ELE bit is set in Register0x2B the “EA”
event Active bit in the source register is latched. The other bits in the source register are not latched. The source register must
be read immediately following the interrupt to determine the axes the event occurred on. The interrupt for the transient event is
cleared by reading the status register.
0x2C TRANSIENT_SRC Register (Read Only)
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
EA
Bit 2
ZTRANSE
Bit 1
YTRANSE
Bit 0
XTRANSE
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Table 39. TRANSIENT_SRC Description
Event Active Flag. Default value: 0.
0: No event flag asserted; 1: one or more event flag has been asserted.
EA
ZTRANSE
Z transient event. Default value: 0.
0: No Z event detected, 1: Z event detected
YTRANSE
Y transient event. Default value: 0.
0: No Y event detected, 1: Y event detected
XTRANSE
X transient event. Default value: 0.
0: No X event detected, 1: X event detected
0x2D: TRANSIENT_THS Transient Threshold Register
The TRANSIENT_THS register sets the threshold limit for the high pass filtered acceleration. The value in the
TRANSIENT_THS register corresponds to a g value which is compared against the values of OUT_X_DELTA, OUT_Y_DELTA,
and OUT_Z_DELTA. If the acceleration exceeds the threshold limit an event flag is raised and an interrupt is generated if
interrupts are enabled.
0x2D TRANSIENT_THS Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DBCNTM
THS6
THS5
THS4
THS3
THS2
THS1
THS0
Table 40. TRANSIENT_THS Description
DBCNTM
Debounce counter mode selection. Default value: 0. 0: increments or decrements debounce; 1: increments or clears counter
THS[6:0]
Transient Threshold: Default value: 000_0000
The minimum threshold resolution is dependent on the selected acceleration g range and the threshold register has a range
of 0 to 127.
Therefore:
• If the selected acceleration g range is 8g mode (FS = 11), the minimum threshold resolution is 0.063g/LSB. The maximum
is 8g.
• If the selected acceleration g range is 4g mode (FS = 10), the minimum threshold resolution is 0.0315g/LSB. The
maximum is 4g.
• If the selected acceleration g range is 2g mode (FS = 01), the minimum threshold resolution is 0.01575g/LSB. The
maximum is 2g.
• The DBCNTM bit behaves in the same manner described previously for the Motion/Freefall 1.
0x2E: TRANSIENT_COUNT Transient Debounce Register
The TRANSIENT_COUNT sets the minimum number of debounce counts continuously matching the condition where the
unsigned value of OUT_X_DELTA or OUT_Y_DELTA or OUT_Z_DELTA register is greater than the user specified value of
TRANSIENT_THS.
0x2E TRANSIENT_COUNT Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
Table 41. TRANSIENT_COUNT Description
D[7-0]
Count value. Default value: 0000_0000.
The time step for the Transient detection debounce counter is set by the value of the system ODR.
Table 42. TRANSIENT_COUNT Relationship with the ODR
Output Data Rate (Hz)
Step
Duration Range
400
2.5 ms
2.5 ms – 0.637s
200
5 ms
5 ms – 1.275s
100
10 ms
10 ms – 2.55s
50
20 ms
20 ms – 5.1s
12.5
80 ms
80 ms – 20.4s
1.56
640 ms
640 ms – 163s
An ODR of 100 Hz and a TRANSIENT_COUNT value of 15 would result in a debounce response time of 150 ms.
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6.6
Tap Detection Registers
For more details of how to configure the tap detection and sample code please refer to Freescale application note, AN3919.
The tap detection registers are referred to as “Pulse”.
0x2F: PULSE_CFG Pulse Configuration Register
This register configures the event flag for the tap detection for enabling/disabling the detection of a single and double pulse
on each of the axes.
0x2F PULSE_CFG Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DPA
ELE
ZDPEFE
ZSPEFE
YDPEFE
YSPEFE
XDPEFE
XSPEFE
Table 43. PULSE_CFG Description
DPA
Double Pulse Abort.
0: Double Pulse detection is not aborted if the start of a pulse is detected during the time period specified by the PULSE_LTCY
register.
1: Setting the DPA bit momentarily suspends the double tap detection if the start of a pulse is detected during the time period
specified by the PULSE_LTCY register and the pulse ends before the end of the time period specified by the PULSE_LTCY
register.
ELE
Pulse event flags are latched into the PULSE_SRC register. Reading of the PULSE_SRC register clears the event flag.
Default value: 0.
0: Event flag latch disabled; 1: Event flag latch enabled
ZDPEFE
Event flag enable on double pulse event on Z-axis. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
ZSPEFE
Event flag enable on single pulse event on Z-axis. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
YDPEFE
Event flag enable on double pulse event on Y-axis. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
YSPEFE
Event flag enable on single pulse event on Y-axis. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
XDPEFE
Event flag enable on double pulse event on X-axis. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
XSPEFE
Event flag enable on single pulse event on X-axis. Default value: 0.
0: Event detection disabled; 1: Event detection enabled
0x30: PULSE_SRC Pulse Source Register
This register indicates a double or single pulse event has occurred. The corresponding axis and event must be enabled in
Register 0x2F for the event to be seen in the source register. The interrupt for the pulse event is cleared by reading the status
register.
0x30 PULSE_SRC Register (Read Only)
Bit 7
—
Bit 6
EA
Bit 5
ZDPE
Bit 4
ZSPE
Bit 3
YDPE
Bit 2
YSPE
Bit 1
XDPE
Bit 0
XSPE
Table 44. TPULSE_SRC Description
EA
Event Active Flag. Default value: 0
0: no event flag has been asserted; 1: one or more events have been asserted
ZDPE
Double pulse on Z-axis event. Default value: 0.
0: no event detected; 1: Double Z event detected
ZSPE
Single pulse on Z-axis event. Default value: 0.
0: no event detected; 1: Single Z event detected
YDPE
Double pulse on Y-axis event. Default value: 0.
0: no event detected; 1: Double Y event detected
YSPE
Single pulse on Y-axis event. Default value: 0.
0: no event detected; 1: Single Y event detected
XDPE
Double pulse on X-axis event. Default value: 0.
0: no event detected; 1: Double X event detected
XSPE
Single pulse on X-axis event. Default value: 0.
0: no event detected; 1: Single X event detected
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0x31 - 0x33: PULSE_THSX, Y, Z Pulse Threshold for X, Y & Z Registers
The pulse threshold can be set separately for the X, Y and Z axes. The threshold values range from 0 to 31 counts with steps
of 0.258g/LSB at a fixed 8g acceleration range, thus the minimum resolution is always fixed at 0.258g/LSB irrespective of the
selected g range.
The PULSE_THSX, PULSE_THSY and PULSE_THSZ registers define the threshold which is used by the system to start the
pulse detection procedure. The threshold value is expressed over 5-bits as an unsigned number.
0x31 PULSE_THSX Register (Read/Write)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
THSX4
Bit 3
THSX3
Bit 2
THSX2
Bit 1
THSX1
Bit 0
THSX0
Bit 2
THSY2
Bit 1
THSY1
Bit 0
THSY0
Table 45. PULSE_THSX Description
THSX4, THSX0
Pulse Threshold on X-axis. Default value: 0_0000.
0x32 PULSE_THSY Register (Read/Write)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
THSY4
Bit 3
THSY3
Table 46. PULSE_THSY Description
THSY4, THSY0
Pulse Threshold on Y-axis. Default value: 0_0000.
0x33 PULSE_THSZ Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
THSZ4
THSZ3
THSZ2
THSZ1
THSZ0
Table 47. PULSE_THSZ Description
THSZ4, THSZ0
Pulse Threshold on Z-axis. Default value: 0_0000.
0x34: PULSE_TMLT Pulse Time Window 1 Register
0x34 PULSE_TMLT Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Tmlt7
Tmlt6
Tmlt5
Tmlt4
Tmlt3
Tmlt2
Tmlt1
Tmlt0
The bits Tmlt7 through Tmlt0 define the maximum time interval that can elapse between the start of the acceleration on the
selected axis exceeding the specified threshold and the end when the acceleration on the selected axis must go below the
specified threshold to be considered a valid pulse.
The minimum time step for the pulse time limit is defined in Table 48. Maximum time for a given ODR is the minimum time
step at the given power mode multiplied by 255. The time steps available are dependent on whether the device is in Normal
Power mode or in Low Power mode. Notice in the table below that the time step is twice as long in Low Power mode.
Table 48. Time Step for PULSE Time Limit at ODR and Power Mode
Output Data Rate (Hz)
Step at Normal Mode
Step at Low Power Mode
400
0.625 ms
1.25 ms
200
1.25 ms
2.5 ms
100
2.5 ms
5.0 ms
50
5 ms
10 ms
12.5
5 ms
10 ms
1.56
5 ms
10 ms
Therefore an ODR setting of 400 Hz with normal power mode would result in a maximum pulse time limit of (0.625 ms * 255)
≥ 159 ms.
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0x35: PULSE_LTCY Pulse Latency Timer Register
0x35 PULSE_LTCY Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Ltcy7
Ltcy6
Ltcy5
Ltcy4
Ltcy3
Ltcy2
Ltcy1
Ltcy0
The bits Ltcy7 through Ltcy0 define the time interval that starts after the first pulse detection. During this time interval, all pulses
are ignored. Note: This timer must be set for single pulse and for double pulse.
The minimum time step for the pulse latency is defined in Table 49. The maximum time is the time step at the ODR and Power
Mode multiplied by 255. Notice that the time step is twice the duration if the device is operating in Low Power mode, as shown
below.
Table 49. Time Step for PULSE Latency at ODR and Power Mode
Output Data Rate (Hz)
Step at Normal Mode
Step at Low Power Mode
400
1.25 ms
2.5 ms
200
2.5 ms
5.0 ms
100
5.0 ms
20 ms
50
10 ms
20 ms
12.5
10 ms
20 ms
1.56
10 ms
20 ms
0x36: PULSE_WIND Second Pulse Time Window Register
0x36 PULSE_WIND Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Wind7
Wind6
Wind5
Wind4
Wind3
Wind2
Wind1
Wind0
The bits Wind7 through Wind0 define the maximum interval of time that can elapse after the end of the latency interval in which
the start of the second pulse event must be detected provided the device has been configured for double pulse detection. The
detected second pulse width must be shorter than the time limit constraints specified by the PULSE_TMLT register, but the end
of the double pulse need not finish within the time specified by the PULSE_WIND register.
The minimum time step for the pulse window is defined in Table 50. The maximum time is the time step at the ODR and Power
Mode multiplied by 255.
Table 50. Time Step for PULSE Detection Window at ODR and Power Mode
6.7
Output Data Rate (Hz)
Step at Normal Mode
Step at Low Power Mode
400
1.25 ms
2.5 ms
200
2.5 ms
5.0 ms
100
5.0 ms
20 ms
50
10 ms
20 ms
12.5
10 ms
20 ms
1.56
10 ms
20 ms
Auto-Sleep Registers
For additional information on how to configure the device for the Auto-Sleep/Wake feature, refer to AN3921.
0x37: ASLP_COUNT Auto-Sleep Inactivity Timer Register
The ASLP_COUNT register sets the minimum time period of inactivity required to change current ODR value from the value
specified in the DR[2:0] to ASLP_RATE (Reg 0x38) value provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2 register.
0x37 ASLP_COUNT Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
Table 51. ASLP_COUNT Description
D[7-0]
Duration value. Default value: 0000 0000
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D7-D0 defines the minimum duration time to change current ODR value from DR to ASLP_RATE. Time step and maximum
value depend on the ODR chosen (see Table 52).
Table 52. ASLP_COUNT Relationship with ODR
Output Data Rate (ODR)
Duration
Step
400
0 to 81s
320 ms
200
0 to 81s
320 ms
100
0 to 81s
320 ms
50
0 to 81s
320 ms
12.5
0 to 81s
320 ms
1.56
0 to 162s
640 ms
In order to wake the device, the desired function or functions must be enabled and set to “Wake From Sleep”. All enabled
functions will still function in sleep mode at the sleep ODR. Only the functions that have been selected for “Wake From Sleep”
will wake the device.
MMA8450Q has 6 functions that can be used to keep the sensor from falling asleep namely, Transient, Orientation, Tap,
Motion/FF1 and Motion/FF2 and the FIFO. One or more of these functions can be enabled. In order to wake the device, functions
are provided namely, Transient, Orientation, Tap, and the two Motion/Freefall. Note that the FIFO does not wake the device. The
Auto-Wake/Sleep interrupt does not affect the wake/sleep, nor does the data ready interrupt. The FIFO gate (bit 7) in Register
0x3A, when set, will hold the last data in the FIFO before transitioning to a different ODR. After the buffer is flushed, it will accept
new sample data at the current ODR. See Register 0x3A for the wake from sleep bits.
If the Auto-Sleep bit is disabled, then the device can only toggle between Standby and Wake Mode by writing to the FS0 and
FS1 bits in Register 0x38 CTRL_REG1. If Auto-Sleep interrupt is enabled, transitioning from Active mode to Auto-Sleep mode
and vice versa generates an interrupt.
0x38: CTRL_REG1 System Control 1 Register
0x38 CTRL_REG1 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ASLP_RATE1
ASLP_RATE0
0
DR2
DR1
DR0
FS1
FS0
Table 53. CTRL_REG1 Description
ASLP_RATE [1:0]
This register configures the Auto-Wake sample frequency when the device is in Sleep Mode.
See Table 54 for more information.
DR[2:0]
Data rate selection. Default value: 000
FS[1:0]
Full Scale selection. Default value: 00
(00: Standby mode; 01: active mode ±2g; 10: active mode ±4g; 11: active mode ±8g)
Table 54. Sleep Mode Poll Rate Description
ASLP_RATE1
ASLP_RATE0
Frequency (Hz)
0
0
50
0
1
25
1
0
12.5
1
1
1.56
It is important to note that when the device is in Auto-Sleep mode, the system ODR and the data rate for all the system
functional blocks are overwritten by the data rate set by the ASLP_RATE field in Register 0x38.
DR[2:0] bits select the output data rate (ODR) for acceleration samples. The default value is 000 for a data rate of 400 Hz.
Table 55. System Output Data Rate Selection
DR2
DR1
DR0
Output Data Rate (ODR)
Time Between Data Samples
0
0
0
400 Hz
2.5 ms
0
0
1
200 Hz
5 ms
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Freescale Semiconductor, Inc.
Table 55. System Output Data Rate Selection
0
1
0
100 Hz
10 ms
0
1
1
50 Hz
20 ms
1
0
0
12.5 Hz
80 ms
1
0
1
1.563 Hz
640 ms
FS[1:0] bits select between standby mode and active mode. The default value is 00 for standby mode.
Table 56. Full Scale Selection
FS1
FS0
Mode
g Range
0
0
Standby
—
0
1
Active
±2g
1
0
Active
±4g
1
1
Active
±8g
0x39: CTRL_REG2 System Control 2 Register
0x39 CTRL_REG2 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ST
BOOT
0
0
0
0
SLPE
MODS
Table 57. CTRL_REG2 Description
ST
BOOT
Self-Test Enable. Default value: 0.
0: Self-Test disabled; 1: Self-Test enabled
Reboot device content (Software Reset). Default value: 0.
0: device reboot disabled; 1: device reboot enabled.
SLPE(1)
Auto-Sleep enable. Default value: 0.
0: Auto-Sleep is not enabled;
1: Auto-Sleep is enabled.
MODS
Low power mode / Normal mode selection. Default value: 0.
0: normal mode; 1: low power mode.
1. When SLPE = 1, the transitioning between sleep mode and wake mode results in a FIFO flush and a reset of internal functional block counters. All functional block
status information are preserve except otherwise stated. See Table 58 for more information about the FIFO_GATE bit in CTRL_REG3 register.
ST bit activates the Self-Test function. When ST is set to one, an output change will occur to the device outputs (refer to Table 2
and Table 3) thus allowing host application to check the functionality of the entire signal chain.
BOOT bit is used to activate the software reset. The Boot mechanism can be enabled in STANDBY and ACTIVE mode.
When the Boot bit is enabled the Boot mechanism resets all functional block registers and loads the respective internal
registers with default NVM values.
The system will automatically transition to standby mode if not already in standby mode before the software reset (re-BOOT
process) can occur.
Note: The I2C communication system is reset to avoid accidental corrupted data access.
0x3A: CTRL_REG3 Interrupt Control Register
0x3A CTRL_REG3 Register (Read/Write)
Bit 7
Bit 6
Bit 5
FIFO_GATE
WAKE_TRANS
WAKE_LNDPRT
Bit 4
Bit 3
Bit 2
WAKE_PULSE WAKE_FF_MT_1 WAKE_FF_MT_2
Bit 1
Bit 0
IPOL
PP_OD
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Table 58. CTRL_REG3 Description
0: FIFO gate is bypassed. FIFO is flushed upon the system mode transitioning from wake-to-sleep mode or from sleep-towake mode.
1: The FIFO input buffer is blocked when transitioning from “wake-to-sleep” mode or from “sleep-to-wake” mode until the
FIFO is flushed. Although the system transitions from “wake-to-sleep” or from “sleep-to-wake” the contents of the FIFO
buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application.
If the FIFO_GATE bit is set to logic 1 and the FIFO buffer is not emptied before the arrival of the next sample, then the
FGERR bit in the SYS_MOD register (0x14) will be asserted. The FGERR bit remains asserted as long as the FIFO buffer
remains un-emptied.
Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register.
FIFO_GATE
WAKE_TRANS
WAKE_LNDPRT
WAKE_PULSE
0: Transient function is bypassed in sleep mode
1: Transient function interrupt can wake up system
0: Orientation function is bypassed in sleep mode
1: Orientation function interrupt can wake up system
0: Pulse function is bypassed in sleep mode
1: Pulse function interrupt can wake up system
WAKE_FF_MT_1
0: Freefall/Motion1 function is bypassed in sleep mode
1: Freefall/Motion1 function interrupt can wake up
WAKE_FF_MT_2
0: Freefall/Motion2 function is bypassed in sleep mode
1: Freefall/Motion2 function interrupt can wake up system
IPOL
Interrupt polarity active high, or active low. Default value 0.
0: active low; 1: active high
PP_OD
Push-pull/Open Drain selection on interrupt pad. Default value 0.
0: push-pull; 1: open drain
IPOL bit selects the polarity of the interrupt signal. When IPOL is ‘0’ any interrupt event will signalled with a logical 0.
PP_OD bit configures the interrupt pin to Push-Pull or in Open Drain mode. The open drain configuration can be used for
connecting multiple interrupt signals on the same interrupt line.
0x3B: CTRL_REG4 Register (Read/Write)
0x3B CTRL_REG4 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT_EN_ASLP
INT_EN_FIFO
INT_EN_TRANS
INT_EN_LNDPRT
INT_EN_PULSE
INT_EN_FF_MT_1
INT_EN_FF_MT_2
INT_EN_DRDY
Table 59. interrupt Enable Register Description
Interrupt Enable
Description
INT_EN_ASLP
Interrupt Enable. Default value: 0.
0: Auto-Sleep/Wake interrupt disabled; 1: Auto-Sleep/Wake interrupt enabled.
INT_EN_FIFO
Interrupt Enable. Default value: 0.
0: FIFO interrupt disabled; 1: FIFO interrupt enabled.
INT_EN_TRANS
INT_EN_LNDPRT
Interrupt Enable. Default value: 0.
0: Transient interrupt disabled; 1: Transient interrupt enabled.
Interrupt Enable. Default value: 0.
0: Orientation (Landscape/Portrait) interrupt disabled.
1: Orientation (Landscape/Portrait) interrupt enabled.
INT_EN_PULSE
Interrupt Enable. Default value: 0.
0: Pulse Detection interrupt disabled; 1: Pulse Detection interrupt enabled
INT_EN_FF_MT_1
Interrupt Enable. Default value: 0.
0: Freefall/Motion1 interrupt disabled; 1: Freefall/Motion1 interrupt enabled
INT_EN_FF_MT_2
Interrupt Enable. Default value: 0.
0: Freefall/Motion2 interrupt disabled; 1: Freefall/Motion2 interrupt enabled
INT_EN_DRDY
Interrupt Enable. Default value: 0.
0: Data Ready interrupt disabled; 1: Data Ready interrupt enabled
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Freescale Semiconductor, Inc.
The corresponding functional block interrupt enable bit allows the functional block to route its event detection flags to the
system’s interrupt controller. The interrupt controller routes the enabled functional block interrupt to the INT1 or INT2 pin.
0x3C: CTRL_REG5 Interrupt Configuration Register
0x3C CTRL_REG5 Register (Read/Write)
Bit 7
Bit 6
INT_CFG_ASLP
INT_CFG_FIFO
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT_1INT_CFG_FF_MT_2 INT_CFG_DRDY
Table 60. Interrupt Configuration Register Description
Interrupt Configuration
INT_CFG_ASLP
INT_CFG_FIFO
INT_CFG_TRANS
INT_CFG_LNDPRT
INT_CFG_PULSE
INT_CFG_FF_MT_1
INT_CFG_FF_MT_2
INT_CFG_DRDY
Description
INT1/INT2 Configuration. Default value: 0.
0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin
INT1/INT2 Configuration. Default value: 0.
0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin
INT1/INT2 Configuration. Default value: 0.
0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin
INT1/INT2 Configuration. Default value: 0.
0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin
INT1/INT2 Configuration. Default value: 0.
0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin
INT1/INT2 Configuration. Default value: 0.
0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin
INT1/INT2 Configuration. Default value: 0.
0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin
INT1/INT2 Configuration. Default value: 0.
0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin
The system’s interrupt controller shown in Figure 10 uses the corresponding bit field in the CTRL_REG5 register to determine
the routing table for the INT1 and INT2 interrupt pins. If the bit value is logic ‘0’ the functional block’s interrupt is routed to INT2,
and if the bit value is logic ‘1’ then the interrupt is routed to INT1. One or more functions can assert an interrupt pin; therefore a
host application responding to an interrupt should read the INT_SOURCE (0x15) register to determine the appropriate sources
of the interrupt.
6.8
User Offset Correction Registers
For more information on how to calibrate the 0g Offset refer to AN3916 Offset Calibration Using the MMA8450Q. The 2’s
complement offset correction registers values are used to realign the Zero-g position of the X, Y, and Z-axis after device board
mount. The resolution of the offset registers is 3.906 mg per LSB. The 2’s complement 8-bit value would result in an offset
compensation range ±0.5g.
0x3D: OFF_X Offset Correction X Register
0x3D OFF_X Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
Table 61. OFF_X Description
D7-D0
X -axis offset trim LSB value. Default value: 0000_0000.
0x3E: OFF_Y Offset Correction Y Register
0x3E OFF_Y Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
Table 62. OFF_Y Description
D7-D0
Y-axis offset trim LSB value. Default value: 0000_0000.
0x3F: OFF_Z Offset Correction Z Register
0x3F OFF_Z Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
Table 63. OFF_Z Description
D7-D0
Z-axis offset trim LSB value. Default value: 0000_0000.
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Appendix A
Table 64. MMA8450Q Register Map
Reg
Name
Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
STATUS
Data Status R
ZYXOW
ZOW
YOW
XOW
ZYXDR
ZDR
YDR
XDR
01
OUT_X_MSB
8-bit X Data R
XD11
XD10
XD9
XD8
XD7
XD6
XD5
XD4
02
OUT_Y_MSB
8-bit Y Data R
YD11
YD10
YD9
YD8
YD7
YD6
YD5
YD4
03
OUT_Z_MSB
8-bit Z Data R
ZD11
ZD10
ZD9
ZD8
ZD7
ZD6
ZD5
ZD4
04
STATUS
Data Status R
ZYXOW
ZOW
YOW
XOW
ZYXDR
ZDR
YDR
XDR
05
OUT_X_LSB
12-bit X Data R
0
0
0
0
XD3
XD2
XD1
XD0
06
OUT_X_MSB
12-bit X Data R
XD11
XD10
XD9
XD8
XD7
XD6
XD5
XD4
07
OUT_Y_LSB
12-bit Y Data R
0
0
0
0
YD3
YD2
YD1
YD0
08
OUT_Y_MSB
12-bit Y Data R
YD11
YD10
YD9
YD8
YD7
YD6
YD5
YD4
09
OUT_Z_LSB
12-bit Z Data R
0
0
0
0
ZD3
ZD2
ZD1
ZD0
0A
OUT_Z_MSB
12-bit Z Data R
ZD11
ZD10
ZD9
ZD8
ZD7
ZD6
ZD5
ZD4
0B
STATUS
Data Status R
ZYXOW
ZOW
YOW
XOW
ZYXDR
ZDR
YDR
XDR
0C
OUT_X_DELTA
8-bit Transient X Data R
XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
0D
OUT_Y_DELTA
8-bit Transient Y Data R
YD7
YD6
YD5
YD4
YD3
YD2
YD1
YD0
0E
OUT_Z_DELTA
8-bit Transient Z Data R
ZD7
ZD6
ZD5
ZD4
ZD3
ZD2
ZD1
ZD0
0F
WHO_AM_I
ID Register R
—
—
—
—
—
—
—
—
10
F_STATUS
FIFO Status R
F_OVF
F_WMRK_FLAG
F_CNT5
F_CNT4
F_CNT3
F_CNT2
F_CNT1
F_CNT0
11
F_8DATA
8-bit FIFO Data R
XD11
XD10
XD9
XD8
XD7
XD6
XD5
XD4
12
F_12DATA
12-bit FIFO Data R
0
0
0
0
XD3
XD2
XD1
XD0
13
F_SETUP
FIFO Setup R/W
F_MODE1
F_MODE0
F_WMRK5
F_WMRK4
F_WMRK3
F_WMRK2
F_WMRK1
F_WMRK0
14
SYSMOD
System Mode R
PERR
FGERR
0
0
0
0
SYSMOD1
SYSMOD0
15
INT_SOURCE
Interrupt Status R
SRC_ASLP
SRC_FIFO
SRC_TRANS
SRC_LNDPRT
SRC_PULSE
SRC_FF_MT_1
SRC_FF_MT_2
SRC_DRDY
16
XYZ_DATA_CFG
Data Config. R/W
FDE
0
0
0
—
ZDEFE
YDEFE
XDEFE
17
HP_FILTER_CUTOFF
HP Filter Setting R/W
0
0
0
0
0
0
SEL1
SEL0
18
PL_STATUS
PL Status R
NEWLP
LO
-
LAPO[2]
LAPO[1]
LAPO[0]
BAFRO[1]
BAFRO[0]
19
PL_PRE_STATUS
Previous PL Status R
-
LO
-
LAPO[2]
LAPO[1]
LAPO[0]
BAFRO[1]
BAFRO[0]
1A
PL_CFG
PL Configuration R/W
DBCNTM
PL_EN
-
-
-
GOFF[2]
GOFF[1]
GOFF[0]
1B
PL_COUNT
PL Debounce R/W
DBNCE[7]
DBNCE[6]
DBNCE[5]
DBNCE[4]
DBNCE[3]
DBNCE [2]
DBNCE [1]
DBNCE [0]
1C
PL_BF_ZCOMP
PL Back/Front and Z
Compensation R/W
BKFR[1]
BKFR[0]
-
-
-
ZLOCK[2]
ZLOCK[1]
ZLOCK[0]
1D
PL_P_L_THS_REG1
Portrait-to-Landscape
Threshold Setting 1 R/W
P_L_THS[7]
P_L_THS[6]
P_L_THS[5]
P_L_THS[4]
P_L_THS[3]
P_L_THS[2]
P_L_THS[1]
P_L_THS[0]
1E
PL_P_L_THS_REG2
Portrait-to-Landscape
Threshold Setting 2 R/W
P_L_THS[7]
P_L_THS[6]
P_L_THS[5]
P_L_THS[4]
P_L_THS[3]
P_L_THS[2]
P_L_THS[1]
P_L_THS[0]
1F
PL_P_L_THS_REG3
Portrait-to-Landscape
Threshold Setting 3 R/W
P_L_THS[7]
P_L_THS[6]
P_L_THS[5]
P_L_THS[4]
P_L_THS[3]
P_L_THS[2]
P_L_THS[1]
P_L_THS[0]
20
PL_L_P_THS_REG1
Landscape-to-Portrait
Threshold Setting 1 R/W
L_P_THS[7]
L_P_THS[6]
L_P_THS[5]
L_P_THS[4]
L_P_THS[3]
L_P_THS[2]
L_P_THS[1]
L_P_THS[0]
21
PL_L_P_THS_REG2
Landscape-to-Portrait
Threshold Setting21 R/W
L_P_THS[7]
L_P_THS[6]
L_P_THS[5]
L_P_THS[4]
L_P_THS[3]
L_P_THS[2]
L_P_THS[1]
L_P_THS[0]
22
PL_L_P_THS_REG3
Landscape-to-Portrait
Threshold Setting 3 R/W
L_P_THS[7]
L_P_THS[6]
L_P_THS[5]
L_P_THS[4]
L_P_THS[3]
L_P_THS[2]
L_P_THS[1]
L_P_THS[0]
23
FF_MT_CFG_1
FF/Motion Config.
1 R/W
ELE
OAE
ZHEFE
ZLEFE
YHEFE
YLEFE
XHEFE
XLEFE
24
FF_MT_SRC_1
FF/Motion Source 1 R
—
EA
ZHE
ZLE
YHE
YLE
XHE
XLE
25
FF_MT_THS_1
FF/Motion Threshold 1 R/W
DBCNTM
THS6
THS5
THS4
THS3
THS2
THS1
THS0
26
FF_MT_COUNT_1
FF/Motion Debounce 1 R/W
D7
D6
D5
D4
D3
D2
D1
D0
27
FF_MT_CFG_2
FF/Motion Config. 2 R/W
ELE
OAE
ZHEFE
ZLEFE
YHEFE
YLEFE
XHEFE
XLEFE
28
FF_MT_SRC_2
FF/Motion Source 2 R
—
EA
ZHE
ZLE
YHE
YLE
XHE
XLE
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Table 64. MMA8450Q Register Map
29
FF_MT_THS_2
FF/Motion Threshold 2 R/W
DBCNTM
THS6
THS5
THS4
THS3
THS2
THS1
THS0
2A
FF_MT_COUNT_2
FF/Motion Debounce 2 R/W
D7
D6
D5
D4
D3
D2
D1
D0
2B
TRANSIENT_CFG
Transient Config. R/W
—
—
—
—
ELE
ZTEFE
YTEFE
XTEFE
2C
TRANSIENT_SRC
Transient Source R
—
—
—
—
EA
ZTRANSE
YTRANSE
XTRANSE
2D
TRANSIENT_THS
Transient Threshold R/W
DBCNTM
THS6
THS5
THS4
THS3
THS2
THS1
THS0
2E
TRANSIENT_COUNT
Transient Debounce R/W
D7
D6
D5
D4
D3
D2
D1
D0
2F
PULSE_CFG
Pulse Config. R/W
DPA
ELE
ZDPEFE
ZSPEFE
YDPEFE
YSPEFE
XDPEFE
XSPEFE
30
PULSE_SRC
Pulse Source R
—
EA
ZDPE
ZSPE
YDPE
YSPE
XDPE
XSPE
31
PULSE_THSX
Pulse X Threshold R/W
0
0
0
THSX4
THSX3
THSX2
THSX1
THSX0
32
PULSE_THSY
Pulse Y Threshold R/W
0
0
0
THSY4
THSY3
THSY2
THSY1
THSY0
33
PULSE_THSZ
Pulse Z Threshold R/W
0
0
0
THSZ4
THSZ3
THSZ2
THSZ1
THSZ0
34
PULSE_TMLT
Pulse First Timer R/W
Tmlt7
Tmlt6
Tmlt5
Tmlt4
Tmlt3
Tmlt2
Tmlt1
Tmlt0
35
PULSE_LTCY
Pulse Latency R/W
Ltcy7
Ltcy6
Ltcy5
Ltcy4
Ltcy3
Ltcy2
Ltcy1
Ltcy0
36
PULSE_WIND
Pulse 2nd Window R/W
Wind7
Wind6
Wind5
Wind4
Wind3
Wind2
Wind1
Wind0
37
ASLP_COUNT
Auto-Sleep Counter R/W
D7
D6
D5
D4
D3
D2
D1
D0
38
CTRL_REG1
Control Reg 1 R/W
ASLP_RATE1
ASLP_RATE0
0
DR2
DR1
DR0
FS1
FS0
39
CTRL_REG2
Control Reg 2 R/W
ST
RST
0
0
0
0
SLPE
MODS
3A
CTRL_REG3
Control Reg3 R/W (Wake
Interrupts from Sleep)
FIFO_GATE
WAKE_TRANS
WAKE_LNDPRT
WAKE_PULSE
WAKE_FF_MT_1
WAKE_FF_MT_2
IPOL
PP_OD
3B
CTRL_REG4
Control Reg4 R/W (Interrupt
Enable Map)
INT_EN_ASLP
INT_EN_FIFO
INT_EN_TRANS
INT_EN_LNDPRT
INT_EN_PULSE
INT_EN_FF_MT_1
INT_EN_FF_MT_2
INT_EN_DRDY
3C
CTRL_REG5
Control reg5 R/W
(Interrupt Configuration)
INT_CFG_ASLP INT_CFG_FIFO INT_CFG_TRANS INT_CFG_LNDPRT
INT_CFG_PULSE
3D
OFF_X
X 8-bit offset
D7
D6
D5
D4
D3
D2
D1
D0
3E
OFF_Y
Y 8-bit offset
D7
D6
D5
D4
D3
D2
D1
D0
3F
OFF_Z
Z 8-bit offset
D7
D6
D5
D4
D3
D2
D1
D0
INT_CFG_FF_MT_1 INT_CFG_FF_MT_2 INT_CFG_DRDY
MMA8450Q
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Freescale Semiconductor, Inc.
43
Table 65. Accelerometer Output Data
12-bit Data
Range ±2g
Range ±4g
Range ±8g
0111 1111 1111
1.999g
+3.998g
+7.996g
0111 1111 1110
1.998g
+3.996g
+7.992g
—
—
—
—
0000 0000 0001
0.001g
+0.002g
+0.004g
0000 0000 0000
0.000g
0.000g
0.000g
1111 1111 1111
-0.001g
-0.002g
-0.004g
—
—
—
—
1000 0000 0001
-1.999g
-3.998g
-7.996g
1000 0000 0000
-2.000g
-4.000g
-8.000g
8- bit Data
Range ±2g
Range ±4g
Range ±8g
0111 1111
1.984g
+3.968g
+7.936g
0111 1110
1.968g
+3.936g
+7.872g
—
—
—
—
0000 0001
+0.016g
+0.032g
+0.064g
0000 0000
0.000g
0.000g
0.000g
1111 1111
-0.016g
-0.032g
-0.064g
—
—
—
—
1000 0001
-1.984g
-3.968g
-7.936g
1000 0000
-2.000g
-4.000g
-8.000g
MMA8450Q
44
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Freescale Semiconductor, Inc.
Appendix B
Figure 13. Distribution of Pre Board Mounted Devices Tested in Sockets (1 count = 3.9 mg)
MMA8450Q
Sensors
Freescale Semiconductor, Inc.
45
Figure 14. Distribution of Post Board Mounted Devices (1 count = 3.9 mg)
MMA8450Q
46
Sensors
Freescale Semiconductor, Inc.
Figure 15. 2g/4g/8g X-axis TCS (%/°C)
MMA8450Q
Sensors
Freescale Semiconductor, Inc.
47
Figure 16. 2g/4g/8g Y-axis TCS (%/°C)
MMA8450Q
48
Sensors
Freescale Semiconductor, Inc.
Figure 17. 2g/4g/8g Z-axis TCS (%/°C)
MMA8450Q
Sensors
Freescale Semiconductor, Inc.
49
Figure 18. 2g/4g/8g X-axis TCO (mg/°C)
MMA8450Q
50
Sensors
Freescale Semiconductor, Inc.
Figure 19. 2g/4g/8g Y-axis TCO (mg/°C)
MMA8450Q
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Freescale Semiconductor, Inc.
51
Figure 20. 2g/4g/8g Z-axis TCO (mg/°C)
MMA8450Q
52
Sensors
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
CASE 2077-02
ISSUE A
16-LEAD QFN
MMA8450Q
Sensors
Freescale Semiconductor, Inc.
53
PACKAGE DIMENSIONS
CASE 2077-02
ISSUE A
16-LEAD QFN
MMA8450Q
54
Sensors
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
CASE 2077-02
ISSUE A
16-LEAD QFN
MMA8450Q
Sensors
Freescale Semiconductor, Inc.
55
Revision History
Revision
Number
Revision
Date
9
02/01/2012
• Corrected Pin Diagram: Pin 8, callout from NC to EN.
9.1
04/13/2012
• Page 39, Corrected register name from 0x3C: CTRL_REG5 register to 0x3B: CTRL_REG4.
• Updated case outline drawing from 2077-01, Issue 0 to 2077-02, Issue A.
Description of Changes
MMA8450Q
56
Sensors
Freescale Semiconductor, Inc.
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MMA8450Q
Rev. 9.1
04/2012
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