Rev 0; 6/07
KIT
ATION
EVALU
LE
B
A
IL
A
AV
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
The MAXQ3100 microcontroller is a low-power, 16-bit
RISC device that incorporates an integrated liquid-crystal
display (LCD) interface that can drive up to 160 segments, two analog comparators with precision internal
1.25V reference voltage, and a real-time clock (RTC)
module with a dedicated battery-backup supply. An internal temperature sensor allows software to monitor device
temperature and optionally interrupt to alert when a temperature conversion is complete. The MAXQ3100 is
uniquely suited for single-phase electricity metering applications that require an external analog front-end, but can
be used in any application that requires high-performance operation. The device operates at a fixed
4.194MHz, generated from the 32.76kHz RTC crystal. The
device has 8kWords of EEPROM, 512 words of RAM,
three 16-bit timers, and two universal synchronous/asynchronous receiver/transmitters (USARTs). The microcontroller core and I/O are powered by a single 3.3V supply,
and an additional battery supply keeps the RTC running
during power outages.
Applications
Utility Meters
Home Appliances
Battery-Powered and
Portable Devices
Consumer Electronics
Electrochemical and
Optical Sensors
Industrial Control
Data-Acquisition
Systems and Data
Loggers
Thermostats/Humidity
Sensors
Security Sensors
Gas and Chemical
Sensors
HVAC
Smart Transmitters
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAXQ3100-EMN+
-40°C to +85°C
80 MQFP
+Denotes a Pb-free/RoHS-compliant device.
Features
♦ High-Performance, Low-Power, 16-Bit RISC Core
4.194MHz Operation, Approaching 1MIPS
per MHz
3.3V Core and I/O
33 Instructions, Most Single-Cycle
Three Independent Data Pointers Accelerate
Data Movement with Automatic Increment/
Decrement
16-Level Hardware Stack
16-Bit Instruction Word, 16-Bit Data Bus
16 x 16-Bit, General-Purpose Working Registers
Optimized for C-Compiler (High-Speed/Density
Code)
♦ Program and Data Memory
8kWords EEPROM
200,000 EEPROM Write/Erase Cycles
512 Words of Internal Data RAM
JTAG-Compatible Debug Port Bootloader for
Programming
♦ Peripheral Features
Up to 27 General-Purpose I/O Pins, Most 5V
Tolerant
160-Segment LCD Driver
Up to 4 COM and 40 Segments
Static, 1/2, and 1/3 LCD Bias Supported
No External Resistors Required
Two Analog Comparators with Internal +1.25V
Precision Reference
Two Serial USARTs, One with Infrared PWM
Support
Digital Temperature Sensor
Three 16-Bit Programmable Timers/Counters
8-Bit, Subsecond, System Timer/Alarm
Battery-Backed, 32-Bit RTC with
Time-of-Day Alarm and Digital Trim
Programmable Watchdog Timer
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
♦ Flexible Programming Interface
Bootloader Simplifies Programming
In-System Programming Through Debug Port
Supports In-Application Programming of EEPROM
Note: Some revisions of this device may incorporate deviations
from published specifications known as errata. Multiple revisions of any device may be simultaneously available through
various sales channels. For information about device errata, go
to: www.maxim-ic.com/errata.
♦ Power Consumption
1.9mA at 4.194MHz, 3.6V Operation
1.9µA Standby Current in Sleep Mode
Low-Power Divide-by-256 Mode
Typical Application Circuits and Pin Configuration appear
at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAXQ3100
General Description
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
ABSOLUTE MAXIMUM RATINGS
Voltage Range on DVDD Relative to DGND ..........-0.5V to +6.0V
Voltage Range on Any Pin Relative to DGND
(3V Tolerant) .........................................-0.5V to (DVDD + 0.5V)
Continuous Output Current
(Any Single I/O Pin)..........................................................25mA
(All I/O Pins Combined) ...................................................25mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature .......................................See IPC/JEDEC
J-STD-020 Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DVDD = VRST to 3.6V, f32KIN = 32.768kHz, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
MIN
TYP
MAX
UNITS
Digital Supply Voltage
PARAMETER
SYMBOL
DVDD
VRST
3.3
3.6
V
Digital Power-Fail Reset
VRST
2.34
2.5
2.71
V
Battery Supply Voltage
VBAT
2.0
3.8
V
Active Current
(Note 2)
CONDITIONS
IDD1
/1 mode
1.9
2.6
IDD2
/2 mode
1.3
1.8
IDD3
/4 mode
1.0
1.4
IDD4
/8 mode
0.8
1.2
IDD5
PMM1 mode
0.7
1.0
Brownout detector disabled
(Note 3), TA = +25°C
1.9
5.0
Brownout detector disabled
(Note 3), TA = +60°C
2.1
10.0
Brownout detector disabled
(Note 3), TA = +85°C
3.3
35.0
I STOP2
Brownout detector enabled (Note 3)
16.3
63.0
I STOP3
Brownout detector enabled, RTC enabled
(Note 3)
16.4
64.0
I STOP1
Stop-Mode Current
mA
μA
ANALOG VOLTAGE COMPARATOR
Comparator Input-Voltage Range
VINPUT
GND
Internal Voltage Reference
VREF
1.15
Input Offset Voltage
VOS
(Note 4)
VCMR
CMMR
Input Common-Mode Voltage
Common-Mode Rejection Ratio
DC Input-Leakage Current
DVDD
V
1.35
V
-10
+10
mV
(Note 4)
1
DVDD
V
(Note 4)
55
TA = +25°C, CMPx pin in tri-state mode
-50
Comparator Setup Time
tCMP_SETUP f SYS = 4.194MHz, V = 20mV (Note 4)
Response Time (CMPx Change
to CMO Valid)
tCMP_RESP
Current Consumed By
Comparator
2
IDD_CMP
f SYS = 4.194MHz, transition CMPx from
DGND to DVDD in ~2ns, tSYS = 1/f SYS
(Note 4)
Per enabled comparator, CMONx = 1,
brownout detector enabled, CMPx pins in
tri-state mode
1.25
dB
+50
nA
0.8
1.6
μs
140 +
(2 x
t SYS)
600 +
(2 x
t SYS)
ns
18.0
39.0
μA
_______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
MAXQ3100
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = VRST to 3.6V, f32KIN = 32.768kHz, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL I/O
Input High Voltage (Port 0, 1, 3,
RESET)
VIH1
0.8 x
DVDD
5.5
V
Input High Voltage (Port 2)
VIH2
0.8 x
DVDD
DVDD
+ 0.3
V
Input Low Voltage
VIL
0.2 x
DVDD
V
Output High Voltage (All Ports)
VOH
I SOURCE = 3mA
DVDD
V
Output Low Voltage (All Ports,
RESET)
VOL
I SINK = 4mA
0.4
V
250
μA
+50
nA
Input Pullup Current
I PULLUP
Input Leakage (All Ports)
IL
DVDD 0.4
DVDD = 3.6V, input mode with weak pullup
enabled
40
Input mode with weak pullup disabled
-50
120
TEMPERATURE SENSOR
Temperature Conversion Time
TCONV
10-bit resolution, f SYS = 4.194MHz
12.5
11-bit resolution, f SYS = 4.194MHz
12-bit resolution, f SYS = 4.194MHz
25
13-bit resolution, f SYS = 4.194MHz
100
ms
50
Temperature Sensor Accuracy
±2
°C
RTC
Battery Supply Current, BatteryBacked Mode
IBAT
Measured on VBAT pin, VBAT = 3.6V,
DVDD = 0V, RTC enabled
1.76
3.1
μA
Battery Supply Leakage Current
IBATL
Measured on VBAT pin, VBAT = 3.6V,
DVDD = 3.6V, RTC enabled
4
200
nA
Trimming Resolution
One 32.768kHz clock per 10s (Note 4)
3.05
ppm
LCD
LCD Supply Voltage
VLCD
LCD Bias Voltage 1
VLCD1
(Note 4)
VADJ + 2/3
(VLCD - VADJ)
V
LCD Bias Voltage 2
VLCD2
(Note 4)
VADJ + 1/3
(VLCD - VADJ)
V
LCD Adjustment Voltage
VADJ
(Note 4)
LCD Digital Operating Current
ILCD
Measured on DVDD pin; LCFG = 0xF7,
LCRA = 0x1B20, LCDx = 0xFF; LCD pins
are unconnected
0.1
40
k
LRA3:LRA0 = 1111
80
k
LCD Bias Resistor
RLCD
LCD Adjust Resistor
RLADJ
2.4
DVDD
0.4 x
VLCD
0
V
V
μA
_______________________________________________________________________________________
3
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = VRST to 3.6V, f32KIN = 32.768kHz, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
LCD Segment Voltage
SYMBOL
VSEGxx
CONDITIONS
MIN
TYP
MAX
Segment is driven at VLCD; VLCD = 3V,
I SEGxx = -3μA, guaranteed by design
VLCD 0.06
VLCD
Segment is driven at VLCD1; VLCD1 = 2V,
I SEGxx = -3μA, guaranteed by design
VLCD1 0.04
VLCD1
Segment is driven at VLCD2; VLCD2 = 1V,
I SEGxx = -3μA, guaranteed by design
VLCD2 0.02
VLCD2
Segment is driven at VADJ; VADJ = 0V,
I SEGxx = +3μA, guaranteed by design
VADJ
0.1
UNITS
V
CLOCK SOURCES
External Crystal Frequency
f32KIN
32.768
4.194
kHz
Internal Clock Frequency
fCLK
f32KIN = 32.768kHz, DVDD = 3.6V
4.110
4.278
System Clock Frequency
f SYS
f SYS = fCLK / system clock divisor
fCLK /
256
fCLK
fTCK
JTAG programming (Note 4)
0
f SYS / 8
MHz
JTAG-COMPATIBLE PROGRAMMING
TCK Frequency
MHz
MEMORY CHARACTERISTICS
EEPROM Write/Erase Cycles
EEPROM Data Retention
Note 1:
Note 2:
Note 3:
Note 4:
4
Theta-JA = +25°C
200,000
Theta-JA = +85°C
50,000
Theta-JA = +85°C
50
Cycles
Years
Specifications to -40°C are guaranteed by design and are not production tested.
Measured on the DVDD pin with DVDD = 3.6V, VBAT = 3.8V, f32KIN = 32.768kHz, executing from EEPROM.
Measured on the DVDD pin with DVDD = 3.6V, VBAT = 3.8V, f32KIN = 32.768kHz, all I/O pins disconnected, and not in reset.
Specification guaranteed by design but not production tested.
_______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
PIN
NAME
FUNCTION
1, 11, 52,
58, 75
DGND
Digital Ground
6, 53, 59,
76
DVDD
Digital Supply Voltage (+3.3V)
General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable Interrupt. These port
pins function as bidirectional I/O pins only. All port pins default to input mode with weak
pullups enabled after a reset. All port pins can be configured as external interrupt inputs. All
alternate functions must be enabled from software.
PIN
2–5, 77–80
P0.0–P0.7;
INT0–INT7;
TXD0, RXD0,
T0G, T0, T1, EX
SPECIAL/ALTERNATE FUNCTION
NAME
NAME
FUNCTION
77
P0.0
INT0
TXD0
Serial Port 0 Transmit
78
P0.1
INT1
RXD0
Serial Port 0 Receive
79
P0.2
INT2
T0G
80
P0.3
INT3
T0
Timer 0 Input
2
P0.4
INT4
T1
Timer 1 Input/Output
3
P0.5
INT5
T1EX
4
P0.6
INT6
—
—
5
P0.7
INT7
—
—
7–10
COM0–COM3
Dedicated LCD Common-Voltage Outputs
12–43
SEG1–SEG31
Dedicated LCD Drive Outputs
Timer 0 Gate Input
Timer 1 External Capture/Reload Input
General-Purpose, Digital, I/O, Type C Port; LCD Segment-Driver Output. These port pins
function as bidirectional I/O pins and LCD segment-driver outputs. All alternate functions
must be enabled from software.
44–51
P2.0–P2.7;
SEG32–SEG39
SPECIAL/ALTERNATE FUNCTION
PIN
NAME
44
P2.0
SEG32
LCD Segment 32
45
P2.1
SEG33
LCD Segment 33
46
P2.2
SEG34
LCD Segment 34
47
P2.3
SEG35
LCD Segment 35
48
P2.4
SEG36
LCD Segment 36
49
P2.5
SEG37
LCD Segment 37
50
P2.6
SEG38
LCD Segment 38
51
P2.7
SEG39
LCD Segment 39
NAME
FUNCTION
54
VLCD
LCD Bias-Control Voltage. Highest LCD drive voltage used in all bias modes. This pin
must be connected to an external supply when using the LCD display controller.
55
VLCD1
LCD Bias, Voltage 1. Next highest LCD drive voltage, used in 1/2 and 1/3 LCD bias modes.
An internal resistor-divider sets the voltage at this pin. External resistors and capacitors
can be used to change LCD voltage or drive capability at this pin. This pin must be shunted
externally to VLCD2 when using 1/2 bias mode.
_______________________________________________________________________________________
5
MAXQ3100
Pin Description
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
MAXQ3100
Pin Description (continued)
PIN
NAME
FUNCTION
56
VLCD2
LCD Bias, Voltage 2. Third highest LCD drive voltage, used in 1/3 LCD bias mode only. An
internal resistor-divider sets the voltage at this pin. External resistors and capacitors can be
used to change LCD voltage or drive capability at this pin. This pin must be shunted
externally to VLCD1 when using 1/2 bias mode.
57
VADJ
LCD Adjustment Voltage. Lowest LCD drive voltage, used in all bias modes. Connect to
DGND through an external resistor to provide external control of the LCD contrast. Leave
disconnected for internal contrast adjustment.
General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable Interrupt. These port
pins function as bidirectional I/O pins only. All port pins default to input mode with weak
pullups enabled after a reset. Port pins P1.0–P1.3 can be configured as external interrupt
inputs. All alternate functions must be enabled from software.
60–63
P1.0–P1.3;
INT8–INT11;
T2B, T2A, TXD1,
RXD1
PIN
SPECIAL/ALTERNATE FUNCTION
NAME
NAME
FUNCTION
60
P1.0
INT8
T2B
Timer 2 Secondary I/O
61
P1.1
INT9
T2A
Timer 2 Primary I/O
62
P1.2
INT10
TXD1
Serial Port 1 Transmit
63
P1.3
INT11
RXD1
Serial Port 1 Receive
General-Purpose, Digital, I/O, Type C Port; External Edge-Selectable Interrupt. These port
pins function as bidirectional I/O pins only. All port pins default to input mode with weak
pullups enabled after a reset. All alternate functions must be enabled from software, except
for the JTAG-compatible functions that are enabled by default following reset.
PIN
64–70
6
P3.0–P3.6;
TDI, TDO, TCK,
TMS, SWQ,
CMP0, CMP1
71
RESET
72
VBAT
73
32KIN
74
32KOUT
NAME
SPECIAL/ALTERNATE FUNCTION
NAME
FUNCTION
64
P3.0
TDI
65
P3.1
TDO
JTAG TAP Data Input
JTAG TAP Data Output
66
P3.2
TCK
JTAG TAP Clock Input
67
P3.3
TMS
JTAG TAP Mode-Select Input
68
P3.4
SQW
RTC Square-Wave Output
69
P3.5
CMP0
Analog Comparator Input 0
70
P3.6
CMP1
Analog Comarator Input 1
Active-Low, Digital Reset Input/Output. The CPU is held in reset when this pin is low and
begins executing from the reset vector when released. The pin must be pulled high by an
external 50k resistor. This pin is driven low as an output when an internal reset condition
occurs.
Digital Battery-Backup Supply. This supply provides an optional battery backup for the
RTC when DVDD power is removed. If this pin is connected to a nominal 3.3V battery then
the RTC will operate and battery-backed register contents will be preserved when DVDD is
removed. If battery backup is not required this pin should be connected directly to DVDD.
32kHz Crystal Input/Output. Connect an external, 6pF 32kHz watch crystal between 32KIN
and 32KOUT to generate the system clock.
_______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
TIMER 0-TYPE
16-BIT TIMER/COUNTER
ANALOG COMPARATOR
+1.25V
REFERENCE
8kW EEPROM
(PROGRAM)
TIMER 1-TYPE
16-BIT TIMER/COUNTER
512W SRAM
(DATA)
TIMER 2-TYPE
16-BIT TIMER/COUNTER
2kW UTILITY ROM
ANALOG COMPARATOR
SERIAL USART
160-SEGMENT LCD
DRIVER
MAXQ3100
SERIAL USART WITH
INFRARED PWM
SUPPORT
MAXQ20 RISC CORE
(16 x 16-BIT ACCUMULATORS)
REAL-TIME CLOCK
WATCHDOG TIMER
DIGITAL TEMPERATURE
SENSOR
EXTERNAL 32.768kHz
CRYSTAL
POWER REDUCTION/
CLOCK GENERATION
3.3V
POR
Detailed Description
The following is an introduction to the primary features
of the microcontroller. More detailed descriptions of the
device features can be found in the data sheets, errata
sheets, and user’s guides described later in the
Additional Documentation section.
MAXQ Core Architecture
The MAXQ3100 is a high-performance, CMOS, 16-bit
RISC microcontroller with EEPROM and an integrated
160-segment LCD controller. It is structured on a highly
advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in
one cycle without pipelining, because the instruction
JTAG
TMS
TDI
TDO
TCK
contains both the op code and data. The result is a
streamlined 4.194 million instructions-per-second
(MIPS) microcontroller.
The highly efficient core is supported by a 16-level
hardware stack, enabling fast subroutine calling and
task switching. Data can be quickly and efficiently
manipulated with three internal data pointers. Multiple
data pointers allow more than one function to access
data memory without having to save and restore data
pointers each time. The data pointers can automatically
increment or decrement following an operation, eliminating the need for software intervention. As a result,
the application speed is greatly increased.
_______________________________________________________________________________________
7
MAXQ3100
Functional Diagram
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special-function registers
control the peripherals and are subdivided into register
modules. The family architecture is modular, so that
new devices and modules can reuse code developed
for existing products.
The architecture is transport-triggered. This means that
writes or reads from certain register locations can also
cause side effects to occur. These side effects form the
basis for the higher-level op codes defined by the
assembler, such as ADDC, OR, JUMP, etc. The op
codes are actually implemented as MOVE instructions
between certain system register locations, while the
assembler handles the encoding, which need not be a
concern to the programmer.
The 16-bit instruction word is designed for efficient execution. Bit 15 indicates the format for the source field of
the instruction. Bits 0 to 7 of the instruction represent the
source for the transfer. Depending on the value of the
format field, this can either be an immediate value or a
source register. If this field represents a register, the
lower four bits contain the module specifier and the
upper four bits contain the register index in that module.
Bits 8 to 14 represent the destination for the transfer. This
value always represents a destination register, with the
lower four bits containing the module specifier and the
upper three bits containing the register subindex within
that module.
Anytime that it is necessary to directly select one of the
upper 24 index locations in a destination module, the
prefix register PFX is needed to supply the extra destination bits. This prefix register write is inserted automatically by the assembler and requires only one
additional execution cycle.
data memory. The configuration of program and data
space depends on the current execution location.
• When executing code from EEPROM memory, the
SRAM and utility ROM are accessible in data space.
• When executing code from SRAM, the EEPROM and
utility ROM are accessible in data space.
• When executing code from the utility ROM, the
EEPROM memory and SRAM are accessible in data
space.
Refer to the MAXQ Family User’s Guide: MAXQ3100
Supplement for more details.
In all cases, whichever memory segment is currently
being executed from cannot be accessed in data space.
To allow the use of lookup tables and similar constructs
in the memory, the utility ROM contains a set of lookup
and block copy routines (refer to the user’s guide supplement for more details).
The incorporation of EEPROM allows the device to be
reprogrammed, eliminating the expense of throwing
away one-time programmable devices during development and field upgrades. Program memory can be
password protected with a 16-word key, denying
access to program memory by unauthorized individuals.
Stack Memory
A 16-bit-wide internal stack provides storage for program return addresses and general-purpose use. The
stack is used automatically by the processor when the
CALL, RET, and RETI instructions are executed and
interrupts serviced. The stack can also be used explicitly to store and retrieve data by using the PUSH, POP,
and POPI instructions.
On reset, the stack pointer, SP, initializes to the top of
the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the
stack location pointed to by SP. The RET, RETI, POP,
and POPI operations retrieve the value at the stack
location pointed to by SP, and then decrement SP.
Memory Organization
The device incorporates several memory areas:
• 2kWords utility ROM
• 8kWords of EEPROM for program storage
• 512 words of SRAM for storage of temporary
variables
• 16-level, 16-bit-wide stack memory for storage of
program return addresses and general-purpose use
The memory is arranged by default in a Harvard architecture, with separate address spaces for program and
8
Utility ROM
The utility ROM is a 2kWord block of internal ROM
memory that defaults to a starting address of 8000h.
The utility ROM consists of subroutines that can be
called from application software. These include:
• In-system programming (bootloader) over the JTAGcompatible debug port
• In-circuit debug routines
• User-callable routines for in-application flash programming and code space table lookup
_______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
512 x 16
DATA SRAM
DATA SPACE
(BYTE MODE)
MAXQ3100
PROGRAM
SPACE
DATA SPACE
(WORD MODE)
A1FFh
A000h
87FFh
4k x 8
UTILITY ROM
2k x 16
UTILITY ROM
87FFh
8FFFh
2k x 16
UTILITY ROM
8000h
8000h
8000h
EXECUTING FROM
1FFFh
8k x 16
PROGRAM EEPROM
0000h
1k x 8
DATA SRAM
03FFh
0000h
512 x 16
DATA SRAM
01FFh
0000h
Figure 1. Memory Map When Executing from EEPROM
_______________________________________________________________________________________
9
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Following any reset, execution begins in the utility
ROM. The ROM software determines whether the program execution should immediately jump to the start of
user-application code (located at address 0000h), or to
the bootloader. Routines within the utility ROM are useraccessible and can be called as subroutines by the
application software. More information on the utility
ROM contents is contained in the user’s guide supplement for this device.
Some applications require protection against unauthorized viewing of program code memory. For these
applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied.
A single password-lock (PWL) bit is implemented in the
SC register. When the PWL is set to one (power-on
reset default), the password is required to access the
utility ROM, including in-circuit debug and in-system
programming routines that allow reading or writing of
internal memory. When PWL is cleared to zero, these
utilities are fully accessible without the password. The
password is automatically set to all ones following a
mass erase.
Programming
The microcontroller’s EEPROM can be programmed by
two different methods: in-system programming and inapplication programming. Both methods afford great flexibility in system design as well as reduce the life-cycle
cost of the embedded system. In-system programming
can be password protected to prevent unauthorized
access to code memory.
In-System Programming
An internal bootloader allows the device to be reloaded
over a simple JTAG-compatible debug port. As a result,
system software can be upgraded in-system, eliminating
the need for a costly hardware retrofit when software
updates are required. Remote software uploads are possible that enable physically inaccessible applications to
be frequently updated. The interface hardware can be a
JTAG connection to another microcontroller, or a connection to a PC serial port using a serial-to-JTAG converter such as the one included in the MAXQ3100
evaluation kit. If in-system programmability is not
required, a commercial gang programmer can be used
for mass programming.
10
Activating the debug port and loading the test access
port (TAP) with the system programming instruction
invokes the bootloader. Setting the SPE bit to 1 during
reset through the debug port executes the bootloadermode program that resides in the utility ROM. When programming is complete, the bootloader can clear the
SPE bit and reset the device, allowing the device to
bypass the utility ROM and begin execution of the application software.
The following bootloader functions are supported:
•
•
•
•
•
Load
Dump
CRC
Verify
Erase
In-Application Programming
The in-application programming feature allows the
microcontroller to modify its own program memory from
its application software. This allows on-the-fly software
updates in mission-critical applications that cannot
afford downtime. Alternatively, it allows the application
to develop custom loader software that can operate
under the control of the application software. The utility
ROM contains user-accessible programming functions
that erase and program memory. These functions are
described in detail in the user’s guide supplement for
this device.
Register Set
Most functions of the device are controlled by sets of
registers. These registers provide a working space for
memory operations as well as configuring and addressing peripheral registers on the device. Registers are
divided into two major types: system registers and
peripheral registers. The common register set, also
known as the system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and
control, and stack pointer. The peripheral registers
define additional functionality that may be included by
different products based on the MAXQ architecture.
This functionality is broken up into discrete modules so
that only the features required for a given product need
to be included. Tables 1 and 4 show the MAXQ3100
register set.
______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
MAXQ3100
Table 1. System Register Map
MODULE NAME (BASE SPECIFIER)
REGISTER
INDEX
AP
(8h)
A
(9h)
PFX
(Bh)
IP
(Ch)
SP
(Dh)
DPC
(Eh)
DP
(Fh)
0h
AP
A[0]
PFX
IP
—
—
—
1h
APC
A[1]
—
—
SP
—
—
2h
—
A[2]
—
—
IV
—
—
3h
—
A[3]
—
—
—
Offs
DP[0]
4h
PSF
A[4]
—
—
—
DPC
—
5h
IC
A[5]
—
—
—
GR
—
6h
IMR
A[6]
—
—
LC[0]
GRL
—
7h
—
A[7]
—
—
LC[1]
BP
DP[1]
8h
SC
A[8]
—
—
—
GRS
—
9h
—
A[9]
—
—
—
GRH
—
Ah
—
A[10]
—
—
—
GRXL
—
Bh
IIR
A[11]
—
—
—
BP[offs]
—
Ch
—
A[12]
—
—
—
—
—
Dh
—
A[13]
—
—
—
—
—
Eh
CKCN
A[14]
—
—
—
—
—
Fh
WDCN
A[15]
—
—
—
—
—
Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register
is 16 bits wide. Registers in module AP are bit addressable.
______________________________________________________________________________________
11
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Table 2. System Register Bit Functions
REGISTER
REGISTER BIT
15
14
13
12
11
10
9
8
7
6
5
4
AP
—
—
—
—
APC
CLR
IDS
—
—
—
MOD2
2
1
0
AP (4 bits)
MOD1
MOD0
PSF
Z
S
—
GPF1
GPF0
OV
C
E
IC
—
—
CGDS
—
—
—
INS
IGE
IM0
IMR
IMS
—
—
—
IM3
—
IM1
SC
TAP
—
—
—
—
—
PWL
—
IIR
IIS
—
—
—
II3
—
II1
II0
CKCN
—
—
—
STOP
SWB
PMME
CD1
CD0
WDCN
POR
EWDI
WD1
WD0
WDIF
WTRF
EWT
RWT
A[0..15]
A[n] (16 bits)
PFX
PFX (16 bits)
—
—
—
—
—
WBS2
WBS1
WBS0
GR.6
GR.5
GR.4
GR.3
GR.2
GR.1
GR.0
GR.8
IP
SP
IP (16 bits)
—
—
—
—
—
—
—
—
—
IV
IV (16 bits)
LC[0]
LC[0] (16 bits)
LC[1]
LC[1] (16 bits)
Offs
DPC
—
—
—
—
—
—
—
—
GR.7
BP
BP (16 bits)
GR.7 GR.6
GR.5
GR.4
GR.3
GR.2 GR.1 GR.0
GRH
GRXL
SDPS1 SDPS0
GR (16 bits)
GRL
GRS
SP (4 bits)
Offs (8 bits)
—
GR
12
3
GR.7 GR.7
GR.7
GR.7
GR.7
GR.7 GR.7 GR.7
GR.15 GR.14
GR.13 GR.12 GR.11 GR.10
GR.9
GR.15 GR.14
GR.13 GR.12 GR.11 GR.10
GR.9
GR.8
GR.7
GR.5
GR.1
GR.0
GR.6
BP[offs]
BP[offs] (16 bits)
DP[0]
DP[0] (16 bits)
DP[1]
DP[1] (16 bits)
GR.4
GR.3
GR.2
______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
REGISTER
REGISTER BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AP
0
0
0
0
0
0
0
0
APC
0
0
0
0
0
0
0
0
PSF
1
0
0
0
0
0
0
0
IC
0
0
0
0
0
0
0
0
IMR
0
0
0
0
0
0
0
0
SC
1
0
0
0
0
0
s
0
IIR
0
0
0
0
0
0
0
0
CKCN
1
0
0
0
0
0
0
0
s
s
0
0
0
s
s
0
A[0..15]
WDCN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PFX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IP
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SP
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
IV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LC[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LC[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Offs
DPC
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
GR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRL
BP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRH
GRXL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BP[offs]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: Bits marked with an “s” have special behavior upon reset. Refer to the user’s guide supplement for this device for more
details.
______________________________________________________________________________________
13
MAXQ3100
Table 3. System Register Reset Values
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Table 4. Peripheral Register Map
REGISTER INDEX
M0
(0h)
M1
(1h)
M2
(2h)
M3
(3h)
0h
PO0
PO1
PO2
PO3
1h
SCON0
SCON1
LCFG
RTRM
2h
SBUF0
SBUF1
LCRA
RCNT
3h
T0CN
T2CNB
LCD0
CCN0
CCN1
4h
T0L
T2H
LCD1
5h
T1CN
T2RH
LCD2
—
6h
T1MD
T2CH
LCD3
TEMPR
7h
EIF0
EIF1
LCD4
TPCFG
8h
PI0
PI1
PI2
PI3
9h
SMD0
SMD1
LCD5
RTSS
Ah
PR0
PR1
LCD6
RTSH
Bh
T0H
T2CNA
LCD7
RTSL
Ch
T1L
T2CFG
LCD8
RSSA
Dh
T1H
T2V
LCD9
RASH
Eh
T1CL
T2C
LCD10
RASL
Fh
T1CH
IRCN
LCD11
PWCN
10h
PD0
—
PD1
PD2
PD3
11h
T2R
LCD12
—
12h
—
—
LCD13
—
13h
—
—
LCD14
—
14h
—
—
LCD15
—
15h
—
—
LCD16
—
16h
—
—
LCD17
—
17h
—
—
LCD18
—
18h
—
—
LCD19
—
19h
—
—
—
—
1Ah
—
—
—
—
1Bh
—
—
—
—
1Ch
—
—
—
—
1Dh
—
—
—
—
1Eh
EIE0
EIE1
—
—
1Fh
EIES0
EIES1
—
—
Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register
is 16 bits wide.
14
______________________________________________________________________________________
______________________________________________________________________________________
11
10
7
IE7
PI0.7
EIR
PR0.7
EIF0
PI0
SMD0
PR0
—
—
—
PR1.7
PI1
SMD1
PR1
SBUF1.7
SBUF1
EIF1
SM0/FE
SCON1
T2C.15
—
PO1
T2CH
IT7
EIES0
T2R.15
EX7
T2RH
PD0.7
PD0
EIE0
ET2L
PD0.6
T1CL.7
T1CL
T2V.15
T1CL.6
T1H.7
T1H
4
REN
PO0.4
SM2
—
IT5
EX5
PD0.5
T1CL.5
T1H.5
T1L.5
REN
—
IT4
EX4
PD0.4
T1CL.4
T1H.4
T1L.4
T0H.4
PR0.4
—
PI0.4
IE4
—
DCEN
T0L.4
TR0
—
PR1.5
—
—
—
T2C.13
T2R.13
T2V.13
T2POL1
PR1.6
—
—
T2C.14
T2R.14
T2V.14
T2OE1
PR1.4
—
—
—
T2C.12
T2R.12
T2V.12
—
SBUF1.6 SBUF1.5 SBUF1.4
SM1
—
IT6
EX6
T1H.6
T1L.6
T1L.7
T1L
T0H.5
T0H.6
—
PI0.5
IE5
—
T1OE
T0L.5
TF0
PR0.5
T0H.7
T2H
SM2
PR0.6
OFS
—
EXF1
T0L.6
T0H
PR1.8
—
T1MD
PR1.9
PI0.6
TF1
T1CN
PR1.15 PR1.14 PR1.13 PR1.12 PR1.11 PR1.10
IE6
T0L.7
T0L
T0M
ET0
T2CNB
5
PO0.5
SBUF0.6 SBUF0.5 SBUF0.4
SM1
PO0.6
6
REGISTER BIT
SBUF0.7
PR0.8
8
T0CN
PR0.9
9
SBUF0
PR0.15 PR0.14 PR0.13 PR0.12 PR0.11 PR0.10
12
SM0/FE
13
SCON0
14
PO0.7
15
PO0
REGISTER
3
PR1.3
—
PI1.3
IE11
T2C.11
T2R.11
T2V.11
TF2
SBUF1.3
TB8
PO1.3
IT3
EX3
PD0.3
T1CL.3
T1H.3
T1L.3
T0H.3
PR0.3
—
PI0.3
IE3
—
EXEN1
T0L.3
GATE
SBUF0.3
TB8
PO0.3
2
1
TI
PO0.1
0
RI
PO0.0
TI
PO1.1
IT1
EX1
PD0.1
T1CL.1
T1H.1
T1L.1
T0H.1
PR0.1
SMOD
PI0.1
IE1
ET1
C/T1
T0L.1
M1
RI
PO1.0
IT0
EX0
PD0.0
T1CL.0
T1H.0
T1L.0
T0H.0
PR0.0
FEDE
PI0.0
IE0
T1M
CP/RL1
T0L.0
M0
PR1.2
ESI
PI1.2
IE10
T2C.10
T2R.10
T2V.10
TF2L
PR1.1
SMOD
PI1.1
IE9
T2C.9
T2R.9
T2V.9
TCC2
PR1.0
FEDE
PI1.0
IE8
T2C.8
T2R.8
T2V.8
TC2L
SBUF1.2 SBUF1.1 SBUF1.0
RB8
PO1.2
IT2
EX2
PD0.2
T1CL.2
T1H.2
T1L.2
T0H.2
PR0.2
ESI
PI0.2
IE2
—
TR1
T0L.2
C/T
SBUF0.2 SBUF0.1 SBUF0.0
RB8
PO0.2
MAXQ3100
Table 5. Peripheral Register Bit Functions
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
15
16
LCD6.7
LCD7.7
LCD8.7
LCD9.7
LCD10.7 LCD10.6 LCD10.5 LCD10.4
LCD11.7 LCD11.6 LCD11.5 LCD11.4
LCD6
LCD7
LCD8
LCD9
LCD10
LCD11
______________________________________________________________________________________
LCD12
PD2.6
LCD9.6
LCD8.6
LCD7.6
LCD6.6
LCD5.6
PI2.6
PD2.5
LCD9.5
LCD8.5
LCD7.5
LCD6.5
LCD5.5
PI2.5
LCD4.5
PD2.4
LCD9.4
LCD8.4
LCD7.4
LCD6.4
LCD5.4
PI2.4
LCD4.4
LCD12.7 LCD12.6 LCD12.5 LCD12.4
PD2.7
LCD5.7
LCD5
PD2
PI2.7
PI2
LCD4.6
LCD3.4
LCD2.4
LCD1.4
LCD4.7
LCD3.5
LCD2.5
LCD1.5
LCD4
LCD3.6
LCD2.6
LCD1.6
LCD3.7
—
LCD0.4
LCD2.7
LRIG
LCD0.5
LCD3
—
LCD0.6
LCD2
FRM1
LCD1.7
FRM2
PCF0
PO2.4
—
—
T2R.4
—
—
TCV.4
T2V.4
DIV0
LCD1
FRM3
FRM0
DUTY0
PCF1
PO2.5
PO2.6
PCF2
—
—
—
T2R.5
—
—
TCV.5
T2V.5
DIV1
4
TR2L
LCD0.7
DUTY1
5
T2POL0
LCD0
—
LCRA
—
PCF3
LCFG
—
PO2.7
PO2
T2R.8
—
T2R.9
—
T2R.10
—
T2R.11
EIE1
T2R.12
—
—
T2C.6
EIES1
T2R.13
T2C.7
T2R.6
T2R.14
T2C.9 T2C.8
T2V.6
T2R.7
T2R.15
T2C.10
T2V.7
DIV2
T2OE0
REGISTER BIT
7
6
T2R
T2C.11
T2V.8
8
—
T2C.12
T2V.9
9
—
T2C.13
T2C.14
T2V.10
10
PD1
T2C.15
T2C
T2V.13
T2V.14
T2V.11
11
IRCN
T2V.15
T2V
T2V.12
12
T2CI
13
T2CFG
14
ET2
15
T2CNA
REGISTER
Table 5. Peripheral Register Bit Functions (continued)
3
LCD12.3
PD2.3
LCD11.3
LCD10.3
LCD9.3
LCD8.3
LCD7.3
LCD6.3
LCD5.3
PI2.3
LCD4.3
LCD3.3
LCD2.3
LCD1.3
LCD0.3
LRA3
—
PO2.3
IT11
EX11
T2R.3
PD1.3
—
TCV.3
T2V.3
T2MD
TR2
LCD12.2
PD2.2
LCD11.2
LCD10.2
LCD9.2
LCD8.2
LCD7.2
LCD6.2
LCD5.2
PI2.2
LCD4.2
LCD3.2
LCD2.2
LCD1.2
LCD0.2
LRA2
SMO
PO2.2
IT10
EX10
T2R.2
PD1.2
IREN
TCV.2
T2V.2
CCF1
CPRL2
2
0
LCD9.0
LCD8.0
LCD7.0
LCD6.0
LCD5.0
PI2.0
LCD4.0
LCD3.0
LCD2.0
LCD1.0
LCD0.0
LRA0
DPE
PO2.0
IT8
EX8
T2R.0
PD1.0
IRBB
TCV.0
T2V.0
C/T2
G2EN
PD2.0
LCD12.1 LCD12.0
PD2.1
LCD11.1 LCD11.0
LCD10.1 LCD10.0
LCD9.1
LCD8.1
LCD7.1
LCD6.1
LCD5.1
PI2.1
LCD4.1
LCD3.1
LCD2.1
LCD1.1
LCD0.1
LRA1
OPM
PO2.1
IT9
EX9
T2R.1
PD1.1
IRTX
TCV.1
T2V.1
CCF0
SS2
1
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
______________________________________________________________________________________
WE
—
—
—
—
—
FT
SQE
RASL.
9
RASL.
8
—
RSSA.7
RSTL.7
—
RSSA.6
RTSL.6
RASL
PD3.6
—
RASL.
10
RTSL.
8
RSSA.
8
RTSH.6
PD3
RASL.
11
RTSL.
9
RSSA.
9
RTSH.7
RTSS.6
—
RASL.
12
RTSL.
10
RSSA.
10
RTSH.
8
—
RASL.
13
RTSL.
11
RSSA.
11
RTSH.
9
PWCN
RASL.
14
RTSL.
12
RSSA.
12
RTSH.
10
RASL.6
RASL.
15
RTSL.
13
RSSA.
13
RSTL.
14
RSSA.
14
RTSH.
11
PI3.6
TPIE
RASL.7
RASH
RSSA
RTSL
RTSH
RTSH.
12
RTSS.7
RTSH.
13
RTSS
RTSH.
14
—
PI3
RTSH.
15
RTSL.
15
RSSA.
15
CMIE
CMIE
ALDF
TRM6
CMF
CMF
RDYE
TRM5
PO3.5
4
CMM
CMM
RDY
TRM4
PO3.4
LCD19.4
LCD18.4
LCD17.4
LCD16.4
LCD15.4
LCD14.4
LCD13.4
3
2
—
—
BUSY
TRM3
PO3.3
CMO
CMO
ASE
TRM2
PO3.2
LCD19.3 LCD19.2
LCD18.3 LCD18.2
LCD17.3 LCD17.2
LCD16.3 LCD16.2
LCD15.3 LCD15.2
LCD14.3 LCD14.2
LCD13.3 LCD13.2
1
0
CMPOL
CMPOL
ADE
TRM1
PO3.1
—
—
RTCE
TRM0
PO3.0
LCD19.1 LCD19.0
LCD18.1 LCD18.0
LCD17.1 LCD17.0
LCD16.1 LCD16.0
LCD15.1 LCD15.0
LCD14.1 LCD14.0
LCD13.1 LCD13.0
PD3.5
—
RASL.5
—
RSSA.5
RTSL.5
RTSH.5
RTSS.5
PI3.5
—
PD3.4
—
RASL.4
—
RSSA.4
RTSL.4
RTSH.4
RTSS.4
PI3.4
—
PD3.3
—
RASL.3
RASH.3
RSSA.3
RTSL.3
RTSH.3
RTSS.3
PI3.3
—
PD3.2
—
RASL.2
RASH.2
RSSA.2
RTSL.2
RTSH.2
RTSS.2
PI3.2
RES1
PD3.1
—
RASL.1
RASH.1
RSSA.1
RTSL.1
RTSH.1
RTSS.1
PI3.1
RES0
PD3.0
BOD
RASL.0
RASH.0
RSSA.0
RTSL.0
RTSH.0
RTSS.0
PI3.0
START
TEMPR TEMPR
TEMPR.7 TEMPR.5 TEMPR.5 TEMPR.4 TEMPR.3 TEMPR.2 TEMPR.1 TEMPR.0
.9
.8
TPIF
TEMPR TEMPR TEMPR TEMPR TEMPR TEMPR
.15
.14
.13
.12
.11
.10
TPCFG
TEMPR
CMON
CCN1
ALSF
CMON
CCN0
RCNT
TSGN
RTRM
PO3.6
LCD19.7 LCD19.6 LCD19.5
LCD19
—
LCD18.7 LCD18.6 LCD18.5
LCD18
PO3
LCD17.7 LCD17.6 LCD17.5
5
LCD17
REGISTER BIT
7
6
LCD16.7 LCD16.6 LCD16.5
8
LCD15.7 LCD15.6 LCD15.5
9
LCD16
10
LCD15
11
LCD14.7 LCD14.6 LCD14.5
12
LCD14
13
LCD13.7 LCD13.6 LCD13.5
14
LCD13
15
MAXQ3100
REGISTER
Table 5. Peripheral Register Bit Functions (continued)
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
17
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Table 6. Peripheral Register Bit Reset Values
REGISTER
PO0
SCON0
SBUF0
T0CN
T0L
T1CN
T1MD
EIF0
PI0
SMD0
PR0
T0H
T1L
T1H
T1CL
T1CH
PD0
EIE0
EIES0
PO1
SCON1
SBUF1
T2CNB
T2H
T2RH
T2CH
EIF1
PI1
SMD1
PR1
T2CNA
T2CFG
T2V
T2C
IRCN
PD1
T2R
EIE1
EIES1
PO2
LCFG
REGISTER BIT
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
Note: Bits marked with an “s” have special behavior upon reset. Refer to the user’s guide supplement for this device for more details.
18
______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
REGISTER
LCRA
LCD0
LCD1
LCD2
LCD3
LCD4
PI2
LCD5
LCD6
LCD7
LCD8
LCD9
LCD10
LCD11
PD2
LCD12
LCD13
LCD14
LCD15
LCD16
LCD17
LCD18
LCD19
PO3
RTRM
RCNT
CCN0
CCN1
TEMPR
TPCFG
PI3
RTSS
RTSH
RTSL
RSSA
RASH
RASL
PWCN
PD3
REGISTER BIT
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
0
0
0
0
0
0
0
0
s
s
s
s
s
s
s
s
s
s
0
s
s
0
s
s
0
s
s
0
s
s
0
s
s
0
s
s
0
s
s
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
s
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
s
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
s
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
s
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
s
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
s
0
0
0
s
0
0
s
s
s
0
0
0
0
s
0
s
s
s
s
0
0
0
0
s
0
s
s
s
s
0
0
0
0
s
0
s
s
s
s
0
1
0
0
s
0
s
s
s
s
0
0
0
0
s
0
s
s
s
s
0
0
0
0
s
0
s
s
s
s
0
s
0
0
s
0
s
s
s
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
s
0
Note: Bits marked with an “s” have special behavior upon reset. Refer to the user’s guide supplement for this device for more details.
______________________________________________________________________________________
19
MAXQ3100
Table 6. Peripheral Register Bit Reset Values (continued)
System Timing
The MAXQ3100 generates its internal system clock from
the external 32.768kHz crystal. This serves as the timebase for the RTC and is multiplied internally by a frequency-locked loop (FLL) to provide a system clock of
4.194MHz. Best performance is achieved when mated
with a 32.768kHz crystal rated for a 6pF load. No external load capacitors are required. The frequency accuracy of a crystal-based oscillator circuit is dependent upon
crystal accuracy, the match between the crystal and the
oscillator capacitor load, ambient temperature, etc.
A crystal warmup counter enhances operational reliability. Each time the external crystal oscillation must restart,
including a power-on reset, the device initiates a crystal
warmup period of approximately 2 seconds. This warmup
period allows time for the crystal amplitude and frequency to stabilize before using it as a clock source.
Power Management
Advanced power-management features minimize power
consumption by dynamically matching the processing
speed of the device to the required performance level.
POWER-ON
RESET
This means device operation can be slowed and power
consumption minimized during periods of reduced
activity. When more processing power is required, the
microcontroller can increase its operating frequency.
Software-selectable clock-divide operations allow flexibility, selecting whether a system clock cycle (SYSCLK)
is 1, 2, 4, or 8 of the 4.194MHz oscillator cycles. By performing this function in software, a lower power state
can be entered without the cost of additional hardware.
For extremely power-sensitive applications, two additional low-power modes are available.
• Divide-by-256 power-management mode (PMM1)
(PMME = 1, CD1:0 = 00b)
• Stop mode (STOP = 1)
In PMM1, one system clock is 256 oscillator cycles, significantly reducing power consumption while the microcontroller functions at reduced speed. The optional
switchback feature allows enabled interrupt sources,
such as the external interrupts, to cause the processor to
quickly exit PMM1 mode and return to a faster internal
clock rate.
RWT
RESET DOG
RESET
XDOG
STARTUP
TIMER
STOP
RESET
WATCHDOG
TIMER
XDOG DONE
WATCHDOG RESET
WATCHDOG INTERRUPT
CLK INPUT
MAXQ3100
STOP
32kHz
CRYSTAL
OSCILLATOR
X32RY
POWER-ON
RESET
ENABLE
GLITCH-FREE
MUX
CLOCK
DIVIDER
CLOCK
GENERATION
SYSTEM CLOCK
DIV 1
DIV 2
DIV 4
DIV 8
PWM1
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
INPUT
FREQUENCYLOCKED LOOP
SWB
SWITCHBACK SOURCE
RESET
SELECTOR
FLLRY
DEFAULT
4-CYCLE
DELAY
STOP
ENABLE
WATCHDOG DONE
Figure 2. Clock Sources
20
______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
• An external reset signal is applied to the RESET pin.
• The RTC time-of-day or subsecond alarms are
activated.
The following peripherals can be enabled during stop
mode:
• Analog comparators
• RTC
• LCD controller
Interrupts
Multiple interrupt sources are available for quick
response to internal and external events. The MAXQ
architecture uses a single interrupt vector (IV), single
interrupt-service routine (ISR) design. For maximum
flexibility, interrupts can be enabled globally, individually, or by module. When an interrupt condition occurs,
its individual flag is set, even if the interrupt source is
disabled at the local, module, or global level. Interrupt
flags must be cleared within the user-interrupt routine
to avoid repeated interrupts from the same source.
Application software must ensure a delay between the
write to the flag and the RETI instruction to allow time
for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a
one-instruction delay, and synchronous interrupt flags
require a two-instruction delay.
When an enabled interrupt is detected, software jumps
to a user-programmable interrupt vector location. The
IV register defaults to 0000h on reset or power-up, so if
it is not changed to a different address, the user program must determine whether a jump to 0000h came
from a reset or interrupt source.
Once software control has been transferred to the ISR,
the interrupt identification register (IIR) can determine if
a system register or peripheral register was the source
of the interrupt. The specified module can then be interrogated for the specific interrupt source and software
can take appropriate action. Because the interrupts are
evaluated by user software, the user can define a
unique interrupt priority scheme for each application.
The following interrupt sources are available.
• Watchdog Interrupt
•
•
•
•
•
External Interrupts 0 to 11
Analog Comparator 0 and 1 Interrupts
Temperature Sensor Interrupt
RTC Time-of-Day and Subsecond Alarms
Serial Port 0 Receive and Transmit Interrupts
•
•
•
•
Serial Port 1 Receive and Transmit Interrupts
Timer 0 Overflow Interrupt
Timer 1 Overflow and External Trigger Interrupts
Timer 2 Low Compare, Low Overflow, Capture/
Compare, and Overflow Interrupts
Reset Sources
Several reset sources are provided for microcontroller
control. Although code execution is halted in the reset
state, the high-frequency oscillator continues to oscillate.
Power-On Reset/Brownout Reset
An internal power-on reset circuit enhances system reliability. This circuit forces the device to perform a
power-on reset whenever a rising voltage on DV DD
climbs above approximately V RST. Additionally, the
device performs a brownout reset whenever DV DD
drops below VRST, a feature that can be optionally disabled in stop mode. The following events occur during
a power-on reset:
• All registers and circuits enter their power-on reset
state.
• I/O pins revert to their reset state, with logic one
states tracking DVDD.
• The power-on reset flag is set to indicate the source
of the reset.
• Code execution begins at location 8000h following a
2-second 32.768kHz warmup.
Watchdog Timer Reset
The watchdog timer functions are described in the
MAXQ Family User’s Guide. Software can determine if
a reset was caused by a watchdog timeout by checking the watchdog timer reset flag (WTRF) in the WDCN
register. Execution resumes at location 8000h following
a watchdog timer reset.
External System Reset
Asserting the external RESET pin low causes the
device to enter the reset state. The external reset functions as described in the MAXQ Family User’s Guide.
Execution resumes at location 8000h after the RESET
pin is released.
______________________________________________________________________________________
21
MAXQ3100
Power consumption reaches its minimum in stop mode.
In this mode, the system clock and all code execution
is halted. Upon receiving one of the following enabled
events, the device executes a 250ms warmup delay
and then begins normal operation from the point in the
code following the setting of the STOP bit:
• An enabled external interrupt pin is triggered.
• An enabled comparator interrupt is triggered.
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
I/O Ports
The microcontroller uses the Type C and Type D bidirectional I/O ports described in the MAXQ Family
User’s Guide. The use of two port types allows for maximum flexibility when interfacing to external peripherals.
Each port has independent, general-purpose I/O pins
and three configure/control registers. Many pins support alternate functions such as timers or interrupts,
which are enabled, controlled, and monitored by dedicated peripheral registers. Using the alternate function
automatically converts the pin to that function.
Type C port pins have Schmitt Trigger receivers and
full CMOS output drivers, and can support alternate
functions. The pin is either tri-stated or a weak pullup
when defined as an input, dependent on the state of
the corresponding bit in the output register.
Type D port pins have Schmitt Trigger receivers and
full CMOS output drivers, and can support alternate
functions. The pin is either tri-stated or a weak pullup
when defined as an input, dependent on the state of
the corresponding bit in the output register. All Type D
pins also have interrupt capability.
DVDD
WEAK
MUX
PD.x
SF DIRECTION
DVDD
SF ENABLE
MUX
PO.x
SF OUTPUT
MAXQ3100
I/O PAD
PORT PIN
PI.x OR SF INPUT
FLAG
INTERRUPT
FLAG
DETECT
CIRCUIT
EIES.x
TYPE D PORT ONLY
Figure 3. Type C/D Port Pin Schematic
22
______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
A binary real-time clock keeps the time of day in
absolute seconds with 1/256-second resolution. The
32-bit second counter can count up to approximately
136 years and be translated to calendar format by the
application software. A time-of-day alarm and independent subsecond alarm can cause an interrupt or wake
the device from stop mode.
The independent subsecond alarm runs from the same
RTC, and allows the application to perform periodic
interrupts up to 8 seconds with a granularity of approximately 3.9ms. This creates an additional timer that can
be used to measure long periods without performance
degradations. Traditionally, long time periods have
been measured using multiple interrupts from shorter
programmable timers. Each timer interrupt required
servicing, with each accompanying interruption slowing
system operation. By using the RTC subsecond timer
as a long-period timer, only one interrupt is needed,
eliminating the performance hit associated with using a
shorter timer.
Higher accuracy can be obtained by using the useraccessible digital RTC trim function. This feature allows
the designer to fine tune the RTC timing to compensate
for crystal inaccuracies and any unintended boardlevel effects that could cause crystal-frequency drift.
The user can enable a 1Hz or 512Hz square-wave output on P3.4. Frequency measurements of these signals
can show if there is any deviation from the expected
frequency, and writes to the RTC trim register can compensate in increments of 1 to 127 steps, with each step
approximately 3.05ppm (30.5µs).
If the VBAT pin is not directly tied to the DVDD pin, then
there may be a short increase in IDD while the device is
switching between VBAT and DVDD as the RTC power
source. IDD can temporarily increase up to 300µA while
DVDD is rising and in the range 1.05 x VBAT < DVDD <
[(1.05 x V BAT ) + 200mV]. A similar effect may be
observed while VBAT is falling and in the range [(0.95 x
DVDD) - 200mV] < VBAT < 0.95 x DVDD.
Programmable Timers
The MAXQ3100 incorporates one instance each of the
timer 0, timer 1, and timer 2 peripherals. These timers
can be used in counter/timer/capture/compare/PWM
functions, allowing precise control of internal and external events. Timer 2 supports optional single-shot, external gating, and polarity control options as well as
carrier generation support for infrared transmit/receive
functions using serial port 0.
Timer 0
The timer 0 peripheral includes the following:
• 8-bit autoreload timer/counter
• 13-bit or 16-bit timer/counter
• Dual 8-bit timer/counter
• External pulse counter
Timer 1
The timer 1 peripheral includes the following:
• 16-bit autoreload timer/counter
• 16-bit capture
• 16-bit counter
• Clock generation output
Timer 2
The timer 2 peripheral includes the following:
• 16-bit autoreload timer/counter
• 16-bit capture
• 16-bit counter
• 8-bit capture and 8-bit timer
• 8-bit counter and 8-bit timer
• Infrared carrier generation support
Watchdog Timer
An internal watchdog timer greatly increases system
reliability. The timer resets the processor if software
execution is disturbed. The watchdog timer is a freerunning counter designed to be periodically reset by
the application software. If software is operating correctly, the counter is periodically reset and never
reaches its maximum count. However, if software operation is interrupted, the timer does not reset, triggering
a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise
or electrostatic discharge (ESD) upsets that could
cause uncontrolled processor operation. The internal
watchdog timer is an upgrade to older designs with
external watchdog devices, reducing system cost and
simultaneously increasing reliability.
The watchdog timer is controlled through bits in the
WDCN register. Its timeout period can be set to one of
four programmable intervals ranging from 212 to 221
system clocks in its default mode, allowing flexibility to
support different types of applications. The interrupt
occurs 512 system clocks before the reset, allowing the
system to execute an interrupt and place the system in
a known, safe state before the device performs a total
system reset. At 4.194MHz, watchdog timeout periods
can be programmed from 976µs to 128s, depending on
the system clock mode.
______________________________________________________________________________________
23
MAXQ3100
Real-Time Clock
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
In-Circuit Debug
Embedded debugging capability is available through
the debug port TAP. Embedded debug hardware and
embedded ROM firmware provide in-circuit debugging
capability to the user application, eliminating the need
for an expensive in-circuit emulator. Figure 4 shows a
block diagram of the in-circuit debugger. The in-circuit
debug features include:
MAXQ3100
CPU
• Hardware debug engine
• Set of registers able to set breakpoints on register,
code, or data accesses
• Set of debug service routines stored in the utility
ROM
The embedded hardware debug engine is an independent hardware block in the microcontroller. The debug
engine can monitor internal activities and interact with
selected internal registers while the CPU is executing
user code. Collectively, the hardware and software features allow two basic modes of in-circuit debugging:
• Background mode allows the host to configure and set
up the in-circuit debugger while the CPU continues to
execute the application software at full speed. Debug
mode can be invoked from background mode.
DEBUG
ENGINE
TMS
TCK
TDI
TDO
TAP
CONTROLLER
CONTROL
BREAKPOINT
ADDRESS
DATA
Figure 4. In-Circuit Debugger
The time base of the serial ports is derived from either a
division of the system clock or the dedicated baud
clock generator. The following table summarizes the
operating characteristics as well as the maximum baud
rate of each mode.
Serial port 0 contains additional functionality to support
low-speed infrared transmission in combination with the
PWM function of timer 2. When enabled in this mode,
the serial port automatically outputs a waveform generated by combining the normal serial port output waveform with the PWM carrier waveform output by timer 2,
using a logical OR or logical NOR function. The output
of serial port 0 in this mode can be used to drive an
infrared LED to communicate using a fixed-frequency
carrier modulated signal. Depending on the drive
strength required, the output may require a buffer when
used for this purpose.
• Debug mode allows the debug engine to take control
of the CPU, providing read/write access to internal registers and memory, and single-step trace operation.
Serial Peripherals
The MAXQ3100 incorporates two 8051-style universal
synchronous/asynchronous receiver/transmitters. The
USARTs allow the device to conveniently communicate
with other RS-232 interface-enabled devices, as well as
PCs and serial modems when paired with an external
RS-232 line driver/receiver. The dual independent
USARTs can communicate simultaneously at different
baud rates with two separate peripherals. The USART
can detect framing errors and indicate the condition
through a user-accessible software bit.
24
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
MODE
TYPE
START BITS
DATA BITS
STOP BIT
MAX BAUD RATE AT 4.194MHz
Mode 0
Synchronous
—
8
—
1.05Mbps
Mode 1
Asynchronous
1
8
1
131kbps
Mode 2
Asynchronous
1
8+1
1
131kbps
Mode 3
Asynchronous
1
8+1
1
131kbps
______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
The MAXQ3100 incorporates a pair of 1-bit analog-todigital comparators. The comparator inputs can be
connected to a wide range of peripherals, including
chemical, motion, or proximity detectors; voltage-supply monitoring; or any other appropriate analog input.
The comparator measures the analog inputs against
the internal +1.25V reference. The polarity of the internal comparator-output signal can be selected to indicate a value above or below the internal reference. The
comparators can be configured to generate an optional
interrupt in addition to setting an internal flag when the
input is out of range. A combination of the two comparators along with appropriate biasing of an input
allows the two comparators to be used as a window
comparator. When not in use, the pins associated with
the comparator are usable as general-purpose I/O. A
useful feature of the comparators is that they can be
used to wake the device from stop mode, allowing the
device to monitor external voltages while in an ultralow-power mode and only wake when necessary.
Temperature Sensor
The internal temperature sensor has a user-selectable
resolution of 10 (0.5°C), 11 (0.25°C), 12 (0.125°C), or
13 (0.0625°C) bits. Higher resolutions require longer
conversion times.
Setting the START bit initiates the temperature conversion, and the temperature sensor hardware clears the
bit when the conversion is complete. This bit can be
polled by software, or, optionally, the temperature conversion complete interrupt can be used to alert the system that the results are ready to be read from the
temperature results register (TEMPR).
Applications Information
Grounds and Bypassing
Careful PC-board layout significantly minimizes
crosstalk among the comparator inputs and other digital
signals. Keep digital and analog lines separate, and use
ground traces as shields between them where possible.
Bypass DVDD with a capacitor as low as 1µF and keep
bypass capacitor leads short for best noise rejection.
This device incorporates both analog and digital components, straddling both the analog and digital ground
planes. For increased accuracy, an LC filter can be
used to isolate pin 59. This pin powers the analog circuitry, and the additional filtering reduces the noise
entering the analog block.
Device Applications
The low-power, high-performance RISC architecture of
the MAXQ3100 makes it an excellent fit for many applications that require analog measurements combined
with the intelligence of a full-featured microcontroller.
Simple voltage-dividers can be used to scale any input
into a value in the range of the +1.25V reference. The
dual comparators allow the device to function as a simple limit comparator or window comparator in a wide
range of analog applications.
CMON
CMO
INTERNAL
1.25V
REFERENCE
CMF
CMPOL
Q
CMM
CMPx
INTERRUPT
REQUEST
SET
CMM
Figure 5. Analog Comparator Functional Diagram
______________________________________________________________________________________
25
MAXQ3100
Analog Comparators
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Additional Documentation
Development and Technical Support
Designers must have four documents to fully use all the
features of this device. This data sheet contains pin
descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user’s guides offer detailed
information about programming, device features, and
operation. The following documents can be downloaded from www.maxim-ic.com/microcontrollers.
• The MAXQ3100 data sheet, which contains electrical/timing specifications and pin descriptions, available at www.maxim-ic.com/MAXQ3100.
• The MAXQ3100 errata sheet, available at
www.maxim-ic.com/errata.
• The MAXQ Family User’s Guide , which contains
detailed information on core features and operation,
including programming, avaliable at www.maximic.com/MAXQUG.
• The MAXQ Family User’s Guide: MAXQ3100
Supplement, which contains detailed information on
features specific to the MAXQ3100, available at
www.maxim-ic.com/MAXQ3100UG.
A variety of highly versatile, affordably priced development tools for this microcontroller are available from
Maxim/Dallas Semiconductor and third-party suppliers,
including:
• Compilers
26
• In-circuit emulators
• Integrated development environments (IDEs)
• JTAG-to-serial converters for programming and
debugging
A partial list of development tool vendors can be found
on our website at www.maxim-ic.com/microcontrollers.
Technical support is available through email at
maxq.support@dalsemi.com.
______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Typical Application Circuit #1
Typical Application Circuit #1 shows a general-purpose
implementation using a MAXQ3100 that reads two sensor inputs, displays result and status information on an
3.3V
LCD display, and also interfaces simultaneously with
an RS-232 and RS-485 networks. I/O pins that are not
dedicated to special functions are available to control
other system functions.
DVDD
MAXQ3100
DIRECT INPUT
FROM USERDEFINED SENSOR
TXD0
RS-232
Tx/Rx
RXD0
CMP0
TXD1
RS-485
Tx/Rx
RXD1
R1
VREF
SCALED
COMPARATOR
INPUT
Px.x
RTS
CMP1
R2
LCD MODULE
BACKUP BATTERY
SEG[39:0]
VBAT
COM[3:0]
NOTE THAT UP TO 160 LCD SEGMENTS
CAN BE DRIVEN IF OTHER MUXED PIN
FUNCTIONS ARE NOT USED.
I2C FRAM
OR EEPROM
P2.3
P2.2
GENERALPURPOSE I/O
TDO
JTAG DOWNLOAD/
DEBUG
CONNECTOR
TDI
TCK
INT7
BUTTON 1
INT6
BUTTON 2
TMS
32KIN
32KOUT
______________________________________________________________________________________
27
MAXQ3100
Typical Application Circuits
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Typical Application Circuits (continued)
Typical Application Circuit #2
Another target application of the MAXQ3100 is in the
electricity metering market. When coupled with an analog front-end, the microcontroller becomes the core of
UNREGULATED
SUPPLY
REGULATOR
3.3V
an affordable electricity metering solution. Such an
application can accurately keep time, incorporate a
versatile display, and allow for multiple modes of communication. See Typical Application Circuit #2.
IR Tx/Rx
CIRCUIT
DVDD
MAXQ3100
CMP0
VREF
BACKUP BATTERY
VBAT
TXD0
CMP1
IR Rx
MODULE
RXD0
ENERGY
METERING IC
CALIBRATION
EQUIPMENT
N
IO
AT
I
L
SO
T0
TXD1
SQW
RXD1
I2C FRAM
OR EEPROM
RS-232
Tx/Rx
P2.3
P2.2
LCD MODULE
SEG[39:0]
COM[3:0]
NOTE THAT UP TO 160 LCD SEGMENTS
CAN BE DRIVEN IF OTHER MUXED PIN
FUNCTIONS ARE NOT USED.
TDO
JTAG DOWNLOAD/
DEBUG
CONNECTOR
TDI
TCK
TMS
32KIN
INT7
BUTTON 1
INT6
BUTTON 2
32KOUT
28
______________________________________________________________________________________
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
65 P3.1/TDO
66 P3.2/TCK
67 P3.3/TMS
68 P3.4/SQW
69 P3.5/CMP0
70 P3.6/CMP1
71 RESET
72 VBAT
73 32KIN
74 32KOUT
75 DGND
76 DVDD
77 P0.0/INT0/TXD0
78 P0.1/INT1/RXD0
79 P0.2/INT2/T0G
80 P0.3/INT3/T0
TOP VIEW
DGND
1
64
P3.0/TDI
P0.4/INT4/T1
2
63
P1.3/INT11/RXD1
P0.5/INT5/T1EX
3
62
P1.2/INT10/TXD1
P0.6/INT6
4
61
P1.1/INTP/T2A
P0.7/INT7
5
60
P1.0/INT8/T2B
DVDD
6
59
DVDD
COM0
7
58
DGND
COM1
8
57
VADJ
COM2
9
56
VLCD2
COM3
10
55
VLCD1
DGND
11
54
VLCD
SEG0
12
53
DVDD
SEG1
13
52
DGND
SEG2
14
51
P2.7/SEG39
SEG3
15
50
P2.6/SEG38
SEG4
16
49
P2.5/SEG37
SEG5
17
48
P2.4/SEG36
SEG6
18
47
P2.3/SEG35
SEG7
19
46
P2.2/SEG34
SEG8
20
45
P2.1/SEG33
SEG9
21
44
P2.0/SEG32
SEG10
22
43
SEG31
SEG11
23
42
SEG30
SEG12
24
41
SEG29
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
MAXQ3100
MQFP
______________________________________________________________________________________
29
MAXQ3100
Pin Configuration
MAXQ3100
Mixed-Signal Microcontroller with Analog
Comparators, LCD, and RTC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/DallasPackInfo).
Revision History
Rev 0; 6/07:
Original release.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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