MAXQ3183-RAN+

19-4955; Rev 0; 12/09 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect The MAXQ3183 is a dedicated electricity measurement front-end that collects and calculates polyphase voltage, current, power, energy, and many other metering and power-quality parameters of a polyphase load. The computed results can be retrieved by an external master through the on-chip serial peripheral interface (SPI™) bus. This bus is also used by the external master to configure the operation of the MAXQ3183 and monitor the status of operations. The MAXQ3183 performs voltage and current measurements using an integrated ADC that can measure up to seven external differential signal pairs. An eighth differential signal pair is used to measure the die temperature. An internal amplifier automatically adjusts the current channel gain to compensate for low-current channel-signal levels. Applications 3-Phase Multifunction Electricity Meters Features ♦ Compatible with 3-Phase/3-Wire, 3-Phase/4-Wire ♦ Phase Current THDN ♦ Fundamental and Total Power and Energy ♦ AC/DC Mode Current and Voltage Measurement ♦ Two Pulse Outputs: Configurable for Active, Reactive, and Apparent Powers ♦ Programmable Meter Constants and Pulse Widths ♦ Programmable No-Load Current Threshold ♦ Programmable Thresholds for Undervoltage and Overvoltage Detection ♦ Programmable Threshold for Overcurrent Detection ♦ Programmable Vector Sum Threshold for Bypass Detection ♦ Amp-Hours in Absence of Voltage Signals ♦ On-Chip Digital Temperature Sensor ♦ Precision Internal Voltage Reference 2.048V (30ppm/°C typical), Also Supports An External Voltage Reference ♦ Supports Software Meter Calibration ♦ Active Power and Energy of Each Phase and Combined 3-Phase (kWh), Positive and Negative ♦ Up to 3-Point Multipoint Calibration to Compensate for Transducer Nonlinearity ♦ Reactive Power and Energy of Each Phase and Combined 3-Phase, Positive and Negative ♦ Power-Fail Detection ♦ Bidirectional Reset Input/Output ♦ Apparent Power and Energy of Each Phase and Combined 3-Phase ♦ SPI-Compatible Serial Interface with Interrupt ♦ Neutral Line Current Measurement ♦ Vector Sum of 3-Phase Currents and Neutral Current ♦ Line Frequency (Hz) ♦ Power Factors ♦ Voltage Phasor Angles Request (IRQ) Output ♦ Single 3.3V Supply, Low Power (35mW typical) Ordering Information PART TEMP RANGE PIN-PACKAGE MAXQ3183-RAN+ -40°C to +85°C 28 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package. ♦ Voltage and Current Phase Sequence Indications ♦ Phase Voltage Absence Detection ♦ Voltage and Current Harmonic Measurement Pin Configuration and Typical Application Circuit appear at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAXQ3183 General Description MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect TABLE OF CONTENTS Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Metering Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Analog Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Precision Pulse Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Power-Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 External High-Frequency Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 External High-Frequency Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Internal RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Master Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 SPI Communications Rate and Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 SPI Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Host Software Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 RAM-Based Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 General Operating Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Global Status Register (STATUS) (0x000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Operating Mode Register 0 (OPMODE0) (0x001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Operating Mode Register 1 (OPMODE1) (0x002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Operating Mode Register 2 (OPMODE2) (0x003) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2 _______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Global Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Interrupt Request Flag Register (IRQ_FLAG) (0x004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Interrupt Mask Register (IRQ_MASK) (0x006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Meter Pulse Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Pulse Configuration—CFP Output (PLSCFG1) (0x01E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Pulse Configuration—CFQ Output (PLSCFG2) (0x01F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 CFP Pulse Width (PLS1_WD) (0x020) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 CFP Pulse Threshold (THR1) (0x022) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 CFQ Pulse Width (PLS2_WD) (0x026) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 CFQ Pulse Threshold (THR2) (0x028) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Calibration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Current Gain, Phase X = A/B/C/N (X.I_GAIN) (A: 0x130, B: 0x21C, C: 0x308, N: 0x12E) . . . . . . . . . . . . . . . . . .37 Voltage Gain, Phase X = A/B/C (X.V_GAIN) (A: 0x132, B: 0x21E, C: 0x30A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Energy Gain, Phase X = A/B/C (X.E_GAIN) (A: 0x134, B: 0x220, C: 0x30C) . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Phase-Angle Compensation, High Range, Phase X = A/B/C (X.PA0) (A: 0x13E, B: 0x22A, C: 0x316) . . . . . . . .38 Phase-Angle Compensation, Medium Range, Phase X = A/B/C (X.PA1) (A: 0x140, B: 0x22C, C: 0x318) . . . . .39 Phase-Angle Compensation, Low Range, Phase X = A/B/C (X.PA2) (A: 0x142, B: 0x22E, C: 0x31A) . . . . . . . . .39 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Overcurrent Level (OCLVL) (0x044) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Overvoltage Level (OVLVL) (0x046) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Undervoltage Level (UVLVL) (0x048) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 No-Load Level (NOLOAD) (0x04A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Current Vector Sum Threshold (ISUMLVL) (0x054) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Phase Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Interrupt Flags, Phase X = A/B/C (X.FLAGS) (A: 0x144, B: 0x230, C: 0x31C) . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Interrupt Mask, Phase X = A/B/C (X.MASK) (A: 0x145, B: 0x231, C: 0x31D) . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Energy Overflow Flags, Phase X = A/B/C (X.EOVER) (A: 0x146, B: 0x232, C: 0x31E) . . . . . . . . . . . . . . . . . . . . .42 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Line Frequency (LINEFR) (0x062) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Power Factor, Phase X = A/B/C (X.PF) (A: 0x1C6, B: 0x2B2, C: 0x39E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 RMS Voltage, Phase X = A/B/C (X.VRMS) (A: 0x1C8, B: 0x2B4, C: 0x3A0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 RMS Current, Phase X = A/B/C (X.IRMS) (A: 0x1CC, B: 0x2B8, C: 0x3A4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Energy, Real Positive, Phase X = A/B/C (X.EAPOS) (A: 0x1E8, B: 0x2D4, C: 0x3C0) . . . . . . . . . . . . . . . . . . . . .44 Energy, Real Negative, Phase X = A/B/C (X.EANEG) (A: 0x1EC, B: 0x2D8, C: 0x3C4) . . . . . . . . . . . . . . . . . . . .45 Energy, Reactive Positive, Phase X = A/B/C (X.ERPOS) (A: 0x1F0, B: 0x2DC, C: 0x3C8) . . . . . . . . . . . . . . . . . .45 Energy, Reactive Negative, Phase X = A/B/C (X.ERNEG) (A: 0x1F4, B: 0x2E0, C: 0x3CC) . . . . . . . . . . . . . . . . .46 Energy, Apparent, Phase X = A/B/C (X.ES) (A: 0x1F8, B: 0x2E4, C: 0x3D0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 _______________________________________________________________________________________ 3 MAXQ3183 TABLE OF CONTENTS (continued) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect TABLE OF CONTENTS (continued) Virtual Register Conversion Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Voltage Units Conversion Coefficient (VOLT_CC) (0x014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Current Units Conversion Coefficient (AMP_CC) (0x016) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Power Units Conversion Coefficient (PWR_CC) (0x018) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Energy Units Conversion Coefficient (ENR_CC) (0x01A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Temperature Conversion Coefficient (TEMP_CC) (0x060) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Virtual Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Real Power, Phase X = A/B/C/T (PWRP.X) (A: 0x801, B: 0x802, C: 0x804, T: 0x807) . . . . . . . . . . . . . . . . . .51 Reactive Power, Phase X = A/B/C/T (PWRQ.X) (A: 0x811, B: 0x812, C: 0x814, T: 0x817) . . . . . . . . . . . . . .51 Apparent Power, Phase X = A/B/C/T (PWRS.X) (A: 0x821, B: 0x822, C: 0x824, T: 0x827) . . . . . . . . . . . . . .52 Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 RMS Volts, Phase X = A/B/C (V.X) (A: 0x831, B: 0x832, C: 0x834) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 RMS Amps, Phase X = A/B/C/N (I.X) (A: 0x841, B: 0x842, C: 0x844, N: 0x840) . . . . . . . . . . . . . . . . . . . . . .52 Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Power Factor (PF.T) (0x867) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Real Energy, Phase A/B/C/T (ENRP.X) (A: 0x8C1, B: 0x8C2, C: 0x8C4, T: 0x8C7) . . . . . . . . . . . . . . . . . . . .53 Reactive Energy, Phase A/B/C/T (ENRQ.X) (A: 0x8D1, B: 0x8D2, C: 0x8D4, T: 0x8D7) . . . . . . . . . . . . . . . .53 Apparent Energy, Phase A/B/C/T (ENRS.X) (A: 0x871, B: 0x872, C: 0x874, T: 0x877) . . . . . . . . . . . . . . . . .53 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Analog Front-End Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Digital Signal Processing (DSP) Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Digital Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Per Sample Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Per DSP Cycle Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Energy Accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 No-Zero-Crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Phase Sequence Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 RMS Voltage, RMS Current, and Energy Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Power Calculation (Active, Reactive, Apparent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Energy Accumulation Start Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 No-Load Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 On Demand Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 RMS Volts, RMS Amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4 _______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Line Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Phasor Angles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Meter Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Generating Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Meter Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Overvoltage and Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Meter Units to Real Units Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Units Conversion Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Calibration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Calibrating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Calibrating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Calibrating Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Interfacing the MAXQ3183 to External Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Connections to the Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Sensor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Voltage Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Voltage-Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Voltage Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Current Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Current Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Current Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Advanced Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Modifying the ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Fine-Tuning the DSP Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Fine-Tuning the Line Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Fundamental Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Harmonic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Current Total Harmonic Distortion Plus Noise (THDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Current Vector Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Low-Power Measurement Mode (LOWPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Advanced Calibrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Calibrating Current Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Calibrating Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 _______________________________________________________________________________________ 5 MAXQ3183 TABLE OF CONTENTS (continued) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect TABLE OF CONTENTS (continued) Calibrating Power/Energy Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Multipoint Phase Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Advanced Register Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Analog Scan Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Time Slot Assignment—Current Channel X = A/B/C (SCAN_IX) (A: 0x008, B: 0x00C, C: 0x00A) . . . . . . . . .73 Time Slot Assignment—Voltage Channel X = A/B/C (SCAN_VX) (A: 0x009, B: 0x00D, C: 0x00B) . . . . . . . .74 Time Slot Assignment—Neutral Current Channel (SCAN_IN) (0x00E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Time Slot Assignment—Temperature Channel (SCAN_TE) (0x00F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Neutral Current and Harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Auxiliary Channel Configuration (AUX_CFG) (0x010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 DSP System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 System Clock Frequency (SYS_KHZ) (0x012) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Cycle Count (CYCNT) (0x01C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Number of Scan Frames per DSP Cycle (NS) (0x040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Line Cycle Noise Rejection Filter (REJ_NS) (0x02C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Line Cycle Averaging Filter (AVG_NS) (0x02E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Meter Measurement Averaging Filter (AVG_C) (0x030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Meter Measurement Highpass Filter (HPF_C) (0x032) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Fundamental Filter Feed-Forward Coefficient (B0FUND) (0x034) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Fundamental Filter Feedback Coefficient (A1FUND) (0x036) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Harmonic Filter Feed-Forward Coefficient (B0HARM) (0x03A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Harmonic Filter Feedback Coefficient (A1HARM) (0x03C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Zero-Cross Lowpass Filter (ZC_LPF) (0x05A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Hardware Mirror Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 ADC Configuration (R_ACFG) (0x04C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 ADC Conversion Rate (R_ADCRATE) (0x04E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 ADC Settling Time (R_ADCACQ) (0x050) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 SPI Configuration (R_SPICF) (0x052) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Communications Timeout (COM_TIMO) (0x056) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Energy Accumulation Timeout (ACC_TIMO) (0x058) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Phase-Angle Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Phase Offset Current Threshold 1 (I1THR) (0x05C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Phase Offset Current Threshold 2 (I2THR) (0x05E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 6 _______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Miscellaneous Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Neutral Current Gain (N.I_GAIN) (0x12E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Gain, Fundamental Energy, Phase X = A/B/C (X.EF_GAIN) (A: 0x136, B: 0x222, C: 0x30E) . . . . . . . . . . . . .88 Linearity Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Linearity Offset, High Range, Phase X = A/B/C (X.OFFS_HI) (A: 0x138, B: 0x224, C: 0x310) . . . . . . . . . . . .88 Linearity Gain Coefficient, Low Range, Phase X = A/B/C (X.GAIN_LO) (A: 0x13A, B: 0x226, C: 0x312) . . .88 Linearity Offset, Low Range, Phase X = A/B/C (X.OFFS_LO) (A: 0x13C, B: 0x228, C: 0x314) . . . . . . . . . . .89 Measurements—RAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 On-Demand RMS Result (N.IRMS) (0x11C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Fundamental Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Fundamental Energy Overflow Flags, Phase X = A/B/C (X.EFOVER) (A: 0x147, B: 0x233, C: 0x31F) . . . . .90 Energy, Fundamental, Real Positive, Phase X = A/B/C (X.EAFPOS) (A: 0x1FC, B: 0x2E8, C: 0x3D4) . . . . .90 Energy, Fundamental, Real Negative, Phase X = A/B/C (X.EAFNEG) (A: 0x200, B: 0x2EC, C: 0x3D8) . . . .91 Energy, Fundamental, Reactive Positive, Phase X = A/B/C (X.ERFPOS) (A: 0x204, B: 0x2F0, C: 0x3DC) . .91 Energy, Fundamental, Reactive Negative, Phase X = A/B/C (X.ERFNEG) (A: 0x208, B: 0x2F4, C: 0x3E0) .92 Energy Fundamental, Apparent, Phase X = A/B/C (X.ESF) (A: 0x20C, B: 0x2F8, C: 0x3E4) . . . . . . . . . . . . .92 Energy Accumulated in the Last DSP Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Real Energy, Phase X = A/B/C (X.ACT) (A: 0x1D0, B: 0x2BC, C: 0x3A8) . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Reactive Energy, Phase X = A/B/C (X.REA) (A: 0x1D4, B: 0x2C0, C: 0x3AC) . . . . . . . . . . . . . . . . . . . . . . . .93 Apparent Energy, Phase X = A/B/C (X.APP) (A: 0x1D8, B: 0x2C4, C: 0x3B0) . . . . . . . . . . . . . . . . . . . . . . . .94 Fundamental Energy Accumulated in the Last DSP Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Fundamental Real Energy, Phase X = A/B/C (X.ACTF) (A: 0x1DC, B: 0x2C8, C: 0x3B4) . . . . . . . . . . . . . . .94 Fundamental Reactive Energy, Phase X = A/B/C (X.REAF) (A: 0x1E0, B: 0x2CC, C: 0x3B8) . . . . . . . . . . . .95 Fundamental Apparent Energy, Phase X = A/B/C (X.APPF) (A: 0x1E4, B: 0x2D0, C: 0x3BC) . . . . . . . . . . . .95 Checksum (CHKSUM) (0x066) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Measurements—Virtual Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Fundamental Real Power, Phase A/B/C/T (PWRPF.X) (A: 0x881, B: 0x882, C: 0x884, T: 0x887) . . . . . . . . . . . . .97 Fundamental Reactive Power, Phase A/B/C/T (PWRQF.X) (A: 0x891, B: 0x892, C: 0x894, T: 0x897) . . . . . . . . .97 Fundamental Apparent Power, Phase A/B/C/T (PWRSF.X) (A: 0x8A1, B: 0x8A2, C: 0x8A4, T: 0x8A7) . . . . . . . .98 Fundamental Real Energy, Phase A/B/C/T (ENRPF.X) (A: 0x8E1, B: 0x8E2, C: 0x8E4, T: 0x8E7) . . . . . . . . . . . .98 Fundamental Reactive Energy, Phase A/B/C/T (ENRQF.X) (A: 0x8F1, B: 0x8F2, C: 0x8F4, T: 0x8F7) . . . . . . . . .98 Fundamental Apparent Energy, Phase A/B/C/T (ENRSF.X) (A: 0x8B1, B: 0x8B2, C: 0x8B4, T: 0x8B7) . . . . . . . .99 Current Total Harmonic Distortion Plus Noise, Phase A/B/C (THDN.X) (A: 0x859, B:0x85A, C: 0x85C) . . . . . . .99 Phasors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Phase B Phasor (VBPH: 0x852) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Phase C Phasor (VCPH: 0x854) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 _______________________________________________________________________________________ 7 MAXQ3183 TABLE OF CONTENTS (continued) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect TABLE OF CONTENTS (continued) Harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 RMS Voltage, Harmonic (V.HARM) (0x830) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 RMS Current, Harmonic/Neutral (I.N, I.HARM) (0x840) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Ratio of Harmonic/Fundamental (HARM_NF) (0x850) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Special Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Specific Design Considerations for MAXQ3183-Based Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 8 _______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Figure 1. External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 2. Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 3. Simplified Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 4a. SPI Interface Timing (CKPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 4b. SPI Interface Timing (CKPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 5. Read SPI Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 6. Write SPI Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 7. Flowchart for Reading from MAXQ3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 8. Flowchart for Writing to MAXQ3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 9. Per Sample Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Figure 10. Computation of RMS Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Figure 11. Phase Compensation for Energy Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Figure 12. Apparent and Reactive Energy Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Figure 13. Sample Voltage Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Figure 14. Sample Current Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Figure 15. Offset Testing Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Figure 16. Phase Offset vs. Input Current Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 LIST OF TABLES Table 1. Command Format for SPI Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 2. Command Format for SPI Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 3. RAM Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 4. Virtual Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 5. Meter Unit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Table 6. Virtual Register Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Table 7. Virtual Registers That Activate Special Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 _______________________________________________________________________________________ 9 MAXQ3183 LIST OF FIGURES MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect ABSOLUTE MAXIMUM RATINGS Voltage Range on DVDD Relative to DGND .........-0.3V to +4.0V Voltage Range on AVDD Relative to AGND..........-0.3V to +4.0V Voltage Range on AGND Relative to DGND .........-0.3V to +0.3V Voltage Range on AVDD Relative to DVDD ..........-0.3V to +0.3V Voltage Range on Any Pin Relative to DGND except VxP, IxN Pins..............................-0.3V to +4.0V Voltage Range on VxP, IxN Relative to AGND ......-0.3V to +4.0V Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Soldering Temperature .............................Refer to the IPC/ JEDEC J-STD-020 Specification. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. METERING SPECIFICATIONS (VAVDD = VDVDD = VRST to 3.6V, Current Channel Dynamic Range 1000:1 at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS Active Energy Linearity Error DR 1000:1 0.1 Reactive Energy Linearity Error DR 1000:1 0.2 % Apparent Energy Linearity Error DR 1000:1 0.5 % % RMS Voltage Linearity Error RMS Current Linearity Error DR 20:1 0.5 DR 500:1 1.0 DR 20:1 0.5 % % Line Frequency Error 0.5 % Power Factor Error 1.0 % ELECTRICAL CHARACTERISTICS (VAVDD = VDVDD = VRST to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VRST 3.6 V POWER-SUPPLY SPECIFICATIONS Digital Supply Voltage VDVDD Power-Fail Interrupt Trip Point VPFW Active mode, EPWRF = 1 2.84 3.13 V Power-Fail Reset Trip Point VRST Active mode 2.70 2.99 V VRST 3.6 V Analog Supply Voltage VAVDD Analog Supply Current IAVDD fCLK = 8MHz 0.9 1.8 mA Digital Supply Current IDVDD fCLK = 8MHz 8.5 13 mA LOWPM = 1 (Note 1) 4.2 Low-Power Measurement Mode Current ILOWPM Stop-Mode Current 0.2 mA 12 μA DIGITAL I/O SPECIFICATIONS Input High Voltage VIH Input Low Voltage VIL Input Hysteresis Input Leakage 10 VIHYS IL 0.7 x VDVDD V 0.3 x VDVDD VDVDD = 3.3V VIN = DGND or VDVDD, pullup off 500 ±0.01 ______________________________________________________________________________________ V mV ±1 μA Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect (VAVDD = VDVDD = VRST to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL Input Low Current IIL RESET Pullup Resistance Output High Voltage (Except RESET) CONDITIONS VIN = 0.4V, weak pullup on RRESET VOL TYP MAX UNITS 150 200 k
-50 50 I OH = -4mA VDVDD - 0.4 I OH = -6mA VDVDD - 0.5 VOH Output Low Voltage MIN μA V I OL = 4mA 0.4 I OL = 6mA 0.5 V SYSTEM CLOCK SOURCES External Clock Input Frequency 0 8.12 MHz External Clock Input Duty Cycle 45 55 % 8.12 MHz External HF Crystal Frequency f SYS Fundamental mode XTAL1, XTAL2 Internal Load Capacitance 16 Internal RC Oscillator Frequency 7.4 7.6 Internal RC Oscillator Accuracy ±2 Internal RC Oscillator Current 50 Internal RC Oscillator Startup Delay (Note 1) pF 8.6 MHz % 120 0.45 μA μs ANALOG-TO-DIGITAL CONVERTER Input Voltage Range Common-Mode Bias 0 VCOMM VREF 1.14 V V Offset Error ±2 mV Offset Error Drift ±8 μV/°C 0.05 % Gain Error (G = 1) Spurious-Free Dynamic Range SFDR 90 dB Total Harmonic Distortion THD 90 dB 7 kHz 30 ppm/°C 2.048 V Input Bandwidth (-3dB) (Note 1) INTERNAL VOLTAGE REFERENCE Temperature Coefficient Output Voltage (Note 1) VREF INTERNAL TEMPERATURE SENSOR Temperature Error +4 °C f SYS/4 MHz (Note 1) -4 ns ns SPI SLAVE-MODE INTERFACE TIMING Maximum SPI Clock Rate SCLK Input Pulse-Width High t SCH (Note 3) 4x t SYS SCLK Input Pulse-Width Low t SCL (Note 3) 4x t SYS ______________________________________________________________________________________ 11 MAXQ3183 ELECTRICAL CHARACTERISTICS (continued) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = VRST to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL SSEL Low to First SCLK Edge (Slave Enable) t SE Last SCLK Edge to SSEL High (Slave Disable) CONDITIONS MIN (Note 3) TYP MAX UNITS 4t SYS ns t SD t SYS + 5 ns MOSI Valid to SCLK Sample Edge (MOSI Setup) t SIS 5 ns SCLK Sample Edge to MOSI Change (MOSI Hold) t SIH t SYS + 5 ns SCLK Shift Edge to MISO Valid (MISO Hold) t SOV 3t SYS +5 ns Note 1: Specifications guaranteed by design but not production tested. Note 2: Specifications to -40°C are guaranteed by design and are not production tested. Note 3: tSYS = 1/fSYS. SPI Slave Mode Timing SHIFT EDGE SSEL tSD SAMPLE EDGE tSCL tSCH SCLK tSE tSOV DATA OUTPUT tSIS tSIH DATA INPUT 12 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect VCOMM CFP, CFQ COUNTERS REF VREF V0P V1P V2P I0P I1P I2P INP I/O REGISTERS SPI ADC TEMP SENSE I/O REGISTERS I0N I1N I2N VN ADC CONTROL, ELECTRICITY METERING DSP, COMMUNICATIONS MANAGER I/O REGISTERS WATCHDOG TIMER RESET 16 x 16 HW MULTIPLY 48-BIT ACCUMULATE POR/ BROWNOUT MONITOR MAXQ3183 I/O BUFFERS CFQ CFP I/O BUFFERS MISO MOSI SCLK SSEL I/O BUFFERS IRQ HF RC OSC/8 SYSCLK ADCCLK ADC CLOCK PRESCALER HF XTAL OSC XTAL1 XTAL2 ______________________________________________________________________________________ 13 MAXQ3183 Block Diagram Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect MAXQ3183 Pin Description PIN NAME FUNCTION POWER PINS 17, 22 DVDD Digital Supply Voltage 25 AVDD Analog Supply Voltage 18 DGND Digital Ground 9 AGND Analog Ground 23 VCOMM 24 VREF Voltage Bias. This pin can be used to create an input common-mode DC offset for ADC channel conversions. Voltage Reference. Reference voltage for the ADC. An external reference voltage can be connected to this pin when extremely high accuracy is required. VOLTAGE AND CURRENT PINS 26, 3, 4 V0P, I0P, I0N Phase A Voltage and Current Analog Inputs 27, 5, 6 V1P, I1P, I1N Phase B Voltage and Current Analog Inputs 28, 7, 8 V2P, I2P, I2N Phase C Voltage and Current Analog Inputs 1 VN Analog Input for Common Voltage 2 INP Analog Input for Neutral Current CLOCK PINS 10 XTAL2 11 XTAL1 12 IRQ Interrupt Request Output. This line is driven low by the device to indicate to the master that an unmasked interrupt has occurred. 13 SSEL Slave Select Input. This line is the active-low slave select input for the SPI interface. 14 SCLK Slave Clock Input. This line is the clock input for the SPI interface. 15 MOSI Master Out-Slave In Input. This line is used by the master to transmit data to the slave (the MAXQ3183) over the SPI interface. 16 MISO Master In-Slave Out Output. This line is used by the MAXQ3183 (the slave) to transmit data back to the master over the SPI interface. 19 CFP Pulse Output 1. Configurable to represent energy or RMS voltage or current. 20 CFQ Pulse Output 2. Configurable to represent energy or RMS voltage or current. 21 14 High-Frequency Crystal Input/Output. When using an external high-frequency crystal, the crystal oscillator circuit should be connected between XTAL1 and XTAL2. When using an externally driven clock (EXTCLK = 1), the clock should be input at XTAL1, with XTAL2 left unconnected. RESET Active-Low Reset Input/Output. An external master can reset the MAXQ3183 by driving this pin low. This pin includes a weak pullup resistor to allow for a combination of wired-OR external reset sources. An RC circuit is not required for power-up, as this function is provided internally. This pin also acts as a reset output when the source of the reset is internal to the device (power-fail, watchdog reset, etc.). In this case, the RESET pin is held low by the device until it exits the reset state, then the RESET pin is released. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect The MAXQ3183 contains four major subsections: the analog front-end, the digital signal processor, the precision pulse generators, and an SPI peripheral for communication to the host processor. Analog Front-End The analog front-end (AFE) is an 8-channel analog-todigital converter (ADC). It operates autonomously in the standard configuration, assigning three channels to phase A, B, and C voltage; three channels to phase A, B, and C current; one channel to neutral current; and the last channel to a temperature sensor. Each channel also contains a programmable-gain amplifier capable of providing a gain of 1, 2, 4, 8, 16, or 32 incoming signals. Only the voltage channels permit gain scaling by the host processor. The MAXQ3183 DSP firmware automatically sets the gain on current channels. Digital Signal Processor The DSP code is permanently embedded in masked ROM and accepts raw current and voltage samples for each of three phases and continuously calculates a host of values including RMS volts, RMS amps, real energy, reactive energy, apparent energy, fundamental and harmonic energy, and power factor. The MAXQ3183 DSP core processes incoming samples from the analog front-end according to user configurations. The host sets these operating parameters by specifying addresses within the device RAM space. When a calculation cycle is complete, the results are placed back into RAM as well. Thus, the DSP core uses the RAM block as both its input (for operating parameters) and output (for calculation results) medium. See the SPI Peripheral section for how the host writes operating parameters and reads results from the RAM. The DSP also calculates certain values such as line frequency and active and reactive powers only when demanded by the host. Precision Pulse Generators The MAXQ3183 includes two precision pulse generators that generate a pulse whenever certain conditions are met. In the MAXQ3183, many meter quantities can be selected for conversion to meter pulses including absolute energy, net energy, reactive energy, voltage, and current. The pulse generators are accumulators. On each DSP cycle, whatever quantity is being measured—real energy, reactive energy, current, or something else—is added to the pulse accumulator. The pulse accumulator is then tested to determine if the value in the accumulator is greater than the threshold. If it is greater, the threshold value is subtracted from the accumulator value and the meter pulse starts. SPI Peripheral The SPI controller is a slave-only device that can read or write any location in the data RAM. Additionally, it can request data from on-demand registers. The MAXQ3183 implements a truly full-duplex communication, rather than the pseudo half-duplex mode used by other SPI peripherals. That is, each time a character is received by the MAXQ3183, a meaningful character is returned to the host. Often, this is a protocol character. In this way, the host can be assured that the command has been received and is valid. Optional error checking can also be enabled to further guarantee proper operation. Operating Modes The MAXQ3183 has two basic modes of operation, each of which is described in the following sections. The Initialization Mode is the default mode upon powerup or following reset; entry to and exit from the other operating modes is only performed as a result of commands sent by the master. Run Mode This mode is the normal operating mode for the MAXQ3183. In this mode, the MAXQ3183 continuously executes the following operations: • Scans analog front-end channels and collects raw voltage and current samples. • Processes voltage and current samples through DSP filters as enabled and configured. • Calculates power, energy, and other required quantities and stores these values in RAM registers. • Responds to register write and read commands from the master. • Outputs power pulses on CFP and CFQ as configured. • Drives IRQ when an interrupt condition has been detected and the interrupt is not masked. Stop Mode This mode places the MAXQ3183 into a power-saving state where it consumes the least possible amount of current. In Stop Mode, all functions are suspended, including the ADC and power and voltage measurement and processing. The MAXQ3183 does not respond to any commands from the master in this operating state. ______________________________________________________________________________________ 15 MAXQ3183 Detailed Description MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Entry into Stop Mode only occurs at the request of the master. To place the MAXQ3183 into Stop Mode, the master must read the ENTER STOP (0xC02) register. Once this register has been read, the MAXQ3183 enters Stop Mode immediately, before the transmission of the final ACK byte by the MAXQ3183. There are three possible ways to bring the MAXQ3183 back out of Stop Mode. • Power Cycle. The MAXQ3183 automatically exits Stop Mode if a power-on reset occurs. Following exit from Stop Mode, all registers are cleared back to their default states, and the MAXQ3183 transitions to Initialization Mode. • External Reset. The MAXQ3183 exits Stop Mode if an external reset is triggered by driving RESET low. Once the RESET pin is released and allowed to return to a high state, the MAXQ3183 comes out of reset and goes into Initialization Mode. All registers are cleared to their default states when exiting Stop Mode in this manner. • External Interrupt. Driving the SSEL pin low causes the MAXQ3183 to exit Stop Mode without undergoing a reset cycle. When exiting Stop Mode in this manner, all register and configuration settings are retained, and the MAXQ3183 automatically resumes electric-metering functions and sample processing. Note that when the master is communicating with the MAXQ3183, the SSEL line is normally driven low at the beginning of each SPI command. This means that if the master sends an SPI command after the MAXQ3183 enters Stop Mode, the MAXQ3183 automatically exits Stop Mode. Reset Sources There are several different sources that can cause the MAXQ3183 to undergo a reset cycle. For any type of hardware reset, the RESET pin is driven low when a reset occurs. External Reset This hardware reset is initiated by an external source (such as the master controller or a manual pushbutton press) driving the RESET pin on the MAXQ3183 low. The RESET line must be held low for at least four cycles of the currently selected clock for the external reset to take effect. Once the external reset takes effect, it remains in effect indefinitely as long as RESET is held low. Once the external reset has been released, the MAXQ3183 clears all registers to their default states and resumes execution in Initialization Mode. When an external reset occurs outside of Stop Mode, execution (in Initialization Mode) resumes after four cycles of the currently selected clock (external high-frequency crystal for Run Mode, 1MHz internal RC oscillator for LOWPM Mode). As the MAXQ3183 enters Initialization Mode, the LOWPM bit is always cleared CLOCK RESET RESET SAMPLING INTERNAL RESET BEGIN RUNNING IN INITIALIZATION MODE Figure 1. External Reset 16 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Power-On Reset When the MAXQ3183 is first powered up, or when the power supply, VDVDD, drops below the VRST power-fail trip point (outside of Stop Mode), the MAXQ3183 is held in power-on reset. Once the power supply rises above the V RST level, the power-on reset state is released and all registers are reset to their defaults and execution resumes in Initialization Mode. The high-frequency external crystal (LOWPM = 0) is always selected as the clock source following any power-on or brownout reset. In Stop Mode brownout detection is disabled, so a power-on reset does not occur until VDVDD drops to a lower level (V POR ). From the master’s perspective, power-on resets and brownout resets both cause the MAXQ3183 to reset in the same way. Watchdog Reset The MAXQ3183 includes a hardware watchdog timer that is armed and periodically reset automatically during normal operation. Under normal circumstances, the MAXQ3183 always resets the watchdog timer often enough to prevent it from expiring. However, if an internal error of some kind causes the MAXQ3183 to lock up or enter an endless execution loop, the watchdog timer expires and triggers an automatic hardware reset. There is no register flag to indicate to the master that a watchdog reset has occurred, but the RESET line strobes low briefly. The watchdog timer does not run during Stop Mode. Software Reset The master initiates a software reset by setting the SWRES (OPMODE0.3) bit to 1. When a software reset occurs, the MAXQ3183 clears all registers to their default states and returns to Initialization Mode, in the BROWNOUT DETECTION BROWNOUT DETECTION (ALWAYS ENABLED OUTSIDE OF STOP MODE) FORCES RESET STATE. POR = 1 BROWNOUT DETECTION DISABLED DURING STOP MODE. NO RESET IS GENERATED. VRST1 BROWNOUT DETECTION DISABLED. POR LEVEL CAUSES RESET. VPOR tPOR INTERNAL RESET STOP MODE Figure 2. Brownout Reset ______________________________________________________________________________________ 17 MAXQ3183 to 0, meaning that the MAXQ3183 always switches to the high-frequency clock before it begins accepting commands in Initialization Mode. When an external reset occurs from Stop Mode, execution (in Initialization Mode) resumes after 128 cycles of the internal RC oscillator (or approximately 128μs). same manner as if an external reset had taken place. Unlike a hardware reset, however, a software reset does not cause the MAXQ3183 to drive the RESET line low. Power-Supply Monitoring In addition to the hardware reset provided by the power-on reset and brownout reset circuits, the MAXQ3183 includes the capability to detect a low power supply on the DVDD pin and alert the master through the interrupt (IRQ) mechanism before a hardware reset occurs. This function, which is always enabled outside of Stop Mode, causes the RAM status register flag PWRF (IRQ_FLAG.0) to be set to 1 whenever V DVDD drops below the V PFW trip point. Once PWRF has been set to 1 by hardware, it can only be cleared by the master (or by a system reset). Whenever PWRF = 1, if the EPWRF interrupt masking bit is also set to 1, the MAXQ3183 drives IRQ low to signal to the master that an interrupt condition (in this case, a powerfail warning) exists and requires attention. Clock Sources All operations including ADC sampling and SPI communications are synchronized to a single system clock. This clock can be obtained from any one of three selectable sources, as shown in Figure 3. External High-Frequency Crystal The default system clock source for the MAXQ3183 is an external high-frequency crystal oscillator circuit connected between XTAL1 and XTAL2. When clocked with an external crystal, a parallel-resonant, AT-cut crystal oscillating in the fundamental mode is required. When using a high-frequency crystal, the fundamental oscillation mode of the crystal operates as inductive reactance in parallel resonance with external capacitors C1 and C2. The typical values of these external capacitors vary with the type of crystal being used and should be selected based on the load capacitance as suggested by the crystal manufacturer. Since noise at XTAL1 and XTAL2 can adversely affect device timing, the crystal and capacitors should always be placed as close as possible to the XTAL1 and XTAL2 pins, with connection traces between the crystal and the device kept as short and direct as possible. In multiple layer boards, avoid running other high-speed digital signals underneath the crystal oscillator circuit if possible, as this could inject unwanted noise into the clock circuit. Following power-up or any system reset, the high-frequency clock is automatically selected as the system clock source. However, before this clock can be used HF CRYSTAL GLITCH-FREE MUX MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect 1MHz INTERNAL OSCILLATOR CLOCK GENERATION SYSTEM CLOCK ENABLE INT/EXT XTAL IN RING IN EXTCLK STOPM POR WATCHDOG TIMER CRYSTAL STARTUP TIMER RING COUNT CLK ENABLE WATCHDOG RESET Figure 3. Simplified Clock Sources 18 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect External High-Frequency Clock Instead of using a crystal oscillator to generate the high-frequency clock, it is also possible to input a highfrequency clock that has been generated by another source (such as a digital oscillator IC) directly into the XTAL1 pin of the MAXQ3183. To use an external high-frequency clock as the system clock source, the XTAL1 pin should be used as the clock input and the XTAL2 pin should be left unconnected. The master should also shut down the internal crystal oscillator circuit by setting the EXTCLK bit (OPMODE0.4) to 1. This bit is only cleared by the MAXQ3183 if a power-on or brownout reset occurs and is unaffected by other resets. When using an external high-frequency clock, the clock signal should be generated by a CMOS driver. If the clock driver is a TTL gate, its output must be connected to DVDD through a pullup resistor to ensure that the correct logic levels are generated. To minimize system noise in the clock circuitry, the external clock source must meet the maximum rise and fall times and the minimum high and low times specified for the clock source in the Electrical Characteristics table. Internal RC Oscillator When the external high-frequency crystal is warming up, or when the MAXQ3183 is placed into LOWPM mode, the system clock is sourced from an internal RC oscillator. This internal oscillator is designed to provide the system approximately 1MHz, although the exact frequency varies over temperature and supply voltage. If no external crystal circuit or high-frequency clock will be used, the MAXQ3183 can be forced to operate infinitely from the internal oscillator by grounding XTAL1. This ensures that the crystal warmup count never completes, so the MAXQ3183 runs from the internal oscillator in all active modes. Master Communications Before the MAXQ3183 can begin performing electricmetering operations, the master must initialize a number of configuration parameters. Since the MAXQ3183 does not contain internal nonvolatile memory, these parameters (stored in internal registers) must be set by the master each time a power-up or reset cycle occurs, or each time a switch is made between LOWPM Mode and Run Mode. The external master communicates with the MAXQ3183 over a standard SPI bus, using commands to read and write values to internal registers on the MAXQ3183. These registers include, among many other items: • Operating mode settings (Stop Mode, LOWPM Mode, external clock mode, etc.) • Status and interrupt flags (power-supply failure, overcurrent/overvoltage detection, etc.) • Masking control for interrupts to determine which conditions cause IRQ to be driven low • Configuration settings for analog channel scanning • Power pulse output configuration • Filter coefficients and configuration • Read-only registers containing accumulated power and energy data As the MAXQ3183 obtains voltage and current measurements in Run Mode or LOWPM Mode, it accumulates, filters, and performs a number of calculations on the collected data. Many of these operations (including the various filtering stages) are configured by settings in registers written by the master. The output results can then be read by the master from various read-only registers in parallel with the ongoing measurement and processing operations. SPI Communications Rate and Format The SPI is an interdevice bus protocol that provides fast, synchronous, full-duplex communications between a designated master device and one or more slave devices. In a MAXQ3183-based design, the MAXQ3183 would be the slave device connected to a designated master microcontroller. The external master initiates all communications transfers. The interrupt request line IRQ, while not technically part of the SPI bus interface, is also used for master/slave communications because it allows the MAXQ3183 to notify the master that an interrupt condition exists. Some SPI peripherals sacrifice speed in favor of simulating a half-duplex operation. This is not the case with the MAXQ3183; it is truly a full-duplex SPI slave. ______________________________________________________________________________________ 19 MAXQ3183 for system execution, a crystal warmup timer must count 65,536 cycles of the high-frequency clock. While this warmup time period is in effect, execution continues using the internal 1MHz oscillator. Once the 65,536-cycle count completes (which requires approximately 8.2ms at 8MHz), the device automatically switches over to the high-frequency clock. This crystal warmup timer is also activated upon exit from Stop Mode, since the high-frequency crystal oscillator is shut down during Stop Mode. MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect During an SPI transfer, data is simultaneously transmitted and received over two serial data lines (MISO and MOSI) with respect to a single serial shift clock (SCLK). The polarity and phase of the serial shift clock are the primary components in defining the SPI data transfer format. The polarity of the serial clock corresponds to the idle logic state of the clock line and, therefore, also defines which clock edge is the active edge. To define a serial shift clock signal that idles in a logic-low state (active clock edge = rising), the clock polarity select (CKPOL; R_SPICF.0) bit should be configured to a 0, while setting CKPOL = 1 causes the shift clock to idle in a logic-high state (active clock edge = falling). The phase of the serial clock selects which edge is used to sample the serial shift data. The clock phase select (CKPHA; R_SPICF.1) bit controls whether the active or SCLK CYCLE # (FOR REFERENCE) 1 2 3 inactive clock edge is used to latch the data. When CKPHA is set to a logic 1, data is sampled on the inactive clock edge (clock returning to the idle state). When CKPHA is set to a logic 0, data is sampled on the active clock edge (clock transition to the active state). Together, the CKPOL and CKPHA bits allow four possible SPI data transfer formats. Transfers over the SPI interface always start with the most significant bit and end with the least significant bit. All SPI data transfers to and from the MAXQ3183 are always 8 bits (one byte) in length. The MAXQ3183 SPI interface does not support 16-bit character lengths. The default format (upon power-up or system reset) for the MAXQ3183 SPI interface is represented in Figure 4a (CKPOL = 0; CKPHA = 0). In this format, the 4 5 6 7 8 SCLK (CKPOL = 0) SCLK (CKPOL = 1) MOSI (FROM MASTER) MSB MISO (FROM SLAVE) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB 4 5 6 7 8 * SSEL (TO SLAVE) *NOT DEFINED BUT NORMALLY MSB OF CHARACTER JUST RECEIVED. Figure 4a. SPI Interface Timing (CKPHA = 0) SCLK CYCLE # (FOR REFERENCE) 1 2 3 SCLK (CKPOL = 0) SCLK (CKPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB SSEL (TO SLAVE) *NOT DEFINED BUT NORMALLY LSB OF PREVIOUSLY TRANSMITTED CHARACTER. Figure 4b. SPI Interface Timing (CKPHA = 1) 20 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect The clock rate used for the SPI interface is determined by the bus master, since the MAXQ3183 always operates as an SPI slave device. However, the maximum clock rate is limited by the system clock frequency of the MAXQ3183. For proper communications operation, the SPI clock frequency used by the master must be less than or equal to the MAXQ3183’s clock frequency divided by 4. For example, when the MAXQ3183 is running at 8MHz, the SPI clock frequency must be 2MHz or less. And if the MAXQ3183 is running in LOWPM Mode (or if the crystal is still warming up), the SPI clock frequency must remain at 250kHz or less for proper communications operation. In addition to limiting the overall SPI bus clock rate, the master must also include a communications delay following each byte transmit/receive cycle. This delay, which provides the MAXQ3183 with time to process an ADC sample, should be a minimum of 400 system clocks. With default settings and running at 8MHz, this delay time is 50μs. Reducing the system clock frequency to 1MHz (LOWPM mode) would increase this delay period by a factor of 8 to 400μs. SPI Communications Protocol All transactions between the master and the MAXQ3183 consist of the master writing to or reading from one of the MAXQ3183’s registers. To the host, the MAXQ3183 looks like a memory array that consists of both RAM and ROM. This is because the ROM firmware in the MAXQ3183 reads its operational parameters from RAM and places its results in RAM. Consequently, configuring a MAXQ3183 is as simple as performing a block write to its RAM locations. Some read-only memory locations in the MAXQ3183 trigger actions within the device to calculate electricitymetering results on the fly. The specific function and purpose of RAM and virtual ROM locations are given in the register map. There are several different categories of internal registers on the MAXQ3183. • RAM Registers. The values of these registers are stored in the internal RAM of the MAXQ3183. Some can be read and written by the master, while others are read-only. RAM registers are either 2 or 4 bytes long (16 or 32 bits), although in some registers not all the bits have defined values. Read/write registers are generally either status/flag registers (which can be written by either the MAXQ3183 or the master), configuration registers (which are written by the master and read by the MAXQ3183 firmware), or data registers (which are read-only and are written by the MAXQ3183 firmware and read by the master). • Virtual Registers. These read-only registers are not stored in RAM; instead, they contain values that are calculated on the fly by the MAXQ3183 firmware when the master reads them. These registers are used by the master to obtain values such as phase A, B, and C active, reactive, and apparent power; power factor; and RMS voltage and current, which are calculated from currently collected data on an as-needed basis. Most virtual registers are 8 bytes in length. • Hardware Registers. These registers control core functions of the MAXQ3183 including the ADC and the SPI slave bus controller. Each of these registers (R_ACFG, R_ADCRATE, R_ADCACQ, R_SPICF, and OPMODE0 (bit 4, EXTCLK only)) has a register location in RAM that “shadows” the value of the hardware register. To read from a hardware register, the master must first read from the special command register UPD_MIR (A00h) to copy the values from the hardware registers to the mirror registers in RAM, and then the mirror register in RAM can be read. To write to a hardware register, the master reverses the process by writing to the mirror RAM register and then reading from the special command register UPD_SFR (900h) to copy the values from the mirror registers to the hardware registers. • Special Command Registers. These registers (UPD_SFR and UPD_MIR) do not return meaningful data when read but instead trigger an operation. Reading UPD_SFR causes values to be copied from the mirror registers to hardware, and reading UPD_MIR causes values to be copied from the hardware to mirror registers. ______________________________________________________________________________________ 21 MAXQ3183 SPI clock idle state is low, and data is shifted in and out on the rising edge of SCLK. Once SPI communication with the MAXQ3183 has been established, it is possible to alter the CKPOL and CKPHA format settings (as well as changing the SSEL signal from active low to active high) if desired by writing to the R_SPICF mirror register and then reading from the special command register UPD_SFR to copy the R_SPICF value into the internal SPI configuration register. Whenever the active clock edge is used for sampling (CKPHA = 0), the transfer cycle must be started with assertion of the SSEL signal. This requirement means that the SSEL signal be deasserted and reasserted between successive transfers. Conversely, when the inactive edge is used for sampling (CKPHA = 1), the SSEL signal may remain low through successive transfers, allowing the active clock edge to signal the start of a new transfer. MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Every defined register on the MAXQ3183 has a 12-bit address (from 0 to 4095). This address is used when addressing the register for either a read or write operation. Addresses 0 to 1023 (000h to 3FFh) are used to address RAM registers. Registers with addresses from 1024 to 4095 (400h to FFFh) are used for virtual registers and special command registers. Each command consists of a read/write command code, a data length (1, 2, 4, or 8 bytes), a 12-bit register address, and the specified number of data bytes followed optionally by a cyclic redundancy check (CRC). Since SPI is a full-duplex interface, the master and slave must both transmit the same number of bytes during the command. When a multiple-byte register is read or written (2/4/8 byte length), the least significant byte is read or written first in the command. Every transaction begins with the master sending 2 bytes that contain the command (read or write), the address to access, and the number of bytes to transfer. Every SPI peripheral must return 1 byte for every byte it receives. If the master is reading 1 or more bytes from the MAXQ3183, it must send dummy bytes during the cycles when it is receiving a multibyte response to a request, meeting the “send a byte to get a byte” requirement. But the MAXQ3183 could require time to calculate the result, and thus might not have it ready when the master sends the dummy byte. For this reason, the MAXQ3183 always sends zero or more bytes of a NAK character (0x4E or ASCII ‘N’) followed by an ACK character (0x41, or ASCII ‘A’) before sending the data. If the master is writing 1 or more bytes, it sends the data to be written immediately after sending the command. The MAXQ3183 returns ACK (0x41) for each data byte. It then returns NAK (0x4E) until the write cycle is complete, after which it returns a final ACK. Immediately after the final ACK, the MAXQ3183 is ready to begin the next transaction; there is no need to wait for any other event. It is not even necessary to toggle SSEL to begin the next transaction. The MAXQ3183 knows that the first transaction is over and is ready for the next. If, for whatever reason, it is necessary to reset the communications between the host and the MAXQ3183 (for Table 1. Command Format for SPI Register Read BYTE 1st byte 2nd byte Sync bytes 3rd byte (1st data byte) ... Nth byte (Last data byte) (N + 1) byte 22 TRANSFERS BIT 7:6 Command Code: 00 Read 01 Reserved 10 Write 11 Reserved 5:4 Data Length: 00 1 Byte 01 2 Bytes 10 4 Bytes 11 8 Bytes 3:0 MSB portion of data address. 7:0 LSB portion of data address. Master sends command; Slave sends 0xC1 byte Master sends address; Slave sends 0xC2 byte Master sends dummy; Slave sends ACK (0x41) or NACK (0x4E) byte 7:0 Master sends dummy; Slave sends data 7:0 ... Master sends dummy; Slave sends data Master sends dummy; Slave sends CRC DESCRIPTION Master sends dummy byte; Slave responds with NACK if busy, or with ACK when processing complete. Master must receive ACK, then receive data. Data, LSB ... ... 7:0 Data, MSB 7:0 Optional CRC ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect MAXQ3183 Table 2. Command Format for SPI Register Write BYTE 1st byte 2nd byte 3rd byte (1st data byte) ... TRANSFERS BIT 7:6 Command code: 00 Read 01 Reserved 10 Write 11 Reserved 5:4 Data Length: 00 1 Byte 01 2 Bytes 10 4 Bytes 11 8 Bytes 3:0 MSB portion of data address. 7:0 LSB portion of data address. 7:0 Data, LSB Master sends command; Slave sends 0xC1 byte Master sends address; Slave sends 0xC2 byte Master sends data; Slave sends ACK (0x41) ... DESCRIPTION ... ... Nth byte (Last data byte) Master sends data; Slave sends ACK (0x41) 7:0 Data, MSB (N + 1) byte Master sends CRC; Slave sends ACK (0x41) 7:0 Optional CRC Sync bytes Master sends dummy; Slave sends ACK (0x41) or NACK (0x4E) byte 7:0 example, if synchronization is lost), the host only needs to wait for the SPI to time out before restarting communication from the first command byte. SPI timeout count starts after receiving the first command byte from the master (after the 8th SPI clock of the first byte). The count stops and clears after receiving the last byte of a transaction (after the 8th SPI clock of the last byte). If the timeout count expires (exceeds COM_TIMO) before the transaction completes, the MAXQ3183 abandons the unfinished transaction and resets the SPI logic to be ready for the next transaction. The default SPI timeout is 360ms. Optionally, a CRC byte can be appended to each transaction. For write commands, the CRC byte is sent by the master, and for read commands the CRC byte is sent by the MAXQ3183. The CRC mode is enabled when the CRCEN bit is set to 1 in OPMODE1 register. Otherwise, the MAXQ3183 assumes no CRC byte is used. The 8-bit CRC is calculated for all bytes in a transaction, from the first command byte sent by the Master sends dummy byte; Slave responds with NACK if busy, or with ACK when processing complete. Master must receive ACK before starting the next transaction. master through the last data byte excluding sync bytes, using the polynomial P = x8 + x5 + x4 + 1. If the transmitted CRC byte does not match the calculated CRC byte (for a write command), the MAXQ3183 ignores the command. The length of the transfer is defined by the first command byte and the status of the CRCEN bit in the OPMODE1 register. There is no special synchronization mechanism provided in this simple protocol. Therefore, the master is responsible for sending/receiving the correct number of bytes. If the master mistakenly sends more bytes than are required by the current command, the extra bytes are either ignored (if the MAXQ3183 is busy processing the previous command) or are interpreted as the beginning of a new command. If the master sends fewer bytes than are required by the current command, the MAXQ3183 waits for SPI timeout, then drops the transaction and resets the communication channel. The duration of the timeout can be configured through the COM_TIMO register. ______________________________________________________________________________________ 23 MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect READING DATA FROM MAXQ3183 THROUGH SPI INTERFACE SSEL SCLK MOSI 00 01 ADDRESS 0xC1 MISO 0xC2 DUMMY DUMMY DUMMY DUMMY NACK (0x4E) ACK (0x41) DATA LSB DATA MSB Figure 5. Read SPI Transfer WRITING DATA TO MAXQ3183 THROUGH SPI INTERFACE SSEL SCLK MOSI 10 01 MISO ADDRESS 0xC1 0xC2 DATA LSB DATA MSB DUMMY DUMMY ACK (0x41) ACK (0x41) NACK (0x4E) ACK (0x41) Figure 6. Write SPI Transfer Figures 5 and 6 show typical 2-byte reading and writing transfers (without CRC byte). Host Software Design Individual message bytes sent through the SPI are processed in a software routine contained in the ROM firmware. For this reason, it is necessary to provide a delay between successive bytes. This byte spacing must be no less than 400 system clocks to ensure that the MAXQ3183 has a chance to read and process the byte before the arrival of the next one. It is strongly recommended that CRC be enabled for both read and write to achieve reliable operations. Register Set Data and device command and control information are located in internal registers. Registers range from 8 to 64 bits in length and are divided into RAM-based registers 24 and virtual registers. The RAM-based registers contain both operating parameters and measurement results. To read any virtual power registers, the host must first confirm that the DSPRDY bit of the IRQ_FLAG register is set, which indicates the last DSP cycle has completed, then proceed to reading all the desired virtual power registers. For best communication efficiency, it is recommended to complete reading the virtual power registers before reading other registers. Virtual power register reads must be completed within 50% of DSP cycle time, from the moment DSPRDY bit is set. Do not forget to clear the DSPRDY bit, otherwise, host software is not able to detect the completion of the new DSP cycle. The MAXQ3183 does not clear the bit; it only sets the bit whenever a DSP cycle processing is completed. Users can clear the bit directly after the confirmation that the bit is set. Clearing the DSPRDY bit does not affect the DSP processing. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect SPI TIMEOUT (360ms) SEND COMMAND BYTE 1 SPI TIMEOUT (360ms) SEND COMMAND BYTE 1 N N GET 0xC1? GET 0xC1? DELAY > 400 SYSCLK DELAY > 400 SYSCLK SEND COMMAND BYTE 2 SEND COMMAND BYTE 2 N N GET 0xC2? GET 0xC2? DELAY > 400 SYSCLK DELAY > 400 SYSCLK SEND DATA BYTE SEND 0x00 Y N N GET 0x4E? N GET 0x41? Y GET DATA BYTE EXIT DONE? SEND 0x00 SEND 0x00 DONE? GET 0x41? DELAY > 400 SYSCLK DELAY > 400 SYSCLK N MAXQ3183 WRITE MAXQ3183 READ MAXQ3183 N GET 0x4E? GET 0x41? EXIT Figure 7. Flowchart for Reading from MAXQ3183 Figure 8. Flowchart for Writing to MAXQ3183 The virtual registers contain calculated values derived from one or more real registers. They are calculated at the time they are requested, and thus can involve addi- tional time to return a value. Most virtual registers are 8 bytes in length and are delivered least significant byte first. ______________________________________________________________________________________ 25 MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Table 3. RAM Register Map x0h 0x00 STATUS x1h x2h x3h x4h OP OP OP MODE0 MODE1 MODE2 0x01 AUX_CFG 0x02 PLS1_WD 0x03 AVG_C SYS_KHZ x5h x6h IRQ_FLAG IRQ_MASK VOLT_CC AMP_CC THR1 HPF_C 0x04 NS 0x05 R_ADCACQ 0x06 TEMP_CC R_ SPICF x7h x8h x9h xAh xBh xCh xDh xEh xFh SCAN _IA SCAN _VA SCAN _IC SCAN _VC SCAN _IB SCAN _VB SCAN _IN SCAN _TE PWR_CC ENR_CC PLS2_WD B0FUND THR2 REJ_NS A1FUND B0HARM OCLVL OVLVL UVLVL NOLOAD ISUMLVL COM_TIMO ACC_TIMO ZC_LPF LINEFR PLSCFG PLSCFG 1 2 CYCNT AVG_NS A1HARM R_ACFG R_ADCRATE I1THR I2THR CHKSUM 0x11 N.IRMS 0x12 N.I_GAIN PHASE A CALIBRATION AND STATUS REGISTERS 0x13 A.I_GAIN 0x14 A.V_GAIN A.PA1 A.PA2 A.E_GAIN A. FLAGS A.EF_GAIN A. MASK A.OFFS_HI A.GAIN_LO A.OFFS_LO A.PA0 B.I_GAIN B.V_GAIN B.PA1 B.PA2 C.E_GAIN C.EF_GAIN A. A. EOVER EFOVER PHASE B CALIBRATION AND STATUS REGISTERS 0x21 0x22 0x23 B.E_GAIN B. FLAGS B.EF_GAIN B. MASK B.OFFS_HI B.GAIN_LO B.OFFS_LO B.PA0 B. B. EOVER EFOVER PHASE C CALIBRATION AND STATUS REGISTERS 0x30 0x31 C.I_GAIN C.OFFS_HI C.GAIN_LO C.OFFS_LO C.PA0 C.V_GAIN C.PA1 C.PA2 C. FLAGS C. MASK C. C. EOVER EFOVER 0x32 PHASE A MEASUREMENT REGISTERS* 0x1C 0x1D A.PF A.ACT A.VRMS A.IRMS A.REA A.APP A.ACTF 0x1E A.REAF A.APPF A.EAPOS A.EANEG 0x1F A.ERPOS A.ERNEG A.ES A.EAFPOS 0x20 A.EAFNEG A.ERFPOS A.ERFNEG A.ESF PHASE B MEASUREMENT REGISTERS* 0x2B B.VRMS B.IRMS B.ACT B.REA B.APP B.ACTF B.REAF 0x2D B.APPF B.EAPOS B.EANEG B.ERPOS 0x2E B.ERNEG B.ES B.EAFPOS B.EAFNEG 0x2F B.ERFPOS B.ERFNEG B.ESF 0x2C B.PF PHASE C MEASUREMENT REGISTERS* 0x39 0x3A C.PF C.VRMS C.IRMS C.ACT C.REA 0x3B C.APP C.ACTF C.REAF C.APPF 0x3C C.EAPOS C.EANEG C.ERPOS C.ERNEG 0x3D C.ES C.EAFPOS C.EAFNEG C.ERFPOS 0x3E C.ERFNEG C.ESF *Read-only. 26 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect x0 x1 x2 x3 x4 x7 0x80 PWRP.A PWRP.B PWRP.C PWRP.T 0x81 PWRQ.A PWRQ.B PWRQ.C PWRQ.T 0x82 PWRS.A PWRS.B PWRS.C PWRS.T V.C 0x83 V.HARM V.A V.B 0x84 I.N, I.HARM I.A I.B I.C 0x85 HARM_NF VBPH VCPH 0x86 x9 xA xC THDN.A THDN.B THDN.C PF.T 0x87 ENRS.A ENRS.B ENRS.C ENRS.T 0x88 PWRPF.A PWRPF.B PWRPF.C PWRPF.T 0x89 PWRQF.A PWRQF.B PWRQF.C PWRQF.T 0x8A PWRSF.A PWRSF.B PWRSF.C PWRSF.T 0x8B ENRSF.A ENRSF.B ENRSF.C ENRSF.T 0x8C ENRP.A ENRP.B ENRP.C ENRP.T 0x8D ENRQ.A ENRQ.B ENRQ.C ENRQ.T 0x8E ENRPF.A ENRPF.B ENRPF.C ENRPF.T 0x8F ENRQF.A ENRQF.B ENRQF.C ENRQF.T SPECIAL FUNCTION REGISTERS 0xC0 DSPVER TEMP_C ENTER STOP ENTER LOWPM EXIT LOWPM Note: All virtual registers are read-only. ______________________________________________________________________________________ 27 MAXQ3183 Table 4. Virtual Register Map MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect RAM-Based Registers The RAM-based registers contain both operating parameters and measurement results. They are divided into a number of categories that are described in the following sections. General Operating Registers Global Status Register (STATUS) (0x000) Bit: 7 6 5 4 3 2 1 0 Name: — CROFF PORF WDTR PHSEQI PHSEQV REVCFQ REVCFP Reset: 0 0 0 0 0 0 0 0 This register contains bits that reflect the global status of the device. 28 BIT NAME 7 — FUNCTION 6 CROFF 5 PORF When set, the last reset was due to power-on-reset. Host should clear this bit to allow the next POR detection. 4 WDTR When set, the last reset was caused by expired watchdog. The bit should be cleared (set to 0) by the host to allow the next watchdog reset detection. 3 PHSEQI 0 = The sequence of currents presented to the inputs is (-A-B-C-). 1 = The sequence of currents presented to the inputs is (-A-C-B-). 2 PHSEQV 0 = The sequence of voltages presented to the voltage inputs is (-A-B-C-). 1 = The sequence of voltages presented to the voltage inputs is reversed (-A-C-B-). This bit is meaningful only for connection systems that include all three voltages. 1 REVCFQ 0 = The quantity being output on the CFQ pin is positive (direct). 1 = The quantity being output on the CFQ pin is negative (reverse). 0 REVCFP 0 = The quantity being output on the CFP pin is positive (direct). 1 = The quantity being output on the CFP pin is negative (reverse). Reserved. When set, the high-frequency crystal has failed and the MAXQ3183 is operating from its internal ring oscillator. Under these circumstances, energy accumulation is not accurate and the SPI bus does not operate at full speed. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect 7 6 5 4 3 2 1 0 Name: — — — EXTCLK SWRES DSPDIS LOWPM — Reset: 0 0 0 0 0 0 0 0 BIT NAME 7:5, 0 — 4 EXTCLK When set, the high-frequency crystal oscillator is disabled and the XTAL1 pin is configured to be a clock input for the device. This is used when it is desired to operate multiple devices from the same clock source for purposes of maintaining synchronization. 3 SWRES When set, forces the internal software to restart from the reset vector. This has the same effect as a power-on reset, but does not specifically reset any hardware peripherals. This bit is automatically cleared after the reset. 2 DSPDIS When set, disables the signal processing software routines. The CPU continues to run at full speed, but only to perform supervisory functions (such as servicing the SPI port). LOWPM When set, causes the CPU to switch its clock source from the external crystal to an internal ring oscillator that operates at a nominal frequency of 1MHz. In this mode, the CPU continues to run, but the host must reconfigure the parameters configured for crystal operation (such as filter settings, timeouts, and pulse widths). 1 FUNCTION Reserved. Operating Mode Register 1 (OPMODE1) (0x002) Bit: 7 6 5 4 3 2 1 0 Name: — — — — CRCEN POPOL — — Reset: 0 0 0 0 0 0 0 0 BIT NAME 7:4, 1:0 — 3 CRCEN If set, a 1-byte CRC is appended to the end of each SPI read and is expected at the end of each SPI write. See the SPI Communications Protocol section for details about how to use the CRC byte for error checking on the SPI bus. POPOL This bit sets the polarity of the output pulse generators. If clear, the pulse outputs are active low; that is, they remain in the high state until a pulse event occurs, at which time they switch low for one pulse-width interval before reverting to the high state. If set, the pulse outputs are active high; that is, they remain in the low state until a pulse event occurs, at which time they switch to the high state for one pulse-width interval before reverting to the low state. 2 FUNCTION Reserved. ______________________________________________________________________________________ 29 MAXQ3183 Operating Mode Register 0 (OPMODE0) (0x001) Bit: MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Operating Mode Register 2 (OPMODE2) (0x003) Bit: 7 6 5 4 3 Name: — DHARA DFUNA DFUN — Reset: 0 0 0 0 0 BIT NAME 7, 3 — 6 5 4 2 1 WIRSYS 0 0 Reserved. DHARA When set, disables automatic determination of the filter parameters for the harmonic filter coefficient. If set by the host software, the host must set a value in the A1HARM filter coefficient register to establish the operating frequency of this filter if harmonic-mode calculations are used. When cleared, the MAXQ3183 automatically determines the value of the harmonic filter coefficient based on the measured line frequency and the harmonic-order requested (AUX_CFG.ORDH). DFUNA When set, disables automatic determination of the filter parameters for the fundamental-mode filter. If set by the host software, the host must set a value in the A1FUND filter coefficient register to establish the operating frequency of this filter if fundamental-mode calculations are used. When clear, the MAXQ3183 automatically determines the value of the fundamental-mode filter coefficient based on the measured line frequency. DFUN When set, fundamental-mode calculations are disabled. Fundamental-mode calculations provide information about power and energy that are consumed only at the fundamental line frequency apart from any harmonics that could be present. Setting this bit disables all fundamental frequency registers but allows the MAXQ3183 to calculate other parameters at a higher rate. Set this bit when (1) fundamental mode values do not need to be read, and (2) R_ADCRATE needs to be reduced below its default value. WIRSYS VAB IA 3P3W Wiring (01) IC VCB 30 0 FUNCTION These bits select the coefficient used in calculating apparent power. 00 = 1-phase, 3-wire (1P3W), or 3-phase, 4-wire (3P4W) (C = 1) 01 = 3-phase, 3-wire (3P3W) (C =
3/2) 10 = three voltages, three currents (3V3A) (C =
3/3) 2:1 0 APPSEL ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect BIT NAME FUNCTION V IA 3P4W Wiring (00) N IB IC VB V VAB 3V3A (10) 2:1 VAC IA IB WIRSYS IC VBC VAN IA 1P3W (00) N IB VBN Selects the mechanism to use for calculating apparent power. 0 APPSEL 0: S = VRMS x IRMS Apparent power is calculated by multiplying, on a per-DSP cycle basis, the product of the RMS volts and RMS amps. 1: S = P 2 + Q2 Apparent power is calculated by finding the length of the power vector. ______________________________________________________________________________________ 31 MAXQ3183 Operating Mode Register 2 (OPMODE2) (0x003) (continued) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Global Interrupt Registers Interrupt Request Flag Register (IRQ_FLAG) (0x004) Bit: 15 14 13 12 11 10 9 8 Name: DSPOR DSPRDY DCHR DCHA NOZX UV OV OC Reset: 0 0 0 0 0 0 0 0 Bit: 7 6 5 4 3 2 1 0 Name: — — — — ISUMOVF EOVF CHSCH PWRF Reset: 0 0 0 0 0 0 0 0 The interrupt request flag register contains bits that indicate the reason the IRQ pin has become active. The active bit must be cleared by the host to avoid continuing firing of the interrupt by the MAXQ3183. BIT 32 NAME FUNCTION 15 DSPOR When set, the DSP was unable to complete processing one cycle when another cycle was due to begin. This indicates that the R_ADCRATE is set too low, and that samples are arriving more quickly than they can be processed. Either increase the value of the R_ADCRATE register or set the DFUN bit in the OPMODE2 register to disable fundamental frequency calculations to reduce the load on the DSP. 14 DSPRDY 13 DCHR When set, the direction of reactive energy flow has changed (that is, from capacitive to inductive or from inductive to capacitive). 12 DCHA When set, the direction of real energy flow has changed (that is, from toward the load to away from the load, or from away from the load to toward the load). 11 NOZX When set, the MAXQ3183 has failed to detect zero crossings on one or more voltage channels in one complete DSP cycle. 10 UV When set, the absolute instantaneous voltage level in one or more voltage channels failed to exceed the trip level set in the UVLVL (Undervoltage Level) register for one DSP cycle. 9 OV When set, the absolute instantaneous voltage level in one or more voltage channels has exceeded the trip level set in the OVLVL (Overvoltage Level) register. 8 OC When set, the absolute instantaneous current in one or more current channels has exceeded the trip level set in the OCLVL (Overcurrent Level) register. 7:4 — Reserved. 3 ISUMOVF 2 EOVF 1 CHSCH 0 PWRF Set when the DSP cycle completes. When set, the vector sum of currents (3 or 4) exceeds the threshold. When set, one or more energy accumulators have an MSB overflow condition. When set, indicates a change of the CHKSUM. The CHKSUM is computed over the configuration and calibration data. The host should review a change in CHKSUM because any change in the configuration or calibration data affects the metering operation and accuracy. When set, a power-supply failure is imminent and the supervisory processor should begin taking steps to save its state and prepare for a loss of power. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 15 14 13 12 11 10 9 8 Name: EDSPOR EDSPRDY EDCHR EDCHA ENOZX EUV EOV EOC Reset: 0 0 0 0 0 0 0 0 Bit: 7 6 5 4 3 2 1 0 Name: — — — — EISUM EEOVF ECHSCH EPWRF Reset: 0 0 0 0 0 0 0 0 BIT NAME 15 EDSPOR 14 EDSPRDY 13 EDCHR When set, the DCHR flag causes the IRQ pin to become active. 12 EDCHA When set, the DCHA flag causes the IRQ pin to become active. 11 ENOZX When set, the NOZX flag causes the IRQ pin to become active. 10 EUV When set, the UV flag causes the IRQ pin to become active. 9 EOV When set, the OV flag causes the IRQ pin to become active. 8 EOC 7:4 — 3 EISUM FUNCTION When set, the DSPOR flag causes the IRQ pin to become active. When set, the DSPRDY flag causes the IRQ pin to become active. When set, the OC flag causes the IRQ pin to become active. Reserved. 2 EEOVF 1 ECHSCH 0 EPWRF When set, the ISUMOVF flag causes the IRQ pin to become active. When set, the EOVF flag causes the IRQ pin to become active. When set, the CHSCH flag enables the IRQ pin to become active. When set, the PWRF flag causes the IRQ pin to become active. ______________________________________________________________________________________ 33 MAXQ3183 Interrupt Mask Register (IRQ_MASK) (0x006) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Meter Pulse Configuration Pulse Configuration—CFP Output (PLSCFG1) (0x01E) Bit: 7 6 5 4 3 2 1 0 Name: QNSEL PHASEC PHASEB PHASEA Reset: 0x0 0 0 0 This register selects which phases are included in the CFP pulse output and also selects which quantity is accumulated to drive the pulse output. BIT 34 NAME FUNCTION 7:3 QNSEL CFP Pulse Output Source Select. This five-bit field determines what meter value will be accumulated in each of the phases to produce the CFP pulse output. All other values are reserved. 00000 = Net real energy 00001 = Absolute real energy 00010 = Net reactive energy 00011 = Absolute reactive energy 00100 = Apparent energy 00110 = IRMS 00111 = VRMS 01000 = Real energy delivered to load 01001 = Real energy delivered to line 01010 = Reactive energy, quadrant I 01011 = Reactive energy, quadrant II 01100 = Reactive energy, quadrant III 01101 = Reactive energy, quadrant IV 2 PHASEC CFP Phase C Inclusion. When this bit is set, phase C is included in CFP pulse generation. 1 PHASEB CFP Phase B Inclusion. When this bit is set, phase B is included in CFP pulse generation. 0 PHASEA CFP Phase A Inclusion. When this bit is set, phase A is included in CFP pulse generation. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 2 1 0 Name: 7 6 QNSEL 5 4 3 PHASEC PHASEB PHASEA Reset: 0x0 0 0 0 This register selects which phases are included in the CFQ pulse output and also selects which quantity is accumulated to drive the pulse output. BIT NAME FUNCTION CFQ Pulse Output Source Select. This five-bit field determines what meter value is accumulated in each of the phases to produce the CFQ pulse output. All other values are reserved. 00000 = Net real energy 00001 = Absolute real energy 00010 = Net reactive energy 00011 = Absolute reactive energy 00100 = Apparent energy 00110 = IRMS 00111 = VRMS 01000 = Real energy delivered to load 01001 = Real energy delivered to line 01010 = Reactive energy, quadrant I 01011 = Reactive energy, quadrant II 01100 = Reactive energy, quadrant III 01101 = Reactive energy, quadrant IV 7:3 QNSEL 2 PHASEC CFQ Phase C Inclusion. When this bit is set, phase C is included in CFQ pulse generation. 1 PHASEB CFQ Phase B Inclusion. When this bit is set, phase B is included in CFQ pulse generation. 0 PHASEA CFQ Phase A Inclusion. When this bit is set, phase A is included in CFQ pulse generation. CFP Pulse Width (PLS1_WD) (0x020) Bit: 15 14 13 12 11 Name: CFP Pulse-Width High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: CFP Pulse-Width Low Byte Reset: 0x9C 10 9 8 2 1 0 This register designates the width of the CFP pulse, that is, the duration of the period that the CFP pulse is in the active state. This value is given in ADC frame times (about 360μs). The default value of 0x9C (156 decimal) provides a pulse width of about 50ms. ______________________________________________________________________________________ 35 MAXQ3183 Pulse Configuration—CFQ Output (PLSCFG2) (0x01F) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect CFP Pulse Threshold (THR1) (0x022) Bit: 31 30 29 28 27 Name: THR1 Byte 3 Reset: 0x00 Bit: 23 22 21 20 19 Name: THR1 Byte 2 Reset: 0x10 Bit: 15 14 13 12 11 Name: THR1 Byte 1 Reset: 0x00 Bit: 7 6 5 4 3 Name: THR1 Byte 0 Reset: 0x00 26 25 24 18 17 16 10 9 8 2 1 0 This register designates the threshold of the CFP pulse. This value is used to set the meter constant for the CFP pulse output. When the CFP pulse accumulator exceeds the value set in this register, the CFP pulse output is activated and the CFP pulse accumulator is reduced by the amount in this register. CFQ Pulse Width (PLS2_WD) (0x026) Bit: 15 14 13 12 11 Name: CFQ Pulse-Width High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: CFQ Pulse-Width Low Byte Reset: 0x9C 10 9 8 2 1 0 This register designates the width of the CFQ pulse; that is, the duration of the period that the CFQ pulse is in the active state. This value is given in ADC frame times (about 360μs). The default value of 0x9C (156 decimal) provides a pulse width of about 50ms. 36 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect 31 30 29 28 27 Name: THR2 Byte 3 Reset: 0x00 Bit: 23 22 21 20 19 Name: THR2 Byte 2 Reset: 0x10 Bit: 15 14 13 12 11 Name: THR2 Byte 1 Reset: 0x00 Bit: 7 6 5 4 3 Name: THR2 Byte 0 Reset: 0x00 26 25 24 18 17 16 10 9 8 2 1 0 This register designates the threshold of the CFQ pulse. This value is used to set the meter constant for the CFQ pulse output. When the CFQ pulse accumulator exceeds the value set in this register, the CFQ pulse output is activated and the CFQ pulse accumulator is reduced by the amount in this register. Calibration Registers Current Gain, Phase X = A/B/C/N (X.I_GAIN) (A: 0x130, B: 0x21C, C: 0x308, N: 0x12E) Bit: 15 14 13 12 11 Name: Current Gain Coefficient High Byte Reset: 0x40 Bit: 7 6 5 4 3 Name: Current Gain Coefficient Low Byte Reset: 0x00 10 9 8 2 1 0 This register contains gain coefficient for phase X current channel. The raw values are taken from the selected measurement quantity and scaled by the factor: X.I _ GAIN 2 14 Note: Bit 15 of this register must be set to zero for correct operation. ______________________________________________________________________________________ 37 MAXQ3183 CFQ Pulse Threshold (THR2) (0x028) Bit: MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Voltage Gain, Phase X = A/B/C (X.V_GAIN) (A: 0x132, B: 0x21E, C: 0x30A) Bit: 15 14 13 12 11 Name: Voltage Gain Coefficient High Byte Reset: 0x40 Bit: 7 6 5 4 3 Name: Voltage Gain Coefficient Low Byte Reset: 0x00 10 9 8 2 1 0 This register contains gain coefficient for phase X voltage channel. The raw values are taken from the selected measurement quantity and scaled by the factor: X.V _ GAIN 2 14 Note: Bit 15 of this register must be set to zero for correct operation. Energy Gain, Phase X = A/B/C (X.E_GAIN) (A: 0x134, B: 0x220, C: 0x30C) Bit: 15 14 13 12 11 Name: Energy Gain Coefficient High Byte Reset: 0x40 Bit: 7 6 5 4 3 Name: Energy Gain Coefficient Low Byte Reset: 0x00 10 9 8 2 1 0 This register contains gain coefficient for phase X energy. The raw values are taken from the selected measurement quantity and scaled by the factor: X.E _ GAIN 2 14 Note: Bit 15 of this register must be set to zero for correct operation. Phase-Angle Compensation, High Range, Phase X = A/B/C (X.PA0) (A: 0x13E, B: 0x22A, C: 0x316) Bit: 15 14 13 12 11 Name: Phase-Angle Offset High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Phase-Angle Offset Low Byte Reset: 0x00 10 9 8 2 1 0 This signed register contains the angle as a fraction of one radian to add to the measured phase angle when the measured current is above the value given in I1THR. This signed value ranges from -0.5 radian (at a value of 0x8000) to +(0.5 - 2-16) radian (at a value of 0x7FFF). 38 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 15 14 13 12 11 Name: Phase-Angle Offset High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Phase-Angle Offset Low Byte Reset: 0x00 10 9 8 2 1 0 This signed register contains the angle, as a fraction of one radian, to add to the measured phase angle when the measured current is between the values given in I1THR and I2THR. This signed value ranges from -0.5 radian (at a value of 0x8000) to +(0.5 - 2-16) radian (at a value of 0x7FFF). Phase-Angle Compensation, Low Range, Phase X = A/B/C (X.PA2) (A: 0x142, B: 0x22E, C: 0x31A) Bit: 15 14 13 12 11 Name: Phase-Angle Offset High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Phase-Angle Offset Low Byte Reset: 0x00 10 9 8 2 1 0 This signed register contains the angle, as a fraction of one radian, to add to the measured phase angle when the measured current is below the value given in I2THR. This signed value ranges from -0.5 radian (at a value of 0x8000) to +(0.5 - 2-16) radian (at a value of 0x7FFF). Limit Registers Overcurrent Level (OCLVL) (0x044) Bit: 15 14 13 12 11 Name: Overcurrent Level High Byte Reset: 0xFF Bit: 7 6 5 4 3 Name: Overcurrent Level Low Byte Reset: 0xFF 10 9 8 2 1 0 This register specifies the fraction of full-scale current that is declared to be an overcurrent condition. When X.IRMS exceeds this level for one DSP cycle, the OCF flag in the X.FLAGS register is set. If the OCM flag is set in the X.MASK register, setting the OCF flag will cause the interrupt bit OC to be set in the IRQ_FLAG register. If the interrupt is enabled, the interrupt pin is driven active. Full scale is represented by 0x10000. The maximum value for this register is 0xFFFF. ______________________________________________________________________________________ 39 MAXQ3183 Phase-Angle Compensation, Medium Range, Phase X = A/B/C (X.PA1) (A: 0x140, B: 0x22C, C: 0x318) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Overvoltage Level (OVLVL) (0x046) Bit: 15 14 13 12 11 Name: Overvoltage Level High Byte Reset: 0xFF Bit: 7 6 5 4 3 Name: Overvoltage Level Low Byte Reset: 0xFF 10 9 8 2 1 0 This register specifies the fraction of full-scale voltage that is declared to be an overvoltage condition. When X.VRMS exceeds this level for one DSP cycle, the OVF flag in the X.FLAGS register is set. If the OVM flag is set in the X.MASK register, setting the OVF flag will cause the interrupt bit OV to be set in the IRQ_FLAG register. If the interrupt is enabled, the interrupt pin is driven active. Full scale is represented by 0x10000. The maximum value for this register is 0xFFFF. Undervoltage Level (UVLVL) (0x048) Bit: 15 14 13 12 11 Name: Undervoltage Level High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Undervoltage Level Low Byte Reset: 0x00 10 9 8 2 1 0 This register specifies the fraction of full-scale voltage below which an undervoltage condition is declared. When X.VRMS falls below this level for one DSP cycle, the UVF flag in the X.FLAGS register is set. If the UVM flag is set in the X.MASK register, setting the UVF flag will cause the interrupt bit UV to be set in the IRQ_FLAG register. If the interrupt is enabled, the interrupt pin is driven active. Full scale is represented by 0x10000. The maximum value for this register is 0xFFFF. No-Load Level (NOLOAD) (0x04A) Bit: 15 14 13 12 11 Name: No-Load Level High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: No-Load Level Low Byte Reset: 0x03 10 9 8 2 1 0 This register specifies the fraction of full-scale current below which a no-load condition is declared. When X.IRMS falls below this level, the MAXQ3183 no longer accumulates power for phase X. Full scale is represented by 0x10000. The maximum value for this register is 0xFFFF. 40 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 15 14 13 12 11 Name: Vector Sum Threshold High Byte Reset: 0xFF Bit: 7 6 5 4 3 Name: Vector Sum Threshold Low Byte Reset: 0xFF 10 9 8 2 1 0 This register specifies the threshold value for the vector sum (of three phase currents or three phase currents plus the neutral current, configurable in the AUX_CFG register) as a fraction of the full-scale current. When the vector sum (RMS) value exceeds this threshold value in one DSP cycle, the ISUMOVF flag in the IRQ_FLAG register is set. If the IRQ_MASK.EISUM bit is set, the interrupt pin is driven active. The host must clear the interrupt flag. Full scale is represented by 0x10000. The maximum value allowed is 0xFFFF. Phase Status Registers Interrupt Flags, Phase X = A/B/C (X.FLAGS) (A: 0x144, B: 0x230, C: 0x31C) Bit: 7 6 5 4 3 2 1 0 Name: — — DCHRF DCHAF NOZXF UVF OVF OCF Reset: 0 0 0 0 0 0 0 0 The X.FLAGS register contains condition flags that relate to the function of phase X (A/B/C) measurements. Once set, these bits can be cleared only by the host. BIT NAME FUNCTION 7:6 — 5 DCHRF Reactive Energy Direction Change. Set when the direction of reactive power flow changes (from capacitive to inductive or from inductive to capacitive). If the DCHRM bit is set, this bit sets the DCHR flag in the IRQ_FLAG register. 4 DCHAF Real Energy Direction Change. Set when the direction of real power flow changes (from toward the load to toward the line, or from toward the line to toward the load). If the DCHAM bit is set, this bit sets the DCHA flag in the IRQ_FLAG register. 3 NOZXF No-Zero Crossing. Set when the voltage waveform in phase X fails to exhibit a zero crossing during one DSP cycle. If the NOZXM bit is set, this bit sets the NOZX flag in the IRQ_FLAG register. 2 UVF Undervoltage. Set when the RMS voltage in phase X falls below the undervoltage threshold set in UVLVL. If the UVM bit is set, this bit sets the UV flag in the IRQ_FLAG register. 1 OVF Overvoltage. Set when the RMS voltage in phase X exceeds the overvoltage threshold set in OVLVL. If the OVM bit is set, this bit sets the OV flag in the IRQ_FLAG register. 0 OCF Overcurrent. Set when the RMS current in phase X exceeds the overcurrent threshold set in OCLVL. If the OCM bit is set, this bit sets the OC flag in the IRQ_FLAG register. Reserved. ______________________________________________________________________________________ 41 MAXQ3183 Current Vector Sum Threshold (ISUMLVL) (0x054) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Interrupt Mask, Phase X = A/B/C (X.MASK) (A: 0x145, B: 0x231, C: 0x31D) Bit: 7 6 5 4 3 2 1 0 Name: DIR_R DIR_A DCHRM DCHAM NOZXM UVM OVM OCM Reset: 0 0 0 0 0 0 0 0 BIT NAME 7 DIR_R Reactive Energy Direction Status 0 = positive 1 = negative 6 DIR_A Active Energy Direction Status 0 = positive 1 = negative 5 DCHRM Reactive Energy Direction Change Mask. If set, a change in reactive power direction on phase X causes the DCHR flag in the IRQ_FLAG register to be set. 4 DCHAM Real Energy Direction Change Mask. If set, a change in real power direction on phase X causes the DCHA flag in the IRQ_FLAG register to be set. 3 NOZXM No-Zero Crossing Mask. If set, a no-zero crossing on phase X causes the NOZX flag in the IRQ_FLAG register to be set. 2 UVM Undervoltage Mask. If set, an undervoltage condition on phase X causes the UV flag in the IRQ_FLAG register to be set. 1 OVM Overvoltage Mask. If set, an overvoltage condition on phase X causes the OV flag in the IRQ_FLAG register to be set. 0 OCM Overcurrent Mask. If set, an overcurrent condition on phase X causes the OC flag in the IRQ_FLAG register to be set. FUNCTION Energy Overflow Flags, Phase X = A/B/C (X.EOVER) (A: 0x146, B: 0x232, C: 0x31E) Bit: 7 6 5 4 3 2 1 0 Name: — — — SOV RNOV RPOV ANOV APOV Reset: 0 0 0 0 0 0 0 0 These bits indicate that an overflow condition has occurred on an energy accumulator. An overflow condition is not an error condition. Rather, it simply indicates that the value in the energy accumulator could be smaller than the previous reading due to the overflow in the counter. To obtain the actual energy usage since the previous reading, 0x100000000 must be added to the difference. These bits, once set, can be cleared only by the host. 42 BIT NAME 7:5 — FUNCTION 4 SOV 3 RNOV When set, indicates an overflow condition on the reactive negative energy accumulator. 2 RPOV When set, indicates an overflow condition on the reactive positive energy accumulator. 1 ANOV When set, indicates an overflow condition on the real negative energy accumulator. 0 APOV When set, indicates an overflow condition on the real positive energy accumulator. Reserved. When set, indicates an overflow condition on the apparent energy accumulator. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Line Frequency (LINEFR) (0x062) Bit: 15 14 13 Name: 12 11 10 9 8 2 1 0 Line Frequency High Byte Reset: Bit: 7 6 5 Name: 4 3 Line Frequency Low Byte Reset: Line frequency, LSB = 0.001Hz. Power Factor, Phase X = A/B/C (X.PF) (A: 0x1C6, B: 0x2B2, C: 0x39E) Bit: 15 14 13 12 11 Name: Power Factor High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Power Factor Low Byte Reset: 0x00 10 9 8 2 1 0 Power factor of phase A/B/C, LSB = 1/214. Note that the power factors are signed integers, and a negative value indicates a reversed power flow direction. RMS Voltage, Phase X = A/B/C (X.VRMS) (A: 0x1C8, B: 0x2B4, C: 0x3A0) Bit: 31 30 29 Name: Bit: 23 22 21 Name: 26 25 24 20 19 18 17 16 10 9 8 2 1 0 RMS Voltage Byte 2 15 14 13 Name: Bit: 27 RMS Voltage Byte 3 Name: Bit: 28 12 11 RMS Voltage Byte 1 7 6 5 4 3 RMS Voltage Byte 0 This register provides the raw RMS voltage over the most recent DSP cycle, LSB = VFS/224. ______________________________________________________________________________________ 43 MAXQ3183 Measurements MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect RMS Current, Phase X = A/B/C (X.IRMS) (A: 0x1CC, B: 0x2B8, C: 0x3A4) Bit: 31 30 29 Name: Bit: 23 22 21 Name: Bit: 27 26 25 24 20 19 18 17 16 10 9 8 2 1 0 RMS Current Byte 2 15 14 13 Name: Bit: 28 RMS Current Byte 3 12 11 RMS Current Byte 1 7 6 5 Name: 4 3 RMS Current Byte 0 This register provides the raw RMS current over the most recent DSP cycle, LSB = IFS/224. Energy, Real Positive, Phase X = A/B/C (X.EAPOS) (A: 0x1E8, B: 0x2D4, C: 0x3C0) Bit: 31 30 29 Name: Bit: 22 21 Name: 14 13 Name: 25 24 20 19 18 17 16 12 11 10 9 8 2 1 0 Real Energy Byte 1 7 Name: 26 Real Energy Byte 2 15 Bit: 27 Real Energy Byte 3 23 Bit: 28 6 5 4 3 Real Energy Byte 0 On every DSP cycle, the contents of the X.ACT register are tested, and, if positive, are added to this register. When this register overflows, the APOV bit in the X.EOVER register is set. 44 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 31 30 29 Name: Bit: 23 22 21 Name: Bit: 27 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Real Energy Byte 2 15 14 13 Name: Bit: 28 Real Energy Byte 3 12 11 Real Energy Byte 1 7 6 5 Name: 4 3 Real Energy Byte 0 On every DSP cycle, the contents of the X.ACT register are tested, and, if negative, absolute values are added to this register. When this register overflows, the ANOV bit in the X.EOVER register is set. Energy, Reactive Positive, Phase X = A/B/C (X.ERPOS) (A: 0x1F0, B: 0x2DC, C: 0x3C8) Bit: 31 30 29 Name: Bit: 23 22 21 Name: Bit: Name: 27 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Reactive Energy Byte 2 15 14 13 Name: Bit: 28 Reactive Energy Byte 3 12 11 Reactive Energy Byte 1 7 6 5 4 3 Reactive Energy Byte 0 On every DSP cycle, the contents of the X.REA register are tested, and, if positive, are added to this register. When this register overflows, the RPOV bit in the X.EOVER register is set. ______________________________________________________________________________________ 45 MAXQ3183 Energy, Real Negative, Phase X = A/B/C (X.EANEG) (A: 0x1EC, B: 0x2D8, C: 0x3C4) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Energy, Reactive Negative, Phase X = A/B/C (X.ERNEG) (A: 0x1F4, B: 0x2E0, C: 0x3CC) Bit: 31 30 29 Name: Bit: 23 22 21 Name: Bit: 27 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Reactive Energy Byte 2 15 14 13 Name: Bit: 28 Reactive Energy Byte 3 12 11 Reactive Energy Byte 1 7 6 5 Name: 4 3 Reactive Energy Byte 0 On every DSP cycle, the contents of the X.REA register are tested, and, if negative, absolute values are added to this register. When this register overflows, the RNOV bit in the X.EOVER register is set. Energy, Apparent, Phase X = A/B/C (X.ES) (A: 0x1F8, B: 0x2E4, C: 0x3D0) Bit: 31 30 29 Name: Bit: 23 22 21 Name: Bit: 15 26 25 24 20 19 18 17 16 14 13 12 11 10 9 8 2 1 0 Apparent Energy Byte 1 7 Name: 27 Apparent Energy Byte 2 Name: Bit: 28 Apparent Energy Byte 3 6 5 4 3 Apparent Energy Byte 0 On every DSP cycle, the contents of the X.APP register are added to this register. When this register overflows, the SOV bit in the X.EOVER register is set. 46 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Voltage Units Conversion Coefficient (VOLT_CC) (0x014) Bit: 15 14 13 12 11 10 Name: Voltage Units Conversion Coefficient High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Voltage Units Conversion Coefficient Low Byte Reset: 0x01 9 8 1 0 This register contains the value by which the raw voltage value in each phase (A.VRMS, B.VRMS, and C.VRMS) is multiplied before being presented to the virtual RMS voltage registers (V.A, V.B, and V.C). To determine the value of VOLT_CC, a voltage value for the least significant bit (VOLT_LSB) of the V.X registers must be selected. Typical values might range from 1mV to 1nV. To avoid significant conversion loss, VOLT_LSB should be chosen such that VOLT_CC is >1000. Once VOLT_LSB is determined, calculate VOLT_CC from the following equation: VOLT _ CC = VFS 24 2 × VOLT _ LSB Current Units Conversion Coefficient (AMP_CC) (0x016) Bit: 15 14 13 12 11 10 Name: Current Units Conversion Coefficient High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Current Units Conversion Coefficient Low Byte Reset 0x01 9 8 1 0 This register contains the value by which the raw current value in each phase (A.IRMS, B.IRMS, C.IRMS, and N.IRMS) is multiplied before being presented to the virtual RMS current registers (I.A, I.B, I.C, and I.N). To determine the value of AMP_CC, a current value for the least significant bit (AMP_LSB) of the I.X registers must be selected. Typical values might range from 1nA to 10μA. To avoid significant conversion loss, AMP_LSB should be chosen such that AMP_CC is >1000. Once determined, calculate AMP_CC from the following equation: AMP _ CC = IFS 24 2 × AMP _ LSB ______________________________________________________________________________________ 47 MAXQ3183 Virtual Register Conversion Coefficients MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Power Units Conversion Coefficient (PWR_CC) (0x018) Bit: 15 14 13 12 11 10 Name: Power Units Conversion Coefficient High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Power Units Conversion Coefficient Low Byte Reset: 0x01 9 8 1 0 This register contains the value by which the raw power value in each phase is multiplied before being presented to the virtual power registers. The table below lists the raw power registers and the corresponding virtual registers. DESCRIPTION RAW VIRTUAL Real power, phase A A.ACT PWRP.A Real power, phase B B.ACT PWRP.B Real power, phase C C.ACT PWRP.C Real power, total — PWRP.T Reactive power, phase A A.REA PWRQ.A Reactive power, phase B B.REA PWRQ.B Reactive power, phase C C.REA PWRQ.C — PWRQ.T A.APP PWRS.A Reactive power, total Apparent power, phase A Apparent power, phase B B.APP PWRS.B Apparent power, phase C C.APP PWRS.C — PWRS.T Real power, phase A, fundamental frequency only A.ACTF PWRPF.A Real power, phase B, fundamental frequency only B.ACTF PWRPF.B Real power, phase C, fundamental frequency only C.ACTF PWRPF.C Apparent power, total Real power, total, fundamental frequency only Reactive power, phase A, fundamental frequency only — PWRPF.T A.REAF PWRQF.A Reactive power, phase B, fundamental frequency only B.REAF PWRQF.B Reactive power, phase C, fundamental frequency only C.REAF PWRQF.C — PWRQF.T Apparent power, phase A, fundamental frequency only A.APPF PWRSF.A Apparent power, phase B, fundamental frequency only B.APPF PWRSF.B Apparent power, phase C, fundamental frequency only C.APPF PWRSF.C — PWRSF.T Reactive power, total, fundamental frequency only Apparent power, total, fundamental frequency only PWR_CC establishes the amount of power represented by one PWR_LSB of the power registers. To avoid significant conversion loss, PWR_LSB should be chosen such that PWR_CC is > 1000. Calculate the value of PWR_CC according to the following formula: PWR _ CC = 48 IFS × VFS 32 2 × PWR _ LSB ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect 15 14 13 12 11 10 Name: Energy Units Conversion Coefficient High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Energy Units Conversion Coefficient Low Byte Reset: 0x01 9 8 1 0 This register contains the value by which the raw accumulated energy value in each phase is multiplied before being presented to the virtual energy registers. The table below lists the raw energy accumulators and the corresponding virtual registers. DESCRIPTION RAW Real energy, phase A, positive direction A.EAPOS Real energy, phase A, reverse direction A.EANEG Real energy, phase B, positive direction B.EAPOS Real energy, phase B, reverse direction B.EANEG Real energy, phase C, positive direction C.EAPOS Real energy, phase C, reverse direction C.EANEG Real energy, total — Reactive energy, phase A, positive direction A.ERPOS Reactive energy, phase A, reverse direction A.ERNEG Reactive energy, phase B, positive direction B.ERPOS Reactive energy, phase B, reverse direction B.ERNEG Reactive energy, phase C, positive direction C.ERPOS Reactive energy, phase C, reverse direction C.ERNEG Reactive energy, total VIRTUAL ENRP.A* ENRP.B* ENRP.C* ENRP.T ENRQ.A* ENRQ.B* ENRQ.C* — ENRQ.T Apparent energy, phase A A.ES ENRS.A Apparent energy, phase B B.ES ENRS.B Apparent energy, phase C C.ES ENRS.C — ENRS.T Apparent energy, total Real energy, phase A, positive direction, fundamental only A.EAFPOS Real energy, phase A, reverse direction, fundamental only A.EAFNEG Real energy, phase B, positive direction, fundamental only B.EAFPOS Real energy, phase B, reverse direction, fundamental only B.EAFNEG Real energy, phase C, positive direction, fundamental only C.EAFPOS Real energy, phase C, reverse direction, fundamental only C.EAFNEG Real energy, total, fundamental only — Reactive energy, phase A, positive direction, fundamental only A.ERFPOS Reactive energy, phase A, reverse direction, fundamental only A.ERFNEG Reactive energy, phase B, positive direction, fundamental only B.ERFPOS Reactive energy, phase B, reverse direction, fundamental only B.ERFNEG ENRPF.A* ENRPF.B* ENRPF.C* ENRPF.T ENRQF.A* ENRQF.B* *These registers represent the algebraic sum of the positive and reverse energy in the two “raw” registers noted. Thus, the energy returned in these virtual registers represents the net energy. ______________________________________________________________________________________ 49 MAXQ3183 Energy Units Conversion Coefficient (ENR_CC) (0x01A) Bit: MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Energy Units Conversion Coefficient (ENR_CC) (0x01A) (continued) DESCRIPTION RAW Reactive energy, phase C, positive direction, fundamental only C.ERFPOS Reactive energy, phase C, reverse direction, fundamental only C.ERFNEG Reactive energy, total, fundamental only Apparent energy, phase A, fundamental only VIRTUAL ENRQF.C* — ENRQF.T A.ESF ENRSF.A Apparent energy, phase B, fundamental only B.ESF ENRSF.B Apparent energy, phase C, fundamental only C.ESF ENRSF.C — ENRSF.T Apparent energy, total, fundamental only *These registers represent the algebraic sum of the positive and reverse energy in the two “raw” registers noted. Thus, the energy accumulated in these virtual registers represents the net energy. To avoid significant conversion loss, ENR_LSB should be chosen such that ENR_CC is > 1000. Calculate the value of ENR_CC according to the following formula: I × VFS × t FR ENR _ CC = FS 2 16 × ENR _ LSB Temperature Conversion Coefficient (TEMP_CC) (0x060) Bit: 15 14 13 12 11 10 Name: Temperature Conversion Coefficient High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Temperature Conversion Coefficient Low Byte Reset: 0x00 9 8 1 0 This register contains the temperature conversion coefficient that is applied to convert the temperature sensor binary output into degrees Celsius, per the following equation, where RAW_TEMP is the raw temperature sensor output. T_C = RAW_TEMP x TEMP_CC/216 - 273.15 Note that TEMP_CC should be obtained by calibrating the temperature sensor at the desired operation condition. Typical approximate value is TEMP_CC = 0x0426. To read temperature, use the special register command 0xC01. 50 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect The virtual registers are calculated values derived from one or more real registers. They are calculated at the time they are requested, and thus could involve additional time to return a value. Most virtual registers are 8 bytes in length and are delivered least significant byte first. Power Real Power, Phase X = A/B/C/T (PWRP.X) (A: 0x801, B: 0x802, C: 0x804, T: 0x807) This signed register contains the real instantaneous power delivered into phase A/B/C or total. Power is calculated from the instantaneous energy measurement according to the following equation: PWRP.X = X.ACT × PWR _ CC × 2 16 NS The register is 8 bytes long, but the most significant 2 bytes are not used. See the PWR_CC register description for more details. Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) Note that the sign bit is bit 47 for all 8-byte signed virtual registers. Reactive Power, Phase X = A/B/C/T (PWRQ.X) (A: 0x811, B: 0x812, C: 0x814, T: 0x817) This signed register contains the reactive instantaneous power delivered into phase A/B/C or total. Power is calculated from the instantaneous energy measurement according to the following equation: PWRQ.X = X.REA × PWR _ CC × 2 16 NS The register is 8 bytes long, but the most signficant 2 bytes are not used. See the PWR_CC register description for more details. Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) ______________________________________________________________________________________ 51 MAXQ3183 Virtual Registers MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Apparent Power, Phase X = A/B/C/T (PWRS.X) (A: 0x821, B: 0x822, C: 0x824, T: 0x827) This register contains the apparent instantaneous power delivered into phase A/B/C or total. Power is calculated from the instantaneous energy measurement according to the following equation: PWRS.X = X.APP × PWR _ CC × 2 16 NS The register is 8 bytes long, but the most significant 2 bytes are not used. See the PWR_CC register description for more details. Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) Voltage and Current RMS Volts, Phase X = A/B/C (V.X) (A: 0x831, B: 0x832, C: 0x834) This register contains the RMS voltage on phase A/B/C. The units are defined by the VOLT_CC setting such that V.X = X.VRMS x VOLT_CC. In this equation, VOLT_CC is the conversion coefficient. See the VOLT_CC register for more information. Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) RMS Amps, Phase X = A/B/C/N (I.X) (A: 0x841, B: 0x842, C: 0x844, N: 0x840) This register contains the RMS current on phase A/B/C or the neutral channel. The units are defined by the AMP_CC setting such that I.X = X.IRMS x AMP_CC. In this equation, AMP_CC is the conversion coefficient. See the AMP_CC register for more information. 52 Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect This signed register contains the power factor of the total power. The power factor is calculated as: PF.T = A.ACT + B.ACT + C.ACT A.APP + B.APP + C.APP It is expressed in units of 0.00001; thus, unity power factor is expressed as decimal 100,000 (0x00000000000186A0). This register is presented as a two’s complement value, so that a load delivering real power to the line (that is, reverse power) is seen as having a power factor of -1 (0x0000FFFFFFFE7960). Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) Energy Real Energy, Phase A/B/C/T (ENRP.X) (A: 0x8C1, B: 0x8C2, C: 0x8C4, T: 0x8C7) This signed register contains the real accumulated energy delivered into phase A/B/C or total. The register is calculated according to the following formula: ENRP.X = ENR_CC x (X.EAPOS - X.EANEG) Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) Reactive Energy, Phase A/B/C/T (ENRQ.X) (A: 0x8D1, B: 0x8D2, C: 0x8D4, T: 0x8D7) This signed register contains the reactive accumulated energy delivered into phase A/B/C or total. The register is calculated according to the following formula: ENRQ.X = ENR_CC x (X.ERPOS - X.ERNEG) Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) Apparent Energy, Phase A/B/C/T (ENRS.X) (A: 0x871, B: 0x872, C: 0x874, T: 0x877) This register contains the apparent accumulated energy delivered into phase A/B/C or total. The register is the product of the ENR_CC and X.ES registers. Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) ______________________________________________________________________________________ 53 MAXQ3183 Power Factor Power Factor (PF.T) (0x867) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Theory of Operation Analog Front-End Operation Whenever the MAXQ3183 is in one of the active operating modes (Run Mode or LOWPM Mode), the analog front-end operates continuously, scanning up to eight scan slots depending on the selected front-end configuration. For each analog scan slot that is enabled, one of the eight differential input pairs is measured. The SCAN_IX and SCAN_VX (X = A/B/C), SCAN_IN, and SCAN_TE registers contain the settings for each slot, which include whether the slot is enabled and the differential input pair to measure during that scan slot. The logical mapping of the slots is fixed in following order: • Slot 0—Phase A Current (IA) • Slot 1—Phase A Voltage (VA) • • • • Slot 2—Phase C Current (IC) Slot 3—Phase C Voltage (VC) Slot 4—Phase B Current (IB) Slot 5—Phase B Voltage (VB) • Slot 6—Neutral Current (IN)—disabled by default • Slot 7—Temperature Measurement—disabled by default The required time for each analog scan slot measurement (t C ) is determined by the MAXQ3183 system clock frequency and the setting of the R_ADCRATE hardware register, as shown below: tC = 1/fCLK x (R_ADCRATE[8:0] + 1) Using the default register settings (R_ADCRATE = 167h = 359d), the time for each analog slot measurement (tC) is 45μs when the MAXQ3183 is running at 8MHz. Since there are eight analog scan slots in the measurement frame, the total time for all measurements (tFR) is tC x 8. Using the default settings with the MAXQ3183 running at 8MHz, the entire sequence of measurements takes 360μs to complete, which, in turn, means that 360μs will elapse, for example, between one phase A current measurement and the next. Even if some of the analog measurement slots (such as neutral current or temperature measurement) are skipped by setting the DADCNV bit in that slot’s register to 1, the time period for that slot will remain in the frame, ensuring that the total frame time is always tC x 8, regardless of which individual slots are enabled or disabled. 54 Digital Signal Processing (DSP) Terminology Establishing the precise definitions of some of the terms used in this document will assist in understanding how the DSP functions. Sample Period: The amount of time required to measure a single data element; 45μs, by default. ADC Frame Period: The amount of time required for the ADC to sample all analog inputs; always equal to 8 sample periods. The inverse of this value is the frame rate; by default 2778 samples per second. This is the rate at which any particular signal is sampled by the MAXQ3183. Line Cycle: The period of time from one positive-going zero crossing on a voltage channel to the next positivegoing zero crossing. At 50Hz, this is nominally 20ms; at 60Hz, this is nominally 16.67ms. Cycle Count: The number of line cycles contained in a single DSP cycle. An integer, this is typically set to some value greater than one to minimize the effect of load variations that may not occur in every line cycle. By default, this value is 16. DSP Cycle: The period of time over which line parameters are calculated. Energy and other parameters are accumulated once per DSP cycle. One DSP cycle is the time of a line cycle multiplied by the cycle count. NS: This value represents the number of ADC frame periods in a DSP cycle. This is a noninteger calculated value. For example, if the cycle count is set to unity, and the line frequency is exactly 50Hz, the NS value would be 20ms/360μs = 55.6. Digital Processing As voltage and current samples are collected, the MAXQ3183 performs a variety of digital filtering, accumulation, and processing calculations to arrive at meter-reading values (such as line frequency, RMS voltage and current, and active and reactive power) that can then be read by the master. The MAXQ3183 calculates and detects values and conditions including the following: • Zero-crossing detection • Line frequency and line period calculation • RMS voltage (phase A, phase B, phase C) • RMS current (phase A, phase B, phase C, neutral current) ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect • Energy accumulation (including energy pulse output function) • Overvoltage detection • Overcurrent detection Per DSP Cycle Operations At the end of each DSP cycle, accumulated information is available that is used to calculate all other operational results in the meter. DSP cycles track the line frequency and have a duration of the number of cycles specified in the CYCNT register. On each phase, the time required for CYCNT cycles to complete is calculated and this value is used to update the duration of one DSP cycle, specified in the NS register. NS contains the number of ADC frame periods in a single DSP cycle. Because line frequency varies slightly from cycle to cycle, and because the ADC frame clock is not synchronized to the line, the value of NS is not an integer, and varies slightly from DSP cycle to DSP cycle. • Undervoltage detection Per Sample Operations On every ADC frame, the input samples are processed as follows: • The voltage and current samples are read. The current sample is shifted to account for the gain applied in the PGA. The phase- and gain-corrected samples are passed to the next stage. • Both the current and voltage signals are passed through highpass filters (HPF) specified by the HPF_C variable. • The current and voltage signals are now split into several components. The first of these components is squared and accumulated to begin the RMS current and voltage process. The second is processed and accumulated to begin the real/reactive power calculation. And a third is processed through a peak filter (specified by B0FUND and A1FUND registers) and then accumulated to provide information for the fundamental frequency power calculations. The result is a set of accumulated values that represent squared voltage, squared current, and real (active) and reactive (P and Q) energies for both the entire usable spectrum and as filtered by the peak filter. The real and Because the value of NS is so critical to accurate calculation of energy, ensuring that it is correct on every cycle is essential. There are two ways to manage the slight variation of NS from cycle to cycle: first, one could simply replace the old value of NS with the newly calculated value on each DSP cycle. This means that NS (and every other value in the meter, since they depend on NS) would have a significant amount of uncertainty. A better method is to use each newly calculated value of NS as an input to a filter. The output of the filter is then the value of NS that is actually used in calculations. In the MAXQ3183, this filter is controlled by the AVG_NS register. X2 HPF ADC V_GAIN VOLTAGE INPUT BPF ENERGY PROCESSING CURRENT INPUT I_GAIN ADC EP EQ ENERGY PROCESSING GAIN SEL I2 EPF EQF BPF HPF X2 V2 Figure 9. Per Sample Operations ______________________________________________________________________________________ 55 MAXQ3183 imaginary components of energy at this point do not yet represent real and reactive power; to obtain usable power values further processing is required. Each of these values is further processed at the end of each DSP cycle. • Power (active, reactive, and apparent) for each phase MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect A second problem with updating NS on every line cycles is the fact that noise impulses that occur at nearly the same time as the zero crossing can shift the zero crossing, affecting the accuracy of the energy measured during the preceding period. For this reason, a second register, REJ_NS contains a value that specifies how far a particular sample can deviate from the average and still be considered valid. If the period of the newly acquired DSP cycle differs from the previously accumulated average value by more than REJ_NS ADC frames, NS is not updated with the new period (but the energy is still accumulated). With this discussion in mind, the signal path for the various reported parameters can be reviewed. RMS Volts and RMS Amps: First, the squared voltage accumulation is divided by NS. This accomplishes the “mean” part of the “root-mean-square” calculation. Then, the square root of the result is taken, producing the raw RMS calculation value. On the voltage channel, the signal is ready for gain compensation to be applied. But on the current channel, there is an additional twist: depending on the amplitude of the current, there may be a gain factor pre-applied before the raw sample is available. To compensate for inaccuracy in the gain factor for the amplifier and for noise seen in the channel at high gain settings, it may be necessary to provide linearity compensation. There are three registers that manage the linearization of the current signal: the X.OFFS_HI (X = A/B/C) register contains a signed value that is added to the raw RMS current signal before further processing; the X.OFFS_LO register contains a signed value that is I2 added to the raw RMS current signal when the current signal is below a low current threshold (1/32 of the full scale) value; and the X.GAIN_LO register contains a gain adjustment that is applied to the current signal when the current signal is below the threshold value. The practical effect of this is to turn what may be a somewhat nonlinear response curve for the current sensor to a much more linear response by two-piece approximation. The “high current” calibration term X.OFFS_HI is used so long as the instantaneous current exceeds the lowcurrent threshold at some instant during a DSP cycle. As long as this threshold is crossed during a DSP cycle, the value in X.OFFS_HI controls the offset current. When the input stays below the low-current threshold for one DSP cycle, the X.OFFS_LO and X.GAIN_LO are applied. The low-current calibration terms (X.GAIN_LO and X.OFFS_LO) remain in effect until the peak of input current waveform exceeds 1/32 of full-scale current at any time during a DSP cycle. As a final step, both voltage and current are passed through an averaging filter that provides smoothing for the signals. The amount of filtering is given in AVG_C. Energy: The per-sample processing produces a pair of digital signals that represent the complex energy signal. From this complex signal, it is desired to extract the real portion and the reactive portion. At first glance, this seems trivial: the real portion is the real part of the complex signal, and the reactive portion is the imaginary part of the complex signal. Apparent power (in voltamperes) is the magnitude of the complex signal, and power angle is the argument of the complex signal. OFFS_HI GAIN_LO OFFS_LO AVG_C LINEARIZATION AVERAGE NS IRMS RAW_I RAW_V V2 AVERAGE NS VRMS AVG_C Figure 10. Computation of RMS Values 56 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect ⎧PA0, IRMS ≥ I1THR ⎫ ⎪ ⎪ PA = ⎨PA1, I1THR > IRMS ≥ I2THR) ⎬ ⎪PA2, I ⎪ RMS < I2THR ⎩ ⎭ To use a constant phase compensation, set I1THR and I2THR to zero and insert the phase compensation value into PA0. The same processing can be performed to calculate the reactive energy value. But reactive energy can be calculated in another way: calculate apparent energy by multiplying the raw RMS volts and raw RMS current, square this value, then subtract the squared real power. The square root of this value is the reactive energy. Similarly, apparent energy can be calculated in either of two ways: either as the product of the raw RMS volts and amps, or as the square root of the sum of the squares of the real and reactive energy. Which of these is selected depends on the value of the APPSEL bit in the OPMODE2 register: if 0, then apparent energy is the product of the raw RMS volts and amps and reactive energy is calculated using the difference of squares method; if 1, apparent energy is calculated using the sum of squares method and reactive energy is calculated directly from the complex energy. Line Frequency and Phasor Angles: Line frequency can be taken directly from the NS value. Recall that NS is the number of frames in a DSP cycle. Since each frame is 360μs, simply multiply NS by 360μs and divide by CYCNT to obtain the line period. The reciprocal of this is the line frequency. To calculate phasor angles, the numbers of samples between zero crossings on phase A and B and on phase A and C are taken. Since NS is the number of samples during a complete DSP cycle, it is easy to calculate the fraction of a complete cycle. The software then converts this value to degrees and adjusts it such that no negative angles are reported. No calibration is required for line frequency and phasor angle calculation. Energy Accumulation Once real and reactive energy over the most recent DSP cycle has been calculated, it is necessary to accumulate the result. For reactive energy, the result accumulated during any DSP cycle may be positive (for an inductive load) or EP EQ REAL/REACTIVE PROCESSING OFFS_HI GAIN_LO OFFS_LO PA0 PA1 PA2 PHASE COMPENSATION LINEARIZATION OFFS_HI GAIN_LO OFFS_LO LINEARIZATION E_GAIN AVG_C AVERAGE EREAL E_RAWREAL E_RAWREACTIVE Figure 11. Phase Compensation for Energy Calculations ______________________________________________________________________________________ 57 MAXQ3183 But current sensors and other external circuitry components introduce a phase distortion to the current signal, and this phase distortion may not be constant at all current values. Consequently, for the most precise measurements, the phase between the voltage and current signals must be compensated. In the MAXQ3183, the energy signals are compensated for phase offset by performing a complex multiplication of the signal with the contents of the appropriate phase offset register. Determining which phase offset register is appropriate is a matter of comparing the incoming RMS current for the phase with the contents of the I1THR and I2THR registers. It is the responsibility of the administrative software to ensure that I1THR is greater than or equal to I2THR. If the raw RMS current is greater than or equal to the contents of I1THR, then the angle expressed in PA0 is used to compensate the phase angle. If the raw RMS current is less than I2THR, then the angle expressed in PA2 is used to compensate the phase angle. And if the raw RMS current falls between I1THR and I2THR then PA1 is used to compensate the phase angle. In this way, a three-piece stepwise approximation of the phase response of the current sensor is available. MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect E_RAWREAL E_RAWREACTIVE RAW_I RAW_V E_GAIN X2 + Y2 AVG_C AVERAGE EAPPARENT AVERAGE EREACTIVE X×Y APPSEL E_GAIN X2 - Y2 AVG_C APPSEL Figure 12. Apparent and Reactive Energy Calculations negative (for a capacitive load). These values are separately accumulated. This means that during any one DSP cycle, only positive or negative reactive energy will be accumulated. Similarly, for real energy, the result accumulated during any DSP cycle can be positive (that is, energy is delivered to the load) or negative (that is, energy is driven back into the line). As is performed for reactive energy, these values are separately accumulated. Apparent energy is also accumulated, but since this value is always positive or zero, there is only one apparent energy accumulator. From time to time, the accumulators generate an overflow. When this occurs, the appropriate bit is set in the overflow status register X.EOVER. When an overflow occurs, supervisory code running on the host processor must make the appropriate adjustments in the reported energy. In many cases, this could simply involve incrementing an overflow counter. The host processor must then clear the overflow indication. No-Zero-Crossing Detection The MAXQ3183 monitors the voltage signal on each phase for zero-crossing events. If no ascending zero crossings are detected within a DSP cycle, the NOZXF (X.FLAGS) flag is set by the MAXQ3183 to notify the master of this condition. If the NOZXM bit is set, this flag sets the NOZX bit in the IRQ_FLAG. If the interrupt enable bit ENOZX is set to 1, the interrupt signal IRQ is driven low by the MAXQ3183 whenever NOZX = 1. The master can clear NOZXF and NOZX back to 0 to remove the interrupt condition. 58 Phase Sequence Status Phase sequence status bits PHSEQV and PHSEQI indicate the order in which zero crossings are detected. When a zero-crossing event occurs on the phase A signal, followed by phase B, phase C, and then phase A again, this bit cleared. If a zero crossing on phase A is then followed by a zero crossing on phase C, then phase B, this bit set to 1. RMS Voltage, RMS Current, and Energy Calculation For each of the three phases, the MAXQ3183 calculates RMS voltage and RMS current values, as well as determines active and reactive energy, using a linecycle-based integration process. Power Calculation (Active, Reactive, Apparent) The power, energy, and RMS calculation process consists of two tasks: continuous accumulation and postprocessing triggered every CYCNT line cycles. The accumulation task accumulates raw data obtained from the AFE during CYCNT line cycles. This task is performed continuously in the background by the MAXQ3183. When a CYCNT line cycles accumulation stage has completed, which is determined by a dedicated frame counter exceeding the NS level, the raw integral accumulator values are saved for postprocessing and cleared, beginning the next cycle of accumulation task. Then, the DSP postprocessing is triggered to process saved integrals and calculate energy, power, etc., values. Note that the background accumulation task continues while foreground postprocessing ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect The MAXQ3183 accumulates raw sums and calculates line-cycle integrals for each voltage-current pair separately. The individual power accumulators are: • PA = VA x IA • PB = IB x VB or -IB x VC or -IB x (VA + VC) or -IB x (VA - VC) • PC = VC x IC The PA and PC accumulators always operate in a single mode: (VA x IA) for the PA accumulator, (VC x IC) for the PC accumulator. Alternately, the operating mode of the PB accumulator is defined by setting the CONCFG[1:0] bits in the OPMODE1 register. Energy Accumulation Start Delay All filters have a certain settling time before accurate energy readings can be accumulated. To avoid accumulation of invalid data from filters that are still settling, an energy accumulation timeout period can be set in the ACC_TIMO register. When ACC_TIMO > 0, computed energy is not accumulated for ACC_TIMO of DSP cycles. The MAXQ3183 will decrement the ACC_TIMO register every DSP cycle until it becomes 0. When ACC_TIMO reaches 0 value, energy accumulation begins (or resumes, if ACC_TIMO was set to nonzero value by the master). Pulse outputs are also disabled when ACC_TIMO > 0. The default value of ACC_TIMO is 0x05. No-Load Feature To avoid “meter creep,” no energy accumulation should take place when measured current is less than a certain threshold. The NOLOAD register can be programmed to enable and configure this feature. If the measured X.IRMS value for a phase (A, B, or C) falls below the NOLOAD threshold, the energy accumulators for this phase are not incremented. Setting NOLOAD = 0 disables this feature. Full scale is represented by 0x10000. On Demand Calculations So far in this discussion, the values being calculated and managed in the MAXQ3183 have been based on fundamental units meaningful to the device itself: voltage as a binary fraction of full-scale voltage; current as a binary fraction of full-scale current, and time as a noninteger multiple of the ADC frame time. But a practical electricity meter must report its results in standard units, such as volts, amperes, and watts. The MAXQ3183 contains a mechanism to convert the internal units (“meter units”) to real world units (“display units”). This conversion is performed in the conversion constant (CC) registers. For some of these values (voltage, current) the calculation is simple: multiply by the conversion constant. For other values (power, energy) the calculation is more complex. In any case, the value in the CC register affects only the conversion from a meter unit to a display unit; calibration is handled separately in the gain adjustment registers for each recorded value. The results of all on-demand calculations are reported as 8-byte (64-bit) values of which no more than 6 bytes (48 bits) are significant. Eight bytes are used as a common length; however, fewer bytes can be requested for those registers known to have smaller maximum values. For example, the power factor virtual register has a maximum value that is expressed in only 3 bytes; consequently, the register can be requested with a length of 4 bytes without loss of data. RMS Volts, RMS Amps These registers (V.A, V.B, V.C, I.A, I.B, I.C) are calculated by simply multiplying the calculated RMS value (A.VRMS, B.VRMS, C.VRMS, A.IRMS, B.IRMS, C.IRMS) by the contents of the VOLT_CC or AMP_CC register. Since the RMS voltage and RMS current are given in 32-bit registers and the conversion coefficients are given in 16-bit registers, the result of the product is 48 bits. Regardless of the internal units used, VOLT_CC and AMP_CC can be tailored so that the LSB of the virtual register can be any value. For example, if one wished to have a 32-bit value representing milliamps, one could multiply by a value that scaled the register such that the LSB was 2-16mA. Then, discard the low-order 16 bits. The result is milliamps with 32 bits of precision; thus, the maximum current that could be represented would be 4,294,967,296mA, or just over 4MA. ______________________________________________________________________________________ 59 MAXQ3183 is taking place, i.e., both tasks are executed simultaneously sharing CPU time. It is essential that the DSP postprocessing calculations be completed before the next DSP trigger to avoid losing accumulated data. The master should allow enough processing time by adjusting the R_ADCRATE register. Default settings provide plenty of CPU time for both tasks. MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect The VOLT_CC and AMP_CC values can be calculated from the full-scale voltage or full-scale current and the desired value of one LSB in the display register: AMP _ CC = VOLT _ CC = IFS 2 24 × AMP _ LSB VFS 24 2 × VOLT _ LSB Example: Assume the full-scale current is 102.4A, and that we desire a 1nA LSB. The calculation would provide an AMP_CC value of: 102.4/(224 x 10-9) = 6104 = 0x17D8 Power The MAXQ3183 measures energy. But power is just energy per unit time, and the MAXQ3183 keeps track of the time unit over which energy is accumulated. This is simply the NS value, the fractional number of samples that comprises one DSP cycle. So converting energy to power is as simple as dividing the accumulated energy over one DSP cycle by NS. Multiplying by a conversion constant (PWR_CC) gives power in user-established units. The power registers (PWRP.A, PWRP.B, PWRP.C, PWRQ.A, PWRQ.B, PWRQ.C, PWRS.A, PWRS.B, PWRS.C) are calculated by multiplying the accumulated energy (A.ACT, A.REA, A.APP, B.ACT, B.REA, B.APP, C.ACT, C.REA, C.APP) by the conversion coefficient (PWR_CC) and then dividing by NS. The result is the 48-bit average power over the most recent DSP cycle, in units established by the conversion coefficient. The PWR_CC value can be calculated from the fullscale voltage, the full-scale current, and the desired value of one LSB in the display register: PWR _ CC = IFS × VFS 2 32 × PWR _ LSB Example: For this example, assume the full-scale current is 102.4A, the full-scale voltage is 558.1V, and that the desired LSB is milliwatts after discarding the 16 LSB; that is, the desired LSB is 2-16 milliwatts. Perform the following calculation: 102.4 x 558.1/(232 x 2-16 x 10-3) = 872 = 0x0368 Power Factor Power factor is calculated as real power divided by apparent power. But note that apparent power can be calculated in either of two ways: either as a square root of the sum of the squares of the real and reactive power, or more commonly as the product of the RMS 60 voltage and current measurement. The power factor as reported could change when one or the other of these methods is used. The power factor is multiplied by 214 before it is reported; thus, unity power factor is given by 16,384 decimal (0x4000). Line Frequency The line frequency is derived directly from the mean NS values over the three phases. It is reported as millihertz; thus, a 50Hz line frequency is reported as decimal 50,000 (0xC350). Phasor Angles The phasor angles are taken directly from the angular measurement values determined at each DSP cycle. The angle is reported in units of 0.01 degree; thus, a 120° phasor is reported as decimal 12,000 (0x2EE0). Energy Energy is read as the net energy directly scaled from the appropriate registers. For example, the energy read from the ENRP.A register (real energy, phase A) is composed of the difference between the A.EAPOS (real energy, positive direction, phase A) and A.EANEG (real energy, negative direction, phase A) registers scaled by the ENR_CC register. Note that the energy registers (ENRP.A, ENRP.B, ENRP.C, ENRP.T, ENRQ.A, ENRQ.B, ENRQ.C, ENRQ.T, ENRS.A, ENRS.B, ENRS.C, ENRS.T) represent the energy, in every case, since the last overflow event. For this reason, software must keep track of overflow and make adjustments accordingly when using this register set. To calculate the ENR_CC register value, begin with the full-scale voltage and full-scale current, the frame time, and the desired LSB value for energy. Then perform the following calculation: I × VFS × t FR ENR _ CC = FS 2 16 × ENR _ LSB Example: It is essential to ensure that the correct units are maintained throughout the calculation. In this example, assume that the full-scale voltage is 558.1V, the full-scale current is 102.4A, the frame time is the default of 360μs, and the desired LSB is 100 milliwatt-hours after the 32 bits are discarded; that is, the LSB is 0.1 x 2-32 watt-hours. Notice, however, that the frame time is given in microseconds and must be converted to hours before the calculation can be performed: 360μs is 100 x 10-9 hours. So the calculation proceeds as follows: 102.4 x 558.1 x 100 x 10-9/(216 x 0.1 x 2-32) = 3745 = 0x0EA1 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Meter Constant A meter constant is the number of pulses that are generated during a standard measurement interval; for example, a meter might specify a meter constant of 1600 pulses per kilowatt-hour. The THR1 and THR2 registers are used to specify the meter constant according to the following formula: The PLS1_WD and PLS2_WD registers contain the time in ADC frame periods that the pulses remain in the active state when triggered. By default, these registers contain decimal 156 (0x9C) giving, at the default frame rate, a pulse width of approximately 50ms. Each pulse generator can select one parameter to be accumulated over any combination of the three phases. For example, one could select real energy accumulated over all three phases for pulse output 1, and reactive energy accumulated over all three phases for pulse output 2. The particular parameters that can be accumulated are given in the register table. Among the quantities that can be accumulated by the pulse subsystem are the arithmetic active energy (that is, the accumulated positive real energy minus the accumulated negative real energy) and the absolute active energy (that is, accumulated positive real energy plus accumulated negative real energy). Other quantities include RMS voltage and current, positive and negative real energy and reactive energy in each of the four quadrants. Select the desired accumulation value in the QNSEL field of the PLSCFG1 and PLSCFG2 register. Also in the pulse configuration registers you can select which phases to include in the accumulation. Set any or all the PHASEA, PHASEB, and PHASEC bits in the PLSCFG1 or PLSCFG2 registers to include them in the accumulation. Generating Pulses On every DSP cycle, the MAXQ3183 adds the value in the selected register (or set of registers) to the pulse accumulator. If the value in the pulse accumulator exceeds the value in the associated threshold register (THR1 or THR2), then a pulse is started and the value in the threshold register is subtracted from the value in the pulse accumulator. THR = 2 16 K M × IFS × VFS × t FR In this formula, THR is the value to be written to the threshold register, KM is the desired meter constant (in pulses per kilowatt hour), IFS and VFS are the full-scale voltage and current, respectively, and tFR is the frame period in units of hours, as in the previous calculation. As an example, assume once again a full-scale voltage value of 558.1V = 0.5581kV, a full-scale current value of 102.4A, a desired meter constant of 1600 pulses per kilowatt hour, and a default frame time of 360μs (88.9 x 10-9 hours). The threshold register value can be calculated as: 65,536/(1600 x 102.4 x 0.5581 x 100 x 10-9) = 7,167,174 = 0x6D5CC6 Increasing the value of the threshold register reduces the meter constant (that is, there are fewer pulses per kilowatt-hour); reducing the threshold register increases the meter constant (that is, there are more pulses per kilowatt-hour.) Interrupts The MAXQ3183 contains an interrupt subsystem to relieve the host processor of the burden of constantly polling the device for status. Instead, under certain circumstances, the MAXQ3183 can activate an external pin to alert the host processor that some condition requiring host attention has occurred. Interrupts are managed globally by the IRQ_MASK and IRQ_FLAG registers. In general, when a bit becomes set in the IRQ_FLAG register, an interrupt is generated if the corresponding bit is set in the IRQ_MASK register. Interrupts can be configured for the following conditions: PWRF: This flag indicates the V DVDD to the MAXQ3183 has fallen below its nominal operating threshold (about 2.85V). This can be taken as an indication that power failure is imminent and that the host processor should begin taking steps to ensure an orderly shutdown. CHSCH: This flag indicates that the CHKSUM register changed its value. ______________________________________________________________________________________ 61 MAXQ3183 Meter Pulse The purpose of a meter pulse is generally to advance a mechanical counter when such a device is used as a display. Meter pulses are also used during calibration since time intervals can be measured with great precision. The MAXQ3183 supports two meter pulse outputs. These outputs can be configured for either active positive or active negative pulses by means of the POPOL bit in the OPMODE1 register. When triggered, the pulse goes to its active state and remains there for a period of time defined by the PLS1_WD or PLS2_WD register, and then returns to the inactive state (unless triggered again). Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect MAXQ3183 EOVF: Energy overflow. This flag indicates that one or more energy accumulators (X.EAPOS, X.EANEG, etc.) have overflowed. In a traditional meter, the host processor would poll the MAXQ3183 to determine which of the energy accumulators have overflowed and adjust its internal accounting registers accordingly. ISUMOVF: The vector sum of currents over the most recent DSP cycle has exceeded the vector sum threshold. OC: The RMS current value on one or more of the phases over the most recent DSP cycle has exceeded the value set in the OCLVL register. OV: The RMS voltage on one or more of the phases over the most recent DSP cycle has exceeded the value set in the OVLVL register. UV: The RMS voltage on one or more of the phases over the most recent DSP cycle has failed to exceed the value set in the UVLVL register. NOZX: Zero crossings were not detected on one or more of the phases during the DSP cycle. DCHA: Tells the host processor that the direction of net real energy flow on one of the three phases has changed during the current DSP cycle as compared to the previous DSP cycle. DCHR: Tells the host processor that the direction of net reactive energy flow on one of the three phases has changed during the current DSP cycle as compared to the previous DSP cycle. DSPRDY: Indicates that the latest DSP cycle has just completed. DSPOR: Indicates that the processing for the previous DSP cycle had not been completed before the current DSP cycle became available for processing. This overflow indication should never be seen in the default configuration; however, under some conditions (faster ADC rate, slower CPU clock) the processing requirements may exceed the number of CPU cycles available for DSP processing. Under these circumstances, the clock rate may be increased, the ADC rate may be reduced (that is, the R_ADCRATE register may be increased), or the functional load (such as fundamental mode calculations) may be cut. Note that when DSPOR becomes set, all DSP calculations as well as all pulse outputs are invalidated. The appropriate host response is to take the remedial action described above and discard the current set of DSP result values. 62 Each phase has a local register that contains copies of the OC, OV, UV, NOZX, DCHA, and DCHR bits. Thus, to determine which phase(s) have exception conditions requires four reads: the IRQ_FLAG register to determine which conditions are active that are causing the interrupt to occur, and then a read to A.FLAGS, B.FLAGS, and C.FLAGS to determine which of the phases have the indicated condition. Finally, each phase has a pair of local registers that contain overflow flags for each energy accumulator. If the EOVF bit is set in the IRQ_FLAG register, the host should then read the A.EOVER, B.EOVER, and C.EOVER registers to determine which of the phases have overflow conditions. If fundamental mode operation is enabled, the host should read A.EFOVER, B.EFOVER, and C.EFOVER as well. Each of these registers contains a bit for each of real and reactive energy in both positive and negative direction as well as apparent energy. Overvoltage and Overcurrent Detection The MAXQ3183 detects overvoltage and overcurrent events and can issue interrupt request signals to the master when these events occur. The overvoltage level can be programmed into the OVLVL register, while the overcurrent level is determined by the OCLVL register. Both OVLVL and OCLVL registers represent the bits 23:8 of the VRMS or IRMS registers. Any time the MAXQ3183 detects the RMS-value exceeding a threshold level, the OV or OC interrupt flag is set. If enabled, any of these flags issues an interrupt request. All interrupt flags are “sticky” bits—the MAXQ3183 never clears them on its own unless a reset occurs. The interrupt flags should be cleared by the master by writing the appropriate register. Meter Units to Real Units Conversion All energy calculations, including various threshold checks, are performed internally in fixed format in meter units. Therefore, the threshold values must be supplied by the user in meter units as well. This section summarizes how to convert real units (V, A, kWh, W, and kAh) into meter units and vice versa. The conversion factors are based on the settings of tFR, VFS, and IFS, defined by the user’s design. t FR is analog scan frame timing. This parameter is defined by the R_ADCRATE setting and system clock frequency fSYS: tFR = (R_ADCRATE + 1) x 8/fSYS Default conditions are R_ADCRATE = 359, fSYS = 8MHz. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect IFS is full-scale current. This is the input current that produces full-scale ADC output; defined by the hardware current transducer ratio ITR and ADC full-scale input voltage VFSADC: IFS = VFSADC x ITR Default conditions are VFSADC = 1.024V. ITR is design dependent. Meter units are defined with respect to the base parameters as shown in Table 5. When reading virtual registers, the MAXQ3183 uses the configurable conversion coefficients AMP_CC, VOLT_CC, PWR_CC, and ENR_CC to return meaningful data. Table 6 describes how to set the coefficients. Table 5. Meter Unit Definitions REGISTER OR ACCUMULATOR METER UNIT (1 LSB) Current RMS: X.IRMS MU_AMP = IFS/224 Pulse output current RMS THR1 or THR2, when pulse output configured to IRMS Voltage RMS: X.VRMS MU_VOLT = VFS/224 Pulse output RMS voltage THR1, or THR2 when pulse output configured to VRMS Energy: X.ACT, X.REA, X.APP, X.EAPOS, X.EANEG, X.ERPOS, X.ERNEG, X.ES Fundamental Energy: X.ACTF, X.REAF, X.APPF, X.EAFPOS, X.EAFNEG, X.ERFPOS, X.ERFNEG, X.ESF Pulse Output Energy: THR1 or THR2 MU_ENR = VFS x IFS x tFR/216 Power: PWRP.X, PWRQ.X, PWRS.X MU_PWR = VFS x IFS/232 When X.ESF Contains Amp-Hours: X.ESF MU_AH = IFS x tFR/216 OCLVL, NOLOAD, I1THR, I2THR IFS/216 OVLVL, UVLVL VFS/216 Table 6. Virtual Register Coefficients OUTPUT RESOLUTION (1 LSB), DEFINED BY USER COEFFICIENT Power: PWRP.X, PWRQ.X, PWRS.X, PWRPF.X, PWRQF.X, PWRSF.X PWR_LSB PWR_CC = MU_PWR/PWR_LSB Voltage: V.X VOLT_LSB VOLT_CC = MU_VOLT/VOLT_LSB Current: I.X AMP_LSB AMP_CC = MU_AMP/AMP_LSB Energy: ENRP.X, ENRQ.X, ENRS.X, ENRPF.X, ENRQF.X, ENRSF.X ENR_LSB ENR_CC = MU_ENR/ENR_LSB VIRTUAL REGISTER ______________________________________________________________________________________ 63 MAXQ3183 VFS is full-scale voltage. This is the input voltage that produces full-scale ADC output; defined by the hardware voltage transducer ratio VTR and ADC full-scale input voltage VFSADC: VFS = VFSADC x VTR Default conditions are VFSADC = 1.024V. VTR is design dependent. MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect I0P R1 544kΩ R2 1kΩ VA (AC) R 10Ω VOP IA (AC) MAXQ3183 VN MAXQ3183 VCOMM R 10Ω I0N Figure 13. Sample Voltage Input Circuit Units Conversion Examples The conversions from meter units to physical units are illustrated with the simplified input circuits in Figures 13 and 14. The voltage input circuit is a voltage-divider. Current input is through a current transfer with turn ratio of 2000:1. The voltage transducer ratio (VTR) = (R1 + R2)/R2 = 545, VFS = 558.1V. The current transducer ratio (ITR) = CT_N/(2 x R) = 2000/(2 x 10) =100 (A/V), IFS = 102.4A. The input circuits should be designed to avoid getting too close to the ADC input full scale at the specified maximum ratings. So for the above circuits, we would specify the maximum input current = 70A (RMS) and maximum voltage = 390V (RMS), to ensure that peak of sinusoudal waveform never exceeds IFS or VFS. Use the default ADC timing tFR = 360μs, we get the following meter unit to physical unit conversion coefficients (these coefficients are not part of the MAXQ3183 registers): MU_AMP = IFS/224 = 6.1E-6 (A) MU_VOLT = VFS/224 = 33.3E-6 (V) MU_PWR = VFS x IFS/232 = 13.3E-6 (W) MU_ENR = VFS x IFS x tFR/216 = 87.2E-9 (Wh) For example, if we get 0x07654AF0 from reading 0x1CC register (phase A current RMS), the current value it represents is 0x07654AF0 x MU_AMP = 47.33 (A) For some low-end host microcontrollers, doing the above math multiplication above could be difficult. For this reason, the MAXQ3183 provides conversions for some commonly needed parameters through the VOLT_CC, AMP_CC, PWR_CC, and ENR_CC registers. For example, if you want to display current in the resolution of 1mA, without having to use a multiplication 64 Figure 14. Sample Current Input Circuit operation to convert from the meter unit value 0x07654AF0, you would set AMP_CC to 0x0190, and read from virtual register 0x831 (phase A RMS current). The output would be 0xB8E45170. Dropping the lower 2 bytes (right shifting 16 bits) gives 0xB8E4, or 47332 decimal (47332mA). AMP_CC is computed as follows: AMP_CC = (IFS/224)/AMP_LSB = MU_AMP/AMP_LSB AMP_LSB = 0.001/216 (A) IFS = 102.4A AMP_CC = (102.4/224)/(0.001/216) = 400d = 0x0190 Calibration Procedure Calibration Overview Calibration ensures that the recorded voltage, current, energy, and power are in accordance with the design criteria. Before creating a calibration regimen, establish the fundamental units of the meter: the full-scale voltage and current. Then adjust the gain registers using calculated calibration constants to produce the expected reading in the raw current, voltage, energy, and power factor registers. The calibration constants should be stored in nonvolatile memory by the host microcontroller. Upon any reset or loss of power, the host microcontroller must reload the MAXQ3183 with the constants. Calibration always follows a set of fundamental steps: • Apply a known signal (voltage/current/power) to the meter. • Read the meter. • Calculate the correction factor based on the difference between the applied signal level and the meter reading. • Write the correction factor to the appropriate register. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Note that these steps can occur more than once for a given signal type to verify readings at different signal levels. There are two methods to read the meter in the above second step. The first is to read the raw register associated with the value under calibration, for example, A.VRMS for the phase A voltage channel; A.IRMS for the phase A current channel, and A.ACT for phase A real power. The second calibration method assigns a pulse output to the value being calibrated and measures the pulse period. In practical use, the method chosen depends on the specific application and the available equipment. For example, in some applications the voltage and current are of no concern, but the energy accumulation must be very accurate. For these applications, meter calibration sets with built-in pulse measurement facilities can make the most sense. The calibration procedure involves the following general steps: • Calibrate voltage for a given phase by applying a known voltage and adjusting the voltage gain (A.V_GAIN for phase A) until the RMS voltage (A.VRMS for phase A) reads the applied voltage in the designated units. • Calibrate current by applying a known current and adjusting the current gain (A.I_GAIN for phase A) until the RMS current (A.IRMS for phase A) reads the applied current in the designated units. If desired, the current can be calibrated at two points (low range and high range) for more accuracy. • Once the current gain and voltage gain are calibrated, the power/energy should not require any additional adjustment for most situations. Although, a separate power gain register is available for further fine-tuning of the power/energy accuracy. One must keep in mind that anytime voltage or current is recalibrated, the power or energy accuracy is naturally affected. So the power gain should be recalibrated to achieve the desired accumulative effect of voltage, current, and power gains. • Calibrate the phase offset by applying a power factor load and adjusting the phase angle offset accordingly. If desired, the phase offset can be calibrated at up to three points for more accuracy. Once these elements are calibrated for each phase, all other information (power factor, reactive power, apparent power, etc.) is also properly calibrated. The descriptions in the following sections deal specifically with phase A, but the same procedure is followed with phases B and C. Calibrating Voltage Ensure that there is no previous value in the gain register, A.V_GAIN, by setting this register to 0x4000. • Apply a known voltage with RMS value close to the desired maximum operating voltage (and less than VFS/√2). • Read the A.VRMS register. Note the value. • Convert the known value to meter units by dividing it by MU_VOLT (= VFS/224). • Divide the applied value (in meter unit) by the value read from the MAXQ3183. The result should be a value between 0 and 2. If the value falls outside of this range, you have probably miscalculated VFS. • Multiply the calculated value by 214. The result is the gain value to be programmed into A.V_GAIN. Ensure the most significant bit is 0. When the gain value is programmed, wait for 2 to 3 seconds, reread the RMS value from A.VRMS. Check that the measured value is correct by comparing A.VRMS against the applied voltage in meter unit. Voltage Calibration Example Assumptions: VFS is 558.1V. The applied voltage is 240 VRMS. • Convert the applied voltage to meter units. This calculation gives 240 x 2 24 /558.1 = 7,214,714 = 0x006E1679. • Read the A.VRMS register. You read 0x0708029. This is 7,372,841 decimal. • Divide the applied voltage by the voltage read from the meter. The result is 7,214,714/7,372,841 = 0.97855. • Convert to integer by multiplying 2 14 : 16,384 x 0.97855 = 16,033 = 0x3EA1. Write this value to the A.V_GAIN register. Calibrating Current Ensure that there is no previous value in the gain register, A.I_GAIN, by setting this register to 0x4000. • Apply a known current with RMS value close to the desired maximum operating current (and much lower than IFS/√2). • Read the A.IRMS register. Note the value. • Convert the known value to meter units by dividing it by MU_AMP (= IFS/224). ______________________________________________________________________________________ 65 MAXQ3183 • Read the meter quantity again to verify the calibration. MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect • Divide the applied value (in meter unit) by the value read from the MAXQ3183. The result should be a value between 0 and 2. If the value falls outside of this range, you have probably miscalculated IFS. • Multiply the calculated value by 214. The result is the gain value to be programmed into A.I_GAIN. Ensure the most significant bit is 0. When the gain value is programmed, wait for approximately 2 to 3 seconds, then reread the RMS value from A.IRMS. Check that the measured value is correct by comparing A.IRMS against the applied current in meter unit. Current Calibration Example Assume IFS is 102.4A and the meter has a base current of 10A and a maximum current of 60A. • The meter is calibrated at the base current of 10A. • Convert the applied current to meter units. This calculation gives 10 x 2 24 /102.4 = 1,638,400 = 0x00190000. • Read the A.IRMS register. You read 0x0017DC85. This is 1,563,781 decimal. • Divide the applied current by the current read from the meter. The result is 1,638,400/1,563,781 = 1.0477. • Multiply by 214 x 1.0477 = 17,166 = 0x430E. Write this value to the A.I_GAIN register. Calibrating Phase Offset For this calibration step, it is necessary to have a power factor meter, capable of measuring phase angle, connected in the same circuit as the MAXQ3183 meter. Note that calibration can be performed at any precision power factor setting. We use a pure resistive load (PF = 1.0) load to illustrate the procedure. • Apply a resistive load to the meter; the current drawn by the load should correspond to the base current of your meter. • Record the phase angle and direction (capacitive or inductive) reported on the power factor meter. • Read and record the real and reactive energy from the X.ACT and X.REA registers. Divide the reactive energy by the real energy. This is the tangent of the power-phase angle. • Read the X.REA register. If the high-order bit is set, the power factor reported in the above step is capacitive. If the high-order bit is clear, the power factor reported in the above step is inductive. • Now determine the correction factor: treating capacitive values as negative and inductive values as positive, subtract the angle read from the MAXQ3183 66 from the angle read from the reference meter. The result is the compensation angle. • Multiply the compensation angle (in radians) by 65,536. This is the value to write into X.PA0. If I1THR and I2THR are left at their default values (0x0000), then the value in X.PA0 is applied to the full measurement range. Alternatively, you could write the same value into X.PA0, X.PA1, and X.PA2. Then the same compensation is applied through the whole measurement range regardless of the I1THR and I2THR settings. If desired, calibrate for the phase angle at up to three different current levels to compensate for nonlinearity in the current sensor. See the Advanced Operation section for more information. Phase Offset Calibration Example Assume the meter is a 10/60 meter; that is, the base current is 10A and the maximum rated current is 60A. IFS is 102.4A and VFS is 558.1V. The test point is 10A and 240V. • Connect the MAXQ3183-based meter under test in series with a lab grade reference meter. See the configuration below. • Apply power to the meter and apply a load of 10A resistive. • Verify that the I1THR, I2THR, A.PA0, A.PA1, and A.PA2 registers contain zero. • Read the power factor on the reference meter. You read 1.5° capacitive. This is not unusual. The load might not be truly resistive or reactance in the test configuration could be reflected in the measurement. • Read the real energy from register A.ACT (0x1D0). You read 0x2865D6 (2,646,510 meter units). • Read the reactive energy from register A.REA (0x1D4). You read 0xFFFFA5C0 (-23,104 meter units). • Divide the reactive by the active power: -23,104/ 2,646,510 = -0.009. LAB METER LOAD V LINE NEUTRAL Figure 15. Offset Testing Setup ______________________________________________________________________________________ UNIT UNDER TEST V Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect • Subtract the UUT phase offset from the reference meter phase offset. In this case, the phase needs to move 1° toward the capacitive. Convert this value to radians: 1° x π/180° = 0.0175 radians. • Multiply this value by 65,536. The result is 572 (0x023C). • Because the phase correction is toward the capacitive, the value must be complemented. The two’s complement of 0x023C is 0xFDC4. This is the value that should be written to the PA0 phase compensation register. At this point, the meter is compensated for a single phase offset. If the phase offset were perfectly flat over all current levels, that would be sufficient (and for many current sensors, particularly current shunts, one point is usually good enough.) Interfacing the MAXQ3183 to External Hardware The MAXQ3183 has all the internal circuitry that is needed for a sophisticated electricity meter, but specific external hardware is required when configuring the meter for a particular application. The most critical decision that must be made is how the load will be connected to the power source, and how the meter will be connected to measure power consumed in the load. This section covers how to select hardware components for a MAXQ3183 electricity meter. Connections to the Power Source Generally, three-phase power as delivered from the utility consists of four wires: three voltage phases and a neutral wire. In one typical three-phase delivery system, measuring from neutral to any phase would read 120V, while measuring from any phase to any other phase would read 208V. Connecting a load so that load current is taken from phase lines and returned to neutral is called a wye-connected load. Connecting a load so that load current is provided by one phase and returned on another phase is called a delta-connected load. The MAXQ3183 can measure power consumed in either a wye-connected or a delta-connected load. If the load is connected in a wye fashion, the voltage is measured from the neutral lead to each of the phases, and the current measuring device is placed in series with the load, most often in the hot lead. The sensor is not placed in the neutral lead to prevent a customer from defrauding the utility by returning the current to ground rather than neutral. A current sensor placed in the hot lead makes fraud even more difficult. A delta-connected load can have current measured in two possible ways. If it is primarily desirable to know how much power is delivered to the load, one can place the current sensor in the load circuit between two phases. But if it is more important to know how much current is being drawn from each supply phase, each current sensor is placed in the line circuit of each single phase. Most utilities are only concerned with the total amount of energy being consumed. If individually accounting for the power delivered by each phase is not a requirement, it is not necessary to measure all three voltages. Instead, knowing only two voltages and the three currents is all that is necessary to measure total energy usage. There are several ways of doing this. In a wye arrangement, one of the phases—usually phase B—–can be considered the voltage reference point instead of neutral. Then the voltage measurements can be made from phase A to phase B and from phase C to phase B. By using some simple arithmetic, the power delivered by phase A, phase B, and phase C can be calculated even though only two voltages are available. A second mechanism is to have a delta-connected load, but with one leg—usually the BC leg—split into two equal loads. The point where the load is split is defined as the reference. In this arrangement, it is only necessary to know the voltage between phase C and the split and phase A and the split, since VC = -VA. Finally, there is the connection arrangement in which the load is in a delta configuration with the current sensor at each load, but it is still desired to determine how much current is in each supply branch. The MAXQ3183 supports all of these connection arrangements. Sensor Selection The MAXQ3183 supports a variety of voltage and current sense elements. This section describes the properties of many of these sensing devices. Voltage Sensors Voltage-Divider A voltage-divider is an ideal voltage-sensing element when there is no need for voltage isolation. Modern resistors have virtually no parasitic capacitance or inductance at the frequencies of interest in an electricity meter and have extremely low variation with temperature. When selecting resistors for a voltage-divider, keep the division ratio high enough so that the peak voltage value cannot exceed the maximum allowable input voltage. In the MAXQ3183, the peak input voltage is about 1V; consequently, a divider in the range of 400:1 to 600:1 is ideal. ______________________________________________________________________________________ 67 MAXQ3183 • Take the inverse tangent of this value. You get -0.5°; that is, 0.5° capacitive. MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect The second consideration is the total power dissipation and voltage hold-off requirements of the resistor. It is tempting to design a 400:1 divider with a 400kΩ resistor in series with a 1kΩ resistor, but that would force the 400kΩ resistor to dissipate about 140mW. This is not an excessive amount of power, but if the design is to use small SMT parts, it can handle greater than a 1/10W SMT resistor. It is better to use a series of several smaller components to improve system reliability. Voltage Transformer If isolation is required between the meter electronics and the line, a voltage transformer is required. A voltage transformer is designed to faithfully transfer an AC voltage applied on the primary side to a sensor on the secondary side. On the primary side, a voltage-divider is used to reduce the voltage to a workable level. On the secondary side, a load resistor is selected so that the current in the transformer windings is safely within the transformer’s linear operating region. Because the impedance seen in the primary side of the transformer is equal to the impedance of the load resistor in the secondary circuit plus impedance of the transformer secondary winding at the operating frequency, it is easy to calculate the value of the required voltage-divider resistors in the primary side. For example, assume we want a 500:1 divider ratio and assume the load resistor is 600Ω and that the impedance of the transformer secondary is 200Ω. The resistor required in the primary is (600 + 200) x 500 = 400kΩ Often, this resistor is constructed from multiple instances of a smaller value resistor; in this case, one might use eight 50kΩ resistors. Doing so minimizes the voltage requirements for the resistor chain and reduces the possibility that a single point of failure will cause a catastrophic failure. Current Sensors Current Shunt A current shunt is a low-value (approximately 100μΩ to a 100mΩ) resistor that converts a large-value current into a small voltage. Shunts make good current sensors because the output is an extremely linear representation of the measured current, current shunts can have very low temperature coefficients, and they are inexpensive. The power dissipated by a current shunt is inversely proportional to its resistance and proportional to the square of the output voltage. Consequently, there is great incentive to reduce the resistance (and hence, the output voltage) of a shunt. Often, full-scale current 68 in a shunt produces only a few millivolts of output, making a front-end amplifier essential. The MAXQ3183 includes a gain-of-32 amplifier in the current channels that is automatically cycled in and out, depending on the input voltage of the current channels. Current shunts operate at line voltage, thus, the AFE must be isolated from the line. That means that in a wye-connected meter, the current sensing must be performed in the neutral return circuit (so that all voltages into the current-sense amplifiers are referenced to neutral). It also means that the use of a shunt is precluded for delta-connected meters; the MAXQ3183 cannot tolerate the line-voltage differential between channels. Current Transformer In a current transformer, the primary is usually one turn of thick wire or buss bar and the secondary is often 1000 turns or more of magnet wire. A ferrite core magnetically couples the two. Thus, a large current in the primary turn creates a small current but large voltage in the secondary winding. For example, assume a current transformer with a 1000 turn secondary. A 10A current in the primary winding induces a 10mA current in the secondary. This current is made to flow through a so-called “burden” resistor, usually 10Ω to 20Ω. Assuming a 20Ω burden, our 10A current thus produces a 200mV signal in the secondary. Advanced Operation Modifying the ADC Operation There are several other registers that directly affect the AFE function. These registers directly affect the hardware functionality, and should be modified only when it is explicitly required. For example, if the MAXQ3183 is operated at some frequency other than the nominal 8MHz system clock, modification of these registers by supervisory code becomes necessary to maintain a 360μs frame time. • R_ACFG: This register contains bits that disable the ADC entirely, disable the voltage reference buffer amplifier, and disable the ADC interrupt. Modifying this register will likely disable or impair operation of the MAXQ3183 internal firmware. • R_ADCRATE: Modify this register to change the rate at which the MAXQ3183 acquires samples. By default, R_ADCRATE contains 359 decimal, which means that the ADC acquires a sample every 360 system clocks. With an 8MHz clock, this translates to 45μs. If the system clock is slower, it may be advantageous to reduce this value to keep a 45μs per sample time constant. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Fine-Tuning the DSP Controls Fine-Tuning the Line Frequency Measurement Line frequency measurement is based on zero-crossing detection. For that purpose each voltage signal is passed through a digital lowpass filter, controlled by the ZC_LPF register. This register specifies the b0 coefficient of a first-order LPF using following formula: b0 = ZC _ LPF 2 16 The MSB of this register must be zero. For each phase A, B, and C, the MAXQ3183 counts the number of scan frames (NS) between zero crossings within a DSP cycle. Each individual phase A, B, or C zero-crossing event contributes the raw NS count that plugs as input to lowpass filter: Yn = Yn - 1 + (AVG_NS/65,536) x (Xn - Yn - 1) The filter coefficient is a signed 16-bit value and can be configured by master. Here Y denotes the global NS value, X denotes individual NS measurements produced by zero-crossing events detected on the phase A, B, or C voltage channel. Note that if all three phase voltages present, the filter above receives three inputs each DSP cycle. The global NS value is used to generate the trigger for DSP processing. Note that the NS value can be configured by the master, which could be necessary if all three voltage signals are lost and no zero-crossings are detected. The line period is then calculated as a product of NS and the scan frame tFR. The reciprocal of this value is the line frequency, which can be obtained as a fixed-point value with 1 LSB = 0.001Hz by reading the LINEFR register. Fundamental Mode Registers The MAXQ3183 keeps another set of real and virtual registers to track power and energy at the fundamental line frequency. These “fundamental mode” registers behave identically to the standard power and energy registers, but are prefiltered to exclude harmonic power. The fundamental mode filter is specified in the B0FUND and A1FUND registers. B0FUND is the feed-forward coefficient and specifies the bandwidth of the fundamental mode filter; A1FUND is the feedback coefficient and specifies the center frequency of the fundamental mode filter. In most cases, you can leave these filters at their default values. If you wish to change the filter parameters, first choose the desired bandwidth: b0 = π x bw x tFR In this equation, bw is the desired bandwidth in hertz and t FR is the frame period, typically 360μs. Set B0FUND to b0 x 216. By default, B0FUND contains decimal 145 (0x91) giving a bandwidth of about 2Hz. To set the center frequency, calculate a1 according to the following formula: a1 = 2 - 2(1 - b0) x cos(2π x fPK x tFR) In this equation, b0 is the previously calculated feedforward coefficient, fPK is the desired center frequency in hertz, and tFR is the ADC frame period. Set A1FUND to a1 x 216. By default, A1FUND contains decimal 950 (0x3B6) giving a center frequency of approximately 50Hz. The fundamental mode filter is, by default, quite sharp with 3dB points only 1Hz off of the center frequency. This means that if the frequency drifts even only slightly, the fundamental mode power measurement is likely to have significant inaccuracy. The MAXQ3183 provides a mechanism to track the frequency by updating the A1FUND register on each DSP cycle. This mechanism is automatically enabled by default. You may wish to disable the automatic tracking facility under some circumstances, particularly if you have defined a broader bandwidth than default and are comfortable that the frequency will not drift beyond the passband. To disable the filter, set the DFUNA bit in the OPMODE2 register. You may also elect to disable fundamental mode operation completely. To do this, set the DFUN bit in the OPMODE2 register. Harmonic Measurement In addition to the ability to measure power and energy at the fundamental frequency, the MAXQ3183 provides a mechanism to isolate a particular harmonic on any voltage or current channel and measure the amplitude of that harmonic. ______________________________________________________________________________________ 69 MAXQ3183 • R_ADCACQ: Modify this register to change the acquisition time. The acquisition time is the time from ADC power-on until conversion starts, and is provided to allow the input amplifiers to settle. By default this is set to 47 decimal, or 6μs at an 8MHz system clock. If the system clock rate is changed, then R_ADCACQ should change so that this value remains about 6μs. MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect To enable harmonic measurement, first select a voltage or current channel to monitor. This is done in the AUX_CFG register. The AUX_MUX field is the 4-bit value that selects one of the three voltage channels or one of the four current channels to monitor. The order of the harmonic is set in ORDH field of the AUX_CFG register. Also in the AUX_CFG register are two bits that enable the auxiliary channel and enable harmonic measurement on the auxiliary channel. To enable the auxiliary channel, set the ENAUX bit. Once set, the MAXQ3183 will perform an RMS calculation on the selected channel. This is useful only for the IN (neutral current) channel, since every other voltage and current already have RMS calculations applied by default. (The DADCNV bit should be cleared in the SCAN_IN register in order to enable sampling the IN channel.) To enable harmonic measurement, set the ENHARM bit. Now, the selected voltage or current signal is passed to a filter that is identical to the second-order fundamental filter, but that has separate parameters (A1HARM, B0HARM). Current Vector Sum Current Total Harmonic Distortion Plus Noise (THDN) The MAXQ3183 supports two forms of current vector sum calculations depending on whether neutral current IN is available: IVS3(t) = IA(t) + IB(t) + IC(t) or IVS4(t) = IA(t) + IB(t) + IC(t) + IN(t) The sum must be calculated on instantaneous sample basis. In a balanced 3-phase system, the vector sum IVS3 should be zero; a nonzero value indicates a current unbalance. When neutral current available, vector sum IVS4 should be always zero, no matter balanced or unbalanced loads; a nonzero value indicates tamper (energy theft) or wrong meter connection. In the MAXQ3183, the samples for IA, IB, IC, and IN are not simultaneous, therefore the device automatically applies an allpass filter to IB, IC, and IN before calculating vector sum. The MAXQ3183 calculates the RMS value of IVS3 or IVS4 on-demand using the AUX channel. To activate vector sum computations, the host must set following configuration bits: For IVS3: 1) AUX_CFG.ENAUX = 1—to enable the AUX channel The MAXQ3183 can output the THDN ratio for selected current channel on-demand. It is calculated as: 2) AUX_CFG.AUX_MUX = 1001b (0x9)—select IA + IB + IC input to the AUX channel THDN.X = X.IRMS 2 X.IRMS 2fund The above settings result in AUX_CFG = 0x0049. −1 This represents the ratio of the power of harmonics plus noise over the power of the fundamental signal. To activate THDN computation, the host must first configure the AUX channel to produce first harmonic (fundamental) on the desired current channel: • Set AUX_CFG = 0x01C3 for current phase A • Set AUX_CFG = 0x01C5 for current phase B • Set AUX_CFG = 0x01C7 for current phase C Then the THDN ratio can be read from one of the following virtual registers: • Register 0x859 returns THDN.A for current phase A • Register 0x85A returns THDN.B for current phase B • Register 0x85C returns THDN.C for current phase C Each register returns a raw binary value representing the THDN ratio with LSB = 2–32. Since computation involves signal filtering, the value THDN could require a few seconds to settle before producing stable output. 70 For IVS4: 1) SCAN_IN.DADCNV = 0—to enable ADC sampling neutral current IN (SCAN_IN = 0x60) 2) AUX_CFG.ENAUX = 1—to enable the AUX channel 3) AUX_CFG.AUX_MUX =1111b (0xF)—select IA + IB + IC + IN input to the AUX channel The above settings result in AUX_CFG = 0x004F. Once the above configuration is set, the MAXQ3183 starts accumulating the specified vector sum. The result can then be read from the N.RMS register as raw value or from I.N virtual register as converted value. If the averaging filter is enabled (AVG_C > 0), the value could require a few seconds to settle before producing stable output. The MAXQ3183 has an additional control bit AUX_CFG.INREV to reverse the sign of IN current. When the bit is set (AUX_CFG = 0x006F), the MAXQ3183 calculates the value (IA + IB + IC - IN) instead of (IA + IB + IC + IN). Doing so allows vector sum computation in case of reverse connection of neutral current sensor. A threshold (ISUMLVL, address 0x054) can also be specified to cause the MAXQ3183 to generate an interrupt when the vector sum exceeds the threshold. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect • Current RMS • Ampere-Hour The ampere-hour value is readable from the X.ESF registers (X = A/B/C). Entry to LOWPM mode only occurs at the request of the master. The master must set the LOWPM_E bit (register address 0xC03) to 1 to place the MAXQ3183 into LOWPM mode. Entering LOWPM mode changes the clock frequency, thereby invalidating a number of configuration registers. As a result, the master must immediately reload the configuration registers and filter with new, updated values before metering measurement operations can continue. The master instructs the MAXQ3183 to exit LOWPM mode by reading the LOWPM_X bit (register address 0xC04). Temperature The MAXQ3183 contains a temperature sensor that can be used by host software for any purpose, including compensating power readings for temperature effects. Use the virtual register command (TEMP_C, address 0xC01) to perform a temperature conversion. The MAXQ3183 returns the value in degrees Celsius, with a resolution of 1°C. Internally, the MAXQ3183 performs a temperature sensor read and scales the sensor output by the TEMP_CC (address 0x060) coefficient to provide an output in degrees Celsius. The conversion formula is: TEMP_C = RAW_TEMP x TEMP_CC/216 - 273.15 Where RAW_TEMP is raw digitized temperature sensor output that is proportional to absolute temperature. Conversion coefficient TEMP_CC must be calibrated and set by the host; the default value is 0x0000. Advanced Calibrations Calibrating Current Offset Ideal hardware should produce a current reading linearly proportional to the input current. However, due to noise or other factors, the RMS current read by the meter might not be precisely linear. The current offset (X.OFFS_HI, X = A/B/C) can be used to compensate the current channel nonlinearity. Since the MAXQ3183 tracks the input current to determine what linearity compensation factors to use, the user must choose two points (ilo and ihi) comfortably above the low current threshold, and get the X.IRMS current readings (rlo and rhi). Then calculate the Y-intercept of the line drawn between the two points, that is, the offset. To calculate the value for the offset register, use the following formula: r i −i r offs = hi lo hi lo 2 4 (i lo − i hi ) In this equation, ihi and rhi are the applied current and the current reading, respectively, in meter units at the higher of the two reference currents; ilo and rlo are the applied current and the current reading, respectively, in meter units at the lower of the two reference currents. The gain (X.I_GAIN) may require recalibration after the offset register updated. Calibrating Linearity The current channel includes a variable-gain amplifier that introduces a gain of 32 when the current falls below the low current threshold (about 1/32 of full-scale current IFS). Because the gain of the amplifier cannot be controlled with arbitrary precision, and because high gain implies increased noise, it may be necessary to calibrate the MAXQ3183 to maintain linearity at the lowest inputs. There are two settings that manage low-current linearity: an offset setting, OFFS_LO; and a gain setting, GAIN_LO. Setting the offset is simple. Ensure no current is flowing in the current circuit. Read X.IRMS. To calculate offset use following formula: offs = -X.IRMS Program the offs into the OFFS_LO register. So, if the user reads 0x0113 from the X.IRMS register, program 0xFEED into the X.OFFS_LO register. Setting the X.GAIN_LO register means applying a current below the low-current threshold, reading the value from the MAXQ3183, and adjusting the gain accordingly. Note that the low-end gain is applied in addition to the overall gain provided in the X.I_GAIN register. Apply a known current with peak value less than the low-current threshold. Ensure that there is no previous value in the low-current gain register, A.GAIN_LO, by ______________________________________________________________________________________ 71 MAXQ3183 Low-Power Measurement Mode (LOWPM) This mode enables a subset of metering functions while operating from the lower frequency internal RC oscillator to conserve power. The actual system clock frequency used is the RC oscillator output frequency divided by 8, which results in a system clock frequency of approximately 1MHz. The parameters provided in the LOWPM are: • Voltage RMS setting this register to 0x4000. Read the A.IRMS register (0x1CC). Note the value. Convert the known value to meter units by multiplying the known value (in amperes) by 224 and dividing by IFS. Divide the results of this calculation by the value read from the MAXQ3183. The result should be a value between 0 and 2. Convert the integer by multiplying 214, and ensure MSB is zero. The result is the gain value to be programmed into A.GAIN_LO. • Convert the applied value to meter units by dividing it by MU_PWR. • Divide the applied value (in meter unit) by the value read from the MAXQ3183. The result should be a value between 0 and 2. If the value falls outside of this range, IFS and/or VFS have probably been miscalculated. • Multiply the calculated value by 214, and ensure the MSB is zero. The result is the gain value to be programmed into A.E_GAIN. • When the gain value is programmed, wait for 1 to 2 seconds, then reread the power value from PWRP.A. Check that the measured value is correct by comparing PWRP.A against the applied power in meter unit. Calibrating Power/Energy Gain Once voltage and current have been calibrated, the energy and power calculation automatically reflects the calibrated voltage and current. However the energy gain factor (X.E_GAIN, X = A/B/C) can be further tuned to achieve even more accurate power and energy result if necessary. For example, if the voltage and current calibration sources are not as accurate as the power/energy calibration source, then the additional gain calibration may be necessary. The following procedure for power/energy gain calibration is outlined for phase A. • Apply a precision unity power factor power (applied value) that is close to the desired normal operating point. • Read the PWRP.A register. Note the value. Multipoint Phase Offset Calibration To perform the calibration at three current levels, note the raw current value (X.IRMS) at each point. Label the current values, from highest to lowest, I0, I1, and I2. Program X.PA0, X.PA1, and X.PA2 with the phase offset values calculated at I 0 , I 1 , and I 2 , respectively, as described in the Calibrating Phase Offset section. Finally, program I1THR with the average of I0 and I1, and program I2THR with the geometric average of I1 and I2. Now as the current changes the phase offset is adjusted accordingly. See Figure 16. PA2 2 I2THR PHASE OFFSET MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect PA0 1 I1THR PA1 0 I2 I1 I0 INPUT CURRENT Figure 16. Phase Offset vs. Input Current Calibration 72 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Analog Scan Configuration Registers Time Slot Assignment—Current Channel X = A/B/C (SCAN_IX) (A: 0x008, B: 0x00C, C: 0x00A) Bit: 7 6 Name: 5 4 3 2 1 0 ADCMX DADCNV — — — Reset A: 0x3 0 0 0 0 Reset B: 0x4 0 0 0 0 Reset C: 0x5 0 0 0 0 These registers configure the time slot normally assigned to current channels A/B/C. We recommend leaving these registers at their default values. If they must be reassigned, one must ensure that all the current and voltage channels are reassigned properly so that the MAXQ3183 computes the power/energy parameters as intended by your setup. BIT NAME FUNCTION 7:4 ADCMX Analog Conversion Select. This four-bit field determines which of the following analog inputs are sampled during this time slot. 0000 = V0P - VN 0001 = V1P - VN 0010 = V2P - VN 0011 = I0P - I0N (Phase A Current: 0011) 0100 = I1P - I1N (Phase B Current: 0100) 0101 = I2P - I2N (Phase C Current: 0101) 0110 = INP - VN 1xxx = Temperature All other values are reserved. 3 DADCNV 2:0 — ADC Disable. When set, disables the ADC for this time slot. Reserved. ______________________________________________________________________________________ 73 MAXQ3183 Advanced Register Configurations MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Time Slot Assignment—Voltage Channel X = A/B/C (SCAN_VX) (A: 0x009, B: 0x00D, C: 0x00B) Bit: 7 Name: 6 5 4 3 2 1 ADCMX DADCNV PGG Reset A: 0x0 0 0x0 Reset B: 0x1 0 0x0 Reset C: 0x2 0 0x0 0 These registers configure the time slot normally assigned to voltage channels A/B/C. The user may wish to change the PGG settings to match the voltage sensor. However, it is recommended that the user not modify the ADCMX settings. BIT 7:4 3 2:0 74 NAME FUNCTION ADCMX Analog Conversion Select. This four-bit field determines which of the following analog inputs are sampled during this time slot. 0000 = V0P - VN (Phase A Voltage: 0000) 0001 = V1P - VN (Phase B Voltage: 0001) 0010 = V2P - VN (Phase C Voltage: 0010) 0011 = I0P - I0N 0100 = I1P - I1N 0101 = I2P - I2N 0110 = INP - VN 1xxx = Temperature DADCNV ADC Disable. When set, disables the ADC for this time slot. PGG Programmable Gain Amplifier Select. This three-bit field configures the programmable-gain amplifier at the front-end of the analog input. The field has the following values: 000 = Gain of 1 001 = Gain of 2 010 = Gain of 4 011 = Gain of 8 100 = Gain of 16 101 = Gain of 32 All other values are reserved and can cause unpredictable behavior if selected. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect 7 3 2 1 0 Name: 6 ADCMX 5 4 DADCNV — — — Reset: 0x6 1 0 0 0 This register configures the time slot normally assigned to the neutral current channel. The user can change the DADCNV bit to enable/disable neutral current sampling. It is recommended to leave the other bits of this register at their default values. BIT 7:4 3 2:0 NAME FUNCTION ADCMX Analog Conversion Select. This four-bit field determines which of the following analog inputs are sampled during this time slot. All other values are reserved. By default, this register is set to 0110. 0000 = V0P - VN 0001 = V1P - VN 0010 = V2P - VN 0011 = I0P - I0N 0100 = I1P - I1N 0101 = I2P - I2N 0110 = INP - VN 1xxx = Temperature DADCNV ADC Disable. When set, disables the ADC for this time slot. — Reserved. ______________________________________________________________________________________ 75 MAXQ3183 Time Slot Assignment—Neutral Current Channel (SCAN_IN) (0x00E) Bit: MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Time Slot Assignment—Temperature Channel (SCAN_TE) (0x00F) Bit: 7 6 5 4 3 2 1 Name: ADCMX DADCNV PGG Reset: 0x8 1 0x2 0 This register configures the time slot normally assigned to the temperature measurement device. This register is managed by the firmware and should not be modified by the host. BIT NAME FUNCTION 7:4 ADCMX Analog Conversion Select. This four-bit field determines which of the following analog inputs are sampled during this time slot. 0000 = V0P - VN 0001 = V1P - VN 0010 = V2P - VN 0011 = I0P - I0N 0100 = I1P - I1N 0101 = I2P - I2N 0110 = INP - VN 0111 = Auto-zero ADC 1xxx = Temperature By default, this register is set to 1000. 3 DADCNV 2:0 76 PGG ADC Disable. When set, disables the ADC for this time slot. Programmable Gain Amplifier Select. This three-bit field configures the programmable-gain amplifier at the front end of the analog input. The field has the following values: 000 = Gain of 1 001 = Gain of 2 010 = Gain of 4 011 = Gain of 8 100 = Gain of 16 101 = Gain of 32 All other values are reserved and can cause unpredictable behavior if selected. This register is managed by the firmware and should not be modified by the host. ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 15 14 13 Name: — — — 12 11 Reset: 0 0 0 0 0 Bit: 7 6 5 4 Name: ENHARM ENAUX INREV — Reset: 0 0 0 0 10 9 8 0 0 0 3 2 1 0 0 0 0 0 ORDH AUX_MUX The MAXQ3183 can monitor the RMS value of one auxiliary channel in addition to its normal processing. The Auxiliary Channel Configuration register selects which input the auxiliary channel processes and what processing is applied to the auxiliary channel. BIT NAME 15:13, 4 — 12:8 ORDH Order of Harmonic (1–21). The output of harmonic voltage is read via virtual register 0x830 and current at 0x840. 7 ENHARM Enable Auxiliary Channel Harmonic Filter. When set, the auxiliary channel is processed through the harmonic filter. The parameters for this filter can be set in the B0HARM and A1HARM registers. 6 ENAUX Enable Auxiliary Channel. When set, enables auxiliary channel processing. 5 INREV Sets the sign of the neutral current, used in the vector sum calculation. 0 = positive, i.e., IN is directly summed with IA + IB + IC. 1 = negative, -IN is summed with IA + IB + IC. 3:0 AUX_MUX FUNCTION Reserved. Auxiliary Channel Input or Current Vector Sum Select. The lower three bits select the input to be processed by the auxiliary channel if the MSB (bit 3) is cleared. When MSB is set, this field selects vector sum computation: 1001 = IA + IB +IC 1111 = IA + IB + I C + IN (INREV = 0) or IA + IB + IC - IN (INREV = -1) 0001 = I N 0010 = VA 0011 = IA 0100 = VB 0101 = IB 0110 = VC 0111 = IC All other values are reserved. ______________________________________________________________________________________ 77 MAXQ3183 Neutral Current and Harmonics Auxiliary Channel Configuration (AUX_CFG) (0x010) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect DSP System Configuration System Clock Frequency (SYS_KHZ) (0x012) Bit: 15 14 13 12 11 Name: System Clock Frequency High Byte Reset: 0x1F Bit: 7 6 5 4 3 Name: System Clock Frequency Low Byte Reset: 0x40 10 9 8 2 1 0 This register contains the system clock frequency in kHz units. Because the default frequency is 8MHz, this register defaults to 0x1F40. Cycle Count (CYCNT) (0x01C) Bit: 15 14 13 12 11 Name: Cycle Count High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Cycle Count Low Byte Reset: 0x10 10 9 8 2 1 0 This register contains the number of line cycles that will be accumulated in a single DSP cycle. When CYCNT line cycles have been accumulated, the DSP performs power, power factor, and energy calculations. By default, the cycle count is 0x10 (16 decimal). 78 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 31 30 29 28 27 Name: Integer Portion, High Byte Reset: 0x03 Bit: 23 22 21 20 19 Name: Integer Portion, Low Byte Reset: 0x28 Bit: 15 14 13 12 11 Name: Fractional Portion, High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Fractional Portion, Low Byte Reset: 0x00 26 25 24 18 17 16 10 9 8 2 1 0 The NS register defines the fundamental timing for the electricity meter. It defines a DSP cycle in terms the period of the ADC scan frame. Generally, this register is calculated and updated automatically by the MAXQ3183 firmware based on the zero-crossing detection, and whether noise rejection (REJ_NS) and averaging (AVG_NS) are enabled. Host code can write to this register in order to set the desired DSP cycle duration. The duration of one scan frame (tFR) is represented as 0x00010000. Filter Coefficients Line Cycle Noise Rejection Filter (REJ_NS) (0x02C) Bit: 15 14 13 12 11 10 Name: Line Cycle Noise Rejection Filter High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Line Cycle Noise Rejection Filter Low Byte Reset: 0xC8 9 8 1 0 This register establishes the sensitivity of the NS rejection filter setting. NS is a measure of the line frequency. If a line cycle occurs that is shorter or longer than the line cycle represented in the NS register, this filter determines whether the cycle is used to update the NS value. For more information, see the NS register description. If this register is zero, noise rejection is disabled for the line cycle counter. ______________________________________________________________________________________ 79 MAXQ3183 Number of Scan Frames per DSP Cycle (NS) (0x040) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Line Cycle Averaging Filter (AVG_NS) (0x02E) Bit: 15 14 13 12 11 Name: Line Cycle Averaging Filter High Byte Reset: 0x40 Bit: 7 6 5 4 3 Name: Line Cycle Averaging Filter Low Byte Reset: 0x00 10 9 8 2 1 0 This register determines whether the NS value is averaged over previous values or whether the most recently measured value is used directly. If the value of this register is nonzero, the NS value is averaged using the following formula: x − y n−1 y n = y n−1 + AVG _ NS n 2 16 If the value of this register is zero, NS is not averaged. The MSB of this register must be zero. Meter Measurement Averaging Filter (AVG_C) (0x030) Bit: 15 14 13 12 11 10 Name: Meter Measurement Averaging Filter High Byte Reset: 0x40 Bit: 7 6 5 4 3 2 Name: Meter Measurement Averaging Filter Low Byte Reset: 0x00 9 8 1 0 This register determines whether the all other measured values in the electricity meter are averaged over time. If the value of this register is nonzero, all measured meter values are averaged using the following formula: x − y n−1 y n = y n−1 + AVG _ C n 2 16 If the value of this register is zero, no averaging is performed. The MSB of this register must be zero. 80 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 15 14 13 12 11 10 Name: Meter Measurement Highpass Filter High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Meter Measurement Highpass Filter Low Byte Reset: 0xC8 9 8 1 0 This register specifies the b0 coefficient of a first-order Butterworth filter using the following formula: b0 = HPF _ C 2 16 The MSB of this register must be zero. Fundamental Filter Feed-Forward Coefficient (B0FUND) (0x034) Bit: 15 14 13 12 11 10 Name: Fundamental Filter Feed-Forward Coefficient High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Fundamental Filter Feed-Forward Coefficient Low Byte Reset: 0x91 9 8 1 0 This register specifies the b0 (feed-forward) coefficient for the fundamental-mode filter using the following formula: b0 = B0FUND 2 16 The MSB of this register must be zero. ______________________________________________________________________________________ 81 MAXQ3183 Meter Measurement Highpass Filter (HPF_C) (0x032) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Fundamental Filter Feedback Coefficient (A1FUND) (0x036) Bit: 31 30 29 28 27 26 Name: Fundamental Filter Feedback Coefficient Byte 3 Reset: 0x00 Bit: 23 22 21 20 19 18 Name: Fundamental Filter Feedback Coefficient Byte 2 Reset: 0x00 Bit: 15 14 13 12 11 10 Name: Fundamental Filter Feedback Coefficient Byte 1 Reset: 0x03 Bit: 7 6 5 4 3 2 Name: Fundamental Filter Feedback Coefficient Byte 0 Reset: 0xB6 25 24 17 16 9 8 1 0 This register specifies the a1 (feedback) coefficient for the fundamental-mode filter using the following formula: a1 = A1FUND 2 16 Harmonic Filter Feed-Forward Coefficient (B0HARM) (0x03A) Bit: 15 14 13 12 11 10 Name: Harmonic Filter Feed-Forward Coefficient High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Harmonic Filter Feed-Forward Coefficient Low Byte Reset: 0x91 9 8 1 0 This register specifies the b0 (feed-forward) coefficient for the harmonic-mode filter using the following formula: b0 = B0HARM 2 16 The MSB of this register must be zero. 82 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 31 30 29 28 27 26 Name: Harmonic Filter Feedback Coefficient Byte 3 Reset: 0x00 Bit: 23 22 21 20 19 18 Name: Harmonic Filter Feedback Coefficient Byte 2 Reset: 0x00 Bit: 15 14 13 12 11 10 Name: Harmonic Filter Feedback Coefficient Byte 1 Reset: 0x18 Bit: 7 6 5 4 3 2 Name: Harmonic Filter Feedback Coefficient Byte 0 Reset: 0x31 25 24 17 16 9 8 1 0 This register specifies the a1 (feedback) coefficient for the harmonic mode filter using the following formula: a1 = A1HARM 2 16 Zero-Cross Lowpass Filter (ZC_LPF) (0x05A) Bit: 15 14 13 12 11 Name: Zero-Cross Lowpass Filter High Byte Reset: 0x0B Bit: 7 6 5 4 3 Name: Zero-Cross Lowpass Filter Low Byte Reset: 0x00 10 9 8 2 1 0 This register specifies the lowpass filter applied for zero-cross detection. The MSB of this register must be zero. ______________________________________________________________________________________ 83 MAXQ3183 Harmonic Filter Feedback Coefficient (A1HARM) (0x03C) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Hardware Mirror Registers ADC Configuration (R_ACFG) (0x04C) Bit: 7 6 Name: ADCASD ADCRY Reset: 0 0 5 4 3 2 1 0 ADCCD ADCBY ADCIE ARBE ADCE 0x0 0 1 1 1 This register is a mirror of a CPU register in the MAXQ3183. This register should not be modified by supervisory code. BIT NAME FUNCTION 7 ADCASD Disable ADC Automatic Shutdown. Normally, the ADC analog section is powered off following a conversion to conserve power. If this bit is set, the ADC leaves the analog section powered on following a conversion. 6 ADCRY ADC Data Ready. When a conversion is complete, this bit is set to indicate that data is available. This bit generates an interrupt if ADCIE is set. 5:4 ADCCD ADC Clock Divider. Sets the division ratio between the CPU master and ADC clock. 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = reserved 3 ADCBY ADC Busy. When set, a single ADC conversion cycle is in progress. The bit is cleared on the conclusion of the conversion cycle. 2 ADCIE ADC Interrupt Enable. If set, the ADC interrupts the CPU at the completion of a conversion cycle. 1 ARBE Reference Buffer Enable. If set, the reference buffer is enabled to drive the REFO pin. 0 ADCE ADC Enable. If set, the ADC hardware is activated. ADC Conversion Rate (R_ADCRATE) (0x04E) Bit: 15 14 13 Reset: — — — Bit: 7 6 5 Name: 12 11 10 9 8 ADC Conversion Rate High Byte — — — — 1 4 3 2 1 0 Name: ADC Conversion Rate Low Byte Reset: 0x67 This register specifies the number of system clock cycles between consecutive ADC conversions. It defaults to 0x167 (359 decimal), which specifies 360 CPU clock cycles between conversions. This register is a mirror of a CPU register in the MAXQ3183. 84 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect 15 14 13 Name: 12 11 10 9 8 ADC Settling Time High Byte Reset: — — — Bit: 7 6 5 Name: — — — — — 4 3 2 1 0 ADC Settling Time Low Byte Reset: — 0x2F This register is a mirror of a CPU register in the MAXQ3183. This register should not be modified by supervisory code. This register specifies the time, in CPU clocks, that the ADC must wait after switching analog mux inputs before beginning its conversion. This register defaults to 0x2F (47 decimal), which specifies a 48 CPU clock-cycle delay from analog mux switching to the start of conversion. SPI Configuration (R_SPICF) (0x052) Bit: 7 6 5 4 3 2 1 0 Name: ESPII SAS — — — CHR CKPHA CKPOL Reset: 1 0 0 0 0 0 0 0 This register is a mirror of a CPU register in the MAXQ3183. This register configures the SPI port of the MAXQ3183. BIT NAME 7 ESPII Enable SPI Interrupt. If set, arrival of a character on the SPI bus causes a CPU interrupt. FUNCTION 6 SAS SPI Slave Select Polarity. If clear, SSEL is assumed to be active low; if set, SSEL is assumed to be active high. 5:3 — 2 CHR SPI Character Length. If clear, characters on the SPI bus are assumed to be 8 bits; if set, characters on the SPI bus are assumed to be 16 bits. 1 CKPHA SPI Clock Phase. If clear, data is sampled on the leading edge of the clock (low-to-high if the clock is active high, and high-to-low if the clock is active low). If set, data is sampled on the trailing edge of the clock (high-to-low if the clock is active high, and low-to-high if the clock is active low). 0 CKPOL SPI Clock Polarity. If clear, the clock is assumed to be active high; if set, the clock is assumed to be active low. Reserved. ______________________________________________________________________________________ 85 MAXQ3183 ADC Settling Time (R_ADCACQ) (0x050) Bit: MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Timeouts Communications Timeout (COM_TIMO) (0x056) Bit: 15 14 13 12 11 Name: Communications Timeout High Byte Reset: 0x03 Bit: 7 6 5 4 3 Name: Communications Timeout Low Byte Reset: 0xE8 10 9 8 2 1 0 This register specifies the duration of SPI timeout in ADC frames (default 360μs). Energy Accumulation Timeout (ACC_TIMO) (0x058) Bit: 15 14 13 12 11 Name: Energy Accumulation Timeout High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Energy Accumulation Timeout Low Byte Reset: 0x05 10 9 8 2 1 0 This register specifies the time in DSP cycles that the MAXQ3183 waits before accumulating energy. If this register is nonzero, it is decremented on each DSP cycle. If the result of the decrement is nonzero, the results of the DSP cycle are discarded and are not accumulated to the energy registers. This register is useful for delaying the initiation of energy accumulation on startup or after some hardware function has been modified. 86 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 15 14 13 12 11 10 Name: Phase Accumulator Current Threshold 1 High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Phase Accumulator Current Threshold 1 Low Byte Reset: 0x00 9 8 1 0 This register specifies the fraction of full-scale current that causes the MAXQ3183 to switch from PA0 to PA1 to provide phase-angle compensation. For more information, see the PA0, PA1, and PA2 register descriptions. The fullscale current is represented by 0x10000. Phase Offset Current Threshold 2 (I2THR) (0x05E) Bit: 15 14 13 12 11 10 Name: Phase Accumulator Current Threshold 2 High Byte Reset: 0x00 Bit: 7 6 5 4 3 2 Name: Phase Accumulator Current Threshold 2 Low Byte Reset: 0x00 9 8 1 0 This register specifies the fraction of full-scale current that causes the MAXQ3183 to switch from PA1 to PA2 to provide phase-angle compensation. For more information, see the PA0, PA1, and PA2 register descriptions. The fullscale current is represented by 0x10000. Miscellaneous Gain Neutral Current Gain (N.I_GAIN) (0x12E) Bit: 15 14 13 12 11 Name: Compensation Coefficient High Byte Reset: 0x40 Bit: 7 6 5 4 3 Name: Compensation Coefficient Low Byte Reset: 0x00 10 9 8 2 1 0 This register contains gain compensation coefficient for the neutral current channel measurement. The raw values are taken from the selected measurement quantity and scaled by N.I_GAIN/214. ______________________________________________________________________________________ 87 MAXQ3183 Phase-Angle Compensation Phase Offset Current Threshold 1 (I1THR) (0x05C) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Gain, Fundamental Energy, Phase X = A/B/C (X.EF_GAIN) (A: 0x136, B: 0x222, C: 0x30E) Bit: 15 14 13 12 11 Name: Gain Coefficient High Byte Reset: 0x40 Bit: 7 6 5 4 3 Name: Gain Coefficient Low Byte Reset: 0x00 10 9 8 2 1 0 This register contains gain coefficient for phase X fundamental energy. The raw values are taken from the selected measurement quantity and scaled by the following factor: X.EF _ GAIN 2 14 Linearity Compensation Linearity Offset, High Range, Phase X = A/B/C (X.OFFS_HI) (A: 0x138, B: 0x224, C: 0x310) Bit: 15 14 13 12 11 Name: Linearity Offset High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Linearity Offset Low Byte Reset: 0x00 10 9 8 2 1 0 This signed register contains the linearity offset for phase X current channel when the programmable gain amplifier is set to unity gain (that is, the measured current is above the low current threshold). The signed value represented by this register is added to the current value according to following formula: X.IRMS + X.OFFS_HI x 24 Linearity Gain Coefficient, Low Range, Phase X = A/B/C (X.GAIN_LO) (A: 0x13A, B: 0x226, C: 0x312) Bit: 15 14 13 12 11 Name: Linearity Coefficient High Byte Reset: 0x40 Bit: 7 6 5 4 3 Name: Linearity Coefficient Low Byte Reset: 0x00 10 9 8 2 1 0 This register contains the linearity coefficient for phase X current channel when the programmable gain amplifier is set to gain of 32 (that is, the measured current is below the low current threshold). The effective gain is given by the equation: X.GAIN _ LO 2 14 88 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect 15 14 13 12 11 Name: Linearity Offset High Byte Reset: 0x00 Bit: 7 6 5 4 3 Name: Linearity Offset Low Byte Reset: 0x00 10 9 8 2 1 0 This signed register contains the linearity offset for phase X current channel when the programmable gain amplifier is set to gain of 32 (that is, the measured current is below the low current threshold). The signed value represented by this register is added to the current value. The total linearity compensation is applied as follows: X.GAIN_LO/214 x (X.IRMS + X.OFFS_LO) Measurements—RAM Registers On-Demand RMS Result (N.IRMS) (0x11C) Bit: 31 30 29 Name: 28 27 26 25 24 18 17 16 10 9 8 2 1 0 RMS Result, Byte 3 Reset: Bit: 23 22 21 Name: 20 19 RMS Result, Byte 2 Reset: Bit: 15 14 13 Name: 12 11 RMS Result, Byte 1 Reset: Bit: Name: 7 6 5 4 3 RMS Result, Byte 0 Reset: This register contains the result of the RMS calculation on the AUX channel. Usually, this is the neutral current channel, but can be defined to be the RMS average of any harmonic of the quantities defined in the AUX_MUX field of the AUX_CFG register. ______________________________________________________________________________________ 89 MAXQ3183 Linearity Offset, Low Range, Phase X = A/B/C (X.OFFS_LO) (A: 0x13C, B: 0x228, C: 0x314) Bit: MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Fundamental Energy Fundamental Energy Overflow Flags, Phase X = A/B/C (X.EFOVER) (A: 0x147, B: 0x233, C: 0x31F) Bit: 7 6 5 4 3 2 1 0 Name: — — — SFOV RNFOV RPFOV ANFOV APFOV Reset: 0 0 0 0 0 0 0 0 These bits indicate an overflow condition has occurred on a fundamental frequency energy accumulator. An overflow condition is not an error condition. Rather, it simply indicates that the value in the energy accumulator could be smaller than the previous reading due to the overflow in the counter. To obtain the actual energy usage since the previous reading, 0x100000000 must be added to the difference. These bits, once set, can be cleared only by the host. BIT NAME 7:5 — FUNCTION Reserved. 4 SFOV 3 RNFOV When set, indicates an overflow condition on the apparent fundamental-mode energy accumulator. When set, indicates an overflow condition on the reactive negative fundamental-mode energy accumulator. 2 RPFOV When set, indicates an overflow condition on the reactive positive fundamental-mode energy accumulator. 1 ANFOV When set, indicates an overflow condition on the real negative fundamental-mode energy accumulator. 0 APFOV When set, indicates an overflow condition on the real positive fundamental-mode energy accumulator. Energy, Fundamental, Real Positive, Phase X = A/B/C (X.EAFPOS) (A: 0x1FC, B: 0x2E8, C: 0x3D4) Bit: 31 30 29 Name: Bit: 22 21 Name: 14 13 Name: 25 24 20 19 18 17 16 12 11 10 9 8 2 1 0 Real Energy Byte 1 7 Name: 26 Real Energy Byte 2 15 Bit: 27 Real Energy Byte 3 23 Bit: 28 6 5 4 3 Real Energy Byte 0 On every DSP cycle, the contents of the X.ACTF register are tested, and if positive, are added to this register. When this register overflows, the APFOV bit in the X.EFOVER register is set. 90 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 31 30 29 Name: Bit: 23 22 21 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Real Energy Byte 2 15 14 13 Name: Bit: 27 Real Energy Byte 3 Name: Bit: 28 12 11 Real Energy Byte 1 7 6 5 Name: 4 3 Real Energy Byte 0 On every DSP cycle, the contents of the X.ACTF register are tested, and, if negative, absolute values are added to this register. When this register overflows, the ANFOV bit in the X.EFOVER register is set. Energy, Fundamental, Reactive Positive, Phase X = A/B/C (X.ERFPOS) (A: 0x204, B: 0x2F0, C: 0x3DC) Bit: 31 30 29 Name: Bit: 23 22 21 Name: 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Reactive Energy Byte 2 15 14 13 Name: Bit: 27 Reactive Energy Byte 3 Name: Bit: 28 12 11 Reactive Energy Byte 1 7 6 5 4 3 Reactive Energy Byte 0 On every DSP cycle, the contents of the X.REAF register are tested, and, if positive, are added to this register. When this register overflows, the RPFOV bit in the X.EFOVER register is set. ______________________________________________________________________________________ 91 MAXQ3183 Energy, Fundamental, Real Negative, Phase X = A/B/C (X.EAFNEG) (A: 0x200, B: 0x2EC, C: 0x3D8) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Energy, Fundamental, Reactive Negative, Phase X = A/B/C (X.ERFNEG) (A: 0x208, B: 0x2F4, C: 0x3E0) Bit: 31 30 29 Name: Bit: 22 21 Name: 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Reactive Energy Byte 2 15 14 13 Name: Bit: 27 Reactive Energy Byte 3 23 Bit: 28 12 11 Reactive Energy Byte 1 7 6 5 Name: 4 3 Reactive Energy Byte 0 On every DSP cycle, the contents of the X.REAF register are tested, and, if negative, absolute values are added to this register. When this register overflows, the RNFOV bit in the X.EFOVER register is set. Energy Fundamental, Apparent, Phase X = A/B/C (X.ESF) (A: 0x20C, B: 0x2F8, C: 0x3E4) Bit: 31 30 29 Name: Bit: 22 21 Name: 14 13 Name: 25 24 20 19 18 17 16 12 11 10 9 8 2 1 0 Apparent Energy Byte 1 7 Name: 26 Apparent Energy Byte 2 15 Bit: 27 Apparent Energy Byte 3 23 Bit: 28 6 5 4 3 Apparent Energy Byte 0 On every DSP cycle, the contents of the X.ESF register are added to this register. When this register overflows, the SFOV bit in the X.EFOVER register is set. When the MAXQ3183 is operating in low-power mode, energy is not accumulated. However, during low-power mode, current values are accumulated to this register, making this register accumulate ampere-hours. 92 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Bit: 31 30 29 Name: Bit: 23 22 21 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Real Energy Byte 2 15 14 13 Name: Bit: 27 Real Energy Byte 3 Name: Bit: 28 12 11 Real Energy Byte 1 7 6 5 Name: 4 3 Real Energy Byte 0 This signed register provides the raw real energy accumulated over the most recent DSP cycle. For each ADC sample period, the real instantaneous power calculated from the instantaneous voltage and current is accumulated. At the end of each DSP cycle, the result of the accumulation over the DSP cycle is copied to this register and is accumulated in X.EAPOS or X.EANEG, depending on the sign of the accumulated energy. LSB of the energy registers is VFS x IFS x tFR/216. Reactive Energy, Phase X = A/B/C (X.REA) (A: 0x1D4, B: 0x2C0, C: 0x3AC) Bit: 31 30 29 Name: Bit: 23 22 21 Name: Bit: Name: 27 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Reactive Energy Byte 2 15 14 13 Name: Bit: 28 Reactive Energy Byte 3 12 11 Reactive Energy Byte 1 7 6 5 4 3 Reactive Energy Byte 0 This signed register provides the raw reactive energy accumulated over the most recent DSP cycle. For each ADC sample period, the reactive instantaneous power calculated from the instantaneous voltage and current is accumulated. At the end of each DSP cycle, the result of the accumulation over the DSP cycle is copied to this register and is accumulated in X.ERPOS or X.ERNEG, depending on the sign of the accumulated energy. ______________________________________________________________________________________ 93 MAXQ3183 Energy Accumulated in the Last DSP Cycle Real Energy, Phase X = A/B/C (X.ACT) (A: 0x1D0, B: 0x2BC, C: 0x3A8) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Apparent Energy, Phase X = A/B/C (X.APP) (A: 0x1D8, B: 0x2C4, C: 0x3B0) Bit: 31 30 29 Name: Bit: 23 22 21 Name: Bit: 27 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Apparent Energy Byte 2 15 14 13 Name: Bit: 28 Apparent Energy Byte 3 12 11 Apparent Energy Byte 1 7 6 5 Name: 4 3 Apparent Energy Byte 0 This signed register provides the raw apparent energy accumulated over the most recent DSP cycle. Fundamental Energy Accumulated in the Last DSP Cycle Fundamental Real Energy, Phase X = A/B/C (X.ACTF) (A: 0x1DC, B: 0x2C8, C: 0x3B4) Bit: 31 30 29 Name: Bit: 23 22 21 Name: Bit: 15 26 25 24 20 19 18 17 16 14 13 12 11 10 9 8 2 1 0 Real Energy Byte 1 7 Name: 27 Real Energy Byte 2 Name: Bit: 28 Real Energy Byte 3 6 5 4 3 Real Energy Byte 0 This signed register accumulates energy in the same fashion as the X.ACT register, but only at the fundamental line frequency. 94 ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect 31 30 29 Name: Bit: 23 22 21 Name: Bit: 27 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Reactive Energy Byte 2 15 14 13 Name: Bit: 28 Reactive Energy Byte 3 12 11 Reactive Energy Byte 1 7 6 5 Name: 4 3 Reactive Energy Byte 0 This signed register accumulates energy in the same fashion as the X.REA register, but only at the fundamental line frequency. Fundamental Apparent Energy, Phase X = A/B/C (X.APPF) (A: 0x1E4, B: 0x2D0, C: 0x3BC) Bit: 31 30 29 Name: Bit: 23 22 21 Name: Bit: Name: 27 26 25 24 20 19 18 17 16 10 9 8 2 1 0 Apparent Energy Byte 2 15 14 13 Name: Bit: 28 Apparent Energy Byte 3 12 11 Apparent Energy Byte 1 7 6 5 4 3 Apparent Energy Byte 0 This register accumulates energy in the same fashion as the X.APP register, but only at the fundamental line frequency. ______________________________________________________________________________________ 95 MAXQ3183 Fundamental Reactive Energy, Phase X = A/B/C (X.REAF) (A: 0x1E0, B: 0x2CC, C: 0x3B8) Bit: MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Checksum (CHKSUM) (0x066) Bit: 15 14 13 Name: 12 11 10 9 8 2 1 0 Checksum High Byte Reset: Bit: 7 6 5 Name: 4 3 Checksum Low Byte Reset: This register contains the calculated 16-bit arithmetic checksum over critical configuration and calibration registers. It is updated on every DSP cycle. In use, the administrative processor records the value in the CHKSUM register and then checks it periodically to verify that no configuration or calibration registers have changed. The MAXQ3183 sets the CHSCH bit when this register’s value changes. The registers included in the checksum calculation include the following: SYS_KHZ 96 THR2 R_ADCRATE A.I_GAIN B.I_GAIN C.I_GAIN VOLT_CC REJ_NS R_ADCACQ A.V_GAIN B.V_GAIN C.V_GAIN AMP_CC AVG_NS R_SPICF A.E_GAIN B.E_GAIN C.E_GAIN PWR_CC AVG_C ISUMLVL A.EF_GAIN B.EF_GAIN C.EF_GAIN ENR_CC HPF_C COM_TIMO A.OFFS_HI B.OFFS_HI C.OFFS_HI CYCNT B0FUND ACC_TIMO A.GAIN_LO B.GAIN_LO C.GAIN_LO PLSCFG1 OCLVL I1THR A.OFFS_LO B.OFFS_LO C.OFFS_LO PLSCFG2 OVLVL I2THR A.PA0 B.PA0 C.PA0 PLS1_WD UVLVL ZC_LPF A.PA1 B.PA1 C.PA1 THR1 NOLOAD N.GAIN A.PA2 B.PA2 C.PA2 PLS2_WD R_ACFG TEMP_CC ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Fundamental Real Power, Phase A/B/C/T (PWRPF.X) (A: 0x881, B: 0x882, C: 0x884, T: 0x887) This signed register contains the real instantaneous power delivered into phase A/B/C or total at the fundamental line frequency only. Power is calculated from the instantaneous energy measurement according to the following equation: PWRPF.X = X.ACTF × PWR _ CC × 2 16 NS Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) Fundamental Reactive Power, Phase A/B/C/T (PWRQF.X) (A: 0x891, B: 0x892, C: 0x894, T: 0x897) This signed register contains the reactive instantaneous power delivered into phase A/B/C or total at the fundamental line frequency only. Power is calculated from the instantaneous energy measurement according to the following equation: PWRQF.X = X.REAF × PWR _ CC × 2 16 NS Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) ______________________________________________________________________________________ 97 MAXQ3183 Measurements—Virtual Registers MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Fundamental Apparent Power, Phase A/B/C/T (PWRSF.X) (A: 0x8A1, B: 0x8A2, C: 0x8A4, T: 0x8A7) This register contains the instantaneous apparent power delivered into phase A/B/C or total at the fundamental line frequency only. Power is calculated from the instantaneous energy measurement according to the following equation: PWRSF.X = X.APPF × PWR _ CC × 2 16 NS Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) Fundamental Real Energy, Phase A/B/C/T (ENRPF.X) (A: 0x8E1, B: 0x8E2, C: 0x8E4, T: 0x8E7) This signed register contains the real accumulated energy delivered into phase A/B/C or total. The register is calculated according to the following formula: ENRPF.X = ENR_CC x (X.EAFPOS - X.EAFNEG) Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) Fundamental Reactive Energy, Phase A/B/C/T (ENRQF.X) (A: 0x8F1, B: 0x8F2, C: 0x8F4, T: 0x8F7) This signed register contains the reactive accumulated energy delivered into phase A/B/C or total. The register is calculated according to the following formula: ENRQF.X = ENR_CC x (X.ERFPOS - X.ERFNEG) 98 Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) ______________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect This register contains the apparent accumulated energy delivered into phase A/B/C or total. The register is the product of the ENR_CC and X.ESF registers. Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 (LSByte) Current Total Harmonic Distortion Plus Noise, Phase A/B/C (THDN.X) (A: 0x859, B:0x85A, C: 0x85C) This signed register contains for a phase current the total harmonic distortion plus noise (power) ratio, computed as below, where X.IRMSFUND is the fundamental current RMS. THDN.X = X.IRMS 2 2 X.IRMS FUND −1 Note that the sign bit is at the most significant bit of byte 5. Byte 7 (MSByte unused) Byte 6 (unused) Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 ______________________________________________________________________________________ 99 MAXQ3183 Fundamental Apparent Energy, Phase A/B/C/T (ENRSF.X) (A: 0x8B1, B: 0x8B2, C: 0x8B4, T: 0x8B7) MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Phasors Phase B Phasor (VBPH: 0x852) This register reports phase angle of voltage phase B with respect to voltage phase A. The value is expressed in units of 0.01 degree; thus, the nominal value is 12000 decimal (0x2EE0). This value is calculated based on zero-crossing detection. It may exhibit noticable error in the presence of harmonics on voltage channels. This register is 2 bytes wide. Phase C Phasor (VCPH: 0x854) This register reports phase angle of voltage phase C with respect to voltage phase A. The value is expressed in units of 0.01 degree; thus, the nominal value is 24000 decimal (0x5DC0). This value is calculated based on zero-crossing detection. It may exhibit noticable error in the presence of harmonics on voltage channels. This register is 2 bytes wide. Harmonics RMS Voltage, Harmonic (V.HARM) (0x830) This register reports the RMS voltage. The units are defined by the VOLT_CC setting. Use AUX_CFG to configure the phase (A/B/C) and harmonic order desired. RMS Current, Harmonic/Neutral (I.N, I.HARM) (0x840) This register reports the harmonic RMS current of selected phase (A/B/C) and harmonic order, harmonic, or the RMS current of the neutral current channel. The units are defined by the AMP_CC setting. Use AUX_CFG to configure the phase (A/B/C) and harmonic order desired. Ratio of Harmonic/Fundamental (HARM_NF) (0x850) This register reports the ratio of the selected harmonic RMS over the fundamental RMS of the same signal (except IN). The master must configure the AUX_CFG register to enable the AUX channel, enable harmonics, and select AUX_MUX before reading this register. This register is 4 bytes wide, LSB = 2-16. Special Commands Table 7 shows the read-only virtual registers that activate special commands when read by the master. Some commands return dummy values. Applications Information Grounds and Bypassing Careful PCB layout significantly minimizes noise on the analog inputs, resulting in less noise on the digital I/O that could cause improper operation. The use of multilayer boards is essential to allow the use of dedicated power planes. The area under any digital components should be a continuous ground plane if possible. Keep any bypass capacitor leads short for best noise rejection and place the capacitors as close to the leads of the devices as possible. The MAXQ3183 must have separate ground areas for the analog (AGND) and digital (DGND) portions, connected together at a single point. Table 7. Virtual Registers That Activate Special Commands DESCRIPTION DATA LENGTH (BYTES) NAME ADDRESS UPD_SFR 0x900 Reading this register copies the mirror registers (R_ADCF, R_ADCRATE, R_ADCACQ, R_SPICF) into hardware SFR registers. The read returns dummy data. 1 UPD_MIR 0xA00 Reading this register copies hardware SFR registers into mirror registers (R_ADCF, R_ADCRATE, R_ADCACQ, R_SPICF). The read returns dummy data. 1 DSPVER 0xC00 Reading this register returns the DSP firmware version number. 2 TEMP_C 0xC01 Reading this register initiates the on-chip temperature sensor conversion. Upon completion, the temperature value is returned in degree Celsius, with a resolution of 1°C. The TEMP_CC register must be configured before reading this register. 2 ENTER STOP 0xC02 Reading this register places the device into Stop Mode. 1 ENTER LOWPM 0xC03 Reading this register places the device into LOWPM Mode. 1 EXIT LOWPM 0xC04 Reading this register exits LOWPM Mode. 1 100 _____________________________________________________________________________________ Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect Additional Documentation Designers must ensure they have the latest MAXQ3183 errata documents. Errata sheets contain deviations from published specifications. A MAXQ3183 errata sheet for any specific device revision is available at www.maxim-ic.com/errata. Technical Support For technical support, go to https://support.maximic.com/micro. Pin Configuration TOP VIEW VN 1 28 V2P INP 2 27 V1P I0P 3 26 V0P I0N 4 25 AVDD I1P 5 24 VREF I1N 6 23 VCOMM I2P 7 22 DVDD I2N 8 21 RESET AGND 9 20 CFQ XTAL2 10 19 CFP XTAL1 11 18 DGND IRQ 12 17 DVDD SSEL 13 16 MISO SCLK 14 15 MOSI Specific Design Considerations for MAXQ3183-Based Systems To reduce the possibility of coupling noise into the microcontroller, the system should be designed with a crystal or oscillator in a metal case that is grounded to the digital plane. Doing so reduces the susceptibility of the design to fast transient noise. Because the MAXQ3183 is designed for use in systems where high voltages are present, care must be taken to route all signal paths, both analog and digital, as far away as possible from the high-voltage components. It is possible to construct more elaborate metering designs using multiple MAXQ3183 devices. This can be accomplished by using a single SPI bus to connect all the MAXQ3183 devices together but using separate slave select lines to individually select each MAXQ3183. MAXQ3183 TSSOP Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 28 TSSOP U28+3 21-0066 _____________________________________________________________________________________ 101 MAXQ3183 CMOS design guidelines for any semiconductor require that no pin be taken above DVDD or below DGND. Violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft failure (unintentional modification of memory contents). Voltage spikes above or below the device’s absolute maximum ratings can potentially cause a devastating IC latchup. Microcontrollers commonly experience negative voltage spikes through either their power pins or generalpurpose I/O pins. Negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. Devices such as keypads can conduct electrostatic discharges directly into the microcontroller and seriously damage the device. System designers must protect components against these transients that can corrupt system memory. Typical Application Circuit VOLTAGE SENSE R1 VA V0P R2 R1 VB V1P R2 MAXQ3183 R1 VC V2P R2 VCOMM CURRENT TRANSFORMER VN I0P R3 R3 I0N I1P R3 R3 I1N I2P R3 LB LC MISO LA MOSI I2N SCLK R3 SSEL MAXQ3183 Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect N MASTER Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 102 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.