MX7672
General Description
The MX7672 is a 12-bit, high-speed, BiCMOS, analog-todigital converter (ADC) that performs conversions in as
little as 3µs while consuming only 110mW of power. The
MX7672 is a plug-in replacement for AD7672.
The MX7672 requires an external -5V reference. A buffered reference input minimizes reference current requirements and allows a single reference to drive several
ADCs. External reference specifications can be chosen
to suit the accuracy of the application. The ADC clock can
be driven from either a crystal or an external clock source,
such as a microprocessor (µP) clock.
Average input range is pin-selectable for 0 to +5V, 0 to
+10V, or ±5V, making the ADC ideal for data-acquisition
and analog input/output cards. A high-speed digital interface (125ns data-access time) with three-state data outputs is compatible with most µPs.
Applications
●●
●●
●●
●●
Telecommunications
Sonar and Radar Signal Processing
High-Speed Data-Acquisition Systems
Personal Computer I/O Boards
Functional Diagram
High-Speed 12-Bit ADC With External
Reference Input Part
Features
●● Plug-In Replacement for AD7672
●● 12-Bit Resolution and Accuracy
●● Fast Conversion Time
• MX7672_ _03 - 3µs
• MX7672_ _05 - 5µs
• MX7672_ _10 - 10µs
●● Operates with +5V and -12V Supplies
●● Buffered Reference Input
●● Low 110mW Power Consumption
●● Choice of +5V, +10V, or ±5V Input Ranges
●● Fast 125ns Bus-Access Time
Ordering Information appears at end of data sheet.
Pin Configurations
TOP VIEW
1
+
AIN1
AIN2
24
2
VREF
VDD
23
3
AGND
VSS
22
4
D11 (MSB)
BUSY
21
5
D10 MX7672 CS
20
6
D9
RD
19
7
D8
CLKOUT
18
8
D7
CLKIN
17
9
D6
D0
16
10
D5
D1
15
11
D4
D2
14
12
DGND
D3
13
PDIP
Pin Configurations continued on last page
19-3126; Rev 1; 1/12
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
Absolute Maximum Ratings
VDD to DGND...........................................................-0.3V to +7V
VSS to DGND.........................................................+0.3V to -17V
AGND to DGND........................................ -0.3V to (VDD + 0.3V)
AIN1, AIN2 to AGND...............................................-15V to +15V
VREF to AGND............................... (VSS - 0.3V) to (VDD + 0.3V)
Digital Input Voltage to DGND
(CLKIN, CS, RD)................................... -0.3V to (VDD + 0.3V)
Digital Output Voltage to DGND
(D11–D0, BUSY, CLKOUT)................... -0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
PDIP (derate 13.3mW/°C above +70°C)....................1067mW
PLCC (derate 10.5mW/°C above +70°C).....................842mW
LCC (derate 10.2mW/°C above +70°C).......................816mW
Operating Temperature Ranges
MX7672K_/L _.....................................................0°C to +70°C
MX7672B_/C _................................................ -40°C to +85°C
MX7672T_/U _.............................................. -55°C to +125°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)
PDIP, LCC....................................................................+260°C
PLCC............................................................................+245°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = +5V ±5%, VSS = -12V ±10%, VREF = -5V, slow-memory mode; fCLK = 4MHz for MX7672_ _03, fCLK = 2.5MHz for MX7672_
_05, fCLK = 1.25MHz for MX7672_ _10; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY (Note 1)
Resolution
Integral Nonlinearity
N
INL
12
Tested range ±5V
MX7672C/L
±1/2
MX7672U, TA = +25°C
±1/2
MX7672U
±3/4
MX7672B/K/T
Differential Nonlinearity
DNL
12 bits, no missing codes over temperature
MX7672C/L/U
Unipolar Offset Error
MX7672B/K/T
MX7672C/L/U
Unipolar Gain Error
MX7672B/K/T
MX7672C/L/U
Bipolar Zero Error
MX7672B/K/T
MX7672C/L/U
Bipolar Gain Error
MX7672B/K/T
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Bits
LSB
±1
±0.9
TA = +25°C
±3
TA = TMIN to TMAX
±4
TA = +25°C
±5
TA = TMIN to TMAX
±6
TA = +25°C
±4
TA = TMIN to TMAX
±6
TA = +25°C
±5
TA = TMIN to TMAX
±7
TA = +25°C
±3
TA = TMIN to TMAX
±4
TA = +25°C
±5
TA = TMIN to TMAX
±6
TA = +25°C
±4
TA = TMIN to TMAX
±6
TA = +25°C
±5
TA = TMIN to TMAX
±7
LSB
LSB
LSB
LSB
LSB
Maxim Integrated │ 2
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
Electrical Characteristics (continued)
(VDD = +5V ±5%, VSS = -12V ±10%, VREF = -5V, slow-memory mode; fCLK = 4MHz for MX7672_ _03, fCLK = 2.5MHz for MX7672_
_05, fCLK = 1.25MHz for MX7672_ _10; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Synchronous Clk
(12.5 clks)
Conversion Time
tCONV
Asynchronous Clk
(12 to 13 clks)
MIN
TYP
MAX
UNITS
3.125
MX7672_ _03
MX7672_ _05
5
MX7672_ _10
10
MX7672_ _03
3.0
MX7672_ _05
4.8
5.2
MX7672_ _10
9.6
10.4
LSB
3.25
LSB
ANALOG AND REFERENCE INPUTS
Unipolar input ranges 0 to +5V, 0 to +10V
Analog Input Current (AIN1/
AIN2)
3.5
Bipolar range ±5V
VREF Input Range (Note 2)
±1.75
-5.05
VREF Input Current
mA
-4.95
V
±3
µA
0.8
V
LOGIC
Input Low Voltage
VINL
CS, RD, CLKIN
Input High Voltage
VINH
CS, RD, CLKIN
Input Current
IIN
V
CS, RD; VIN = 0V to VDD
±10
CLKIN; VIN = 0V to VDD
±20
10
pF
0.4
V
Input Capacitance (Note 2)
CIN
Output Low Voltage
VOL
D11–D0, BUSY, CLKOUT, ISINK = 1.6mA
Output High Voltage
VOH
D11–D0, BUSY, CLKOUT,
ISOURCE = 200µA
High-Impedance State Leakage
Current
ILKG
D11–D0, VOUT = 0V to VDD
High-Impedance State Output
Capacitance (Note 2)
2.4
4.0
µA
V
COUT
±10
µA
15
pF
POWER REQUIREMENTS
Supply Voltage
VDD
4.75
5
5.25
VSS
-13.2
-12
-10.8
IDD
7
V
ISS
CS = RD = VDD, VAIN1 = VAIN2 = 5V,
BUSY = HIGH
PD
VDD = 5V, VSS = -12V
110
179
mW
Power-Supply Rejection,
VDD Only
FS change, VSS = -12V, VDD = 4.75V
to 5.25V
±1/4
±2
LSB
Power-Supply Rejection,
VSS Only
FS change, VDD = 5V, VSS = -10.8V
to -13.2V
±1/2
±1
LSB
Supply Current
Power Dissipation
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-12
mA
Maxim Integrated │ 3
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
Timing Characteristics
(VDD = +5V, VSS = -12V, 100% production tested, unless otherwise noted.) (Note 3, Figures 7, 9, 10)
PARAMETER
SYMBOL CONDITIONS
TA = +25°C
ALL GRADES
MIN
TYP
MAX
TA = TMIN to TMAX
MX7672K/L/B/C
TA = TMIN to TMAX
MX7672T/U
MIN
MIN
TYP
MAX
TYP
UNITS
MAX
CS to RD Setup Time
(Note 2)
t1
RD to BUSY Delay
t2
CL = 50pF
70
190
230
270
ns
Data-Access Time (Note 4)
t3
CL = 100pF
50
125
150
170
ns
RD Pulse Width (Note 2)
t4
t3
t3
t3
ns
CS to RD Hold Time
(Note 2)
t5
0
0
0
ns
Data-Setup Time After
BUSY (Note 4)
t6
Bus-Relinquish Time
(Note 5)
t7
Delay Between Read
Operations
t8
CLKIN to BUSY Delay
(Note 2)
t9
RD to CLKIN Setup/Hold
Time (Notes 2, 6)
t10
0
CL = 100pF
0
ns
40
70
90
100
ns
30
75
85
90
ns
200
200
120
25
0
100
200
150
25
100
25
ns
180
ns
100
ns
Note 1: VDD = +5V, VSS = -12V, 1 LSB = FS/4096. Performance over power-supply tolerance is guaranteed by power-supply rejection test.
Note 2: Guaranteed by design.
Note 3: All inputs are 0 to +5V swing with tr = tf = 5ns (10% to 90% of +5V) and timed from a voltage level of +1.6V.
Note 4: t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross +0.8V or
+2.4V.
Note 5: t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuit of Figure 2.
Note 6: For predictable conversion times, RD to CLKIN falling edge must be outside this window. If t10 < 25ns, conversion will skip
first falling CLKIN edge and start on second falling CLKIN edge. If t10 > 100ns, conversion will start on first falling CLKIN
edge.
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Maxim Integrated │ 4
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
Pin Description
PIN
24-PIN
28-PIN
—
1, 8, 15, 22
1
2
NAME
FUNCTION
N.C.
No Connection
2
AIN1
Analog Input
3
VREF
Voltage-Reference Input
3
4
AGND
Analog Ground
4–11
5–13
D11–D4
12
14
DGND
Digital Ground
13–16
16–19
D3–D0
Three-State Data Outputs
17
20
CLKIN
18
21
CLKOUT
19
23
RD
20
24
CS
21
25
BUSY
22
26
VSS
Negative Supply, -12V
23
27
VDD
Positive Supply, +5V
24
28
AIN2
Analog Input
Three-State Data Outputs. They are active when CS and RD are low. D11 is the
most significant bit.
Clock Input. Connect an external TTL-compatible clock to CLKIN. Alternatively,
insert a crystal or ceramic resonator between CLKIN and CLKOUT.
Clock Output. When using an external clock, an inverted CLKIN signal appears on
CLKOUT. See CLKIN description.
READ Input. Along with CS, this active-low signal enables the three-state drivers
and starts a conversion.
CHIP SELECT. Along with RD, this active-low signal enables the three-state drivers
and starts a conversion.
BUSY. Low while a conversion is in progress. BUSY indicates converter status.
Figure 1. Load Circuits for Access Time
Figure 2. Load Circuits for Bus-Relinquish Time
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Figure 3. MX7672 Operational Diagram
Maxim Integrated │ 5
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
Detailed Description
Clock
Converter Operation
Internal Clock Oscillator
The MX7672 uses a successive approximation technique
to convert an analog input to a 12-bit digital output code.
The control logic provides easy interface to most µPs
(Figure 3).
Figure 4 shows the MX7672 analog-equivalent circuit. The
internal digital-to-analog converter (DAC) is controlled by
a successive approximation register (SAR), has an output
impedance of 2.5kΩ, and connects directly to the comparator input. The analog inputs AIN1 and AIN2 connect to
the same comparator input through 5kΩ resistors.
A conversion starts at the falling edge of CS and RD and
cannot be restarted after initiation. The BUSY output goes
low when the conversion starts and can be used to control
an external sample-and-hold when measuring wide bandwidth input signals.
Figure 6 shows the MX7672 clock circuitry. Minimize the
capacitive load on the CLKOUT pin for low power dissipation and to avoid digital coupling of the CLKOUT buffer
current to the comparator. CLKOUT should be left open if
an external clock source is used to drive CLKIN. Connect
a crystal/ceramic resonator between CLKOUT and CLKIN
if the internal oscillator is used.
Control Inputs Synchronization
When RD is not synchronized with the ADC clock, the
conversion time can vary from 12 to 13 clock cycles. The
SAR changes state on the falling edge of the CLKIN input
(or rising edge on the CLKOUT pin). Use the following
guidelines to ensure a fixed conversion time: The MX7672
RD input should go low at the rising edge of CLKIN. In
this case, the conversion lasts 12.5 clock cycles, and
The SAR is set, asynchronously with the clock input, to
half scale when CS and RD go low. At the second falling
edge of CLKIN (or rising edge of CLKOUT) following a
conversion start, the output of the comparator is latched
into the SAR most significant bit (MSB/D11) (Figure 5).
The MSB is kept if the analog input is greater than half
scale or dropped if it is smaller. The next bit (D10) is then
set with the DAC output either at 1/4 scale (if the MSB
was dropped) or 3/4 scale (if the MSB was kept). The
conversion continues in this manner until the LSB is tried.
At conversion end, following a falling CLKIN signal, BUSY
goes high, and the SAR result is latched into three-state
output buffers.
Figure 5. Operating Waveforms Using an External Clock
Source for CLKIN
Figure 4. MX7672 AIN Inputs
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Figure 6. MX7672 Internal Clock Circuit
Maxim Integrated │ 6
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
the conversion time is 3.125µs when fCLK = 4MHz, 5µs
when fCLK = 2.5MHz, and 10µs when fCLK = 1.25MHz.
The delay from the falling edge of RD to the falling edge
of CLKIN must not be less than 100ns to ensure the 12.5
clock cycle conversion time (Figure 7). This gives the
external sample-and-hold 1.5 clock cycles to settle from
hold transients. An additional 1/2 clock cycle of settling
can be allowed for the sample-and-hold by having RD go
low at the falling edge of CLKIN. This results in a 13-cycle
conversion time (3.25µs, 5.2µs, and 10.4µs).
Slow-Memory Mode
Digital Interface
ROM Mode
Timing and Control
CS and RD control conversion start and data-read operations. Figure 8 shows the logic equivalent for the conversion and the data-output control circuitry. A logic-low
at both inputs starts a conversion. Once a conversion
is in progress, it cannot be restarted. The BUSY output
remains low during the entire conversion cycle.
Figures 9 and 10 outline the two interface modes (slow
memory and ROM). Slow-memory mode is for µPs that
can be forced into a wait state for periods as long as the
MX7672 conversion time. ROM mode is for µPs that cannot be forced into a wait state. In both interface modes, a
processor read operation to the ADC address starts the
conversion. In the ROM mode, a second read operation
accesses the conversion result.
Figure 7. MX7672 RD and CLKIN for Synchronous Operation
and Conversion Time of 12.5 Clock Cycles
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The timing diagram in Figure 9 illustrates slow-memory
mode, which is designed for µPs with a wait state. CS
and RD go low, triggering a conversion, and are kept low
until the conversion is complete. BUSY responds by going
low, and data from the previous conversion remains on
the three-state data outputs. At conversion end, BUSY
returns high, and the output latches transfer the new
conversion results to the three-state data outputs. The µP
completes the read operation by taking CS and RD high.
The ROM mode avoids placing the µP into a wait state.
A conversion begins with a read operation. While CS and
RD are low, data from the last conversion is available on
the data outputs. A second read operation reads the new
data and begins the conversion process again. A delay
at least as long as the MX7672 conversion time must be
allowed between read operations. The data on the output
bus is in a parallel format in either mode.
Application Hints
Digital Bus Noise
If the data bus connected to the ADC is active during a
conversion, coupling from the data pins to the ADC comparator may cause LSBs of error. Using slow-memory
mode avoids this problem by placing the µP into a wait
state during the conversion. In ROM mode, if the data bus
is active during the conversion, use three-state drivers to
isolate the bus from the ADC.
Figure 8. Logic for Control Inputs CS and RD Internal
Maxim Integrated │ 7
MX7672
ROM Mode
Digital noise is generated in the ADC when RD or CS
go high, and the output data drivers are disabled after a
conversion is started. This noise will feed into the ADC
comparator and cause large errors if it coincides with the
time the SAR is latching a bit decision. To avoid this problem, RD and CS should be active for less than one clock
cycle. In other words, the RD and CS low pulse should
be less than 250ns for the MX7672_ _03, 400ns for the
MX7672_ _05, and 1µs for the MX7672_ _10. If this cannot be done, the RD or CS signal must go high at a rising
edge of CLKIN, since the comparator output is always
latched at falling edges of CLKIN.
Physical Layout
For the best system performance, PCBs should be used
for the MX7672; wire-wrap boards are not recommended.
Separate the digital-analog-signal lines as much as possible in the board layout. Do not run analog and digital
lines parallel to each other or digital lines underneath the
MX7672 package.
Grounding
Figure 11 shows the recommended system ground connections. Establish a single-point analog ground (star
ground), separate from the logic ground, at AGND of the
MX7672. Connect all other analog grounds and DGND of
the MX7672 to this star ground (no other digital grounds
should be connected to this point). For noise-free operation of the ADC, use a low-impedance ground return to the
power supply from this star ground.
Power-Supply Bypassing
The ADC’s high-speed comparator is sensitive to high
frequency noise in the VDD and VSS power supplies.
These supplies should be bypassed to the analog star
ground with 0.1µF and 10µF bypass capacitors with
minimum lead length for supply noise rejection. If the +5V
power supply is very noisy, a small (10Ω to 20Ω) resistor
can be connected (Figure 11) to filter external noise.
Driving the Analog Input
The input signal leads to AIN and the input return leads to
AGND should be as short as possible to minimize input noise
coupling. Use shielded cables if the leads must be long.
The input impedance at each AIN is typically 5kΩ. The
amplifier driving AIN must have low enough DC output
impedance for low gain error. Furthermore, low AC output
impedance is needed since the analog input current is
modulated at the clock rate during a conversion (up to
4MHz for MX7672_ _03, 2.5MHz for MX7672_ _05, or
1.25MHz for the MX7672_ _10). The output impedance of
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High-Speed 12-Bit ADC With External
Reference Input Part
the driving amplifier is equal to its open-loop output impedance divided by the loop gain at the frequency of interest.
MX7672_ _05/10 - The MX7672_ _05/10 maximum clock
rate of 2.5MHz makes it possible to drive AIN with amplifiers like the OP42, AD711 or a Maxim OP27. A MAX400
or a Maxim OP07 can also be used up to 1.25MHz clock
rate.
MX7672_ _03 - The MX7672_ _03, with a maximum 4MHz
clock rate, might exhibit settling problems with the above
amplifiers. An LF356, LF400, or LT1056 can be used to
drive the input. Alternatively, an emitter follower buffer
inside the feedback loop of a Maxim OP27, an OP42, or
an AD711 improves high-frequency output impedance.
Reference Input
VREF connects to an external -5V source. This may be
either a precision negative reference, a positive reference
(such as the MX584) connected as a two-terminal device
to provide -5V (Figure 16), or an existing system reference.
The allowed input range at REFIN is -5.1V to -4.9V. VREF
(and AIN2 in bipolar input operation) should be bypassed
to ground with a 10µF electrolytic capacitor in parallel with
a 0.1µF ceramic capacitor.
If the external reference is biased from a power supply
other than VSS, care must be taken to ensure that VSS
is applied to the ADC before VREF. If supply sequencing
is uncertain, connect a diode between VSS and VREF, as
shown in Flgure 12. No diode is needed if the reference
source is powered from the same supply as VSS.
MX7672 to Sample-and-Hold Interface
The analog input to the ADC must be stable to within
1/2 LSB during the entire conversion for specified 12-bit
accuracy. This limits the input-signal bandwidth to less
than 6Hz for sinusoidal inputs, even when using the faster
MX7672_ _03. A sample-and-hold should be used for
higher bandwidth signals.
The BUSY output from the MX7672 may be used to
provide the TRACK/HOLD signal to the sample-and-hold
amplifier. However, since the ADC’s DAC is switched at
approximately the same time as the BUSY signal goes
low, sample-and-hold transients caused by DAC switching may result in code-dependent errors due to sampleand-hold aperture delay. Adding a NAND (inverted AND)
gate ensures that the sample-and-hold is switched to the
hold mode BEFORE any disturbances occur (Figures 13
and 14). The NAND gate solution works only if the width
of the RD pulse is wider than the RD to BUSY delay in
the MX7672. If this is not the case, use a flip-flop, which
is set by the falling edge of RD and reset by the rising
edge of BUSY.
Maxim Integrated │ 8
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
Figure 9. Slow-Memory Mode Timing Diagram
Figure 10. ROM-Mode Timing Diagram
Figure 11. Power-Supply Grounding Practice
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Figure 12. VREF/VSS Diode Clamp (See Reference Input section)
Maxim Integrated │ 9
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
Figure 13. MX7672—AD585 Sample-and-Hold Interface
Figure 14. MX7672—HA5320 Sample-and-Hold Interface
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Maxim Integrated │ 10
MX7672
For synchronous RD and CLKIN, the hold settling time
allowed for the sample-and-hold is 375ns (MX7672_03),
600ns (MX7672_ _05), and 1.5µs (MX7672_ _ 10).
The maximum sampling rate is 125kHz with a 2.5MHz
clock and 64.5kHz with a 1MHz clock, allowing for a 3µs
sample-and-hold acquisition time.
Although this circuit works well for the 1MHz clock rate, a
faster sample-and-hold amplifier, such as the HA5320, is
recommended at a 2.5MHz clock rate.
MX7672_ _03—Figure 14 is the MX7672_ _03 to HA5320
interface. The maximum sampling rate is 210kHz wtth a
4MHz clock, which allows a 1.5µs acquisition time. The
HA5320 can also be replaced by a HA5330 for higher
throughput.
Analog Input Ranges
The MX7672 provides three selectable analog input
ranges: 0 to +5V, 0 to +10V, and ±5V. Figure 15 shows the
High-Speed 12-Bit ADC With External
Reference Input Part
configuration for the two analog inputs (AIN1 and AIN2)
for these ranges.
Unipolar Operation
Figure 16 shows unipolar operation using an MX584 voltage reference configured for -5V.
Figure 17 shows the nominal input/output transfer function
of the MX7672. Code transitions occur halfway between
successive integer LSB values. The output coding is
binary with 1 LSB = Full Scale (FS)/4096. FS is either +5V
or +10V, based on the analog input configurations.
Offset and Full-Scale Adjustment
In applications requiring offset and FS range adjustment, use the circuit in Figure 18. Note: The amplifier
shown could also be a sample-and-hold. Offset should be
adjusted first. Apply ½ LSB (0.61mV) at the analog input
(AIN1 or AIN2) and adjust the offset of the amplifier until
Figure 15. Analog Input Range Configurations
Figure 16. Unipolar Operation Using an MX584 Reference
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Figure 17. MX7672 Ideal Unipolar Transfer Function
Maxim Integrated │ 11
MX7672
the digital output code changes between 0000 0000 0000
and 0000 0000 0001.
0V to +5V range: ½ LSB = 0.61mV
0V to +10V range: ½ LSB = 1.22mV
To adjust the full-scale range, apply FS - 3/2 LSB (last
code transition) at the analog input and adjust R1 until
the output code switches between 1111 1111 1110 and
1111 1111 1111.
0V to +5V range: FS - 3/2 LSB = 4.99817V
0V to +10V range: FS - 3/2 LSB = 9.99634V
High-Speed 12-Bit ADC With External
Reference Input Part
apply -FS/2 + ½ LSB (-4.99878V) at VIN and adjust the
10kΩ potentiometer (Figure 18) until the output code
switches between 0000 0000 0000 and 0000 0000 0001.
Gain is adjusted at full scale or bipolar zero. For full-scale
adjustment, apply FS/2 - 3/2 LSBs (4.99634V) to VIN
and adjust the 200Ω potentiometer until the output code
switches between 1111 1111 1110 and 1111 1111 1111.
Alternatively, to adjust gain at bipolar zero, apply -1.22mV
at VIN and adjust the 200Ω potentiometer until the output
code switches between 0111 1111 1111 and 1000 0000
0000.
Bipolar Operation
The bipolar input range is ±5V. VIN is applied to AIN1. +5V
to AIN2, and -5V to VREF. This requires two reference
voltages: -5V for the VREF input and +5V for the AIN2
input. Figure 19 shows these reference voltages are produced from a MAX675 reference and a MAX400 op amp
configured as an inverting amplifier.
The ideal input/output transfer characteristic after offset
and gain adjustment is shown in Figure 20. The LSB is
2.44mV (10V/4096).
The resistors used in bipolar applications should be the
same type from the same manufacturer to obtain low
temperature drifts. 0.1% resistors are recommended for
applications where offset and full-scale adjustments must
be made in bipolar circuits. If low tolerances are used,
larger value potentiometers must be used, which results
in poor trim resolution and higher temperature drift.
Offset and Gain Adjustment
Figure 19. Bipolar Operation with Offset and Gain-Error Adjust
Figure 18. Unipolar Operation with Gain Adjust
Figure 20. Ideal Input/Output Transfer Characteristic for Bipolar
Operation
In bipolar operation, the offset is trimmed at negative
full scale and should always be adjusted first. For offset,
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Maxim Integrated │ 12
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
Ordering Information
PART
26 VSS
27 VDD
28 AIN2
1 N.C.
2 AIN1
3 VREF
4 AGND
Pin Configurations (continued)
MX7672KN03+
D10 6
D9 7
MX7672
D8 9
D7 10
N.C.
VSS
AIN1
VDD
VREF
1
AIN2
AGND
2
28 27
26
0°C to +70°C
24 PDIP
±1
MX7672KP03+
0°C to +70°C
24 CS
MX7672BE03+
-40°C to +85°C
23 RD
5µs MAXIMUM CONVERSION TIME
22 N.C.
MX7672KN05+
0°C to +70°C
24 PDIP
±1
21 CLKOUT
MX7672LN05+
0°C to +70°C
24 PDIP
±½
28
PLCC†
±1
PLCC†
±1
±½
MX7672KP05+
0°C to +70°C
28
19 D0
MX7672LP05+
0°C to +70°C
28 PLCC†
MX7672TE05+
-55°C to +125°C 28 LCC†*
±1
MX7672UE05+
-55°C to +125°C 28 LCC†*
±3/4
10µs MAXIMUM CONVERSION TIME
+
MX7672KN10+
0°C to +70°C
24 PDIP
±1
MX7672LN10+
0°C to +70°C
24 PDIP
±1/2
MX7672KP10+
0°C to +70°C
28 PLCC†
±1
MX7672LP10+
0°C to +70°C
28 PLCC†
±½
MX7672TE10+
-55°C to +125°C 28 LCC†*
±1
MX7672UE10+
LCC†*
-55°C to +125°C 28
5
25
BUSY
†Contact factory for availability.
D10
6
24
CS
*Contact factory for processing to MIL-STD-883.
23
RD
22
N.C.
D9
7
N.C.
8
D8
9
21
CLKOUT
D7
10
20
CLKIN
D6
11
19
D0
PLCC
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18
D1
D2
DGND
16 17
D3
D4
15
N.C.
14
D5
MX7672
13
±3/4
+Denotes a lead(Pb)-free/RoHS-compliant package.
D11 (MSB)
12
±1
28 LCC†
20 CLKIN
LCC
3
LINEARITY
(LSB)
25 BUSY
D1 18
D2 17
D3 16
N.C. 15
D4 13
DGND 14
D5 12
D6 11
4
PINPACKAGE
3µs MAXIMUM CONVERSION TIME
D11 (MSB) 5
N.C. 8
TEMP RANGE
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
24 PDIP
N24+3
21-0043
—
28 PLCC
Q28+2
21-0049
90-0235
28 LCC
L28+2
21-4497
90-0178
Maxim Integrated │ 13
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
Revision History
REVISION
NUMBER
REVISION
DATE
0
4/91
Initial release
1
1/12
Remove CERDIP packages from Ordering Information
DESCRIPTION
PAGES
CHANGED
—
1, 13
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2012 Maxim Integrated Products, Inc. │ 14
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