3D7612W-20K

3D7608 & 3D7612 8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS (SERIES 3D7608 & 3D7612: PARALLEL INTERFACE) FEATURES • • • • • • • • • All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Programmable via latched parallel interface Increment range: 0.25ns through 800us Pulse w idth tolerance: 1% (See Table 1) Supply current: 8mA typical Temperature stability: ±1.5% max (-40C to 85C) Vdd stability: ±0.5% max (4.75V to 5.25V) TRIG RES P0 P2 P4 P6 NC GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 data 3 delay devices, inc. VDD OUT OUTB P1 P3 P5 P7 AE TRIG RES P0 P2 P4 P6 P8 NC P10 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11  PACKAGES / PINOUTS VDD OUT OUTB P1 P3 P5 P7 P9 AE P11 3D7608R-xx SOIC 3D7612W -xx SOL For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION The 3D7608 & 3D7612 devices are versatile 8- & 12-bit programmable monolithic pulse generators. A rising-edge on the trigger input (TRIG) initiates the pulse, which is presented on the output pins (OUT,OUTB). The pulse width, programmed via the parallel interface, can be varied over 255 (3D7608) or 4095 (3D7612) equal steps according to the formula: tPW = tinh + addr * tinc where addr is the programmed address, tinc is the pulse width increment (equal to the device dash number), and tinh is the inherent (address zero) pulse width. The device also offers a reset input (RES), which can be used to terminate the pulse before the programmed time has expired. PIN DESCRIPTIONS TRIG RES OUT OUTB Trigger Input Reset Input Pulse Output Complementary Pulse Output AE Address Enable Input P0-P11 Address Inputs VDD +5 Volts GND Ground NC Do not connect externally The all-CMOS 3D7608 & 3D7612 integrated circuits have been designed as reliable, economic alternatives to hybrid TTL pulse generators. The 3D7608 is offered in a standard 16-pin SOIC, and the 3D7612 is offered in a standard 20-pin SOL. TABLE 1: PART NUMBER SPECIFICATIONS PART # (8-BIT) 3D7608R-0.25 3D7608R-0.5 3D7608R-1 3D7608R-2 3D7608R-5 3D7608R-10 3D7608R-20 3D7608R-50 3D7608R-100 3D7608R-200 3D7608R-500 3D7608R-1K 3D7608R-2K 3D7608R-5K 3D7608R-10K 3D7608R-20K 3D7608R-50K PART # (12-BIT) 3D7612W-0.25 3D7612W-0.5 3D7612W-1 3D7612W-2 3D7612W-5 3D7612W-10 3D7612W-20 3D7612W-50 3D7612W-100 3D7612W-200 3D7612W-500 3D7612W-1K 3D7612W-2K 3D7612W-5K 3D7612W-10K 3D7612W-20K 3D7612W-50K Pulse Width Increment 0.25ns ± 0.12ns 0.50ns ± 0.25ns 1.0ns ± 0.5ns 2.0ns ± 1.0ns 5.0ns ± 2.5ns 10ns ± 5.0ns 20ns ± 10ns 50ns ± 25ns 100ns ± 50ns 200ns ± 100ns 500ns ± 250ns 1.0us ± 0.5us 2.0us ± 1.0us 5.0us ± 2.5us 10us ± 5.0us 20us ± 10us 50us ± 25us Maximum P.W. (8-Bit) 73.25ns ± 3ns 137.5ns ± 3ns 265ns ± 3ns 520ns ± 6ns 1.28us ± 13ns 2.56us ± 26ns 5.11us ± 52ns 12.8us ± 128ns 25.5us ± 255ns 51.0us ± 510ns 128us ± 1.3us 255us ± 2.6us 510us ± 5.2us 1.28ms ± 13us 2.55ms ± 26us 5.10ms ± 52us 12.8ms ± 128us Maximum P.W. (12-Bit) 1.03us ± 10ns 2.05us ± 21ns 4.10us ± 41ns 8.19us ± 82ns 20.5us ± 205ns 41.0us ± 410ns 81.9us ± 819ns 205us ± 2.1us 410us ± 4.1us 819us ± 8.2us 2.05ms ± 21us 4.10ms ± 41us 8.19ms ± 82us 20.5ms ± 205us 41.0ms ± 410us 81.9ms ± 819us 205ms ± 2.1 ms PART # (8-BIT) 3D7608R-100K 3D7608R-200K 3D7608R-500K 3D7608R-800K Pulse Width Increment 100us ± 50us 200us ± 100us 500us ± 250us 800us ± 400us Maximum P.W. (8-Bit) 25.5ms ± 260us 51.0ms ± 510us 128ms ± 1.3ms 204ms ± 2.1ms NOTE: Any increment between 0.25ns and 800us (50us for the 12-bit generator) not shown is also available as a standard device. 2006 Data Delay Devices Doc #06009 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 3D7608 & 3D7612 APPLICATION NOTES GENERAL INFORMATION Figure 1 illustrates the main functional blocks of the 3D7608 & 3D7612. Since these devices are CMOS designs, all unused input pins must be returned to well-defined logic levels, VDD or Ground. The pulse generator architecture is comprised of a number of delay cells (for fine control) and an oscillator & counter (for coarse control). Each device is individually trimmed for maximum accuracy and linearity throughout the address range. The change in pulse width from one address setting to the next is called the increment, or LSB. It is nominally equal to the device dash number. The minimum pulse width, achieved by setting the address to zero, is called the inherent pulse width. For best performance, it is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. Also, signal traces should be kept as short as possible. error is less than 1.0 LSB at every address (see Table 1). The absolute error is defined as follows: eabs = tPW – (tinh + addr * tinc) where tinh is the nominal inherent delay. The absolute error is limited to 1.5 LSB or 3.0 ns, whichever is greater, at every address. The inherent pulse width error is the deviation of the inherent width from its nominal value. It is limited to 2.0 ns from the nominal inherent pulse width of 10 ns. PULSE WIDTH STABILITY The characteristics of CMOS integrated circuits are strongly dependent on power supply and temperature. The 3D7608 & 3D7612 utilize novel compensation circuitry to minimize the performance variations induced by fluctuations in power supply and/or temperature. With regard to stability, the output pulse width of the 3D7608 & 3D7612 at a given address, addr, can be split into two components: the inherent pulse width (tinh) and the relative pulse width (tPW - tinh). These components exhibit very different stability coefficients, both of which must be considered in very critical applications. The thermal coefficient of the relative pulse width is limited to ±250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of ±1.5% from the room-temperature pulse width. This holds for all dash numbers. The thermal coefficient of the inherent pulse width is nominally +10ps/C for dash numbers less than 1, and +15ps/C for all other dash numbers. The power supply sensitivity of the relative pulse width is ±0.5% over the 4.75V to 5.25V operating range, with respect to the pulse width at the nominal 5.0V power supply. This holds for all dash numbers. The sensitivity of the inherent pulse width is nominally –1ps/mV for all dash numbers. It should also be noted that the DNL is also adversely affected by thermal and supply variations, particularly at the MSL/LSB crossovers (ie, 63 to 64, 127 to 128, etc). PULSE WIDTH ACCURACY There are a number of ways of characterizing the pulse width accuracy of a programmable pulse generator. The first is the differential nonlinearity (DNL), also referred to as the increment error. It is defined as the deviation of the increment at a given address from its nominal value. For most dash numbers, the DNL is within 0.5 LSB at every address (see Table 1: Pulse Width Step). The integrated nonlinearity (INL) is determined by first constructing the least-squares best fit straight line through the pulse-width-versusaddress data. The INL is then the deviation of a given width from this line. For all dash numbers, the INL is within 1.0 LSB at every address. The relative error is defined as follows: erel = (tPW – tinh) – addr * tinc where addr is the address, tPW is the measured width at this address, tinh is the measured inherent width, and tinc is the nominal increment. It is very similar to the INL, but simpler to calculate. For most dash numbers, the relative Doc #06009 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D7608 & 3D7612 APPLICATION NOTES (CONT’D) TRIGGER & RESET TIMING Figure 2 shows the timing diagram of the device when the reset input (RES) is not used. In this case, the pulse is triggered by the rising edge of the TRIG signal and ends at a time determined by the address loaded into the device. While the pulse is active, any additional triggers occurring are ignored. Once the pulse has ended, and after a short recovery time, the next trigger is recognized. Figure 3 shows the timing for the case where a reset is issued before the pulse has ended. Again, there is a short recovery time required before the next trigger can occur. ADDRESS UPDATE The 3D7608/3D7612 can operate in one of two addressing modes. In the transparent mode (AE held high), the parallel address inputs must persist for the duration of the output pulse, in accordance with Figure 4. In the latched mode, the address data is stored internally, which allows the parallel inputs to be connected to a multi-purpose data bus. Timing for this mode is also shown in Figure 4. TRIGGER TRG RESET RES INPUT LOGIC DELAY LINE OSCILLATOR/ COUNTER OUTPUT LOGIC OUT OUTB PULSE OUT BIT-SHIFT LOGIC ADDR ENABLE AE 8- OR 12-BIT LATCH P0 P1 P7 P8 P9 P10 P11 Figure 1: Functional block diagram tTW TRIG tID OUT OUTB tPW tRTO Figure 2: Timing Diagram (RES=0) tTW TRIG tRW RES tRTR tID OUT OUTB tRD Figure 3: Timing Diagram (with reset) Doc #06009 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D7608 & 3D7612 APPLICATION NOTES (CONT’D) Addr TRIG OUT VALID VALID tOA tAT1 Transparent Mode (AE=1) tAW AE tDS Addr VALID tDH tAT1 tOA TRIG OUT tAT2 Latched Mode Figure 4: Address Update Doc #06009 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 3D7608 & 3D7612 DEVICE SPECIFICATIONS TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -10 -55 MAX 7.0 VDD+0.3 10 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 4.75V to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL TR & TF MIN 2.0 0.8 1.0 1.0 -4.0 TYP 8.0 MAX 12.0 UNITS mA V V µA µA mA mA 2.5 ns NOTES -35.0 4.0 15.0 2.0 VIH = VDD VIL = 0V VDD = 4.75V VOH = 2.4V VDD = 4.75V VOL = 0.4V CLD = 5 pf *IDD(Dynamic) = 2 * CLD * VDD * F where: CLD = Average capacitance load/output (pf) F = Trigger frequency (GHz) Input Capacitance = 5 pf typical Output Load Capacitance (CLD) = 25 pf max TABLE 4: AC ELECTRICAL CHARACTERISTICS (-40C to 85C, 4.75V to 5.25V) PARAMETER Trigger Width Trigger Inherent Delay Output Pulse Width Re-trigger Time Reset Width Reset to Output Low End of Reset to Next Trigger AE Width Data Setup to AE Low Data Hold from AE Low Output Low to AE High Data Valid to Trigger AE High to Trigger SYMBOL tTW tID tPW tRTO tRW tRD tRTR tAW tDS tDH tOA tAT1 tAT2 MIN 5 TYP MAX 5 3 TBD 5 3 12 10 3 3 10 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns REFER TO Figure 2 & 3 Figure 2 & 3 Figure 2 Figure 2 Figure 3 Figure 3 Figure 3 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Doc #06009 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 5 3D7608 & 3D7612 TYPICAL APPLICATIONS EN TRIG RES OUT OUTB FOUT AE Addr AE Addr 3D7608 or 3D7612 FOUT = 1 / (tPW + tID + tNOR) EN tID + tNOR FOUT Figure 5: Programmable Oscillator IN 0V TRIG RES AE Addr OUT OUTB +5 SETB D CK RESB OUT D-FF Q QB 3D7608/12 R-Edge Delay TRIG OUT OUTB +5 SETB D CK RESB AER AEF Addr 0V RES AE Addr 3D7608/12 F-Edge Delay D-FF Q QB IN tPW R + tID + tFF OUT tPW F + tID + tFF Figure 6: Programmable Delay Line Doc #06009 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 6 3D7608 & 3D7612 SILICON DEVICE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (Vcc): 5.0V ± 0.1V Input Pulse: High = 3.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 20ns Period: PERIN = 2 x Prog’d Pulse Width OUTPUT: Rload: Cload: Threshold: 10KΩ ± 10% 5pf ± 10% 1.5V (Rising & Falling) Dev ice Under Test 10KΩ 5pf Digital Scope 470Ω NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER REF PULSE GENERATOR OUT TRIG TRIG DEVICE UNDER TEST (DUT) OUT IN TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER Figure 7: Test Setup PERIN PW IN tRISE INPUT SIGNAL 2.4 1.5 0.6 tFALL VIH 2.4 1.5 0.6 VIL tPW tID OUTPUT SIGNAL 1.5 VOH 1.5 VOL Figure 8: Timing Diagram Doc #06009 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 7