WP2002A-Y-JCS

DB LECTRO Inc. SPECIFICATION CUSTOMER : Ver:0 MODULE NO.: WP2002A-Y-JCS APPROVED BY: ( FOR CUSTOMER USE ONLY ) SALES BY APPROVED BY CHECKED BY PREPARED BY ISSUED DATE: 第 1 頁，共 18 頁 www.dblectro.com Version modify record NO. Version Date Modify contents Page Remarks 第 2 頁，共 18 頁 www.dblectro.com Contents 1.Module Classification Information 2.Precautions in use of LCD Modules 3.General Specification 4.Absolute Maximum Ratings 5.Electrical Characteristics 6.Optical Characteristics 7.Interface Pin Function 8.Contour Drawing & Block Diagram 9.Function Description 10.Character Generator ROM Pattern 11.Instruction Table 12.Timing Characteristics 13.Initializing of LCM 14.Quality Assurance 15.Reliability 第 3 頁，共 18 頁 www.dblectro.com 1.Module Classification Information WP 2002 A－Y－ JCS 6 ○ Brand：DB LECTRO Inc. Display Type：H→Character Type, G→Graphic Type , P→PLED Display Font：Character 16 words, 2Lines. Model serials no. Backlight Type： Y→Yellow Green 6 JCS: English and Japanese standard font ○ Special Code 2.Precautions in use of PLED Modules (1)Avoid applying excessive shocks to the module or making any alterations or modifications to it. (2)Don’t make extra holes on the printed circuit board, modify its shape or change the components of PLED module. (3)Don’t disassemble the PLEDM. (4)Don’t operate it above the absolute maximum rating. (5)Don’t drop, bend or twist PLEDM. (6)Soldering: only to the I/O terminals. (7)Storage: please storage in anti-static electricity container and clean environment. 3.General Specification Item Number of Characters Module dimension View area Active area Dot size Dot pitch Character size Character pitch LCD type Duty PLED , Green 1/16 Dimension 20 characters x 2 Lines 116.0 x 37.0 x 9.5(MAX) 75.0 x 16.0 71.37 x 11.87 0.57 x 0.67 0.6 x 0.7 2.97 x 5.57 3.60 x 6.30 Unit － mm mm mm mm mm mm mm 第 4 頁，共 18 頁 www.dblectro.com 4.Absolute Maximum Ratings Item Operating Temperature Storage Temperature Input Voltage Supply Voltage For Logic Supply Voltage For LCD Symbol TOP TST VI VDD-VSS VBT- VSS Min -20 -30 -0.3 -0.3 -0.3 Typ 25 － － － － Max +50 +70 VDD 7 5.0 Unit ℃ ℃ V V V 5.Electrical Characteristics Item Supply Voltage For Logic Supply Voltage For LCD Input High Volt. Input Low Volt. Output High Volt. Output Low Volt. Supply Current Symbol VDD-VSS VBT VIH VIL VOH VOL IDD Condition － Ta=25℃ － － － － VDD=5V Min 4.5 2.0 0.7 VDD -0.3 2.4 － － Typ 5.0 2.5 － － － － 0.35 Max 5.5 5.0 VDD 0.55 － 0.4 0.6 Unit V V V V V V mA 6.Optical Characteristics Item View Angle Contrast Ratio Response Time T fall Brightness Symbol (V)θ (H)φ CR T rise 100 lux － － With polarizer － Condition Min Typ 80 80 100 10 10 40 － Max Unit deg deg － us us nits 第 5 頁，共 18 頁 www.dblectro.com 7.Interface Pin Function Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS VDD ※VBT RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 NC NC Level 0V 5.0V Ground Supply Voltage for logic Description (Variable) Operating voltage for PLED Brightness adjhstment H/L H/L H,H→L H/L H/L H/L H/L H/L H/L H/L H/L － － H: DATA, L: Instruction code H: Read(MPU→Module) L: Write(MPU→Module) Chip enable signal Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 ※Brightness Control VBT Brightness(nits) Power consumption(measured with random texts) 2.5V 20(typical) 50mW 3.0V 45(typical) 63mW Note:1.When random texts pattern is running,averagely,at any instance,about 1/4 of pixels will be on. 2.If VBT is not operated within 2V and 3V,non-uniformity display may occur. 3.You have to use the saving mode by VBT 2.5V in order to make long life. 第 6 頁，共 18 頁 www.dblectro.com 8.Contour Drawing &Block Diagram 4 8.5 2.9 116 93 75.0(VA) 71.37(AA) 6.5 4 9.5 MAX 4.9 4 16 37.0 0.5 31.2 16(VA) 11.87(AA) 15 29 2 1 4 59.0 4.0 108 4- 3.5 PTH 4- 5.5 PAD 1.6 2.97 2.5 2.54 (P2.54*7) 17.78 8.34 0.6 0.57 0.63 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vss Vdd Vo RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 NC NC 16 15 5.57 0.7 0.67 2 1 0.73 PIN DETAIL DOT SIZE SCALE 5/1 MPU 80 series or 68 series RS R/W E DB0~DB7 Com1~16 Controller/Com Driver 20X2 LCD Bias and Power Circuit Vdd Vbt Vss 18.5 D M CL1 CL2 Vdd,Vss,V1~V5 Seg Driver Character located 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DDRAM address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DDRAM address 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 第 7 頁，共 18 頁 ~ 20 13 53 www.dblectro.com 9.Function Description The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written or read from DDRAM or CGRAM. When address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected. RS 0 0 1 1 R/W 0 1 0 1 Operation IR write as an internal operation (display clear, etc.) Read busy flag (DB7) and address counter (DB0 to DB7) Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM) Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR) Busy Flag (BF) When the busy flag is 1, the controller LSI is in the internal operation mode, and the next instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. next instruction must be written after ensuring that the busy flag is 0. Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM The Display Data RAM (DDRAM) This DDRAM is used to store the display data represented in 8-bit character codes. Its extended capacity is 80×8 bits or 80 characters. Below figure is the relationships between DDRAM addresses and positions on the liquid crystal display. High bits Low bits Example: DDRAM addresses 4E AC (hexadecimal) AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0 第 8 頁，共 18 頁 www.dblectro.com Display position DDRAM address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 2-Line by 16-Character Display Character Generator ROM (CGROM) The CGROM generate 5×8 dot or 5×10 dot character patterns from 8-bit character codes. See Table 2. Character Generator RAM (CGRAM) In CGRAM, the user can rewrite character by program. For 5×8 dots, eight character patterns can be written, and for 5×10 dots, four character patterns can be written. Write into DDRAM the character code at the addresses shown as the left column of table 1. To show the character patterns stored in CGRAM. 第 9 頁，共 18 頁 www.dblectro.com Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns Table 1. F o r 5 * 8 d o t c h a ra c te r p a tte rn s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 3 2 1 0 C G R A M A d d re ss 5 H ig h 4 3 2 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C h a ra c te r P a tte rn s ( C G R A M d a ta ) 7 * * * * * * * * * * * * * * * * * 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C h a ra c te r p a tte rn ( 2 ) C h a ra c te r p a tte rn ( 1 ) H ig h Low 0 0 0 0 *0 0 0 0 0 0 0 *0 0 1 Low 00 00 01 01 00010 10 11 11 00 00 01 01 00 1 10 10 11 11 00 00 1 1 1 1 1 1 1 0 0 1 1 H ig h ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** Low 0 0 0 0 0 0 C u rs o r p a tte rn 0 C u rs o r p a tte rn 0 0 0 0 * 1 1 1 * * * F o r 5 * 1 0 d o t c h a ra c te r p a tte rn s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 3 2 1 0 C G R A M A d d re ss 5 H ig h 0 0 0 0 0 0 0 0 1 1 1 1 4 3 2 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 C h a ra c te r P a tte rn s ( C G R A M d a ta ) 7 * * * * * * * * * * * * 6 * * * * * * * * * * * * 5 4 3 0 0 0 0 0 0 0 0 0 * 2 Low 0 0 0 0 0 0 0 0 0 * 0 0 0 0 0 0 0 0 0 * 0 0 0 0 0 * C h a ra c te r p a tte rn 0 0 0 1 0 H ig h Low Low H ig h *0 *0 * * * * * * * * *0 * * 0 0 0 0 *0 0 0 0 0 C u rs o r p a tte rn : " H ig h " 第 10 頁，共 18 頁 www.dblectro.com 10.Character Generator ROM Pattern Table.2 Upper 4 bit Lower 4 bit L LLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH CG RAM (1) LLLL LLLH (2) LLHL (3) LLHH (4) LHLL (5) LHLH (6) LHHL (7) LHHH (8) HLLL (1) HLLH (2) HLHL (3) HLHH (4) HHLL (5) HHLH (6) HHHL (7) HHHH (8) 第 11 頁，共 18 頁 www.dblectro.com 11.Instruction Table Instruction Code Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display 0 0 0 0 0 0 0 0 0 1 Write “00H” to DDRAM and set DDRAM address to “00H” from AC Set DDRAM address to “00H” from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction and Execution time (fosc=270Khz) Description 1.52ms Return Home 0 0 0 0 0 0 0 0 1 － 1.52ms Entry Mode Set 0 0 0 0 0 0 0 1 I/D SH enable the shift of entire display. I/D=1:Increment；0: Decrement SH=1:Display shift on Set display (D), cursor (C), and blinking 37μs Display ON/OFF Control of cursor (B) on/off control bit. 0 0 0 0 0 0 1 D C B D=1:Display on C=1:Cursor display on B=1:Cursor blink on Set cursor moving and display shift control bit, and the direction, without 37μs Cursor or Display Shift 0 0 0 0 0 1 S/C R/L － － changing of DDRAM data. S/C=1:Shift display；0:Move cursor R/L=1:Shift right；0:Shift leftf Set interface data length (DL) DL=1:8-bit；0:4-bit 37μs Function Set 0 0 0 0 1 DL N F － － Set numbers of display lines(N) N=1:Dual line；0:Single line Set display font type (F) F=1:5x10 dots；0:5x8dots 37μs Set CGRAM Address Set DDRAM Address 0 0 0 0 0 1 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 37μs 37μs AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. Whether during internal operation or not Read Busy Flag and Address can be known by reading BF. The 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 contents of address counter can also be read. BF=1:Internal operation BF=0:Ready for instruction Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM). 0μs Write Data to RAM Read Data from RAM 1 1 0 1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 37μs 37μs ＊ ”－”：don’t care 第 12 頁，共 18 頁 www.dblectro.com 12.Timing Characteristics RS VIH1 VIL1 VIH1 VIL1 tAS R/W E DB0 to DB7 VIL1 tAH VIL1 PWEH VIH1 VIL1 VIH1 VIL1 tAH tEf VIL1 tEr VIL1 tDSW VIH1 Valid data tH VIH1 VIL1 tcycE 12.1 Write Operation Ta=25℃, VDD=5.0± 0.5V Item Symbol tcycE PWEH tEr,tEf tAS tAH tDSW tH Min 500 230 － 40 10 80 10 Typ － － － － － － － Max － － 20 － － － － Unit ns ns ns ns ns ns ns Enable cycle time Enable pulse width (high level) Enable rise/fall time Address set-up time (RS, R/W to E) Address hold time Data set-up time Data hold time 第 13 頁，共 18 頁 www.dblectro.com 12.2 Read Operation RS VIH1 VIL1 VIH1 VIL1 tAS R/W E DB0 to DB7 VIH1 tAH VIH1 PWEH VIH1 VIL1 VIH1 VIL1 tAH tEf VIL1 tEr t DDR tDHR Valid data VOH1 *VOL1 VOH1 VOL1* tcycE NOTE: *VOL1 is assumed to be 0.8V at 2 MHZ operation. Ta=25℃, VDD=5.0± 0.5V Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Address set-up time (RS, R/W to E) Address hold time Data delay time Data hold time Symbol tcycE PWEH tEr,tEf tAS tAH tDDR tDHR Min 500 230 － 40 10 － 5 Typ － － － － － － － Max － － 20 － － 160 － Unit ns ns ns ns ns ns ns 第 14 頁，共 18 頁 www.dblectro.com 13.Initializing of LCM Power on Wait for more than 15 ms after VCC rises to 4.5 V BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. ) 0 0 0 0 1 1 * * * * Wait for more than 4.1 ms BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. ) 0 0 1 0 0 1 * * * * Wait for more than 100 µs BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set ( Interface is 8 bits long. ) 0 0 1 * * * * 0 0 1 BF can be checked after the following instructions. When BF is not checked , the waiting time between instructions is longer than execution instruction time. RS R/W DB7 0 0 0 0 0 0 0 0 0 0 0 0 DB6 0 0 0 0 DB5 1 0 0 0 DB4 DB3 DB2 NF 1 0 1 0 0 0 0 0 0 1 DB1 DB0 * * 0 0 0 1 I/D S Function set ( Interface is 8 bits long. Specify the number of display lines and font. ) The number of display lines and character font can not be changed after this point. Display off Display clear Entry mode set Initialization ends 第 15 頁，共 18 頁 8-Bit Ineterface www.dblectro.com Power on Wait for more than 15 ms after VCC rises to 4.5 V BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set ( Interface is 8 bits long. ) Wait for more than 4.1 ms BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set ( Interface is 8 bits long. ) Wait for more than 100 µs BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1 Function set ( Interface is 8 bits long. ) RS R/W DB7 DB6 DB5 DB4 0 0 1 0 0 0 0 0 0 0 1 0 0 0 NF * * 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 I/D S 0 0 0 BF can be checked after the following instructions. When BF is not checked , the waiting time between instructions is longer than execution instruction time. Function set ( Set interface to be 4 bits long. ) Interface is 8 bits in length. Function set ( Interface is 4 bits long. Specify the number of display lines and character font. ) The number of display lines and character font can not be changed after this point. Display off Display clear Entry mode set Initialization ends 4-Bit Ineterface 第 16 頁，共 18 頁 www.dblectro.com 14.Quality Assurance Screen Cosmetic Criteria Item Defect Judgment Criterion A)Clear Size: d mm Acceptable Qty in active area d ≦0.1 Disregard 0.1