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AP7217C-13SPG-13

AP7217C-13SPG-13

  • 厂商:

    DIODES

  • 封装:

  • 描述:

    AP7217C-13SPG-13 - 1.25V 600mA CMOS LDO - Diodes Incorporated

  • 数据手册
  • 价格&库存
AP7217C-13SPG-13 数据手册
AP7217C 1.25V 600mA CMOS LDO Features • • • • • • • • • • • Very Low Dropout Voltage Low Current Consumption: Typ. 40µA Output Voltage: 1.25V Guaranteed 600mA (min) Output Input Range up to 5.5V Current Limiting Stability with Low ESR Capacitors Thermal shutdown Protection Low Temperature Coefficient SOP-8L-EP: Available in “Green” Molding Compound (No Br, Sb) Lead Free Finish / RoHS Compliant (Note 1) General Description The AP7217C low-dropout linear regulator operates from a 2.5V to 5.5V supply and delivers a guaranteed 600mA (min) continuous load current. The space-saving SOP-8L-EP package is suitable for “pocket” and hand-held applications. Applications • • • • CD and MP3 Players Cellular and PCS Phones Digital Still Camera Hand-Held Computers Typical Application U1 VIN 4 VIN VOUT 2 VOUT ON CIN 1uF AP7217C GND 7 EN 8 OFF COUT 1uF AP7217C Rev. 3 DS31424 1 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Ordering Information A P 7217C - 13 S P G - 1 3 Output voltage 13 : 1.25V Package SP : SOP-8L-EP Green G : Green Packing 13 : Tape & Reel Device AP7217C-13SPG-13 Notes: Package Code SP Packaging (Note 2) SOP-8L-EP 13” Tape and Reel Quantity Part Number Suffix 2500/Tape & Reel -13 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html. 2. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. Pin Assignments (1) SOP-8L-EP ( Top View ) GND VOUT GND VIN 1 2 3 4 8 7 6 5 EN GND GND GND SOP-8L-EP Pin Descriptions Pin Name GND VOUT VIN EN Pin No. 1, 3, 5, 6, 7 2 4 8 Ground Voltage Output Supply Voltage High Enable Description AP7217C Rev. 3 DS31424 2 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Block Diagram EN On Off Enable VIN Bandgap ERROR AMP Current Limit VOUT R1 + R2 GND Absolute Maximum Ratings Symbol ESD HBM ESD MM VIN IOUT PD TJ Parameter Human Body Model ESD Protection Machine Model ESD Protection Input Voltage Output Current Power Dissipation SOP-8L-EP Operating Junction Temperature Range Rating 3.5 500 +6 PD/ (VIN-VO) 1650 -40 to +125 Unit KV V V mA mW ºC Recommended Operating Conditions Symbol VIN IOUT TA Parameter Input Voltage Output Current Operating Ambient Temperature Min 2.5 0 -40 Max 5.5 600 85 Unit V mA ºC AP7217C Rev. 3 DS31424 3 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Electrical Characteristics (TA = 25°C, CIN= 1µF, COUT= 1µF, VEN= VIN, unless otherwise noted) Symbol IQ ISTB Parameter Quiescent Current Standby Current Output Voltage Accuracy VOUT Temperature Coefficient Dropout Voltage Maximum Output Current Current Limit Short Circuit Current Line Regulation Load Regulation Power Supply Rejection EN Input Threshold Test Conditions IO = 0mA VEN = Off VIN = 5.0V IO = 30mA, VIN = 5V -40°C to 85°C, IOUT = 30mA IOUT = 100mA, VOUT = 1.25V IOUT = 600mA, VOUT = 1.25V VIN = 5.3V VIN = 5.3V VIN = 5.3V 4.3V ≤ VIN ≤ 5.5V; IOUT = 30mA 1mA ≤ IOUT ≤ 100mA, VIN = 5.3V VIN = 4.3V+ 0.5Vp-pAC, F = 1KHz IOUT = 50mA Output ON Output OFF Min - Typ. 40 2 Max 60 5 1.275 Unit µA µA V ppm / oC mV mA 1.225 1.25 ±100 1250 2000 VOUT VDROPOUT IOUT ILIMIT ISHORT ∆VLINE/∆VIN/VOUT ∆VOUT PSRR VEH VEL IEN θJA θJC Notes: 600 750 70 0.01 10 55 1.6 -0.1 82 12 0.25 0.1 ±0.2 20 mA mA %/V mV dB V V µA ºC/W ºC/W Enable Pin Current Thermal Resistance SOP-8L-EP (Note 3) Junction-to-Ambient Thermal Resistance SOP-8L-EP (Note 3) Junction-to-Case 3. Test condition for SOP-8L-EP: Device mounted on 2oz copper, minimum recommended pad layout on top & bottom layer with thermal vias, double sided FR-4 PCB. AP7217C Rev. 3 DS31424 4 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Typical Performance Characteristics Output Current vs. Dropout Voltage (Vout=1.25V) 2500 800 700 Input Voltage vs. Max Iout (Vout=1.25V) Dropout Voltage (mV 2000 600 Max Iout (mA 100mA 200mA 300mA 400mA 500mA 600mA 1500 500 400 300 200 100 1000 500 0 0 2.5V 3V 4V 5V 5.5V Output Current Input Voltage Q uiescent Current vs Input Voltage 55 55 Quiescent Current vs. Tem perature Quiescent Current (uA) 50 45 40 35 30 25 2.5V 3V 4V 5V 5.5V Quiescent Current (uA) 50 45 40 35 30 25 -40℃ 0℃ 25℃ 85℃ 100℃ 120℃ Input Voltage Tem perature AP7217C Rev. 3 DS31424 5 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Typical Performance Characteristics Load Transient Response (VOUT =1.25V) (Continued) Load Transient Response (VOUT =1.25V) AP7217C Rev. 3 DS31424 6 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Application Note Input Capacitor A 1µF ceramic capacitor is recommended to connect between IN and GND pins to decouple input power supply glitch and noise. The amount of the capacitance may be increased without limit. A lower ESR (Equivalent Series Resistance) capacitor allows the use of less capacitance, while higher ESR type requires more capacitance. This input capacitor must be located as close as possible to the device to assure input stability and less noise. For PCB layout, a wide copper trace is required for both IN and GND. Output Capacitor The output capacitor is required to stabilize and help the transient response of the LDO. The AP7217C is designed to have excellent transient response for most applications with a small amount of output capacitance. The AP7217C is stable with any small ceramic output capacitors of 1.0µF or higher value, and the temperature coefficients of X7R or X5R type. Additional capacitance helps to reduce undershoot and overshoot during transient. For PCB layout, the output capacitor must be placed as close as possible to OUT and GND pins, and keep the leads as short as possible. Thermal Considerations Thermal Shutdown Protection limits power dissipation in AP7217C. When the operation junction temperature exceeds 140°C, the Over Temperature Protection circuit starts the thermal shutdown function and turns the pass element off. The pass element turn on again after the junction temperature cools by 30°C. For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is: PD = (VIN − VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junctions to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) - TA ) / θJA Where TJ(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. Vin Iin IN OUT Iout Vout C AP7217C GND Co ESR Iq ENABLE/SHUTDOWN Operation The AP7217C (SOP-8L-EP) is turned on by setting the EN pin high, and is turned off by pulling it low. If this feature is not used, the EN pin should be tied to IN pin to keep the regulator output on at all time. To ensure proper operation, the signal source used to drive the EN pin must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. Current Limit Protection When output current at OUT pin is higher than current limit threshold, the current limit protection will be triggered and clamp the output current to approximately 750mA to prevent over-current and to protect the regulator from damage due to overheating. Short circuit protection When VOUT pin is shorted to GND or VOUT voltage is less than 200mV, short circuit protection will be triggered and clamp the output current to approximately 70mA. AP7217C Rev. 3 DS31424 7 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Marking Information (1) SOP-8L-EP ( Top View ) 8 5 Logo Part No. 7217C-13 : for 1.25V 7217C-13 YY WW X X E 1 4 G : Green YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X : Internal Code SOP-8L-EP Package Information (1) Package Type: SOP-8L-EP (All Dimensions in mm) Detail "A" Exposed pad 7°~9° 3.85/3.95 5.90/6.10 3.70/4.10 45° 0.35max. 7°~9° 1 1.30/1.50 1.75max. 0.15/0.25 3.3Ref. 1 Bottom View 0/0.13 0.254 1.27typ 4.85/4.95 1 0.3/0.5 Gauge Plane Seating Plane 0.62/0.82 Detail "A" 8x-0.60 Exposed pad 6x-1.27 8x-1.55 Land Pattem Recommendation (Unit:mm) 5.4 AP7217C Rev. 3 DS31424 8 of 9 www.diodes.com 2.4Ref. OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDING TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated website, harmless against all damages. Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel. Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application. Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks. LIFE SUPPORT Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein: A. Life support devices or systems are devices or systems which: 1. are intended to implant into the body, or 2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user. B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or to affect its safety or effectiveness. Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems. Copyright © 2009, Diodes Incorporated www.diodes.com AP7217C Rev. 3 DS31424 9 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated
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