AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR Description
The AP7362 is a 1.5A adjustable output voltage linear regulator with ultra-low dropout. The device includes pass element, error amplifier, band-gap, current limit and thermal shutdown circuitry. The integrated Enable block allows the part to be turned on and off via a logic signal. A logic high level on EN turns the device on and a logic low turns the part off. The low dropout voltage characteristics and fast transient response to step changes in load make it suitable for low voltage microprocessor applications. The typical quiescent current is approximately 0.5mA and changes little with load current. The built-in current-limit and thermal-shutdown functions prevent damage to the IC in fault conditions. This device is available in U-DFN2030-8 and SO-8EP packages.
Pin Assignments
(Top View)
ADJ/ NC OUT OUT OUT
8 7 6 5
1
2
3
4
GND EN IN IN
N EW PRODUCT
U-DFN2030-8
GND EN IN
1 2
(Top View)
8 7
ADJ/NC OUT OUT OUT
3 4
6 5
Features
• • • • • • • • • • • • • • • 1.5A ultra-low dropout linear regulator with EN Ultra-low dropout: 220mV at 1.5A Stable with 10µF input/output capacitor, any type Wide input voltage range: 2.7V to 5.5V Adjustable output voltage: 0.6V to 5.0V Fixed output options: 1V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V Low ground pin current 25nA quiescent current in shutdown mode VADJ accuracy of ±1.5% @ 25°C VADJ accuracy of ±3% over line, load and temperature Excellent Load/Line Transient Response Current limit and thermal shutdown protection Ambient temperature range: -40ºC to 85ºC U-DFN2030-8, SO-8EP: Available in “Green” Molding Compound (No Br, Sb) Lead Free Finish/ RoHS Compliant (Note 1)
IN
SO-8EP
Typical Application Circuit
VIN
IN OUT AP7362 10µF Enable EN GND 10µF
VOUT
Fixed Output
VIN
IN OUT AP7362 10µF Enable ADJ GND R2
VOUT
R1 10µF
Applications
• • • • ASIC power supplies in printers, graphics cards, DVD players, STBs, routers, etc FPGA and DSP core or I/O power supplies SMPS regulator Conversion from 3.3Vor 5V rail
EN
Adjustable Output
⎛ R⎞ V OUT = VREF ⎜ 1 + 1 ⎟ where R 2 ≤ 10 k Ω ⎜ R2 ⎟ ⎝ ⎠
Notes:
1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html.
AP7362
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR Pin Descriptions
Pin Name GND EN IN OUT ADJ Pin Number 1 2 3, 4 5, 6, 7 8 8 Ground. Enable input, active high. Voltage input pin. Voltage output pin. Output feedback pin for adjustable version only – a resistor divider from this pin to the OUT pin and ground sets the output voltage. No connection for fixed output version. The exposed pad (EP) is used to remove heat from the package and it is recommended that it is connected to a copper area. The die is electrically connected to the exposed pad. It is recommended to connect it externally to GND, but should not be the only ground connection. Description
N EW PRODUCT
NC
EP
EP
Functional Block Diagram
IN
Current Limit and Thermal Shutdown
OUT
IN
Current Limit and Thermal Shutdown
OUT
EN
Gate Driver
R
EN
Gate Driver
ADJ
0.605V
R
0.605V
GND
GND
Fixed Version
Adjustable Version
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR
Absolute Maximum Ratings (Note 2)
Symbol ESD HBM ESD MM VIN VOUT, VEN IOUT Parameter Human Body Model ESD Protection Machine Model ESD Protection Input Voltage OUT, EN Voltage Continuous Load Current Storage Temperature Range Maximum Junction Temperature Ratings 2000 200 -0.3 to 6.0 -0.3V to VIN + 0.3 Internal Limited -65 to 150 150 °C °C Unit V V V V
N EW PRODUCT
TST TJ
Notes:
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress Ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol VIN IOUT TA TJ
Notes:
Parameter Input voltage Output Current Operating Ambient Temperature Operating Junction Temperature (Note 3)
Min 2.7 0 -40 -40
Max 5.5 1.5 85 125
Unit V A °C °C
3. Operating junction temperature must be evaluated and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ-MAX), and package thermal resistance (θJA).
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR Electrical Characteristics
TA = 25 C, VIN = 3.3V, VOUT =1.8V, IOUT = 10mA, VEN = VIN, CIN = 10μF, COUT = 10μF, VEN = 2V, unless otherwise stated. Minimum and maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely o parametric norm at TA = 25 C, and are provided for reference purposes only.
o
Symbol VADJ VADJ
Parameter ADJ Pin Voltage ADJ Pin Voltage (A Grade) ADJ Pin Bias Current Dropout Voltage (Note 4)
Test Conditions VIN = VIN-Min to VIN-Max, IOUT= 10mA to 1.5A VIN = VIN-Min to VIN-Max, IOUT= 10mA to 1.5A VIN = VIN-Min to VIN-Max IOUT = 1.5A, VOUT = 2.5V VIN = VIN-Min to VIN-Max IOUT = 10mA to 1.5A IOUT = 10mA to 1.5A VEN < VIL VOUT ≥ VOUT-NOM -5% OUT grounded VIN = VIN-Min to VIN-Max VIN = VIN-Min to VIN-Max VEN = VIN VEN = 0V From VEN < VIL to VOUT = OFF, IOUT = 1.5A From VEN > VIH to VOUT = ON, IOUT = 1.5A VIN = 3.0V, IOUT = 1.5A, f = 120Hz VIN = 3.0V, IOUT = 1.5A, f = 1kHz F = 120Hz, COUT = 10μF ceramic BW = 100Hz – 100kHz, COUT = 10μF ceramic TJ rising TJ falling from TSHDN U-DFN2030-8 (Note 6) SO-8EP (Note 6) U-DFN2030-8 (Note 6) SO-8EP (Note 6) TA = 25 C Over temp Over temp Over temp
o
Min
Typ.
Max
Unit V V nA mV %/V %/A mA μA A A V nA μs μs dB μV/√Hz μV(rms) °C
o
TA = 25oC Over temp TA = 25oC Over temp TA = 25oC Over temp
o TA = 25 C Over temp o TA = 25 C Over temp o TA = 25 C Over temp o TA = 25 C Over temp o TA = 25 C Over temp
0.584 0.605 0.626 0.575 0.635 0.596 0.605 0.614 0.587 0.623 50 190 0.04 0.05 0.18 0.33 1 750 240 280 -
N EW PRODUCT
IADJ VDropout
ΔVOUT /ΔVIN Line Regulation (Note 5) ΔVOUT /ΔIOUT Load Regulation (Note 5) IGND ISHDN IOUT-PK ISC VIH VIL IIH IIL td(off) td(on) PSRR ρn(l/f) en TSHDN THYS θJA θJC
Notes:
Ground Pin Current in Normal Operation Mode Ground Pin Current Peak Output Current Short Circuit Current Enable Logic High Enable Logic Low Enable Pin High Current Enable Pin Low Current Turn-off delay Turn-on delay Ripple Rejection Output Noise Density Output Noise Voltage Thermal shutdown threshold Thermal shutdown hysteresis Thermal Resistance Junction-toAmbient Thermal Resistance Junction-toCase
1.2 1.3 0.025 0.125 15 3.6 3.7 2 1.4 0.65 1 0.1 25 25 65 61 1.0 90 170 10 174.0 52.8 28.2 10.0
C/W C/W
o
4. Dropout voltage is the minimum voltage difference between the input and the output at which the output voltage drops 2% below its nominal value. For any output voltage less than 2.5V, the minimum VIN operating voltage is the limiting factor. 5. The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the adjust voltage tolerance specification. 6. Device mounted on 2” x 2” FR-4 substrate PCB, 2oz copper with minimum recommended pad layout.
AP7362
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR
Typical Performance Characteristics
Unless otherwise specified: TJ=25°C, VIN=2.7V, VEN=VIN, CIN=10μF, COUT=10μF, IOUT=10mA, VOUT=1.8V
Noise Density 10k
Noise Density 10k
COUT=10μF CER
NOISE(nV/ROOT-Hz)
COUT=10μF TANT
NOISE(nV/ROOT-Hz)
1k
1k
N EW PRODUCT
100
100
10 100 1000 10k 100k FREQUENCY(Hz)
10 100 1000 FREQUENCY(Hz) 10k 100k
I GND vs Load Current 3 2.5 2 IGND (mA) 1.5 1 0.5 0 0 0.5 ILOAD (A) 1 1.5 1 -50 -25 IGND(nA) 100 1k
I GND(OFF) vs Temperature
VEN = 0.65V
10
0
25
50
75
100
125
TEMPERATURE(℃ )
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR Typical Performance Characteristics (cont.)
Unless otherwise specified: TJ=25°C, VIN=2.7V, VEN=VIN, CIN=10μF, COUT=10μF, IOUT=10mA, VOUT=1.8V
VADJ vs Temperature 0.615
Dropout Voltage vs Load Current 0.3 DROPOUT VOLTAGE(V)
0.610
125°C
0.2
25°C
N EW PRODUCT
VADJ (V)
0.605
0.600
-40°C
0.1
0.595
0.590 -50 -25 0 25 50 75 100 125 TEMPERATURE(℃ )
0 0 0.5 1 LOAD CURRENT(A) 1.5
VEN vs Temperature 1.3
2
Turn-on Characeristics
IL=0A
1.2
V OUT(V)
VEN (V)
1.1
1
1
125°C
0.9
25°C -40°C
0.8 -50
0
-25
0
25
50
75
100
125
0
1 VIN (V)
2
3
TEMPERATURE(℃ )
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR
Typical Performance Characteristics (cont.)
Unless otherwise specified: TJ=25°C, VIN=2.7V, VEN=VIN, CIN=10μF, COUT=10μF, IOUT=10mA, VOUT=1.8V
Turn-on Time
Turn-on Time
N EW PRODUCT
VOUT=1.2V (500mV/div) IL=0A, COUT=10μF CER
VOUT=1.2V (500mV/div) IL=1.5A, COUT=10μF CER
VIN=3.0V (2V/div)
VIN=3.0V (2V/div)
Time (10μs/div) Load Transient Response VIN=VEN=3.3V COUT=10μF CER
REJECTION RATIO(dB)
Time (10μs/div)
P SRR 90 80 70 60 50 40
VOUT=1.8V (50mV/div)
VIN=3.3V CIN=1μF CER
30 VOUT=1.8V
=1A 20 IOUT
ILOAD=100mA to 1.5A (1A/div)
10 COUT=1μF CER 0 0.1 1 10 FREQUENCY(kHz) 100 1000
Time (40μs/div)
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR
Application Information
Input Capacitor
A minimum 2.2μF ceramic capacitor is recommended between IN and GND pins to decouple input power supply glitch and noise. The amount of the capacitance may be increased without limit. Larger input capacitor like 10μF will provide better load transient response. This input capacitor must be located as close as possible to the device to assure input stability and reduce noise. For PCB layout, a wide copper trace is required for both IN and GND pins. A lower ESR capacitor type allows the use of less capacitance, while higher ESR type requires more capacitance.
⎛V ⎞ R1 = R 2 ⎜ OUT − 1⎟ ⎜V ⎟ ⎝ REF ⎠
To maintain the stability of the internal reference voltage, R2 need to be kept smaller than 10kΩ.
No Load Stability
Other than external resistor divider, no minimum load is required to keep the device stable. The device will remain stable and regulated in no load condition.
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Output Capacitor
The output capacitor is required to stabilize and help the transient response of the LDO. The AP7362 is stable with any type of capacitor, with no limitations on minimum or maximum ESR. The device is designed to have excellent transient response for most applications with a small amount of output capacitance. The device is also stable with multiple capacitors in parallel, which can be of any type of value. Additional capacitance helps to reduce undershoot and overshoot during transient loads. This capacitor should be placed as close as possible to OUT and GND pins for optimum performance.
Stability And Phase Margin
Any regulator which operates using a feedback loop must be compensated in such a way as to ensure adequate phase margin, which is defined as the difference between the phase shift and -180 degrees at the frequency where the loop gain crosses unity (0 dB). For most LDO regulators, the ESR of the output capacitor is required to create a zero to add enough phase lead to ensure stable operation. The AP7362 has an internal compensation circuit which maintains phase margin regardless of the ESR of the output capacitor, any type of capacitor can be used. Below two charts show the gain/phase plot of the AP7362 with an output of 1.2V, 10 μF ceramic output capacitor, delivering 1.5A load current and no load. It can be seen the phase margin is about 90° (which is very stable).
120 100 80 60 LOOP GAIN(dB) 140
Adjustable Operation
The AP7362 provides output voltage from 0.6V to 5.0V through external resistor divider as shown below.
VIN
IN OUT AP7362 10µF Enable ADJ GND R2
VOUT
PHASE GAIN
120 100 60 40 20 0 -20 -40 -60 100k -80 1M PHASE MARGIN( °) 80
R1 10µF
40 20 0 -20 -40 -60 -80 -100
EN
VIN=2.7V VOUT=1.2V IL=1.5A COUT=10μF CER
Adjustable Output
The output voltage is calculated by:
⎛ R⎞ VOUT = VREF ⎜ 1 + 1 ⎟ ⎜ R2 ⎟ ⎠ ⎝
-120 100
1k
10k
FREQUENCY(Hz)
Gain-Bandwidth Plot for 1.5A Load
Where VREF=0.6V (the internal reference voltage) Rearranging the equation will give the following that is used for adjusting the output to a particular voltage:
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR Application Information (cont.)
120 100 80 60 40 LOOP GAIN(dB) 20 0 -20 -40 -60 -80 -100 -120 100 1k 10k 100k FREQUENCY(Hz) 140 120
the heat dissipation of the regulator, protecting it from damage due to overheating.
PHASE GAIN
100 60 40 20 0 -20 -40 -60 -80 1M PHASE MARGIN( °) 80
Low Quiescent Current
The AP7362, consumes only around 0.5mA for all input voltage range and load currents, this provides great power saving in portable and low power applications.
N EW PRODUCT
VIN=2.7V VOUT=1.2V IL=0A COUT=10μF CER
Output Noise
This is the integrated value of the output noise over a specified frequency range. Input voltage and output load current are kept constant during the measurement. Results are expressed in μVrms or μV √Hz. The AP7362 is a low noise regulator and needs no external noise reduction capacitor. Output voltage noise is typically 100μVrms overall noise level between 100 Hz and 100 kHz Noise is specified in two ways: Output noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. Output noise voltage is the RMS sum of spot noise over a specified bandwidth. Spot noise is measured in units μV/√Hz or nV/√Hz and total output noise is measured in μV(rms). The primary source of noise in low-dropout regulators is the internal reference.
Gain-Bandwidth Plot for no Load
ON/OFF Input Operation
The AP7362 is turned on by setting the EN pin high, and is turned off by pulling it low. If this feature is not used, the EN pin should be tied to IN pin to keep the regulator output on at all time. To ensure proper operation, the signal source used to drive the EN pin must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH.
Short Circuit Protection
When output current at OUT pin is higher than current limit threshold, the current limit protection will be triggered and clamp the output current to prevent over-current and to protect the regulator from damage due to overheating.
Power Dissipation
The device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad is critical to avoid thermal shutdown and ensure reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated by: PD = (VIN - VOUT) X IOUT The maximum power dissipation, handled by the device, depends on the junction to ambient thermal resistance, and maximum ambient temperature, which can be calculated by the equation in the following:
Thermal Shutdown Protection
Thermal protection disables the output when the junction temperature rises to approximately +170°C, allowing the device to cool down. When the junction temperature reduces to approximately +160°C the output circuitry is enabled again. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits
PD _ max =
( +150°C - TA ) R θJA
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR Ordering Information
AP 7362 - XX XX - X
Output Blank 10 : 12 : 15 : 18 : 25 : 33 : : ADJ 1 .0V 1 .2 V 1 .5 V 1 .8 V 2 .5V 3 .3V
Package HA : U - DFN 2 0 3 0 -8 SP : SO-8EP
Packing 7 /13 : Tap e & Reel
N EW PRODUCT
Device AP7362-XXHA-7 AP7362-XXSP-13
Package Code HA SP
Packaging (Note 7) U-DFN2030-8 SO-8EP
7”/13” Tape and Reel Quantity Part Number Suffix 3000/Tape & Reel -7 2500/Tape & Reel -13
Notes: 7. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.
Marking Information
(1) U-DFN2030-8
( Top View ) XX Y WX
XX : Identification Code Y : Year : 0~9 W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week X : A~Z : Internal code
Package U-DFN2030-8 U-DFN2030-8 U-DFN2030-8 U-DFN2030-8 U-DFN2030-8 U-DFN2030-8 U-DFN2030-8 Identification Code RA RB RC RD RE RF RG
Device AP7362ADJ AP7362-10 AP7362-12 AP7362-15 AP7362-18 AP7362-25 AP7362-33
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR
Marking Information
(2) SO-8EP
( Top View )
8 5
Logo Part Number
N EW PRODUCT
AP7362 for ADJ AP7362-10 for 1.0V AP7362-12 for 1.2V AP7362-15 for 1.5V AP7362-18 for 1.8V AP7362-25 for 2.5V AP7362-33 for 3.3V
AP7362-VV YY WW X E
1 4
YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X : Internal code SO-8-EP
Package Outline Dimensions (All Dimensions in mm)
(1) Package Type: U-DFN2030-8
TOP MARK
0.10 C 8X0.08 C 0.57/0.63 0/0.05 0.25 A
0.15Typ.
Seating Plane
Side View
6x-0.50 C
C L
8x-0.30
2X-
1.95/2.05
(Pin #1 ID)
B
A
C L
2.95/3.05
1.50/1.70
C L 1.40/1.60
2.60
Pin1
1.60
Land Pattern Recommendation (Unit: mm)
2X0.25 B 8X0.30/0.60 0.50Typ. 0.20/0.30 0.10 CAB
Top View Bottom View
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1.70
2.60
C L
8x-0.60
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR Package Outline Dimensions (cont.) (All Dimensions in mm)
(2) Package Type: SO-8EP
Detail "A" Exposed pad
7°~9°
3.85/3.95
5.90/6.10
3.70/4.10
45° 0.35max.
N EW PRODUCT
7°~9° 1 1.30/1.50 1.75max.
0.15/0.25 3.3Ref.
1
Bottom View
0/0.13
0.254
1.27typ 4.85/4.95 1
0.3/0.5
Gauge Plane Seating Plane
0.62/0.82
Detail "A"
8x-0.60
Exposed pad
6x-1.27 8x-1.55
Land Pattem Recommendation (Unit:mm)
Notes:
8. Co planarity applies to the exposed heat sink slug as well as the terminals.
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2.4Ref.
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AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR
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N EW PRODUCT
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