PRELIMINARY DATA SHEET
1G bits DDR Mobile RAM
WTR (Wide Temperature Range) EDD10161BBH-TS (64M words × 16 bits)
Specifications
• Density: 1G bits • Organization: 16M words × 16 bits × 4 banks • Package: 60-ball FBGA Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.7V to 1.95V • Data rate: 400Mbps/333Mbps (max.) • 2KB page size Row address: A0 to A13 Column address: A0 to A9 • Four internal banks for concurrent operation • Interface: LVCMOS • Burst lengths (BL): 2, 4, 8 • Burst type (BT): Sequential (2, 4, 8) Interleave (2, 4, 8) • /CAS Latency (CL): 3 • Precharge: auto precharge option for each burst access • Driver strength: normal, 1/2, 1/4 • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms Average refresh period: 7.8µs • Operating ambient temperature range TA = −25°C to +85°C
Features
• DLL is not implemented • Low power consumption • Double-data-rate architecture; two data transfers per one clock cycle • The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver. • Data inputs, outputs, and DM are synchronized with DQS • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Burst termination by burst stop command and Precharge command • Wide temperature range TA = −25°C to +85°C • Low Power Function below is not supported Partal Array Self-Refresh (PASR) Auto Temperature Compensated Self-Refresh Deep power-down mode
Document No. E1444E30 (Ver. 3.0) Date Published October 2009 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2008-2009
EDD10161BBH-TS
Ordering Information
Part number EDD10161BBH-5BTS-F EDD10161BBH-6ETS-F Die revision B Organization (words × bits) 64M × 16 Internal banks 4 Data rate Mbps (max.) 400 333 /CAS latency 3 3 Package 60-ball FBGA
Part Number
E D D 10 16 1 B BH - 5B TS - F
Elpida Memory
Environment Code F: Lead Free (RoHS Compliant) and Halogen Free
Spec Detail TS: WTR (-25°C to +85°C)
Type D: Monolithic Device
Product Family D: DDR Mobile RAM
Density / Bank 10: 1Gb / 4-bank Organization 16: x16 Power Supply, Interface 1: 1.8V, LVCMOS, w/o Low Power Function
Speed 5B: DDR400 (3-3-3) 6E: DDR333 (3-3-3) Package BH: FBGA Die Rev.
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Pin Configurations
/xxx indicate active low signal.
60-ball FBGA 1 A
VSS DQ15 VSSQ VDDQ DQ0 VDD
2
3
7
8
9
B
VDDQ DQ13 DQ14 DQ1 DQ2 VSSQ
C
VSSQ DQ11 DQ12 DQ3 DQ4 VDDQ
D
VDDQ DQ9 DQ10 DQ5 DQ6 VSSQ
E
VSSQ UDQS DQ8 DQ7 LDQS VDDQ
F
VSS UDM NC A13 LDM VDD
G
CKE CK /CK /E W /CAS /RAS
H
A9 A11 A12 /CS BA0 BA1
J
A6 A7 A8 A10 A0 A1
K
VSS A4 A5 A2 A3 VDD
(Top View)
Pin name A0 to A13 BA0, BA1 DQ0 to DQ15 UDQS, LDQS /CS /RAS /CAS /WE DM0 to DM3
Function Address inputs Bank select address Data-input/output Input and output data strobe Chip select Row address strobe Column address strobe Write enable Input mask
Pin name CK /CK CKE VDD VSS VDDQ VSSQ NC
Function Clock input Differential clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................12 Pin Function.................................................................................................................................................13 Command Operation ...................................................................................................................................15 Simplified State Diagram .............................................................................................................................21 Operation of the DDR Mobile RAM .............................................................................................................22 Timing Waveforms.......................................................................................................................................46 Package Drawing ........................................................................................................................................55 Recommended Soldering Conditions..........................................................................................................56
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Electrical Specifications
• All voltages are referenced to VSS (GND). • After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD IOS PD TA Tstg Rating –0.5 to +2.3 –0.5 to +2.3 50 1.0 –25 to +85 –55 to +125 Unit V V mA W °C °C Note
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = −25°C to +85°C)
Parameter Supply voltage Pins Symbol VDD, VDDQ VSS, VSSQ All other input VIH pins CK, /CK VIL VIN (DC) VIX VID (DC) VID (AC) DQ, DM, DQS VIHD (DC) VILD (DC) VIHD (AC) VILD (AC) min. 1.7 0 0.8 × VDDQ –0.3 –0.3 0.4 × VDDQ 0.4 × VDDQ 0.6 × VDDQ 0.7× VDDQ –0.3 0.8× VDDQ –0.3 typ. 1.8 0 — — — max. 1.95 0 VDDQ + 0.3 0.2 × VDDQ VDDQ + 0.3 Unit V V V V V V V V V V V V 6 5 5 Notes 1
Input high voltage Input low voltage DC input voltage level AC Input differential cross point voltage DC input differential voltage AC input differential voltage DC input high voltage DC input low voltage AC input high voltage AC input low voltage
0.5 × VDDQ 0.6 × VDDQ — — — — — — VDDQ + 0.6 VDDQ + 0.6 VDDQ + 0.3 0.3 × VDDQ VDDQ + 0.3 0.2 × VDDQ
Notes: 1. 2. 3. 4. 5.
VDDQ must be equal to VDD. VIH (max.) = 2.3V (pulse width ≤ 5ns). VIL (min.) = –0.5V (pulse width ≤ 5ns). All voltage referred to VSS and VSSQ must be same potential. VID (DC) and VID (AC) are the magnitude of the difference between the input level on CK and the input level on /CK. 6. The value of VIX is expected to be 0.5 × VDDQ and must track variations in the DC level of the same.
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
DC Characteristics 1 (TA = –25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter Symbol Grade max. Unit Test condition One bank active-precharge, CKE = H, /CS = H between valid commands, tCK = tCK (min.), tRC = tRC (min.), Address bus inputs are SWITCHING; Data bus inputs are STABLE All banks idle, CKE = L, /CS = H, tCK = tCK (min.), Address and control inputs are SWITCHING; Data bus inputs are STABLE All banks idle, CKE = L, /CS = H, CK = L, /CK = H, Address and control inputs are SWITCHING; Data bus inputs are STABLE All banks idle, CKE = H, /CS = H, tCK = tCK (min.), Address and control inputs are SWITCHING; Data bus inputs are STABLE All banks idle, CKE = H, /CS = H, CK = L, /CK = H, Address and control inputs are SWITCHING; Data bus inputs are STABLE One bank active, CKE = L, /CS = H, tCK = tCK (min.), Address and control inputs are SWITCHING; Data bus inputs are STABLE One bank active, CKE = L, /CS = H, CK = L, /CK = H; Address and control inputs are SWITCHING; Data bus inputs are STABLE One bank active, CKE = H, /CS = H, tCK = tCK (min.), Address and control inputs are SWITCHING; Data bus inputs are STABLE One bank active, CKE = H, /CS = H, CK = L, /CK = H, Address and control inputs are SWITCHING; Data bus inputs are STABLE One bank active, Continuous burst reads or writes; tCK = tCK (min.), CL = 3, BL = 4, IOUT = 0mA, Address inputs are SWITCHING, 50% data change each burst transfer CKE = H, tCK = tCK (min.), tRFC = tRFC (min.), Address and control inputs are SWITCHING; Data bus inputs are STABLE CKE = L Notes
Operating current (ACT-PRE)
IDD0
-5B -6E
85 60
mA
Standby current in power-down IDD2P
3.2
mA
Standby current in power-down IDD2PS with clock stop
3.0
mA
Standby current in non power-down
IDD2N
6.0
mA
Standby current in non powerIDD2NS down with clock stop
4.0
mA
Active standby current in power-down
IDD3P
5.0
mA
Active standby current in power-down with clock stop
IDD3PS
4.0
mA
Active standby current in non power-down
IDD3N
10
mA
Active standby current in non power-down with clock stop
IDD3NS
7.0
mA
Burst operating current
IDD4
-5B -6E
135 120
mA
Auto-refresh current Self-refresh current
IDD5 IDD6
120 4.0
mA mA
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by Test Conditions. 3. Definitions for IDD: L is defined as VIN ≤ 0.1 × VDDQ; H is defined as VIN ≥ 0.9 × VDDQ; STABLE is defined as inputs stable at an H or L level; SWITCHING is defined as: Address and command: inputs changing between H and L once per two clock cycles; Data bus inputs: DQ changing between H and L once per clock cycle; DM and DQS are STABLE. DC Characteristics 2 (TA = −25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. –2.0 –1.5 0.9 × VDDQ — max. 2.0 1.5 — 0.1 × VDDQ Unit µA µA V V Test condition 0 ≤ VIN ≤ VDDQ 0 ≤ VOUT ≤ VDDQ, DQ = disable IOH = − 0.1mA IOL = 0.1 mA Notes
Pin Capacitance (TA = +25°C, VDD and VDDQ = 1.7V to 1.95V)
Parameter Input capacitance Symbol CI1 CI2 Delta input capacitance Cdi1 Cdi2 Data input/output capacitance Delta input/output capacitance CI/O Cdio Pins CK, /CK All other input-only pins CK, /CK All other input-only pins DQ, DM, DQS DQ, DM, DQS min. 1.5 1.5 — — 2.0 — typ. — — — — — — max. 3.5 3.0 0.25 1.0 4.5 1.0 Unit pF pF pF pF pF pF Notes 1 1 1 1 1, 2 1
Notes: 1. These parameters are measured on conditions: TA = +25°C. 2. DOUT circuits are disabled.
f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V,
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
AC Characteristics (TA = −25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
-5B Parameter Clock cycle time CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS-in cycle time DQS output access time from CK, /CK DQ-out high-impedance time from CK, /CK DQ-out low-impedance time from CK, /CK DQS to DQ skew DQ/DQS output hold time from DQS Data hold skew factor DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width Read preamble Read postamble Write preamble setup time Write preamble Write postamble Write command to first DQS latching transition DQS falling edge to CK setup time DQS falling edge hold time from CK DQS input high pulse width DQS input low pulse width Address and control input setup time Address and control input hold time Address and control input pulse width Mode register set command cycle time Active to Precharge command period Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read/Write delay Precharge to active command period Column address to column address delay Active to active command period Write recovery time Symbol tCK tCH tCL tHP tAC tDSC tDQSCK tHZ tLZ tDQSQ tQH tQHS tDS tDH tDIPW tRPRE tRPST tWPRES tWPRE tWPST tDQSS tDSS tDSH tDQSH tDQSL tIS tIH tIPW tMRD tRAS tRC tRFC tRCD tRP tCCD tRRD tWR min. 5.0 0.45 0.45 min. ( tCH, tCL) 2.0 0.9 2.0 — 1.0 — tHP − tQHS — 0.48 0.48 1.6 0.9 0.4 0 0.25 0.4 0.75 0.2 0.2 0.40 0.40 0.9 0.9 2.3 2 40 55 78 15 15 1 10 15 max. — 0.55 0.55 — 5.0 1.1 5.0 5.0 — 0.4 — 0.5 — — — 1.1 0.6 — — 0.6 1.25 — — — — — — — — 120000 — — — — — — — -6E min. 6.0 0.45 0.45 min. ( tCH, tCL) 2.0 0.9 2.0 — 1.0 — tHP − tQHS — 0.6 0.6 1.6 0.9 0.4 0 0.25 0.4 0.75 0.2 0.2 0.40 0.40 1.1 1.1 2.7 2 42 60 78 18 18 1 12 15 max. — 0.55 0.55 — 5.0 1.1 5.0 5.0 — 0.5 — 0.65 — — — 1.1 0.6 — — 0.6 1.25 — — — — — — — — 120000 — — — — — — — Unit ns tCK tCK tCK ns tCK ns ns ns ns ns ns ns ns ns tCK tCK ns tCK tCK tCK tCK tCK tCK tCK ns ns ns tCK ns ns ns ns ns tCK ns ns 3 3 3 7 3 3 2, 8 5, 8 6, 8 3 4 2, 8 Notes
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
-5B Parameter Autoprecharge write recovery and precharge time Self-refresh exit period Internal Write to Read command delay Average periodic refresh interval Symbol tDAL tSREX tWTR tREF min. — 120 2 — max. — — — 7.8 -6E min. — 120 1 — max. — — — 7.8 ns tCK µs Unit Notes 9
Notes: 1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver strength is assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VDDQ/2. 3. The timing reference level is VDDQ/2. 4. Output valid window is defined to be the period between two successive transition of data out signals. The signal transition is defined to occur when the signal level crossing VDDQ/2. 5. tHZ is defined as DOUT transition delay from low-Z to high-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from high-Z to low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 8. tAC, tDQSCK, tHZ and tLZ are specified with 15pF bus loading condition. 9. Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and minimum 1 clock for tRP. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher integer.
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Test Conditions
Parameter Input high voltage Input low voltage Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate Output load Symbol VIH (AC) VIL (AC) VID (AC) VIX (AC) SLEW CL Value 0.8 × VDDQ 0.2 × VDDQ 1.4 VDDQ/2 with VDD=VDDQ 1 15 Unit V V V V V/ns pF 1 Note 1 1 1
Note: 1. VDD = VDDQ
tCK tCH tCL VID
/CK CK
VIH
VIX
VIL
tLZ tAC
T slew rate =
(VIH − VIL) T
DQOUT (DQOUT)
Q1
Q2
VDDQ/2
Test Condition (Wave form and Timing Reference)
DQ
CL
Output Load
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Timing Parameter Measured in Clock Cycle
Number of clock cycle tCK Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 3) Burst stop command to DQ high-Z (CL = 3) Read command to write command delay (to output all data) (CL = 3) Pre-charge command to high-Z (CL = 3) Write command to data in latency Write recovery DM to data in latency Mode register set command cycle time Self-refresh exit to non-column command Auto-refresh period Power-down entry Power-down exit to command input CKE minimum pulse width Symbol tWPD tRPD tWRD tBSTW tBSTZ tRWD tHZP tWCD tWR tDMD tMRD tSREX tRFC tPDEN tPDEX tCKE 5.0ns min. 4 + BL/2 BL/2 3 + BL/2 3 3 3 + BL/2 3 1 3 0 2 24 16 2 1 2 max. 6.0ns min. 4 + BL/2 BL/2 2 + BL/2 3 3 3 + BL/2 3 1 3 0 2 20 13 2 1 2 max. 7.5ns min. 3 + BL/2 BL/2 2 + BL/2 3 3 3 + BL/2 3 1 2 0 2 16 11 1 1 2 max. Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Block Diagram
CK /CK CKE
Clock generator
Bank 3 Bank 2 Bank 1
Address, BA0, BA1
Mode register
Row address buffer and refresh counter
Row decoder
Memory cell array Bank 0
Sense amp.
Command decoder
/CS /RAS /CAS /WE
Column address buffer and burst counter
Column decoder
Control logic
Data control circuit
Latch circuit
DQS
Input & Output buffer
DM
DQ
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Pin Function
CK, /CK (input pins) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the /CK falling edge. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VDDQ/2 level. DQSs for write operation are referred to the cross point of the CK and the /CK. The other input signals are referred at CK rising edge. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A13 (input pins) Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the /CK falling edge in a bank active command cycle. Column address is loaded at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle (See “Address Pins Table”). This column address becomes the starting address of a burst operation. [Address Pins Table]
Address (A0 to A13) Part number EDD10161BBH Page size 2KB Organization × 16 bits Row address AX0 to AX13 Column address AY0 to AY9
A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write command, auto precharge function is enabled. BA0 and BA1 (input pins) BA0 and BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL.
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
CKE (input pin) CKE controls power-down mode, self-refresh function with other command inputs. The CKE level must be kept for 2 clocks at least, that is, if CKE changes at the cross point of the CK rising edge and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper hold time tIH. DQ0 to DQ15 (input/output pins) Data are input to and output from these pins. UDQS and LDQS (input and output pin): DQS provides the read data strobes (as output) and the write data strobes (as input). Each DQS pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table). UDM and LDM (input pin) DM is the reference signals of the data input mask function. DM is sampled at the cross point of DQS and VDDQ/2. When DM = high, the data input at the same timing are masked while the internal burst counter will be counting up. Each DM pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table). [DQS and DM Correspondence Table]
Part number EDD10161BBH Organization × 16 bits DQS LDQS UDQS Data mask LDM UDM DQs DQ0 to DQ7 DQ8 to DQ15
VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VDD must be equal to VDDQ.
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Command Operation
Command Truth Table The DDR Mobile RAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE Command Ignore command No operation Burst stop command Column address and read command Read with auto precharge Column address and write command Write with auto precharge Row address strobe and bank active Precharge select bank Precharge all bank Refresh Symbol DESL NOP BST READ READA WRIT WRITA ACT PRE PALL REF SELF Mode register set MRS EMRS n–1 H H H H H H H H H H H H H H n H H H H H H H H H H H L H H /CS H L L L L L L L L L L L L L /RAS /CAS /WE × H H H H H H L L L L L L L × H H L L L L H H H L L L L × H L H H L L H L L H H L L BA1 × × × V V V V V V × × × L H BA0 × × × V V V V V V × × × L L AP × × × L H L H V L H × × L L Address × × × V V V V V × × × × V V
Remark: H: VIH. L: VIL. ×: Don’t care V: Valid address input Note: The CKE level must be kept for 1 CK cycle at least. Ignore command [DESL] When /CS is high at the cross point of the CK rising edge and the VDDQ/2 level, all input signals are neglected and internal state is held. No operation [NOP] As long as this command is input at the cross point of the CK rising edge and the VDDQ/2 level, address and data input are neglected and internal state is held. Burst stop command [BST] This command stops a current burst operation. Column address strobe and read command [READ] This command starts a read operation. The start address of the burst read is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation, all output buffers become high-Z. Read with auto precharge [READA] This command starts a read operation. After completion of the read operation, precharge is automatically executed. Column address strobe and write command [WRIT] This command starts a write operation. The start address of the burst write is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. Write with auto precharge [WRITA] This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Row address strobe and bank activate [ACT] This command activates the bank that is selected by BA0 and BA1 (See Bank Select Signal Table) and determines the row address (Address Pins Table in “Pin Function”). Precharge selected bank [PRE] This command starts precharge operation for the bank selected by BA0 and BA1. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL. Precharge all banks [PALL] This command starts a precharge operation for all banks. Refresh [REF/SELF] This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another is self-refresh. For details, refer to the CKE truth table section. Mode register set/Extended mode register set [MRS/EMRS] The DDR Mobile RAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins in the mode register set cycle. For details, refer to "Mode register and extended mode register set".
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR Mobile RAM.
Current state Precharging*
1
/CS H L L L L L L L
/RAS /CAS /WE × H H H H L L L × H H H H L L L L × H H H L × H H H H L L L × H H H H L L L × H H L L H H L × H H L L H H L L × H H L × × H H L L H H L × H H L L H H L × H L H L H L × × H L H L H L H L × H L × × × H L H L H L × × H L H L H L ×
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE × × × × × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 ×
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* NOP ILLEGAL
11 11 11 11
Idle*
2
H L L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS DESL NOP BST
NOP NOP NOP ILLEGAL* ILLEGAL* Activating NOP Refresh/ 12 Self-refresh* Mode register set* NOP NOP ILLEGAL ILLEGAL ILLEGAL
12 11 11
Refresh 3 (auto-refresh)*
H L H L L
Activating*
4
H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL
11 11 11 11 11
Active*
5
H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP NOP Starting read operation Starting write operation ILLEGAL*
11
Pre-charge ILLEGAL
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
Current state Read*
6
/CS H L L L L L L L
/RAS /CAS /WE × H H H H L L L × H H H H L L L × H H H × H H L L H H L × H H L L H H L × H H L × H L H L H L × × H L H L H L × × H L H
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP Burst stop Interrupting burst read operation to start new read ILLEGAL* ILLEGAL*
13 11
Interrupting burst read operation to start pre-charge ILLEGAL
Read with auto preH 7 charge* L L L L L L L Write*
8
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL
14 14 11, 14 11, 14
H L L L
DESL NOP BST READ/READA
NOP NOP Burst Stop Interrupting burst write operation to start read operation. Interrupting burst write operation to start new write operation. ILLEGAL*
11
L L L L Write recovering*
9
H L L L × H H H H L L L
L H H L × H H L L H H L
L H L × × H L H L H L ×
BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 ×
WRIT/WRITA ACT PRE, PALL
Interrupting write operation to start pre-charge. ILLEGAL NOP NOP ILLEGAL Starting read operation. Starting new write operation. ILLEGAL* ILLEGAL* ILLEGAL
11 11
H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL
Preliminary Data Sheet E1444E30 (Ver. 30)
18
EDD10161BBH-TS
Current state
/CS
/RAS × H H H H L L L
/CAS × H H L L H H L
/WE × H L H L H L ×
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 ×
Command DESL NOP BST READ/READA WRIT/WRIT A ACT PRE, PALL
Operation NOP NOP ILLEGAL ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL
14 14 11, 14 11, 14
Write with auto preH 1 charge* L L L L L L L
Remark: Notes: 1. 2. 3. 4. 5. 6.
H: VIH. L: VIL. ×: Don’t care. The DDR Mobile RAM is in "Precharging" state for tRP after precharge command is issued. The DDR Mobile RAM reaches "IDLE" state tRP after precharge command is issued. The DDR Mobile RAM is in "Refresh" state for tRFC after auto-refresh command is issued. The DDR Mobile RAM is in "Activating" state for tRCD after ACT command is issued. The DDR Mobile RAM is in "Active" state after "Activating" is completed. The DDR Mobile RAM is in "READ" state until burst data have been output and DQ output circuits are turned off. 7. The DDR Mobile RAMis in "READ with auto precharge" from READA command until burst data has been output and DQ output circuits are turned off. 8. The DDR Mobile RAM is in "WRITE" state from WRIT command to the last burst data are input. 9. The DDR Mobile RAM is in "Write recovering" for tWR after the last data are input. 10. The DDR Mobile RAM is in "Write with auto precharge" until tWR after the last data has been input. 11. This command may be issued for other banks, depending on the state of the banks. 12. All banks must be in "IDLE". 13. Before executing a write command to stop the preceding burst read operation, BST command must be issued. 14. The DDR Mobile RAM supports the concurrent auto precharge feature, a read with auto precharge or a write with auto precharge, can be followed by any command to the other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply (e.g. contention between READ data and WRITE data must be avoided.) The minimum delay from a read or write command with auto precharge, to a command to a different bank, is summarized below.
To command (different bank, noninterrupting command) Read or Read w/AP Write or Write w/AP Precharge or Activate Minimum delay (Concurrent AP supported) BL/2 CL (rounded up)+ (BL/2) 1 1 + (BL/2) + tWTR BL/2 1
From command Read w/AP
Units tCK tCK tCK tCK tCK tCK
Write w/AP
Read or Read w/AP Write or Write w/AP Precharge or Activate
Preliminary Data Sheet E1444E30 (Ver. 30)
19
EDD10161BBH-TS
CKE Truth Table
CKE Current state Idle Idle Active/Idle Command Auto-refresh command (REF) Self-refresh entry (SELF) Power-down entry (PDEN) n–1 H H H H L L L L n H L L L H H H H /CS L L L H L H L H /RAS L L H × H × H × /CAS L L H × H × H × /WE H H H × H × H × Address × × × × × × × × Notes 2 2
Self-refresh
Self-refresh exit (SELFX)
Power-down
Power-down exit (PDEX)
Notes: 1. H: VIH . L: VIL × : Don’t care. 2. All the banks must be in IDLE before executing this command. 3. The CKE level must be kept for 1 clock cycle at least. Auto-refresh command [REF] This command executes auto-refresh. The bank and the ROW addresses to be refreshed are internally determined by the internal refresh controller. The output buffer becomes high-Z after auto-refresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last autorefresh command. The average refresh cycle is 7.8µs. To allow for improved efficiency in scheduling, some flexibility in the absolute refresh interval (64ms) is provided. A maximum of eight auto-refresh commands can be posted to the DDR Mobile RAM or the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 8 × tREF. Self-refresh entry [SELF] This command starts self-refresh. The self-refresh operation continues as long as CKE is held low. During the selfrefresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is terminated by a self-refresh exit command. Power-down mode entry [PDEN] tPDEN after the cycle when [PDEN] is issued, the DDR Mobile RAM enters into power-down mode. In power-down mode, power consumption is suppressed by deactivating the input initial circuit. Power-down mode continues while CKE is held low. No internal refresh operation occurs during the power-down mode. Self-refresh exit [SELFX] This command is executed to exit from self-refresh mode. tSREX after [SELFX], the device will be into idle state. Power-down exit [PDEX] The DDR Mobile RAM can exit from power-down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
Preliminary Data Sheet E1444E30 (Ver. 30)
20
EDD10161BBH-TS
Simplified State Diagram
EXTENDED MODE REGISTER SET
SELF REFRESH
SR ENTRY
RS
EM
SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
AUTO REFRESH
CKE CKE_
IDLE POWER DOWN
ACTIVE POWER DOWN
CKE_ CKE BST WRITE
ACTIVE
ROW ACTIVE
BST READ
WRITE WRITE WITH AP READ WITH AP READ
WRITE
READ READ WITH AP
READ
WRITE WITH AP
READ WITH AP
PRECHARGE
WRITEA
PRECHARGE PRECHARGE
READA
POWER APPLIED
POWER ON
PRECHARGE PRECHARGE
Automatic sequence Manual input
Preliminary Data Sheet E1444E30 (Ver. 30)
21
EDD10161BBH-TS
Operation of the DDR Mobile RAM
Initialization The DDR Mobile RAM is initialized in the power-on sequence according to the following. 1. Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up simultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are from the same power source. Also assert and hold Clock Enable (CKE) to a LV-CMOS logic high level. 2. Once the system has established consistent device power and CKE is driven high, it is safe to apply stable clock. 3. There must be at least 200µs of valid clocks before any command may be given to the DRAM. During this time NOP or deselect (DESL) commands must be issued on the command bus. 4. Issue a precharge all command. 5. Provide NOPs or DESL commands for at least tRP time. 6. Issue an auto-refresh command followed by NOPs or DESL command for at least tRFC time. Issue the second auto-refresh command followed by NOPs or DESL command for at least tRFC time. Note as part of the initialization sequence there must be two auto-refresh commands issued. The typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11. 7. Using the MRS command, load the base mode register. Set the desired operating modes. 8. Provide NOPs or DESL commands for at least tMRD time. 9. Using the MRS command, program the extended mode register for the desired operating modes. 10. Provide NOP or DESL commands for at least tMRD time. 11. The DRAM has been properly initialized and is ready for any valid command.
Preliminary Data Sheet E1444E30 (Ver. 30)
22
EDD10161BBH-TS
Mode Register and Extended Mode Register Set There are two mode registers, the mode register and the extended mode register so as to define the operating mode. Parameters are set to both through the A0 to the A13 and BA0 and BA1 pins by the mode register set command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are set by inputting signal via the A0 to the A13 and BA0 and BA1 pins during mode register set cycles. BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode register must be set. Mode Register The mode register has four fields; Reserved /CAS latency Burst type Burst length : A13 through A7 : A6 through A4 : A3 : A2 through A0
Following mode register programming, no command can be issued before at least 2 clocks have elapsed. /CAS Latency /CAS latency must be set to 3. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become high-Z. The burst length is programmable as 2, 4 and 8 . Burst Type (Burst Sequence) The burst type specifies the order in which the burst data will be addressed. This order is programmable as either “Sequential” or “Interleave”. “Burst Operation” shows the addressing sequence for each burst length for each burst type.
BA0 0
MRS
BA1 0
A13 0
A12 0
A11 A10 A9
A8 0
A7 0
A6
A5
A4
A3 BT
A2
A1 BL
A0
0
0
0
LMODE
A6 A5 A4 CAS Latency 0 0 0
0 1
1
1 1
A3 Burst Type 0 Sequential 1 Interleave
Burst Length A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 BT = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved BT = 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
0 0 1
1 0
0
1 1
0 1 0
1 0
1
0 1
Reserved Reserved Reserved
3 Reserved
Reserved Reserved
Reserved
Mode Register Set
Preliminary Data Sheet E1444E30 (Ver. 30)
23
EDD10161BBH-TS
Extended Mode Register The extended mode register is as follows; Reserved Driver Strength : A13 through A7, A4 through A0 : A6 through A5
Following extended mode register programming, no command can be issued before at least 2 clocks have elapsed. Driver Strength
BA1 BA0 A13 1 0 0
A12 A11 A10 0 0
A9 0
A8 0
A7 0
A6
A5 DS
A4 0
A3 0
A2 0
A1 0
A0 0
0
A6 A5 Driver Strength 0 0 1 1 0 1 0 1 Normal 1/2 strength 1/4 strength Reserved
Extended Mode Register Set
Preliminary Data Sheet E1444E30 (Ver. 30)
24
EDD10161BBH-TS
Power-Down Mode and CKE Control DDR Mobile RAM will be into power-down mode at the second CK rising edge after CKE to be low level with NOP or DESL command at first CK rising edge after CKE signal to be low.
CK /CK CKE
Command
Valid*1
NOP
NOP
Valid*2
NOP
Address
Valid*1
Valid*2
Power-down mode Notes: 1. Valid*1 can be either Activate command or Precharge command, When Valid*1 is Activate command, power-down mode will be active power-down mode, while it will be precharge power down mode, if Valid*1 will be Precharge command. 2. Valid*2 can be any command as long as all of specified AC parameters are satisfied.
Power-Down Entry and Exit However, if the CKE has one clock cycle high and on clock cycle low just as below, even DDR Mobile RAM will not enter power-down mode, this command flow does not hurt any data and can be done.
CK /CK CKE
Command
PRE
NOP
NOP
ACT
Note: Assume PRE and ACT command is closing and activating same bank.
CKE Control
Preliminary Data Sheet E1444E30 (Ver. 30)
25
EDD10161BBH-TS
Burst Operation The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2 Starting Ad. Addressing(decimal) A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 Sequence A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
Preliminary Data Sheet E1444E30 (Ver. 30)
26
EDD10161BBH-TS
Read/Write Operations Bank Active A read or a write operation begins with the bank active command [ACT]. The bank active command determines a bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after the ACT is issued. Read Operation The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read command is issued. The burst length (BL) determines the length of a sequential output data by the read command that can be set to 2, 4 or 8 . The starting address of the burst read is defined by the column address, the bank select address (See “Pin Function”) in the cycle when the read command is issued. The data output timing is characterized by CL and tAC. The read burst start (CL-1) × tCK + tAC (ns) after the clock rising edge where the read command is latched. The DDR Mobile RAM outputs the data strobe through DQS pins simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the DQS pins are driven low from high-Z state. This low period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe. The DQ pins become high-Z in the next cycle after the burst read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become high-Z. This low period of DQS is referred as read postamble.
CK /CK Command NOP ACT tRCD NOP READ NOP
Address
Row
Column tRPRE
BL = 2 DQS DQ
out0 out1 tRPST
BL = 4
out0 out1 out2 out3
BL = 8
out0 out1 out2 out3 out4 out5 out6 out7 CL = 3 BL: Burst length
Read Operation (Burst Length)
Preliminary Data Sheet E1444E30 (Ver. 30)
27
EDD10161BBH-TS
t0 CK /CK t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
Command
READ
NOP
tRPRE
tRPST
DQS
tAC,tDQSCK
VTT
DQ
out0
out1
out2
out3
VTT
Read Operation (/CAS Latency) Write Operation The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4 or 8. The latency from write command to data input is fixed to 1. The starting address of the burst write is defined by the column address, the bank select address (See “Pin Function”) in the cycle when the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPRE prior to the first rising edge of DQS, DQS must be set to low. tWPST after the last falling edge of DQS, the DQS pins can be changed to high-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is referred as write postamble.
CK /CK Command NOP ACT Row tRCD NOP WRIT Column tWPRE tWPRES BL = 2 DQS DQ in0 in1 tWPST NOP
Address
BL = 4
in0
in1
in2
in3
BL = 8
in0
in1
in2
in3
in4
in5
in6
in7 BL: Burst length
Write Operation
Preliminary Data Sheet E1444E30 (Ver. 30)
28
EDD10161BBH-TS
Burst Stop Burst Stop Command during Burst Operation The burst stop (BST) command stops the burst read and sets all output buffers to high-Z. tBSTZ (= CL) cycles after a BST command issued, all DQ and DQS pins become high-Z. The BST command is also supported for the burst write operation. No data will be written in subsequent cycles. Note that bank address is not referred when this command is executed.
t0 CK /CK t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
Command
READ
BST tBSTZ
NOP
DQS
DQ
out0
out1
CL: /CAS latency
Burst Stop during a Read Operation
Preliminary Data Sheet E1444E30 (Ver. 30)
29
EDD10161BBH-TS
Auto Precharge Read with Auto Precharge The precharge is automatically performed after completing a read operation. The precharge starts BL/2 (= tRPD) clocks after READA command input. tRAS lock out mechanism for READA allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column command to the other active bank can be issued the next cycle after the last data output. Read with auto precharge command does not limit row commands execution for other bank.
CK /CK
tRAS (min) tRCD (min)
tRP (min)
BL/2 (= tRPD)
Command
ACT
READA
NOP
ACT
DQS tAC,tDQSCK DQ out0 out1 out2 out3
Note: Internal auto-precharge starts at the timing indicated by "
".
Read with auto precharge Write with Auto Precharge The precharge is automatically performed after completing a burst write operation. The precharge operation is started Write latency (WL) + BL/2 + tWR (= tWPD) clocks after WRITA command issued. A column command to the other banks can be issued the next cycle after the internal precharge command issued. Write with auto precharge command does not limit row commands execution for other bank.
CK /CK
tRAS (min)
tRCD (min)
tRP
NOP
Command
ACT
NOP
WRITA
ACT
WL + BL/2 + tWR (= tWPD)
DM
DQS
DQ
in1
in2
in3
".
in4
BL = 4
Note: Internal auto-precharge starts at the timing indicated by "
Burst Write (BL = 4)
Preliminary Data Sheet E1444E30 (Ver. 30)
30
;;;;; ;
EDD10161BBH-TS
Command Intervals A Read Command to the Consecutive Read Command Interval
Destination row of the consecutive read command Bank address Same Row address State Same Operation 1. ACTIVE 2. Same Different — 3. Different Any ACTIVE IDLE The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘A read command to the consecutive precharge interval’ section. The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank without interrupting the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued.
t0 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 CK /CK Command
ACT NOP READ READ NOP
Address BA
Row
Column A Column B
DQ
out A0
out A1
out B0
out out B1 B2
out B3
Column = A Column = B Read Read
Column = A Dout
Column = B Dout
DQS
Bank0 Active
CL = 3 BL = 4 Bank0
READ to READ Command Interval (same ROW address in the same bank)*
Note: n ≥ 4
Preliminary Data Sheet E1444E30 (Ver. 30)
31
CK /CK
Command
Address BA
DQ
DQS
Note: n ≥ 4
;; ;;;
EDD10161BBH-TS
tn+4 tn+5 tn+6
t0
t1
t2
tn
tn+1
tn+2
tn+3
ACT
NOP
ACT
NOP
READ
READ
NOP
Row0
Row1
Column A Column B
out out A0 A1
Bank0 Dout
out out out out B0 B1 B2 B3
Bank3 Dout
Column = A Column = B Read Read
Bank0 Active
Bank3 Active
Bank0 Read
Bank3 Read
CL = 3 BL = 4
READ to READ Command Interval (different bank)*
Preliminary Data Sheet E1444E30 (Ver. 30)
32
A Write Command to the Consecutive Write Command Interval
Destination row of the consecutive write command Bank address 1. Same Row address State Same
2.
Same
3.
Different
CK /CK Command
Address BA
DQ
DQS
Preliminary Data Sheet E1444E30 (Ver. 30)
;;;;;
EDD10161BBH-TS
Operation ACTIVE Different — Any ACTIVE IDLE The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank to interrupt the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘A write command to the consecutive precharge interval’ section. The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued.
t0 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6
ACT Row NOP WRIT WRIT
NOP
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Column = B Write
Column = A Write
Bank0 Active
BL = 4 Bank0
WRITE to WRITE Command Interval (same ROW address in the same bank)
33
CK /CK Command
Address BA
DQ
DQS
;;;; ;;
EDD10161BBH-TS
tn+4 tn+5 t0 t1 t2 tn tn+1 tn+2 tn+3
ACT NOP ACT NOP
WRIT
WRIT
NOP
Row0
Row1
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Bank0 Write Bank3 Write
Bank0 Active
Bank3 Active
BL = 4 Bank0, 3
WRITE to WRITE Command Interval (different bank)
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
A Read Command to the Consecutive Write Command Interval with the BST Command
Destination row of the consecutive write command Bank address 1. Same Row address State Same ACTIVE Operation Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘A read command to the consecutive precharge interval’ section. Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued.
2.
Same
Different
—
3.
Different
Any
ACTIVE IDLE
t0 CK /CK
t1
t2
t3
t4
t5
t6
t7
t8
Command
READ
BST
NOP tBSTW (≥ tBSTZ)
WRIT
NOP
DM
tBSTZ (= CL)
DQ
High-Z
out0 out1
in0
in1
in2
in3
DQS
OUTPUT
INPUT
BL = 4 CL = 3
READ to WRITE Command Interval
Preliminary Data Sheet E1444E30 (Ver. 30)
35
EDD10161BBH-TS
A Write Command to the Consecutive Read Command Interval: To Complete the Burst Operation
Destination row of the consecutive read command Bank address 1. Same Row address State Same ACTIVE Operation To complete the burst operation, the consecutive read command should be performed tWRD after the write command. Precharge the bank tWPD after the preceding write command. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘A read command to the consecutive precharge interval’ section. To complete a burst operation, the consecutive read command should be performed tWRD after the write command. Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued.
2.
Same
Different
—
3.
Different
Any
ACTIVE IDLE
t0 CK /CK
t1
t2
t3
tn
tn + 1
tn + 2
tn + 3
tn + 4
Command
WRIT
NOP
READ
NOP
tWRD (min)
tWTR*
DM
DQ
in0
in1
in2
in3
out0
out1
out2
DQS
INPUT
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
OUTPUT
BL = 4 CL = 3
WRITE to READ Command Interval
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
A Write Command to the Consecutive Read Command Interval: To Interrupt the Write Operation
Destination row of the consecutive read command Bank address 1. 2. 3. Same Same Different Row address State Same Different Any ACTIVE — ACTIVE IDLE Operation DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. —*
1
DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. —*
1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case. WRITE to READ Command Interval (Same bank, same ROW address)
t0 CK /CK t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
READ
NOP
DM
DQ
in0
in1
in2
out0 out1 out2 out3
High-Z High-Z
DQS
Data masked
BL = 4 CL = 3
[WRITE to READ delay = 1 clock cycle]
Preliminary Data Sheet E1444E30 (Ver. 30)
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EDD10161BBH-TS
t0 CK /CK t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
NOP
READ
NOP
DM
DQ
in0
in1
in2
in3
out0 out1 out2 out3
High-Z High-Z
DQS
Data masked
BL = 4 CL = 3
[WRITE to READ delay = 2 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
CK /CK
Command
WRIT
NOP
tWTR*
READ
NOP
DM
DQ
in0
in1
in2
in3
out0 out1 out2 out3
DQS
Data masked
BL = 4 CL = 3
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
[WRITE to READ delay = 4 clock cycle]
Preliminary Data Sheet E1444E30 (Ver. 30)
38
;;;;;;; ;
EDD10161BBH-TS
A Write Command to the Bust Stop Command Interval: To Interrupt the Write Operation WRITE to BST Command Interval (Same bank, same ROW address)
t0 t1 t2 t3 t4 t5 t6 t7 CK /CK Command
WRIT BST NOP
DM
DQ
in0
in1
DQS
BL = 4 or longer
Data will be written
Following data will not be written.
[WRITE to BST delay = 1 clock cycle]
t2 t3 t4
t0
t1
t5
t6
t7
CK
/CK
Command
WRIT
NOP
BST
NOP
DM
DQ
in0
in1
in2
in3
DQS
Data will be written
Following data will not be written.
BL = 8 or longer
[WRITE to BST delay = 2 clock cycle]
Preliminary Data Sheet E1444E30 (Ver. 30)
39
; ;; ;
EDD10161BBH-TS
t6 t7 t0 t1 t2 t3 t4 t5 CK /CK Command
WRIT NOP BST NOP
DM
DQ
in0
in1
in2
in3
in4
in5
DQS
BL = 8 or longer
Data will be written
Following data will not be written.
[WRITE to BST delay = 3 clock cycle]
Preliminary Data Sheet E1444E30 (Ver. 30)
40
EDD10161BBH-TS
A READ Command to the Consecutive Precharge Command Interval Operation by each case of destination bank of the consecutive Precharge command.
Bank address 1. 2. Same Different Operation The PRE and PALL command can interrupt a read operation. To complete a burst read operation, tRPD is required between the read and the precharge command. Please refer to the following timing chart. The PRE command does not interrupt a read command. No interval timing is required between the read and the precharge command.
READ to PRECHARGE Command Interval (same bank) : To output all data To complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued.
t0 CK /CK Command
NOP
READ
t1
t2
t3
t4
t5
t6
t7
t8
NOP
PRE/ PALL
NOP
DQ
out0 out1 out2 out3
DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4) READ to PRECHARGE Command Interval (same bank): To stop output data A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become high-Z tHZP (= CL) after the precharge command.
t0 CK /CK Command
NOP READ PRE/PALL NOP
t1
t2
t3
t4
t5
t6
t7
t8
High-Z
DQ
out0 out1
High-Z
DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 4, 8)
Preliminary Data Sheet E1444E30 (Ver. 30)
41
EDD10161BBH-TS
A Write Command to the Consecutive Precharge Command Interval (same bank) Operation by each case of destination bank of the consecutive Precharge command.
Bank address 1. 2. Same Different Operation The PRE and PALL command can interrupt a write operation. To complete a burst write operation, tWPD is required between the write and the precharge command. Please refer to the following timing chart. The PRE command does not interrupt a write command. No interval timing is required between the write and the precharge command.
WRITE to PRECHARGE Command Interval (same bank) The minimum interval tWPD is necessary between the write command and the precharge command.
t0 CK /CK Command t1 t2 t3 t4 tn tn + 1 tn + 2
WRIT
NOP
PRE/PALL
NOP
tWPD
tWR
DM
DQS
DQ
in0
in1
in2
in3
Last data input
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
Preliminary Data Sheet E1444E30 (Ver. 30)
42
EDD10161BBH-TS
t0 CK /CK Command t1 t2 t3 tn tn + 1 tn + 2 tn + 3
WRIT
NOP
PRE/PALL
NOP
tWPD
tWR
DM
DQS
DQ
in0
in1
Last data input
in2
in3
Data masked
BL = 4
WRITE to PRECHARGE Command Interval (same bank) (BL = 4, DM to mask data)
Preliminary Data Sheet E1444E30 (Ver. 30)
43
EDD10161BBH-TS
Bank Active Command Interval
Destination row of the consecutive ACT command Bank address 1. 2. Same Different Row address Any Any State ACTIVE ACTIVE IDLE Operation Two successive ACT commands can be issued at tRC interval. In between two successive ACT operations, precharge command should be executed. Precharge the bank. tRP after the precharge command, the consecutive ACT command can be issued. tRRD after an ACT command, the next ACT command can be issued.
CK /CK
Command
ACTV ACT
ACT
NOP
PRE
NOP
ACT
NOP
Address
ROW: 0
ROW: 1
ROW: 0
BA
Bank0 Active Bank3 Active
Bank0 Precharge Bank0 Active
tRRD
tRC
Bank Active to Bank Active Mode Register Set to Bank-Active Command Interval The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
CK /CK Command
MRS NOP ACT NOP
Address
CODE
BS and ROW
Mode Register Set tMRD
Bank3 Active
Mode Register Set to Bank Active
Preliminary Data Sheet E1444E30 (Ver. 30)
44
EDD10161BBH-TS
DM Control DM can mask input data. By setting DM to low, data can be written. UDM and LDM can mask the upper and lower byte of input data, respectively. When DM is set to high, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
t1 DQS t2 t3 t4 t5 t6
DQ
Mask
Mask
DM Write mask latency = 0
DM Control
Preliminary Data Sheet E1444E30 (Ver. 30)
45
EDD10161BBH-TS
Timing Waveforms
Command and Addresses Input Timing Definition
CK /CK
tIS
tIH
Command (/RAS, /CAS, /WE, /CS)
tIS
tIH
Address
= Don't care
Read Timing Definition (1)
CK /CK Command
READ
tLZ (min.)
tHZ (max.)
DQ (Output)
High-Z
High-Z
tLZ (min.)
DQS
High-Z
High-Z
CL = 3 BL = 2
Preliminary Data Sheet E1444E30 (Ver. 30)
46
EDD10161BBH-TS
Read Timing Definition (2)
/CK CK
tDQSCK
tAC (min.)
DQS
tAC (min.)
Fastest DQ (Output)
tDSC
tQH tDQSQ
Slowest DQ (Output) Data valid window
tDQSCK
tAC (max.)
DQS
tDQSQ
Fastest DQ (Output)
tAC (max.)
Slowest DQ (Output) Data valid window
tQH
tQHS
BL = 4 = Invalid
Write Timing Definition
tCK
/CK CK
tDQSS
tWPRES
tDSC
tDSS
tDSH
tDSS
DQS
tWPRE
tDQSL
tDQSH
tWPST
DQ (Din)
tDS
tDH
tDIPW
DM
tDS
tDH
tDIPW
tDIPW
BL = 4
= Don't care
Preliminary Data Sheet E1444E30 (Ver. 30)
47
EDD10161BBH-TS
Initialize Sequence
VDD
VDDQ /CK CK Clock cycle is necessary CKE VIH 2 refresh cycles are necessary
/CS
/RAS
/CAS
/WE
BA0
BA1
A10 Address key Address Address key
DM High-Z DQ, DQS
200µs
tCK
tRP
tRFC
tRFC
tMRD
tMRD
VDD/VDDQ powered up clock stable
Precharge All Banks Command is necessary
Auto-Refresh Command is necessary
Auto-Refresh Command is necessary
Mode Register Set Command is necessary
Extended Mode Register Set Command is necessary
Activate Command
= Don't care
Preliminary Data Sheet E1444E30 (Ver. 30)
48
EDD10161BBH-TS
Read Cycle
tCK tCH tCL CK /CK VIH CKE tRCD tIS tIH /CS tIS tIH /RAS tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A10 tIS tIH Address tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRAS tIS tIH tRP tIS tIH tRC
DM High-Z tRPRE tDSC tRPST
DQS (output)
DQ (output)
High-Z Bank Bank 0 Active Bank 0 Read Bank 0 Precharge
CL = 3 BL = 4 Bank0 Access = Don't care
Preliminary Data Sheet E1444E30 (Ver. 30)
49
EDD10161BBH-TS
Write Cycle
tCK tCH tCL
CK /CK
VIH
CKE
tRC tRAS tIS tIH tIS tIH tRP tIS tIH
tRCD tIS tIH
/CS
tIS tIH
/RAS
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CAS
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/WE
tIS tIH
tIS tIH
tIS tIH
tIS tIH
BA
tIS tIH
tIS tIH
tIS tIH
tIS tIH
A10
tIS tIH
tIS tIH
tIS tIH
tIS tIH
Address
tIS tIH
tIS tIH
tDQSS
tDQSL
tWPST
DQS (input)
tDQSH
tDS
tDS
tDH
DM
tDS tDH
DQ (input)
tDH
tWR
Bank Bank 0 Active
Bank 0 Write
Bank 0 Precharge
CL = 2 BL = 4 Bank0 Access = Don't care
Preliminary Data Sheet E1444E30 (Ver. 30)
50
EDD10161BBH-TS
Mode Register Set Cycle
T0
/CK CK CKE /CS /RAS /CAS /WE BA Address DM
High-Z
DQS
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
VIH
code
valid
code
R: b
C: b
High-Z
DQ
tRP Precharge If needed
tMRD
b
Mode register set
Bank 3 Active
Bank 3 Read
Bank 3 Precharge
CL = 3 BL = 4 = Don't care
Read/Write Cycle
T0 /CK CK CKE /CS /RAS /CAS /WE BA Address DM DQS DQ a Read tRWD Bank 0 Active Bank 0 Bank 3 Read Active Bank 3 Write b Write tWRD Bank 3 Read Read cycle CL = 3 BL = 4 = Don't care b’’ Read R:a C:a R:b C:b C:b'' T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Tn Tn+1 Tn+2 Tn+3 Tn+4
VIH
Preliminary Data Sheet E1444E30 (Ver. 30)
51
EDD10161BBH-TS
Auto-Refresh Cycle
/CK CK CKE /CS /RAS /CAS /WE BA Address A10=1 R: b C: b VIH
DM DQS DQ tRP Precharge If needed Auto Refresh High-Z High-Z tRFC Bank 0 Active Bank 0 Read CL = 3 BL = 4 = Don't care b
Preliminary Data Sheet E1444E30 (Ver. 30)
52
EDD10161BBH-TS
Self-Refresh Cycle
/CK CK CKE
tIS
tIH CKE = low
/CS /RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM DQS DQ tRP
tSREX
Precharge If needed
Self refresh entry
Self refresh exit
Bank 0 Active
Bank 0 Read BL = 4 = Don't care
Preliminary Data Sheet E1444E30 (Ver. 30)
53
EDD10161BBH-TS
Power-Down Entry and Exit
/CK CK CKE /CS /RAS /CAS /WE BA Address DM DQS DQ
tRP
A10=1
tIS
tIH CKE = low
tCKE
R: b
R: c
tPDEN
tPDEX Power down exit Bank 0 Active Bank 0 Read
Precharge If needed
Power down entry
BL = 4 = Don't care
Preliminary Data Sheet E1444E30 (Ver. 30)
54
EDD10161BBH-TS
Package Drawing
60-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm 9.00 ± 0.10
INDEX MARK
0.15 S A
11.00 ± 0.10
0.15 S B
0.20 S
1.00 max. S
0.10 S
0.35 ± 0.05
A
60-φ0.45 ± 0.05
φ0.08 M S A B
B
0.8
INDEX MARK 1.6 0.8 6.4 ECA-TS2-0302-01
Preliminary Data Sheet E1444E30 (Ver. 30)
55
0.4
7.2
EDD10161BBH-TS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDD10161BBH. Type of Surface Mount Device EDD10161BBH: 60-ball FBGA < Lead free (Sn-Ag-Cu) >
Preliminary Data Sheet E1444E30 (Ver. 30)
56
EDD10161BBH-TS
N OTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E1444E30 (Ver. 30)
57
EDD10161BBH-TS
Mobile RAM is a trademark of Elpida Memory, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0706
Preliminary Data Sheet E1444E30 (Ver. 30)
58
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