PRELIMINARY DATA SHEET
512M bits DDR SDRAM WTR (Wide Temperature Range)
EDD5116AFTA-TI (32M words × 16 bits)
Specifications
• Density: 512M bits • Organization ⎯ 8M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: ⎯ DDR400: VDD, VDDQ = 2.6V ± 0.1V ⎯ DDR333: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 400Mbps/333Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.5, 3 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period: 7.8μs • Operating ambient temperature range ⎯ TA = −40°C to +85°C
Features
• Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver • Data inputs, outputs, and DM are synchronized with DQS • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Wide temperature range ⎯ TA = −40°C to +85°C
Document No. E0894E30 (Ver. 3.0) Date Published November 2006 (K) Japan Printed in Japan URL: http://www.elpida.com ©Elpida Memory, Inc. 2006
EDD5116AFTA-TI
Ordering Information
Part number EDD5108AFTA-5BTI-E EDD5116AFTA-6BTI-E Mask version F Organization (words × bits) 32M × 16 Internal banks 4 Data rate Mbps (max.) 400 333 JEDEC speed bin (CL-tRCD-tRP) DDR400B (3-3-3) DDR333B (2.5-3-3) Package 66-pin Plastic TSOP (II)
Part Number
E D D 51 16 A F TA - 5B TI - E
Elpida Memory Environment Code E: Lead Free (RoHS compliant) Spec Detail TI: WTR (−40°C to +85°C) Speed 5B: DDR400B (3-3-3) 6B: DDR333B (2.5-3-3) Package TA: TSOP (II) Die Rev. Type D: Monolithic Device Product Family D: DDR SDRAM Density / Bank 51: 512M / 4-bank Organization 16: x16 Power Supply, Interface A: 2.5V, SSTL_2
Speed Grade Compatibility
Operating Frequencies Speed bin DDR400B DDR333B CL2 133MHz 133MHz CL2.5 166MHz 166MHz CL3 200MHz 166MHz
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (Top view) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
Pin name A0 to A12 BA0, BA1 DQ0 to DQ15 LDQS, UDQS /CS /RAS /CAS /WE UDM, LDM
Function Address inputs Bank select address Data-input/output Input and output data strobe Chip select Row address strobe command Column address strobe command Write enable Input mask
Pin name CK /CK CKE VREF VDD VSS VDDQ VSSQ NC
Function Clock input Differential Clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Speed Grade Compatibility............................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................13 Pin Function.................................................................................................................................................14 Command Operation ...................................................................................................................................16 Simplified State Diagram .............................................................................................................................23 Operation of the DDR SDRAM ....................................................................................................................24 Timing Waveforms.......................................................................................................................................43 Package Drawing ........................................................................................................................................49 Recommended Soldering Conditions..........................................................................................................50
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Electrical Specifications
• All voltages are referenced to VSS (GND). • After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD IOS PD TA Tstg Rating –1.0 to +3.6 –1.0 to +3.6 50 1.0 –40 to +85 –55 to +125 Unit V V mA W °C °C Note
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (TA = –40°C to +85°C)
Parameter Supply voltage Symbol VDD, VDDQ VDD, VDDQ VSS, VSSQ Input reference voltage Termination voltage Input high voltage Input low voltage VREF VTT VIH (DC) VIL (DC) Speed DDR400 DDR333 min. 2.5 2.3 0 0.49 × VDDQ VREF – 0.04 VREF + 0.15 –0.3 –0.3 0.5 × VDDQ − 0.2V 0.36 typ. 2.6 2.5 0 0.50 × VDDQ VREF — — — 0.5 × VDDQ — max. 2.7 2.7 0 0.51 × VDDQ VREF + 0.04 VDDQ + 0.3 VREF – 0.15 VDDQ + 0.3 0.5 × VDDQ + 0.2V VDDQ + 0.6 Unit V V V V V V V V V V 5, 6 2 3 4 Notes 1 1
Input voltage level, VIN (DC) CK and /CK inputs Input differential cross point VIX (DC) voltage, CK and /CK inputs Input differential voltage, VID (DC) CK and /CK inputs
Notes: 1. 2. 3. 4. 5. 6.
VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable DC excursion of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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DC Characteristics 1 (TA = –40°C to +85°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
Parameter Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Idle power down standby current Floating idle standby current Quiet idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto-refresh current Self-refresh current Operating current (4 banks interleaving) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A Grade max. 120 160 5 30 25 30 60 215 215 220 5 400 Unit mA mA mA mA mA mA mA mA mA mA mA mA Test condition CKE ≥ VIH, tRC = tRC (min.) CKE ≥ VIH, BL = 4, CL = 3, tRC = tRC (min.) CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH DQ, DQS, DM = VREF CKE ≥ VIH, /CS ≥ VIH DQ, DQS, DM = VREF CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) CKE ≥ VIH, BL = 2, CL = 3 CKE ≥ VIH, BL = 2, CL = 3 tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH Input ≥ VDD – 0.2 V Input ≤ 0.2 V BL = 4 Notes 1, 2, 9 1, 2, 5 4 4, 5 4, 10 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6
1, 5, 6, 7
DC Characteristics 1 (TA = –40°C to +85°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333]
Parameter Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Idle power down standby current Floating idle standby current Quiet idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto-refresh current Self-refresh current Operating current (4 banks interleaving) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A Grade max. 105 140 5 30 20 30 55 185 185 205 5 380 Unit mA mA mA mA mA mA mA mA mA mA mA mA Test condition CKE ≥ VIH, tRC = tRC (min.) CKE ≥ VIH, BL = 4, CL = 2.5, tRC = tRC (min.) CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH, DQ, DQS, DM = VREF CKE ≥ VIH, /CS ≥ VIH, DQ, DQS, DM = VREF CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) CKE ≥ VIH, BL = 2, CL = 2.5 CKE ≥ VIH, BL = 2, CL = 2.5 tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH Input ≥ VDD – 0.2 V Input ≤ 0.2 V BL = 4 Notes 1, 2, 9 1, 2, 5 4 4, 5 4, 10 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6
1, 5, 6, 7
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Notes: 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one clock cycle. 6. DQ, DM and DQS transition twice per one clock cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycle. 10. Command/Address stable at ≥ VIH or ≤ VIL. DC Characteristics 2 (TA = –40°C to +85°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400] (TA = –40°C to +85°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333]
Parameter Input leakage current Output leakage current Output high current Output low current Symbol ILI ILO IOH IOL min. –2 –5 –15.2 15.2 max. 2 5 — — Unit µA µA mA mA Test condition VDD ≥ VIN ≥ VSS VDDQ ≥ VOUT ≥ VSS VOUT = 1.95V VOUT = 0.35V Notes
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400] (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333]
Parameter Input capacitance Symbol CI1 CI2 Delta input capacitance Cdi1 Cdi2 Data input/output capacitance Delta input/output capacitance CI/O Cdio Pins CK, /CK All other input pins CK, /CK All other input-only pins DQ, DM, DQS DQ, DM, DQS min. 2.0 2.0 — — 4.0 — typ. — — — — — — max. 3.0 3.0 0.25 0.5 5 0.5 Unit pF pF pF pF pF pF Notes 1 1 1 1 1, 2 1
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ΔVOUT = 0.2V. 2. DOUT circuits are disabled.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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AC Characteristics (TA = –40°C to +85°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
-5B Parameter Clock cycle time CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS output access time from CK, /CK DQS to DQ skew DQ/DQS output hold time from DQS Data hold skew factor Data-out high-impedance time from CK, /CK Data-out low-impedance time from CK, /CK Read preamble Read postamble DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width Write preamble setup time Write preamble Write postamble Symbol tCK tCH tCL tHP tAC tDQSCK tDQSQ tQH tQHS tHZ tLZ tRPRE tRPST tDS tDH tDIPW tWPRES tWPRE tWPST min. 5 0.45 0.45 min (tCH, tCL) –0.7 –0.55 — tHP – tQHS — — –0.7 0.9 0.4 0.4 0.4 1.75 0 0.25 0.4 0.72 0.2 0.2 0.35 0.35 0.6 0.6 2.2 2 40 55 70 15 15 tRCD min. 10 15 (tWR/tCK)+ (tRP/tCK) 2 — max. 8 0.55 0.55 — 0.7 0.55 0.4 — 0.5 0.7 0.7 1.1 0.6 — — — — — 0.6 1.28 — — — — — — — — 120000 — — — — — — — — — 7.8 Unit ns tCK tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns tCK ns ns ns ns ns ns ns ns tCK tCK µs 13 8 8 7 9 8 8 7 5, 11 6, 11 2, 11 2, 11 3 Notes 10
Write command to first DQS latching transition tDQSS DQS falling edge to CK setup time DQS falling edge hold time from CK DQS input high pulse width DQS input low pulse width Address and control input setup time Address and control input hold time Address and control input pulse width Mode register set command cycle time Active to Precharge command period Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read/Write delay Precharge to active command period Active to Autoprecharge delay Active to active command period Write recovery time Auto precharge write recovery and precharge time Internal write to Read command delay Average periodic refresh interval tDSS tDSH tDQSH tDQSL tIS tIH tIPW tMRD tRAS tRC tRFC tRCD tRP tRAP tRRD tWR tDAL tWTR tREF
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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AC Characteristics (TA = –40°C to +85°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333]
-6B Parameter Clock cycle time (CL = 2) (CL = 2.5) CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS output access time from CK, /CK DQS to DQ skew DQ/DQS output hold time from DQS Data hold skew factor Data-out high-impedance time from CK, /CK Data-out low-impedance time from CK, /CK Read preamble Read postamble DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width Write preamble setup time Write preamble Write postamble Symbol tCK tCK tCH tCL tHP tAC tDQSCK tDQSQ tQH tQHS tHZ tLZ tRPRE tRPST tDS tDH tDIPW tWPRES tWPRE tWPST min. 7.5 6 0.45 0.45 min (tCH, tCL) –0.7 –0.6 — tHP – tQHS — — –0.7 0.9 0.4 0.45 0.45 1.75 0 0.25 0.4 0.75 0.2 0.2 0.35 0.35 0.75 0.75 2.2 2 42 60 72 18 18 tRCD min. 12 15 (tWR/tCK)+ (tRP/tCK) 1 — — — — — 120000 — — — — — — — max. 12 12 0.55 0.55 — 0.7 0.6 0.45 — 0.55 0.7 0.7 1.1 0.6 — — — — — 0.6 1.25 — — — Unit ns ns tCK tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns tCK ns ns ns ns ns ns ns ns tCK tCK 13 8 8 7 9 8 8 7 5, 11 6, 11 2, 11 2, 11 3 Notes 10
Write command to first DQS latching transition tDQSS DQS falling edge to CK setup time DQS falling edge hold time from CK DQS input high pulse width DQS input low pulse width Address and control input setup time Address and control input hold time Address and control input pulse width Mode register set command cycle time Active to Precharge command period Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read/Write delay Precharge to active command period Active to Autoprecharge delay Active to active command period Write recovery time Auto precharge write recovery and precharge time Internal write to Read command delay tDSS tDSH tDQSH tDQSL tIS tIH tIPW tMRD tRAS tRC tRFC tRCD tRP tRAP tRRD tWR tDAL tWTR
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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-6B Parameter Average periodic refresh interval Symbol tREF min. — max. 7.8 Unit µs Notes
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see ‘Timing Waveforms’ section. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.6V ± 0.1V (DDR400), 2.5V ± 0.2V (DDR333). VDD power supply variation per cycle expected to be less than 0.4V/400 cycle. 13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For –5B Speed at CL = 3, tCK = 5ns, tWR = 15ns and tRP= 15ns, tDAL = (15ns/5ns) + (15ns/5ns) = (3) + (4) tDAL = 6 clocks
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Test Conditions
Parameter Input reference voltage Termination voltage Input high voltage Input low voltage Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate Symbol VREF VTT VIH (AC) VIL (AC) VID (AC) VIX (AC) SLEW Value VDDQ/2 VREF VREF + 0.31 VREF − 0.31 0.62 VREF 1 Unit V V V V V V V/ns
tCK CK VID /CK tCL tCH VIX VDD VIH VIL VREF VSS
VDD VREF VSS
Δt
SLEW = (VIH (AC) – VIL (AC))/Δt
VTT Measurement point DQ CL = 30pF RT = 50Ω
Input Waveforms and Output Load
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Timing Parameter Measured in Clock Cycle
Number of clock cycle tCK Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 2) (CL = 2.5) (CL = 3) Burst stop command to DQ High-Z (CL = 2) (CL = 2.5) (CL = 3) Read command to write command delay (to output all data) (CL = 2) (CL = 2.5) (CL = 3) Pre-charge command to High-Z (CL = 2) (CL = 2.5) (CL = 3) Write command to data in latency Write recovery DM to data in latency Self-refresh exit to non-read command Self-refresh exit to read command Power down entry Power down exit to command input Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read/Write delay Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTW tBSTZ tBSTZ tBSTZ tRWD tRWD tRWD tHZP tHZP tHZP tWCD tWR tDMD tSNR tSRD tPDEN tPDEX 5ns min. 1 + BL/2 + tWR BL/2 1 + BL/2 + tWTR — — 3 — — 3 — — 3 + BL/2 — — 3 1 3 0 15 200 1 1 8 11 14 3 3 max. — — — — — — — — 3 — — — — — 3 1 — 0 — — 1 — ⎯ ⎯ ⎯ ⎯ ⎯ 6ns min. 1 + BL/2 + tWR BL/2 1 + BL/2 + tWTR — 3 3 — 2.5 3 — 3 + BL/2 3 + BL/2 — 2.5 3 1 3 0 12 200 1 1 7 10 12 3 3 max. — — — — — — — 2.5 3 — — — — 2.5 3 1 — 0 — — 1 — ⎯ ⎯ ⎯ ⎯ ⎯ Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
Active to Precharge command period tRAS tRC tRFC tRCD
Precharge to active command period tRP
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Block Diagram
CK /CK CKE
Clock generator
Bank 3 Bank 2 Bank 1
A0 to A12, BA0, BA1
Mode register
Row address buffer and refresh counter
Row decoder
Memory cell array Bank 0
Sense amp.
Command decoder
/CS /RAS /CAS /WE
Column address buffer and burst counter
Column decoder
Control logic
Data control circuit
Latch circuit
DQS
CK, /CK
DLL
Input & Output buffer
DM
DQ
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Pin Function
CK, /CK (input pins) The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock input to this pin. The other input signals are referred at CK rising edge. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the /CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0 to the A9, at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle. This column address becomes the starting address of a burst operation. [Address Pins Table]
Address (A0 to A12) Part number EDD5116AFTA Row address AX0 to AX12 Column address AY0 to AY9
A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0 and BA1 (input pins) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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CKE (input pin) This pin determines whether or not the next CK is valid. If CKE is high, the next CK rising edge is valid. If CKE is low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. CKE must be maintained high throughout read or write access. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper hold time tIH. LDM and UDM (input pins) DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and VREF. DMs provide the byte mask function. When DM = high, the data input at the same timing are masked while the internal burst counter will be count up. In ×16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM controls the upper byte (DQ8 to DQ15) of write data. DQ0 to DQ15 (input/output pins) Data is input to and output from these pins. LDQS and UDQS (input and output pins) DQS provides the read data strobes (as output) and the write data strobes (as input). In ×16 products, LDQS is the lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal. VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Command Operation
Command Truth Table DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other combinations than those in the table below are illegal.
CKE Command Ignore command No operation Burst stop in read command Column address and read command Read with auto-precharge Column address and write command Write with auto-precharge Row address strobe and bank active Precharge select bank Precharge all bank Refresh Symbol DESL NOP BST READ READA WRIT WRITA ACT PRE PALL REF SELF Mode register set MRS EMRS n–1 H H H H H H H H H H H H H H n H H H H H H H H H H H L H H /CS H L L L L L L L L L L L L L /RAS /CAS /WE × H H H H H H L L L L L L L × H H L L L L H H H L L L L × H L H H L L H L L H H L L BA1 × × × V V V V V V × × × L L BA0 × × × V V V V V V × × × L H AP × × × L H L H V L H × × L L Address × × × V V V V V × × × × V V
Remark: H: VIH. L: VIL. ×: VIH or VIL V: Valid address input Note: The CKE level must be kept for 1 CK cycle at least. Ignore command [DESL] When /CS is high at the cross point of the CK rising edge and the VREF level, every input are neglected and internal status is held. No operation [NOP] As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data input are neglected and internal status is held. Burst stop in read operation [BST] This command stops a burst read operation, which is not applicable for a burst write operation. Column address strobe and read command [READ] This command starts a read operation. The start address of the burst read is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation, the output buffer becomes high-Z. Read with auto-precharge [READA] This command starts a read operation. After completion of the read operation, precharge is automatically executed. Column address strobe and write command [WRIT] This command starts a write operation. The start address of the burst write is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. Write with auto-precharge [WRITA] This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Row address strobe and bank activate [ACT] This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12). (See Bank Select Signal Table) Precharge selected bank [PRE] This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL. Precharge all banks [PALL] This command starts a precharge operation for all banks. Refresh [REF/SELF] This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another is self-refresh. For details, refer to the CKE truth table section. Mode register set/Extended mode register set [MRS/EMRS] The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins (the A0 to the A12, BA0 to BA1) in the mode register set cycle. For details, refer to "Mode register and extended mode register set".
CKE Truth Table
CKE Current state Idle Idle Idle Command Auto-refresh command (REF) Self-refresh entry (SELF) Power down entry (PDEN) n–1 H H H H Self-refresh Self-refresh exit (SELFX) L L Power down Power down exit (PDEX) L L n H L L L H H H H /CS L L L H L H L H /RAS L L H × H × H × /CAS L L H × H × H × /WE H H H × H × H × Address × × × × × × × × Notes 2 2
Remark: H: VIH. L: VIL. ×: VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM.
Current state Precharging*
1
/CS H L L L L L L L
/RAS /CAS /WE × H H H H L L L × H H H H L L L L × H H H L × H H H H L L L × H H H H L L L × H H L L H H L × H H L L H H L L × H H L × × H H L L H H L × H H L L H H L × H L H L H L × × H L H L H L H L × H L × × × H L H L H L × × H L H L H L ×
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE × × × × × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 ×
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* NOP ILLEGAL
11 11 11 11
Next state ldle ldle — — — — ldle — ldle ldle
11 11 11
Idle*
2
H L L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SELF MRS DESL NOP BST
NOP NOP ILLEGAL* ILLEGAL* ILLEGAL* Activating NOP Refresh/ 12 Self-refresh* Mode register set* NOP NOP ILLEGAL ILLEGAL ILLEGAL
12
— — — Active ldle ldle/ Self-refresh ldle ldle ldle — — — Active Active
Refresh 3 (auto-refresh)*
H L L L L
Activating*
4
H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL
11 11 11 11 11
— — — — — — Active Active Active
Active*
5
H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL
Starting read operation Read/READA Write Starting write operation recovering/ precharging ILLEGAL*
11
— Idle —
Pre-charge ILLEGAL
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Current state Read*
6
/CS H L L L L L L L
/RAS /CAS /WE × H H H H L L L × H H H H L L L × H H H × H H L L H H L × H H L L H H L × H H L × H L H L H L × × H L H L H L × × H L H
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP BST Interrupting burst read operation to start new read ILLEGAL* ILLEGAL*
13 11
Next state Active Active Active Active — — Precharging — Precharging Precharging —
14 14 11, 14 11, 14
Interrupting burst read operation to start pre-charge ILLEGAL
Read with auto-preH 7 charge* L L L L L L L Write*
8
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL
— — — — — Write recovering Write recovering — Read/ReadA
H L L L
DESL NOP BST READ/READA
NOP NOP ILLEGAL Interrupting burst write operation to start read operation. Interrupting burst write operation to start new write operation. ILLEGAL*
11
L L L L Write recovering*
9
H L L L × H H H H L L L
L H H L × H H L L H H L
L H L × × H L H L H L ×
BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 ×
WRIT/WRITA ACT PRE, PALL
Write/WriteA — Idle — Active Active —
Interrupting write operation to start precharge. ILLEGAL NOP NOP ILLEGAL Starting new write operation. ILLEGAL* ILLEGAL* ILLEGAL
11 11
H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL
Starting read operation. Read/ReadA Write/WriteA — — —
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Current state Write with auto10 pre-charge*
/CS H L L L L L L L
/RAS × H H H H L L L
/CAS × H H L L H H L
/WE × H L H L H L ×
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 ×
Command DESL NOP BST READ/READA WRIT/WRIT A ACT PRE, PALL
Operation NOP NOP ILLEGAL ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL
14 14 11, 14 11, 14
Next state Precharging Precharging — — — — — —
Remark: Notes: 1. 2. 3. 4. 5. 6.
H: VIH. L: VIL. ×: VIH or VIL The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued. The DDR SDRAM is in "Active" state after "Activating" is completed. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned off. 7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been output and DQ output circuits are turned off. 8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input. 9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input. 10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input. 11. This command may be issued for other banks, depending on the state of the banks. 12. All banks must be in "IDLE". 13. Before executing a write command to stop the preceding burst read operation, BST command must be issued. 14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or a write with auto-precharge enabled, may be followed by any column command to other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply. (E.g. Conflict between READ data and WRITE data must be avoided.) The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank, is summarized below.
From command Read w/AP
To command (different bank, noninterrupting command) Read or Read w/AP Write or Write w/AP Precharge or Activate
Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/2) 1 1 + (BL/2) + tWTR BL/2 1
Units tCK tCK tCK tCK tCK tCK
Write w/AP
Read or Read w/AP Write or Write w/AP Precharge or Activate
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Command Truth Table for CKE
Current State CKE n–1 n Self-refresh H L L L L L Self-refresh recovery H H H H H H H H Power down H L L L All banks idle H H H H H H H H H H L Row active H L × H H H H L H H H H L L L L × H H L H H H H H L L L L L × × × /CS × H L L L × H L L L H L L L × H L × H L L L L H L L L L × × × /RAS /CAS /WE Address × × H H L × × H H L × H H L × × H × × H L L L × H L L L × × × × × H L × × × H L × × H L × × × H × × × H L L × × H L L × × × × × × × × × × × × × × × × × × × H × × × × H L × × × H L × × × × × × × × × × × Maintain power down mode Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table CBR (auto) refresh × × × × × × × × × × × × × × Operation INVALID, CK (n-1) would exit self-refresh Self-refresh recovery Self-refresh recovery ILLEGAL ILLEGAL Maintain self-refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CK (n – 1) would exit power down EXIT power down → Idle Notes
OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table Self-refresh 1
OPCODE Refer to operations in Function Truth Table Power down Refer to operations in Function Truth Table Power down 1 1
Remark: H: VIH. L: VIL. ×: VIH or VIL Note: 1. Self-refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Auto-refresh command [REF] This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined by the internal refresh controller. The average refresh cycle is 7.8 μs. The output buffer becomes high-Z after autorefresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last auto-refresh command. Self-refresh entry [SELF] This command starts self-refresh. The self-refresh operation continues as long as CKE is held low. During the selfrefresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is terminated by a self-refresh exit command. Power down mode entry [PDEN] tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held low. No internal refresh operation occurs during the power down mode. [PDEN] do not disable DLL. Self-refresh exit [SELFX] This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied.To issue read command, tSRD has to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command within 7.8 μs. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Simplified State Diagram
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
CKE CKE_ ACTIVE CKE_ CKE ROW ACTIVE IDLE POWER DOWN
ACTIVE POWER DOWN
BST READ
WRITE Write WRITE WITH AP WRITE READ READ WITH AP READ WITH AP
Read
READ
WRITE WITH AP
READ WITH AP
PRECHARGE WRITEA PRECHARGE PRECHARGE READA
POWER APPLIED
POWER ON
PRECHARGE PRECHARGE
Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Operation of the DDR SDRAM
Power-up Sequence (1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined). Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. (2) Start clock and maintain stable condition for a minimum of 200 µs. (3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high. (4) Issue precharge all command for the device. (5) Issue EMRS to enable DLL. (6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of clock input is required to lock the DLL after every DLL reset). (7) Issue precharge all command for the device. (8) Issue 2 or more auto-refresh commands. (9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting the DLL.
(4) CK /CK (5) (6) (7) (8) (9)
Command
PALL
EMRS
MRS
PALL tRP
REF REF tRFC
REF tRFC
MRS 2 cycles (min.)
Any command
2 cycles (min.)
2 cycles (min.) 2 cycles (min.) DLL reset with A8 = High
DLL enable
Disable DLL reset with A8 = Low 200 cycles (min)
Power-up Sequence after CKE Goes High
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Mode Register and Extended Mode Register Set There are two mode registers, the mode register and the extended mode register so as to define the operating mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode register must be set. Remind that no other parameters shown in the table bellow are allowed to input to the registers.
BA0 0 MRS A8 DLL Reset A6 A5 A4 CAS Latency 0 0 0 Reserved 0 No 1 Yes 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Reserved 2 3 Reserved Reserved 2.5 Reserved A3 Burst Type 0 Sequential 1 Interleave A2 A1 A0 Burst Length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved BA1 0 A12 0 A11 A10 A9 0 0 0 A8 DR A7 0 A6 A5 A4 A3 BT A2 A1 BL A0
LMODE
Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
BA0 BA1 1 0
A12 A11 A10 A9 0 0 0 0
A8 0
A7 0
A6 0
A5 0
A4 0
A3 0
A2 0
A1 DS
A0 DLL
EMRS A1 Driver Strength 0 Normal 1 Weak A0 DLL Control 0 DLL Enable 1 DLL Disable
Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0)
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Burst Operation The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2 Starting Ad. Addressing(decimal) A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 Sequence A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Read/Write Operations Bank active A read or a write operation begins with the bank active command [ACT]. The bank active command determines a bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after the ACT is issued. Read operation The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read command is issued. The burst length (BL) determines the length of a sequential output data by the read command that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A12 and BA0, BA1 pins in the cycle when the read command is issued. The data output timing are characterized by CL and tAC. The read burst start CL • tCK + tAC (ns) after the clock rising edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven low from VTT level. This low period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is referred as read postamble.
t0 CK /CK tRCD Command NOP ACT NOP READ NOP t1 t5 t6 t7 t8 t9 t10 t11
Address
Row
Column tRPRE
BL = 2 DQS DQ
out0 out1 tRPST
BL = 4
out0 out1 out2 out3
BL = 8
out0 out1 out2 out3 out4 out5 out6 out7 CL = 3 BL: Burst length
Read Operation (Burst Length)
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t5 t5.5 t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 CK /CK Command READ NOP tRPRE tRPST DQS VTT CL = 3 tAC,tDQSCK DQ out0 out1 out2 out3 VTT
Read Operation (/CAS Latency)
Write operation The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPRE prior to the first rising edge of the DQS should be set to low and tWPST after the last falling edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is referred as write postamble.
t0 t1 tn tn+0.5 tn+1 tn+2 tn+3 tn+4 tn+5
CK
/CK
tRCD
Command
NOP
ACT
NOP
WRITE
NOP
Address
Row
Column
tWPRE
tWPRES
BL = 2
in0
in1
DQS DQ
tWPST
BL = 4
in0
in1
in2
in3
BL = 8
in0
in1
in2
in3
in4
in5
in6
in7
BL: Burst length
Write Operation
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Burst Stop Burst stop command during burst read The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed.
t0 CK /CK t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
Command
READ
BST tBSTZ
NOP 3 cycles
DQS CL = 3 DQ out0 out1
CL: /CAS latency
Burst Stop during a Read Operation
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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Auto Precharge Read with auto-precharge The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2) cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge command does not limit row commands execution for other bank. Refer to ‘Function truth table and related note(Notes.*14)‘.
CK /CK tRPD tRAP (min) = tRCD (min) BL/2 cycles tRP (min)
Command
ACT
READA
NOP
ACT
DQS tAC,tDQSCK DQ out0 out1 out2 out3
Note: Internal auto-precharge starts at the timing indicated by "
".
Read with auto-precharge Write with auto-precharge The precharge is automatically performed after completing a burst write operation. The precharge operation is started (1 + BL/ 2 + tWR) cycles after WRITA command issued. A column command to the other banks can be issued the next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row commands execution for other bank. Refer to the ‘Read with Auto-Precharge Enabled, Write with AutoPrecharge Enabled’ section. Refer to ‘Function truth table and related note(Notes.*14)‘.
CK /CK tRAS (min) tRCD (min) Command ACT NOP WRITA NOP ACT tRP
1 + BL/2 + tWR cycles DM DQS
DQ
in1
in2
in3 ".
in4 BL = 4
Note: Internal auto-precharge starts at the timing indicated by "
Burst Write (BL = 4)
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Command Intervals A Read command to the consecutive Read command Interval
Destination row of the consecutive read command Bank address 1. Same Row address State Same ACTIVE Operation The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘A read command to the consecutive precharge interval’ section. The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank without interrupting the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued.
2.
Same
Different
—
3.
Different
Any
ACTIVE IDLE
t0 CK /CK Command ACT Row NOP
t4
t5
t6
t7
t8
t9
t10
t11
READ
READ
NOP
Address BA
Column A Column B
DQ Column = A Column = B Read Read
out out A0 A1
out B0
out B1
out B2
out B3
Column = A Dout
Column = B Dout
DQS Bank0 Active CL = 3 BL = 4 Bank0
READ to READ Command Interval (same ROW address in the same bank)
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t0 CK /CK Command ACT Row0 NOP ACT Row1 NOP READ READ NOP t1 t2 t5 t6 t7 t8 t9 t10 t11
Address BA
Column A Column B
DQ Column = A Column = B Read Read
out out A0 A1 Bank0 Dout
out out out out B0 B1 B2 B3 Bank3 Dout
DQS Bank0 Active Bank3 Active Bank0 Read Bank3 Read CL = 3 BL = 4
READ to READ Command Interval (different bank)
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A Write command to the consecutive Write command Interval
Destination row of the consecutive write command Bank address 1. Same Row address State Same
2.
Same
3.
Different
CK /CK Command
Address BA
DQ
DQS
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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EDD5116AFTA-TI
Operation ACTIVE Different — Any ACTIVE IDLE The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank to interrupt the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘A write command to the consecutive precharge interval’ section. The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued.
t0 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 ACT NOP WRIT WRIT NOP Row Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = B Write Column = A Write Bank0 Active BL = 4 Bank0
WRITE to WRITE Command Interval (same ROW address in the same bank)
33
CK /CK Command
Address BA
DQ
DQS
;;;; ;;
EDD5116AFTA-TI
tn+4 tn+5 t0 t1 t2 tn tn+1 tn+2 tn+3 ACT NOP ACT NOP WRIT WRIT NOP Row0 Row1 Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Write Bank3 Write Bank0 Active Bank3 Active BL = 4 Bank0, 3
WRITE to WRITE Command Interval (different bank)
Preliminary Data Sheet E0894E30 (Ver. 3.0)
34
EDD5116AFTA-TI
A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive write command Bank address 1. Same Row address State Same ACTIVE Operation Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘A read command to the consecutive precharge interval’ section. Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued.
2.
Same
Different
—
3.
Different
Any
ACTIVE IDLE
t0 CK /CK
t1
t2
t3
t4
t5
t6
t7
t8
Command
READ
BST
NOP tBSTW (≥ tBSTZ)
WRIT
NOP
DM tBSTZ (= CL)
DQ High-Z DQS
out0 out1
in0
in1
in2
in3
OUTPUT
INPUT
BL = 4 CL = 3
READ to WRITE Command Interval
Preliminary Data Sheet E0894E30 (Ver. 3.0)
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EDD5116AFTA-TI
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read command Bank address 1. Same Row address State Same ACTIVE Operation To complete the burst operation, the consecutive read command should be performed tWRD (= 1 + BL/2 + tWTR) after the write command. Precharge the bank tWPD after the preceding write command. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘A read command to the consecutive precharge interval’ section. To complete a burst operation, the consecutive read command should be performed tWRD (= 1 + BL/2 + tWTR) after the write command. Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued.
2.
Same
Different
—
3.
Different
Any
ACTIVE IDLE
t0 CK /CK
t1
t2
t3
t4
t5
t6
t7
t8
Command
WRIT
NOP tWRD (min) 1 + BL/2 + tWTR cycles tWTR*
READ
NOP
DM
DQ
in0
in1
in2
in3
out0
out1
out2
DQS
INPUT
OUTPUT BL = 4 CL = 3
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
WRITE to READ Command Interval
Preliminary Data Sheet E0894E30 (Ver. 3.0)
36
EDD5116AFTA-TI
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read command Bank address 1. 2. 3. Same Same Different Row address State Same Different Any ACTIVE — ACTIVE IDLE Operation DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. —*
1
DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. —*
1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case. WRITE to READ Command Interval (Same bank, same ROW address)
t0 CK /CK t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
READ 1 cycle CL=3
NOP
DM
DQ
in0
in1
in2
out0 out1 out2 out3
High-Z High-Z
DQS
Data masked
BL = 4 CL = 3
[WRITE to READ delay = 1 clock cycle]
Preliminary Data Sheet E0894E30 (Ver. 3.0)
37
Command
Command
Preliminary Data Sheet E0894E30 (Ver. 3.0)
;;;;;
EDD5116AFTA-TI
t7 t8 t0 t1 t2 t3 t4 t5 t6 CK /CK WRIT NOP READ NOP 2 cycle CL=3 DM DQ in0 in1 in2 in3 out0 out1 out2 out3 High-Z DQS High-Z Data masked BL = 4 CL = 3
[WRITE to READ delay = 2 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
WRIT
NOP
READ
NOP
3 cycle
CL=3
tWTR*
DM
DQ
in0
in1
in2
in3
out0 out1 out2 out3
DQS
Data masked
BL = 4 CL = 3
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
[WRITE to READ delay = 3 clock cycle]
38
EDD5116AFTA-TI
A Read command to the consecutive Precharge command interval (same bank): To output all data To complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued.
t0 CK /CK Command NOP
READ
t1
t2
t3
t4
t5
t6
t7
t8
NOP
PRE/ PALL
NOP
DQ
out0 out1 out2 out3
DQS tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4) READ to PRECHARGE Command Interval (same bank): To stop output data A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP (= CL) after the precharge command.
t0 CK /CK Command NOP READ PRE/PALL CL = 3 DQ out0 out1 High-Z NOP High-Z t1 t2 t3 t4 t5 t6 t7 t8
DQS tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 2, 4, 8)
Preliminary Data Sheet E0894E30 (Ver. 3.0)
39
A Write command to the consecutive Precharge command interval (same bank) The minimum interval tWPD is necessary between the write command and the precharge command.
t0 t1 t2 t3 t4 t5 t6
CK /CK
Command
DM
DQS
DQ
Precharge Termination in Write Cycles During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command is issued, the invalid data must be masked by DM.
t0 t1 t2 t3 t4 t5 t6 t7
CK /CK
Command
DM
DQS
DQ
Preliminary Data Sheet E0894E30 (Ver. 3.0)
;;;;;;; ;; ;
EDD5116AFTA-TI
t7 WRIT NOP PRE/PALL NOP tWPD tWR in0 in1 in2 in3 Last data input
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
WRIT
NOP
PRE/PALL
NOP
tWR
in0
in1
in2
in3
Data masked
Precharge Termination in Write Cycles (same bank) (BL = 4)
40
EDD5116AFTA-TI
Bank active command interval
Destination row of the consecutive ACT command Bank address 1. 2. Same Different Row address Any Any State ACTIVE ACTIVE IDLE Operation Two successive ACT commands can be issued at tRC interval. In between two successive ACT operations, precharge command should be executed. Precharge the bank. tRP after the precharge command, the consecutive ACT command can be issued. tRRD after an ACT command, the next ACT command can be issued.
CK /CK
Command
ACTV ACT
ACT
NOP
PRE
NOP
ACT
NOP
Address
ROW: 0
ROW: 1
ROW: 0
BA Bank0 Active Bank3 Active tRC Bank0 Precharge Bank0 Active
tRRD
Bank Active to Bank Active Mode register set to Bank-active command interval The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
CK /CK Command MRS NOP ACT NOP
Address
CODE Mode Register Set tMRD
BS and ROW Bank3 Active
Preliminary Data Sheet E0894E30 (Ver. 3.0)
41
EDD5116AFTA-TI
DM Control DM can mask input data. In ×16 products, UDM and LDM can mask the upper and lower byte of input data respectively. By setting DM to low, data can be written. When DM is set to high, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
t1 DQS t2 t3 t4 t5 t6
DQ
Mask
Mask
DM Write mask latency = 0
DM Control
Self-Refresh The self-refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self-refresh mode, the DDR SDRAM retains data without external clocking. The self-refresh command is initiated like an auto-refresh command except CKE is disabled (low). The DLL is automatically disabled upon entering self-refresh, and is automatically enabled upon exiting self-refresh. Any time the DLL is enabled a DLL reset must follow and 200 clock cycles should occur before a read command can be issued. Input signals except CKE are “Don’t care” during self-refresh. Since CKE is an SSTL2 input, VREF must be maintained during self-refresh. The procedure for exiting self-refresh requires a sequence of commands. First, CK must be stable prior to CKE going back high. Once CKE is high, the DDR SDRAM must have NOP commands issued for tSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. The use of self-refresh mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self-refresh mode. Upon exit from self-refresh an extra auto-refresh command is recommended.
t0 t1 t2 t3 t4 t5 t6 tm tn
tCK
tCH tCL /CK CK tRP*1 tIS CKE tIS ≥ tSNR*3 ≥ tSRD*2
tIS tIH
Command
SELF NOP NOP NOP Valid
Notes: 1. Device must be in the “All banks idle” state prior to entering self-refresh mode. 2. tSRD is applied for a read or a read with autoprecharge command. 3. tSNR is applied for any command except a read or a read with autoprecharge command.
Preliminary Data Sheet E0894E30 (Ver. 3.0)
42
Timing Waveforms
Command and Addresses Input Timing Definition
CK /CK
Read Timing Definition
/CK CK
DQS
DQ (Dout)
Write Timing Definition
/CK CK
DQS
DQ (Din)
DM
Preliminary Data Sheet E0894E30 (Ver. 3.0)
;;;;;;
EDD5116AFTA-TI
tIS tIH Command (/RAS, /CAS, /WE, /CS) VREF tIS tIH Address VREF
tCK
tCH
tCL
tDQSCK
tDQSCK
tDQSCK
tDQSCK tRPST
tRPRE
tDQSQ
tLZ
tAC
tQH tAC
tDQSQ
tAC
tQH tHZ
tQH
tDQSQ tQH
tDQSQ
tCK
tDQSS
tDSS
tDSH
tDSS
VREF
tWPRES
tWPRE
tDQSL
tDQSH
tWPST
VREF
tDS
tDH
tDIPW
VREF
tDS
tDH
tDIPW
tDIPW
43
EDD5116AFTA-TI
Read Cycle
tCK tCH tCL
; ;; ; ;; ; ;;
CK /CK VIH tRC CKE tRCD tRAS tRP tIS tIH tIS tIH tIS tIH tIS tIH /CS tIS tIH tIS tIH tIS tIH tIS tIH /RAS tIS tIH tIS tIH tIS tIH tIS tIH /CAS tIS tIH tIS tIH tIS tIH tIS tIH /WE tIS tIH tIS tIH tIS tIH tIS tIH BA tIS tIH tIS tIH tIS tIH tIS tIH A10 tIS tIH tIS tIH tIS tIH Address DM DQS High-Z tRPRE tRPST DQ (output) High-Z Bank Bank 0 Active Bank 0 Read Bank 0 Precharge CL = 2 BL = 4 Bank0 Access = VIH or VIL
Preliminary Data Sheet E0894E30 (Ver. 3.0)
; ;; ;; ; ;
44
;;; ;; ; ; ;
EDD5116AFTA-TI
Write Cycle
tCK tCH tCL CK /CK VIH tRC CKE tRAS tRCD tRP tIS tIH tIS tIH tIS tIH tIS tIH /CS tIS tIH tIS tIH tIS tIH tIS tIH /RAS tIS tIH tIS tIH tIS tIH tIS tIH /CAS tIS tIH tIS tIH tIS tIH tIS tIH /WE tIS tIH tIS tIH tIS tIH tIS tIH BA tIS tIH tIS tIH tIS tIH tIS tIH A10 tIS tIH tIS tIH tIS tIH Address tDQSS tDQSL tWPST DQS (input) tDQSH tDS tDS
tDH
DM
tDS
tDH
DQ (input)
tWR
tDH
Bank Bank 0 Active
Bank 0 Write
Bank 0 Precharge
CL = 2 BL = 4 Bank0 Access = VIH or VIL
Preliminary Data Sheet E0894E30 (Ver. 3.0)
45
EDD5116AFTA-TI
Mode Register Set Cycle
0 /CK CK CKE /CS /RAS /CAS /WE BA Address DM High-Z DQS High-Z DQ (output) tRP Precharge If needed tMRD Mode register set Bank 3 Active Bank 3 Read Bank 3 Precharge CL = 2 BL = 4 = VIH or VIL b valid code code R: b C: b VIH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Read/Write Cycle
/CK CK CKE /CS /RAS /CAS /WE BA Address DM DQS DQ (output) DQ (input) Bank 0 Active High-Z tRWD Bank 0 Bank 3 Read Active Bank 3 Write a b tWRD Bank 3 Read Read cycle CL = 2 BL = 4 =VIH or VIL b’’ R:a C:a R:b C:b C:b''
VIH
Preliminary Data Sheet E0894E30 (Ver. 3.0)
46
EDD5116AFTA-TI
Auto-Refresh Cycle
/CK CK CKE /CS /RAS /CAS /WE BA Address A10=1 R: b C: b VIH
DM DQS DQ (output) High-Z DQ (input) Precharge If needed tRP Auto Refresh tRFC Bank 0 Active Bank 0 Read CL = 2 BL = 4 = VIH or VIL b
Preliminary Data Sheet E0894E30 (Ver. 3.0)
47
EDD5116AFTA-TI
Self-Refresh Cycle
/CK CK CKE
tIS
tIH CKE = low
/CS /RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM DQS DQ (output) High-Z DQ (input) tRP tSNR tSRD Precharge If needed Self refresh entry Self refresh exit Bank 0 Active Bank 0 Read CL = 2.5 BL = 4 = VIH or VIL
Preliminary Data Sheet E0894E30 (Ver. 3.0)
48
EDD5116AFTA-TI
Package Drawing
66-pin Plastic TSOP (II) Solder plating: Lead free (Sn-Bi)
Unit: mm
22.22 ± 0.10 *1
A
66
34
PIN#1 ID
1
0.65
33
B 0.80 Nom 0 to 8°
0.17 to 0.32 0.91 max.
0.13 M S A B
11.76 ± 0.20
10.16
0.25
1.0 ± 0.05
1.20 max
0.09 to 0.20
S
0.10 S
0.10 +0.08 −0.05
0.15 0.60 +0.20 −
Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. ECA-TS2-0143-01
Preliminary Data Sheet E0894E30 (Ver. 3.0)
49
EDD5116AFTA-TI
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDD5116AFTA-TI. Type of Surface Mount Device EDD5116AFTA-TI: 66-pin Plastic TSOP (II) < Lead free (Sn-Bi) >
Preliminary Data Sheet E0894E30 (Ver. 3.0)
50
EDD5116AFTA-TI
N OTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0894E30 (Ver. 3.0)
51
EDD5116AFTA-TI
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0894E30 (Ver. 3.0)
52
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